hw/ide/via.c

   1 /*
   2  * QEMU IDE Emulation: PCI VIA82C686B support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  * Copyright (c) 2010 Huacai Chen <zltjiangshi@gmail.com>
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26 #include "qemu/osdep.h"
  27 #include "hw/hw.h"
  28 #include "hw/pci/pci.h"
  29 #include "sysemu/sysemu.h"
  30 #include "sysemu/dma.h"
  31
  32 #include "hw/ide/pci.h"
  33 #include "trace.h"
  34
  35 static uint64_t bmdma_read(void *opaque, hwaddr addr,
  36                            unsigned size)
  37 {
  38     BMDMAState *bm = opaque;
  39     uint32_t val;
  40
  41     if (size != 1) {
  42         return ((uint64_t)1 << (size * 8)) - 1;
  43     }
  44
  45     switch (addr & 3) {
  46     case 0:
  47         val = bm->cmd;
  48         break;
  49     case 2:
  50         val = bm->status;
  51         break;
  52     default:
  53         val = 0xff;
  54         break;
  55     }
  56
  57     trace_bmdma_read_via(addr, val);
  58     return val;
  59 }
  60
  61 static void bmdma_write(void *opaque, hwaddr addr,
  62                         uint64_t val, unsigned size)
  63 {
  64     BMDMAState *bm = opaque;
  65
  66     if (size != 1) {
  67         return;
  68     }
  69
  70     trace_bmdma_write_via(addr, val);
  71     switch (addr & 3) {
  72     case 0:
  73         bmdma_cmd_writeb(bm, val);
  74         break;
  75     case 2:
  76         bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
  77         break;
  78     default:;
  79     }
  80 }
  81
  82 static const MemoryRegionOps via_bmdma_ops = {
  83     .read = bmdma_read,
  84     .write = bmdma_write,
  85 };
  86
  87 static void bmdma_setup_bar(PCIIDEState *d)
  88 {
  89     int i;
  90
  91     memory_region_init(&d->bmdma_bar, OBJECT(d), "via-bmdma-container", 16);
  92     for(i = 0;i < 2; i++) {
  93         BMDMAState *bm = &d->bmdma[i];
  94
  95         memory_region_init_io(&bm->extra_io, OBJECT(d), &via_bmdma_ops, bm,
  96                               "via-bmdma", 4);
  97         memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
  98         memory_region_init_io(&bm->addr_ioport, OBJECT(d),
  99                               &bmdma_addr_ioport_ops, bm, "bmdma", 4);
 100         memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
 101     }
 102 }
 103
 104 static void via_ide_set_irq(void *opaque, int n, int level)
 105 {
 106     PCIDevice *d = PCI_DEVICE(opaque);
 107
 108     if (level) {
 109         d->config[0x70 + n * 8] |= 0x80;
 110     } else {
 111         d->config[0x70 + n * 8] &= ~0x80;
 112     }
 113
 114     level = (d->config[0x70] & 0x80) || (d->config[0x78] & 0x80);
 115     n = pci_get_byte(d->config + PCI_INTERRUPT_LINE);
 116     if (n) {
 117         qemu_set_irq(isa_get_irq(NULL, n), level);
 118     }
 119 }
 120
 121 static void via_ide_reset(void *opaque)
 122 {
 123     PCIIDEState *d = opaque;
 124     PCIDevice *pd = PCI_DEVICE(d);
 125     uint8_t *pci_conf = pd->config;
 126     int i;
 127
 128     for (i = 0; i < 2; i++) {
 129         ide_bus_reset(&d->bus[i]);
 130     }
 131
 132     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_WAIT);
 133     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
 134                  PCI_STATUS_DEVSEL_MEDIUM);
 135
 136     pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0);
 137     pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4);
 138     pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170);
 139     pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374);
 140     pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-23h */
 141     pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e);
 142
 143     /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/
 144     pci_set_long(pci_conf + 0x40, 0x0a090600);
 145     /* IDE misc configuration 1/2/3 */
 146     pci_set_long(pci_conf + 0x44, 0x00c00068);
 147     /* IDE Timing control */
 148     pci_set_long(pci_conf + 0x48, 0xa8a8a8a8);
 149     /* IDE Address Setup Time */
 150     pci_set_long(pci_conf + 0x4c, 0x000000ff);
 151     /* UltraDMA Extended Timing Control*/
 152     pci_set_long(pci_conf + 0x50, 0x07070707);
 153     /* UltraDMA FIFO Control */
 154     pci_set_long(pci_conf + 0x54, 0x00000004);
 155     /* IDE primary sector size */
 156     pci_set_long(pci_conf + 0x60, 0x00000200);
 157     /* IDE secondary sector size */
 158     pci_set_long(pci_conf + 0x68, 0x00000200);
 159     /* PCI PM Block */
 160     pci_set_long(pci_conf + 0xc0, 0x00020001);
 161 }
 162
 163 static void via_ide_realize(PCIDevice *dev, Error **errp)
 164 {
 165     PCIIDEState *d = PCI_IDE(dev);
 166     uint8_t *pci_conf = dev->config;
 167     int i;
 168
 169     pci_config_set_prog_interface(pci_conf, 0x8f); /* native PCI ATA mode */
 170     pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
 171     dev->wmask[PCI_INTERRUPT_LINE] = 0xf;
 172
 173     qemu_register_reset(via_ide_reset, d);
 174
 175     memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops,
 176                           &d->bus[0], "via-ide0-data", 8);
 177     pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]);
 178
 179     memory_region_init_io(&d->cmd_bar[0], OBJECT(d), &pci_ide_cmd_le_ops,
 180                           &d->bus[0], "via-ide0-cmd", 4);
 181     pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[0]);
 182
 183     memory_region_init_io(&d->data_bar[1], OBJECT(d), &pci_ide_data_le_ops,
 184                           &d->bus[1], "via-ide1-data", 8);
 185     pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[1]);
 186
 187     memory_region_init_io(&d->cmd_bar[1], OBJECT(d), &pci_ide_cmd_le_ops,
 188                           &d->bus[1], "via-ide1-cmd", 4);
 189     pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]);
 190
 191     bmdma_setup_bar(d);
 192     pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
 193
 194     vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
 195
 196     for (i = 0; i < 2; i++) {
 197         ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
 198         ide_init2(&d->bus[i], qemu_allocate_irq(via_ide_set_irq, d, i));
 199
 200         bmdma_init(&d->bus[i], &d->bmdma[i], d);
 201         d->bmdma[i].bus = &d->bus[i];
 202         ide_register_restart_cb(&d->bus[i]);
 203     }
 204 }
 205
 206 static void via_ide_exitfn(PCIDevice *dev)
 207 {
 208     PCIIDEState *d = PCI_IDE(dev);
 209     unsigned i;
 210
 211     for (i = 0; i < 2; ++i) {
 212         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
 213         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
 214     }
 215 }
 216
 217 void via_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
 218 {
 219     PCIDevice *dev;
 220
 221     dev = pci_create_simple(bus, devfn, "via-ide");
 222     pci_ide_create_devs(dev, hd_table);
 223 }
 224
 225 static void via_ide_class_init(ObjectClass *klass, void *data)
 226 {
 227     DeviceClass *dc = DEVICE_CLASS(klass);
 228     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 229
 230     k->realize = via_ide_realize;
 231     k->exit = via_ide_exitfn;
 232     k->vendor_id = PCI_VENDOR_ID_VIA;
 233     k->device_id = PCI_DEVICE_ID_VIA_IDE;
 234     k->revision = 0x06;
 235     k->class_id = PCI_CLASS_STORAGE_IDE;
 236     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 237 }
 238
 239 static const TypeInfo via_ide_info = {
 240     .name          = "via-ide",
 241     .parent        = TYPE_PCI_IDE,
 242     .class_init    = via_ide_class_init,
 243 };
 244
 245 static void via_ide_register_types(void)
 246 {
 247     type_register_static(&via_ide_info);
 248 }
 249
 250 type_init(via_ide_register_types)