target/rx/helper.c

   1 /*
   2  *  RX emulation
   3  *
   4  *  Copyright (c) 2019 Yoshinori Sato
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "qemu/osdep.h"
  20 #include "qemu/bitops.h"
  21 #include "cpu.h"
  22 #include "exec/log.h"
  23 #include "exec/cpu_ldst.h"
  24 #include "hw/irq.h"
  25
  26 void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte)
  27 {
  28     if (env->psw_pm == 0) {
  29         env->psw_ipl = FIELD_EX32(psw, PSW, IPL);
  30         if (rte) {
  31             /* PSW.PM can write RTE and RTFI */
  32             env->psw_pm = FIELD_EX32(psw, PSW, PM);
  33         }
  34         env->psw_u = FIELD_EX32(psw, PSW, U);
  35         env->psw_i = FIELD_EX32(psw, PSW, I);
  36     }
  37     env->psw_o = FIELD_EX32(psw, PSW, O) << 31;
  38     env->psw_s = FIELD_EX32(psw, PSW, S) << 31;
  39     env->psw_z = 1 - FIELD_EX32(psw, PSW, Z);
  40     env->psw_c = FIELD_EX32(psw, PSW, C);
  41 }
  42
  43 #define INT_FLAGS (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR)
  44 void rx_cpu_do_interrupt(CPUState *cs)
  45 {
  46     RXCPU *cpu = RX_CPU(cs);
  47     CPURXState *env = &cpu->env;
  48     int do_irq = cs->interrupt_request & INT_FLAGS;
  49     uint32_t save_psw;
  50
  51     env->in_sleep = 0;
  52
  53     if (env->psw_u) {
  54         env->usp = env->regs[0];
  55     } else {
  56         env->isp = env->regs[0];
  57     }
  58     save_psw = rx_cpu_pack_psw(env);
  59     env->psw_pm = env->psw_i = env->psw_u = 0;
  60
  61     if (do_irq) {
  62         if (do_irq & CPU_INTERRUPT_FIR) {
  63             env->bpc = env->pc;
  64             env->bpsw = save_psw;
  65             env->pc = env->fintv;
  66             env->psw_ipl = 15;
  67             cs->interrupt_request &= ~CPU_INTERRUPT_FIR;
  68             qemu_set_irq(env->ack, env->ack_irq);
  69             qemu_log_mask(CPU_LOG_INT, "fast interrupt raised\n");
  70         } else if (do_irq & CPU_INTERRUPT_HARD) {
  71             env->isp -= 4;
  72             cpu_stl_data(env, env->isp, save_psw);
  73             env->isp -= 4;
  74             cpu_stl_data(env, env->isp, env->pc);
  75             env->pc = cpu_ldl_data(env, env->intb + env->ack_irq * 4);
  76             env->psw_ipl = env->ack_ipl;
  77             cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
  78             qemu_set_irq(env->ack, env->ack_irq);
  79             qemu_log_mask(CPU_LOG_INT,
  80                           "interrupt 0x%02x raised\n", env->ack_irq);
  81         }
  82     } else {
  83         uint32_t vec = cs->exception_index;
  84         const char *expname = "unknown exception";
  85
  86         env->isp -= 4;
  87         cpu_stl_data(env, env->isp, save_psw);
  88         env->isp -= 4;
  89         cpu_stl_data(env, env->isp, env->pc);
  90
  91         if (vec < 0x100) {
  92             env->pc = cpu_ldl_data(env, 0xffffffc0 + vec * 4);
  93         } else {
  94             env->pc = cpu_ldl_data(env, env->intb + (vec & 0xff) * 4);
  95         }
  96         switch (vec) {
  97         case 20:
  98             expname = "privilege violation";
  99             break;
 100         case 21:
 101             expname = "access exception";
 102             break;
 103         case 23:
 104             expname = "illegal instruction";
 105             break;
 106         case 25:
 107             expname = "fpu exception";
 108             break;
 109         case 30:
 110             expname = "non-maskable interrupt";
 111             break;
 112         case 0x100 ... 0x1ff:
 113             expname = "unconditional trap";
 114         }
 115         qemu_log_mask(CPU_LOG_INT, "exception 0x%02x [%s] raised\n",
 116                       (vec & 0xff), expname);
 117     }
 118     env->regs[0] = env->isp;
 119 }
 120
 121 bool rx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 122 {
 123     RXCPU *cpu = RX_CPU(cs);
 124     CPURXState *env = &cpu->env;
 125     int accept = 0;
 126     /* hardware interrupt (Normal) */
 127     if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 128         env->psw_i && (env->psw_ipl < env->req_ipl)) {
 129         env->ack_irq = env->req_irq;
 130         env->ack_ipl = env->req_ipl;
 131         accept = 1;
 132     }
 133     /* hardware interrupt (FIR) */
 134     if ((interrupt_request & CPU_INTERRUPT_FIR) &&
 135         env->psw_i && (env->psw_ipl < 15)) {
 136         accept = 1;
 137     }
 138     if (accept) {
 139         rx_cpu_do_interrupt(cs);
 140         return true;
 141     }
 142     return false;
 143 }
 144
 145 hwaddr rx_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 146 {
 147     return addr;
 148 }