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target/arm: Add a timer to predict PMU counter overflow
[qemu/ar7.git] / target / xtensa / translate.c
bloba435d9c36cf174e1a481307038e5110e135c6197
1 /*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include "qemu/osdep.h"
32
33 #include "cpu.h"
34 #include "exec/exec-all.h"
35 #include "disas/disas.h"
36 #include "tcg-op.h"
37 #include "qemu/log.h"
38 #include "sysemu/sysemu.h"
39 #include "exec/cpu_ldst.h"
40 #include "exec/semihost.h"
41 #include "exec/translator.h"
42
43 #include "exec/helper-proto.h"
44 #include "exec/helper-gen.h"
45
46 #include "trace-tcg.h"
47 #include "exec/log.h"
48
49
50 struct DisasContext {
51 DisasContextBase base;
52 const XtensaConfig *config;
53 uint32_t pc;
54 int cring;
55 int ring;
56 uint32_t lbeg_off;
57 uint32_t lend;
58
59 bool sar_5bit;
60 bool sar_m32_5bit;
61 bool sar_m32_allocated;
62 TCGv_i32 sar_m32;
63
64 unsigned window;
65 unsigned callinc;
66 bool cwoe;
67
68 bool debug;
69 bool icount;
70 TCGv_i32 next_icount;
71
72 unsigned cpenable;
73
74 uint32_t *raw_arg;
75 xtensa_insnbuf insnbuf;
76 xtensa_insnbuf slotbuf;
77 };
78
79 static TCGv_i32 cpu_pc;
80 static TCGv_i32 cpu_R[16];
81 static TCGv_i32 cpu_FR[16];
82 static TCGv_i32 cpu_SR[256];
83 static TCGv_i32 cpu_UR[256];
84
85 #include "exec/gen-icount.h"
86
87 typedef struct XtensaReg {
88 const char *name;
89 uint64_t opt_bits;
90 enum {
91 SR_R = 1,
92 SR_W = 2,
93 SR_X = 4,
94 SR_RW = 3,
95 SR_RWX = 7,
96 } access;
97 } XtensaReg;
98
99 #define XTENSA_REG_ACCESS(regname, opt, acc) { \
100 .name = (regname), \
101 .opt_bits = XTENSA_OPTION_BIT(opt), \
102 .access = (acc), \
103 }
104
105 #define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX)
106
107 #define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \
108 .name = (regname), \
109 .opt_bits = (opt), \
110 .access = (acc), \
111 }
112
113 #define XTENSA_REG_BITS(regname, opt) \
114 XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX)
115
116 static const XtensaReg sregnames[256] = {
117 [LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP),
118 [LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP),
119 [LCOUNT] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP),
120 [SAR] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL),
121 [BR] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN),
122 [LITBASE] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R),
123 [SCOMPARE1] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE),
124 [ACCLO] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16),
125 [ACCHI] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16),
126 [MR] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16),
127 [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16),
128 [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16),
129 [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16),
130 [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER),
131 [WINDOW_START] = XTENSA_REG("WINDOW_START",
132 XTENSA_OPTION_WINDOWED_REGISTER),
133 [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU),
134 [MMID] = XTENSA_REG_BITS("MMID", XTENSA_OPTION_ALL),
135 [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU),
136 [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU),
137 [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU),
138 [IBREAKENABLE] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG),
139 [MEMCTL] = XTENSA_REG_BITS("MEMCTL", XTENSA_OPTION_ALL),
140 [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR),
141 [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL),
142 [DDR] = XTENSA_REG("DDR", XTENSA_OPTION_DEBUG),
143 [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG),
144 [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG),
145 [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG),
146 [DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG),
147 [DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG),
148 [DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG),
149 [CONFIGID0] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL, SR_R),
150 [EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION),
151 [EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
152 [EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
153 [EPC1 + 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
154 [EPC1 + 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
155 [EPC1 + 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
156 [EPC1 + 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
157 [DEPC] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION),
158 [EPS2] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
159 [EPS2 + 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
160 [EPS2 + 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
161 [EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
162 [EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
163 [EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
164 [CONFIGID1] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL, SR_R),
165 [EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION),
166 [EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2",
167 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
168 [EXCSAVE1 + 2] = XTENSA_REG("EXCSAVE3",
169 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
170 [EXCSAVE1 + 3] = XTENSA_REG("EXCSAVE4",
171 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
172 [EXCSAVE1 + 4] = XTENSA_REG("EXCSAVE5",
173 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
174 [EXCSAVE1 + 5] = XTENSA_REG("EXCSAVE6",
175 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
176 [EXCSAVE1 + 6] = XTENSA_REG("EXCSAVE7",
177 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
178 [CPENABLE] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR),
179 [INTSET] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT, SR_RW),
180 [INTCLEAR] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT, SR_W),
181 [INTENABLE] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT),
182 [PS] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL),
183 [VECBASE] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR),
184 [EXCCAUSE] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION),
185 [DEBUGCAUSE] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG, SR_R),
186 [CCOUNT] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT),
187 [PRID] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID, SR_R),
188 [ICOUNT] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG),
189 [ICOUNTLEVEL] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG),
190 [EXCVADDR] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION),
191 [CCOMPARE] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT),
192 [CCOMPARE + 1] = XTENSA_REG("CCOMPARE1",
193 XTENSA_OPTION_TIMER_INTERRUPT),
194 [CCOMPARE + 2] = XTENSA_REG("CCOMPARE2",
195 XTENSA_OPTION_TIMER_INTERRUPT),
196 [MISC] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR),
197 [MISC + 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR),
198 [MISC + 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR),
199 [MISC + 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR),
200 };
201
202 static const XtensaReg uregnames[256] = {
203 [EXPSTATE] = XTENSA_REG_BITS("EXPSTATE", XTENSA_OPTION_ALL),
204 [THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER),
205 [FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR),
206 [FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR),
207 };
208
209 void xtensa_translate_init(void)
210 {
211 static const char * const regnames[] = {
212 "ar0", "ar1", "ar2", "ar3",
213 "ar4", "ar5", "ar6", "ar7",
214 "ar8", "ar9", "ar10", "ar11",
215 "ar12", "ar13", "ar14", "ar15",
216 };
217 static const char * const fregnames[] = {
218 "f0", "f1", "f2", "f3",
219 "f4", "f5", "f6", "f7",
220 "f8", "f9", "f10", "f11",
221 "f12", "f13", "f14", "f15",
222 };
223 int i;
224
225 cpu_pc = tcg_global_mem_new_i32(cpu_env,
226 offsetof(CPUXtensaState, pc), "pc");
227
228 for (i = 0; i < 16; i++) {
229 cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
230 offsetof(CPUXtensaState, regs[i]),
231 regnames[i]);
232 }
233
234 for (i = 0; i < 16; i++) {
235 cpu_FR[i] = tcg_global_mem_new_i32(cpu_env,
236 offsetof(CPUXtensaState, fregs[i].f32[FP_F32_LOW]),
237 fregnames[i]);
238 }
239
240 for (i = 0; i < 256; ++i) {
241 if (sregnames[i].name) {
242 cpu_SR[i] = tcg_global_mem_new_i32(cpu_env,
243 offsetof(CPUXtensaState, sregs[i]),
244 sregnames[i].name);
245 }
246 }
247
248 for (i = 0; i < 256; ++i) {
249 if (uregnames[i].name) {
250 cpu_UR[i] = tcg_global_mem_new_i32(cpu_env,
251 offsetof(CPUXtensaState, uregs[i]),
252 uregnames[i].name);
253 }
254 }
255 }
256
257 static inline bool option_enabled(DisasContext *dc, int opt)
258 {
259 return xtensa_option_enabled(dc->config, opt);
260 }
261
262 static void init_sar_tracker(DisasContext *dc)
263 {
264 dc->sar_5bit = false;
265 dc->sar_m32_5bit = false;
266 dc->sar_m32_allocated = false;
267 }
268
269 static void reset_sar_tracker(DisasContext *dc)
270 {
271 if (dc->sar_m32_allocated) {
272 tcg_temp_free(dc->sar_m32);
273 }
274 }
275
276 static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
277 {
278 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
279 if (dc->sar_m32_5bit) {
280 tcg_gen_discard_i32(dc->sar_m32);
281 }
282 dc->sar_5bit = true;
283 dc->sar_m32_5bit = false;
284 }
285
286 static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
287 {
288 TCGv_i32 tmp = tcg_const_i32(32);
289 if (!dc->sar_m32_allocated) {
290 dc->sar_m32 = tcg_temp_local_new_i32();
291 dc->sar_m32_allocated = true;
292 }
293 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
294 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
295 dc->sar_5bit = false;
296 dc->sar_m32_5bit = true;
297 tcg_temp_free(tmp);
298 }
299
300 static void gen_exception(DisasContext *dc, int excp)
301 {
302 TCGv_i32 tmp = tcg_const_i32(excp);
303 gen_helper_exception(cpu_env, tmp);
304 tcg_temp_free(tmp);
305 }
306
307 static void gen_exception_cause(DisasContext *dc, uint32_t cause)
308 {
309 TCGv_i32 tpc = tcg_const_i32(dc->pc);
310 TCGv_i32 tcause = tcg_const_i32(cause);
311 gen_helper_exception_cause(cpu_env, tpc, tcause);
312 tcg_temp_free(tpc);
313 tcg_temp_free(tcause);
314 if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
315 cause == SYSCALL_CAUSE) {
316 dc->base.is_jmp = DISAS_NORETURN;
317 }
318 }
319
320 static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
321 TCGv_i32 vaddr)
322 {
323 TCGv_i32 tpc = tcg_const_i32(dc->pc);
324 TCGv_i32 tcause = tcg_const_i32(cause);
325 gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr);
326 tcg_temp_free(tpc);
327 tcg_temp_free(tcause);
328 }
329
330 static void gen_debug_exception(DisasContext *dc, uint32_t cause)
331 {
332 TCGv_i32 tpc = tcg_const_i32(dc->pc);
333 TCGv_i32 tcause = tcg_const_i32(cause);
334 gen_helper_debug_exception(cpu_env, tpc, tcause);
335 tcg_temp_free(tpc);
336 tcg_temp_free(tcause);
337 if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
338 dc->base.is_jmp = DISAS_NORETURN;
339 }
340 }
341
342 static bool gen_check_privilege(DisasContext *dc)
343 {
344 #ifndef CONFIG_USER_ONLY
345 if (!dc->cring) {
346 return true;
347 }
348 #endif
349 gen_exception_cause(dc, PRIVILEGED_CAUSE);
350 dc->base.is_jmp = DISAS_NORETURN;
351 return false;
352 }
353
354 static bool gen_check_cpenable(DisasContext *dc, uint32_t cp_mask)
355 {
356 cp_mask &= ~dc->cpenable;
357
358 if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) && cp_mask) {
359 gen_exception_cause(dc, COPROCESSOR0_DISABLED + ctz32(cp_mask));
360 dc->base.is_jmp = DISAS_NORETURN;
361 return false;
362 }
363 return true;
364 }
365
366 static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
367 {
368 tcg_gen_mov_i32(cpu_pc, dest);
369 if (dc->icount) {
370 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
371 }
372 if (dc->base.singlestep_enabled) {
373 gen_exception(dc, EXCP_DEBUG);
374 } else {
375 if (slot >= 0) {
376 tcg_gen_goto_tb(slot);
377 tcg_gen_exit_tb(dc->base.tb, slot);
378 } else {
379 tcg_gen_exit_tb(NULL, 0);
380 }
381 }
382 dc->base.is_jmp = DISAS_NORETURN;
383 }
384
385 static void gen_jump(DisasContext *dc, TCGv dest)
386 {
387 gen_jump_slot(dc, dest, -1);
388 }
389
390 static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
391 {
392 TCGv_i32 tmp = tcg_const_i32(dest);
393 if (((dc->base.pc_first ^ dest) & TARGET_PAGE_MASK) != 0) {
394 slot = -1;
395 }
396 gen_jump_slot(dc, tmp, slot);
397 tcg_temp_free(tmp);
398 }
399
400 static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
401 int slot)
402 {
403 TCGv_i32 tcallinc = tcg_const_i32(callinc);
404
405 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
406 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
407 tcg_temp_free(tcallinc);
408 tcg_gen_movi_i32(cpu_R[callinc << 2],
409 (callinc << 30) | (dc->base.pc_next & 0x3fffffff));
410 gen_jump_slot(dc, dest, slot);
411 }
412
413 static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
414 {
415 gen_callw_slot(dc, callinc, dest, -1);
416 }
417
418 static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
419 {
420 TCGv_i32 tmp = tcg_const_i32(dest);
421 if (((dc->base.pc_first ^ dest) & TARGET_PAGE_MASK) != 0) {
422 slot = -1;
423 }
424 gen_callw_slot(dc, callinc, tmp, slot);
425 tcg_temp_free(tmp);
426 }
427
428 static bool gen_check_loop_end(DisasContext *dc, int slot)
429 {
430 if (dc->base.pc_next == dc->lend) {
431 TCGLabel *label = gen_new_label();
432
433 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
434 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
435 if (dc->lbeg_off) {
436 gen_jumpi(dc, dc->base.pc_next - dc->lbeg_off, slot);
437 } else {
438 gen_jump(dc, cpu_SR[LBEG]);
439 }
440 gen_set_label(label);
441 gen_jumpi(dc, dc->base.pc_next, -1);
442 return true;
443 }
444 return false;
445 }
446
447 static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
448 {
449 if (!gen_check_loop_end(dc, slot)) {
450 gen_jumpi(dc, dc->base.pc_next, slot);
451 }
452 }
453
454 static void gen_brcond(DisasContext *dc, TCGCond cond,
455 TCGv_i32 t0, TCGv_i32 t1, uint32_t addr)
456 {
457 TCGLabel *label = gen_new_label();
458
459 tcg_gen_brcond_i32(cond, t0, t1, label);
460 gen_jumpi_check_loop_end(dc, 0);
461 gen_set_label(label);
462 gen_jumpi(dc, addr, 1);
463 }
464
465 static void gen_brcondi(DisasContext *dc, TCGCond cond,
466 TCGv_i32 t0, uint32_t t1, uint32_t addr)
467 {
468 TCGv_i32 tmp = tcg_const_i32(t1);
469 gen_brcond(dc, cond, t0, tmp, addr);
470 tcg_temp_free(tmp);
471 }
472
473 static bool check_sr(DisasContext *dc, uint32_t sr, unsigned access)
474 {
475 if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) {
476 if (sregnames[sr].name) {
477 qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not configured\n", sregnames[sr].name);
478 } else {
479 qemu_log_mask(LOG_UNIMP, "SR %d is not implemented\n", sr);
480 }
481 return false;
482 } else if (!(sregnames[sr].access & access)) {
483 static const char * const access_text[] = {
484 [SR_R] = "rsr",
485 [SR_W] = "wsr",
486 [SR_X] = "xsr",
487 };
488 assert(access < ARRAY_SIZE(access_text) && access_text[access]);
489 qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not available for %s\n", sregnames[sr].name,
490 access_text[access]);
491 return false;
492 }
493 return true;
494 }
495
496 #ifndef CONFIG_USER_ONLY
497 static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
498 {
499 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
500 gen_io_start();
501 }
502 gen_helper_update_ccount(cpu_env);
503 tcg_gen_mov_i32(d, cpu_SR[sr]);
504 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
505 gen_io_end();
506 }
507 }
508
509 static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
510 {
511 tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);
512 tcg_gen_or_i32(d, d, cpu_SR[sr]);
513 tcg_gen_andi_i32(d, d, 0xfffffffc);
514 }
515 #endif
516
517 static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
518 {
519 static void (* const rsr_handler[256])(DisasContext *dc,
520 TCGv_i32 d, uint32_t sr) = {
521 #ifndef CONFIG_USER_ONLY
522 [CCOUNT] = gen_rsr_ccount,
523 [INTSET] = gen_rsr_ccount,
524 [PTEVADDR] = gen_rsr_ptevaddr,
525 #endif
526 };
527
528 if (rsr_handler[sr]) {
529 rsr_handler[sr](dc, d, sr);
530 } else {
531 tcg_gen_mov_i32(d, cpu_SR[sr]);
532 }
533 }
534
535 static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
536 {
537 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
538 if (dc->sar_m32_5bit) {
539 tcg_gen_discard_i32(dc->sar_m32);
540 }
541 dc->sar_5bit = false;
542 dc->sar_m32_5bit = false;
543 }
544
545 static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)
546 {
547 tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);
548 }
549
550 static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
551 {
552 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
553 }
554
555 static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)
556 {
557 tcg_gen_ext8s_i32(cpu_SR[sr], s);
558 }
559
560 #ifndef CONFIG_USER_ONLY
561 static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
562 {
563 gen_helper_wsr_windowbase(cpu_env, v);
564 }
565
566 static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
567 {
568 tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1);
569 }
570
571 static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)
572 {
573 tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);
574 }
575
576 static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
577 {
578 gen_helper_wsr_rasid(cpu_env, v);
579 }
580
581 static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)
582 {
583 tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);
584 }
585
586 static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
587 {
588 gen_helper_wsr_ibreakenable(cpu_env, v);
589 }
590
591 static void gen_wsr_memctl(DisasContext *dc, uint32_t sr, TCGv_i32 v)
592 {
593 gen_helper_wsr_memctl(cpu_env, v);
594 }
595
596 static void gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v)
597 {
598 tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f);
599 }
600
601 static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
602 {
603 unsigned id = sr - IBREAKA;
604 TCGv_i32 tmp = tcg_const_i32(id);
605
606 assert(id < dc->config->nibreak);
607 gen_helper_wsr_ibreaka(cpu_env, tmp, v);
608 tcg_temp_free(tmp);
609 }
610
611 static void gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
612 {
613 unsigned id = sr - DBREAKA;
614 TCGv_i32 tmp = tcg_const_i32(id);
615
616 assert(id < dc->config->ndbreak);
617 gen_helper_wsr_dbreaka(cpu_env, tmp, v);
618 tcg_temp_free(tmp);
619 }
620
621 static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v)
622 {
623 unsigned id = sr - DBREAKC;
624 TCGv_i32 tmp = tcg_const_i32(id);
625
626 assert(id < dc->config->ndbreak);
627 gen_helper_wsr_dbreakc(cpu_env, tmp, v);
628 tcg_temp_free(tmp);
629 }
630
631 static void gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
632 {
633 tcg_gen_andi_i32(cpu_SR[sr], v, 0xff);
634 }
635
636 static void gen_check_interrupts(DisasContext *dc)
637 {
638 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
639 gen_io_start();
640 }
641 gen_helper_check_interrupts(cpu_env);
642 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
643 gen_io_end();
644 }
645 }
646
647 static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
648 {
649 tcg_gen_andi_i32(cpu_SR[sr], v,
650 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
651 }
652
653 static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
654 {
655 TCGv_i32 tmp = tcg_temp_new_i32();
656
657 tcg_gen_andi_i32(tmp, v,
658 dc->config->inttype_mask[INTTYPE_EDGE] |
659 dc->config->inttype_mask[INTTYPE_NMI] |
660 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
661 tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
662 tcg_temp_free(tmp);
663 }
664
665 static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
666 {
667 tcg_gen_mov_i32(cpu_SR[sr], v);
668 }
669
670 static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
671 {
672 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
673 PS_UM | PS_EXCM | PS_INTLEVEL;
674
675 if (option_enabled(dc, XTENSA_OPTION_MMU)) {
676 mask |= PS_RING;
677 }
678 tcg_gen_andi_i32(cpu_SR[sr], v, mask);
679 }
680
681 static void gen_wsr_ccount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
682 {
683 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
684 gen_io_start();
685 }
686 gen_helper_wsr_ccount(cpu_env, v);
687 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
688 gen_io_end();
689 }
690 }
691
692 static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
693 {
694 if (dc->icount) {
695 tcg_gen_mov_i32(dc->next_icount, v);
696 } else {
697 tcg_gen_mov_i32(cpu_SR[sr], v);
698 }
699 }
700
701 static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v)
702 {
703 tcg_gen_andi_i32(cpu_SR[sr], v, 0xf);
704 }
705
706 static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
707 {
708 uint32_t id = sr - CCOMPARE;
709 uint32_t int_bit = 1 << dc->config->timerint[id];
710 TCGv_i32 tmp = tcg_const_i32(id);
711
712 assert(id < dc->config->nccompare);
713 tcg_gen_mov_i32(cpu_SR[sr], v);
714 tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
715 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
716 gen_io_start();
717 }
718 gen_helper_update_ccompare(cpu_env, tmp);
719 tcg_temp_free(tmp);
720 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
721 gen_io_end();
722 }
723 }
724 #else
725 static void gen_check_interrupts(DisasContext *dc)
726 {
727 }
728 #endif
729
730 static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
731 {
732 static void (* const wsr_handler[256])(DisasContext *dc,
733 uint32_t sr, TCGv_i32 v) = {
734 [SAR] = gen_wsr_sar,
735 [BR] = gen_wsr_br,
736 [LITBASE] = gen_wsr_litbase,
737 [ACCHI] = gen_wsr_acchi,
738 #ifndef CONFIG_USER_ONLY
739 [WINDOW_BASE] = gen_wsr_windowbase,
740 [WINDOW_START] = gen_wsr_windowstart,
741 [PTEVADDR] = gen_wsr_ptevaddr,
742 [RASID] = gen_wsr_rasid,
743 [ITLBCFG] = gen_wsr_tlbcfg,
744 [DTLBCFG] = gen_wsr_tlbcfg,
745 [IBREAKENABLE] = gen_wsr_ibreakenable,
746 [MEMCTL] = gen_wsr_memctl,
747 [ATOMCTL] = gen_wsr_atomctl,
748 [IBREAKA] = gen_wsr_ibreaka,
749 [IBREAKA + 1] = gen_wsr_ibreaka,
750 [DBREAKA] = gen_wsr_dbreaka,
751 [DBREAKA + 1] = gen_wsr_dbreaka,
752 [DBREAKC] = gen_wsr_dbreakc,
753 [DBREAKC + 1] = gen_wsr_dbreakc,
754 [CPENABLE] = gen_wsr_cpenable,
755 [INTSET] = gen_wsr_intset,
756 [INTCLEAR] = gen_wsr_intclear,
757 [INTENABLE] = gen_wsr_intenable,
758 [PS] = gen_wsr_ps,
759 [CCOUNT] = gen_wsr_ccount,
760 [ICOUNT] = gen_wsr_icount,
761 [ICOUNTLEVEL] = gen_wsr_icountlevel,
762 [CCOMPARE] = gen_wsr_ccompare,
763 [CCOMPARE + 1] = gen_wsr_ccompare,
764 [CCOMPARE + 2] = gen_wsr_ccompare,
765 #endif
766 };
767
768 if (wsr_handler[sr]) {
769 wsr_handler[sr](dc, sr, s);
770 } else {
771 tcg_gen_mov_i32(cpu_SR[sr], s);
772 }
773 }
774
775 static void gen_wur(uint32_t ur, TCGv_i32 s)
776 {
777 switch (ur) {
778 case FCR:
779 gen_helper_wur_fcr(cpu_env, s);
780 break;
781
782 case FSR:
783 tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80);
784 break;
785
786 default:
787 tcg_gen_mov_i32(cpu_UR[ur], s);
788 break;
789 }
790 }
791
792 static void gen_load_store_alignment(DisasContext *dc, int shift,
793 TCGv_i32 addr, bool no_hw_alignment)
794 {
795 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
796 tcg_gen_andi_i32(addr, addr, ~0 << shift);
797 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
798 no_hw_alignment) {
799 TCGLabel *label = gen_new_label();
800 TCGv_i32 tmp = tcg_temp_new_i32();
801 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
802 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
803 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
804 gen_set_label(label);
805 tcg_temp_free(tmp);
806 }
807 }
808
809 #ifndef CONFIG_USER_ONLY
810 static void gen_waiti(DisasContext *dc, uint32_t imm4)
811 {
812 TCGv_i32 pc = tcg_const_i32(dc->base.pc_next);
813 TCGv_i32 intlevel = tcg_const_i32(imm4);
814
815 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
816 gen_io_start();
817 }
818 gen_helper_waiti(cpu_env, pc, intlevel);
819 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
820 gen_io_end();
821 }
822 tcg_temp_free(pc);
823 tcg_temp_free(intlevel);
824 }
825 #endif
826
827 static bool gen_window_check(DisasContext *dc, uint32_t mask)
828 {
829 unsigned r = 31 - clz32(mask);
830
831 if (r / 4 > dc->window) {
832 TCGv_i32 pc = tcg_const_i32(dc->pc);
833 TCGv_i32 w = tcg_const_i32(r / 4);
834
835 gen_helper_window_check(cpu_env, pc, w);
836 dc->base.is_jmp = DISAS_NORETURN;
837 return false;
838 }
839 return true;
840 }
841
842 static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
843 {
844 TCGv_i32 m = tcg_temp_new_i32();
845
846 if (hi) {
847 (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
848 } else {
849 (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
850 }
851 return m;
852 }
853
854 static void gen_zero_check(DisasContext *dc, const uint32_t arg[])
855 {
856 TCGLabel *label = gen_new_label();
857
858 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[2]], 0, label);
859 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
860 gen_set_label(label);
861 }
862
863 static inline unsigned xtensa_op0_insn_len(DisasContext *dc, uint8_t op0)
864 {
865 return xtensa_isa_length_from_chars(dc->config->isa, &op0);
866 }
867
868 static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
869 {
870 xtensa_isa isa = dc->config->isa;
871 unsigned char b[MAX_INSN_LENGTH] = {cpu_ldub_code(env, dc->pc)};
872 unsigned len = xtensa_op0_insn_len(dc, b[0]);
873 xtensa_format fmt;
874 int slot, slots;
875 unsigned i;
876 uint32_t op_flags = 0;
877 struct {
878 XtensaOpcodeOps *ops;
879 uint32_t arg[MAX_OPCODE_ARGS];
880 uint32_t raw_arg[MAX_OPCODE_ARGS];
881 } slot_prop[MAX_INSN_SLOTS];
882 uint32_t debug_cause = 0;
883 uint32_t windowed_register = 0;
884 uint32_t coprocessor = 0;
885
886 if (len == XTENSA_UNDEFINED) {
887 qemu_log_mask(LOG_GUEST_ERROR,
888 "unknown instruction length (pc = %08x)\n",
889 dc->pc);
890 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
891 return;
892 }
893
894 dc->base.pc_next = dc->pc + len;
895 for (i = 1; i < len; ++i) {
896 b[i] = cpu_ldub_code(env, dc->pc + i);
897 }
898 xtensa_insnbuf_from_chars(isa, dc->insnbuf, b, len);
899 fmt = xtensa_format_decode(isa, dc->insnbuf);
900 if (fmt == XTENSA_UNDEFINED) {
901 qemu_log_mask(LOG_GUEST_ERROR,
902 "unrecognized instruction format (pc = %08x)\n",
903 dc->pc);
904 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
905 return;
906 }
907 slots = xtensa_format_num_slots(isa, fmt);
908 for (slot = 0; slot < slots; ++slot) {
909 xtensa_opcode opc;
910 int opnd, vopnd, opnds;
911 uint32_t *raw_arg = slot_prop[slot].raw_arg;
912 uint32_t *arg = slot_prop[slot].arg;
913 XtensaOpcodeOps *ops;
914
915 dc->raw_arg = raw_arg;
916
917 xtensa_format_get_slot(isa, fmt, slot, dc->insnbuf, dc->slotbuf);
918 opc = xtensa_opcode_decode(isa, fmt, slot, dc->slotbuf);
919 if (opc == XTENSA_UNDEFINED) {
920 qemu_log_mask(LOG_GUEST_ERROR,
921 "unrecognized opcode in slot %d (pc = %08x)\n",
922 slot, dc->pc);
923 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
924 return;
925 }
926 opnds = xtensa_opcode_num_operands(isa, opc);
927
928 for (opnd = vopnd = 0; opnd < opnds; ++opnd) {
929 if (xtensa_operand_is_visible(isa, opc, opnd)) {
930 uint32_t v;
931
932 xtensa_operand_get_field(isa, opc, opnd, fmt, slot,
933 dc->slotbuf, &v);
934 xtensa_operand_decode(isa, opc, opnd, &v);
935 raw_arg[vopnd] = v;
936 if (xtensa_operand_is_PCrelative(isa, opc, opnd)) {
937 xtensa_operand_undo_reloc(isa, opc, opnd, &v, dc->pc);
938 }
939 arg[vopnd] = v;
940 ++vopnd;
941 }
942 }
943 ops = dc->config->opcode_ops[opc];
944 slot_prop[slot].ops = ops;
945
946 if (ops) {
947 op_flags |= ops->op_flags;
948 } else {
949 qemu_log_mask(LOG_UNIMP,
950 "unimplemented opcode '%s' in slot %d (pc = %08x)\n",
951 xtensa_opcode_name(isa, opc), slot, dc->pc);
952 op_flags |= XTENSA_OP_ILL;
953 }
954 if ((op_flags & XTENSA_OP_ILL) ||
955 (ops && ops->test_ill && ops->test_ill(dc, arg, ops->par))) {
956 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
957 return;
958 }
959 if (ops->op_flags & XTENSA_OP_DEBUG_BREAK) {
960 debug_cause |= ops->par[0];
961 }
962 if (ops->test_overflow) {
963 windowed_register |= ops->test_overflow(dc, arg, ops->par);
964 }
965 if (ops->windowed_register_op) {
966 uint32_t reg_opnd = ops->windowed_register_op;
967
968 while (reg_opnd) {
969 unsigned i = ctz32(reg_opnd);
970
971 windowed_register |= 1 << arg[i];
972 reg_opnd ^= 1 << i;
973 }
974 }
975 coprocessor |= ops->coprocessor;
976 }
977
978 if ((op_flags & XTENSA_OP_PRIVILEGED) &&
979 !gen_check_privilege(dc)) {
980 return;
981 }
982
983 if (op_flags & XTENSA_OP_SYSCALL) {
984 gen_exception_cause(dc, SYSCALL_CAUSE);
985 return;
986 }
987
988 if ((op_flags & XTENSA_OP_DEBUG_BREAK) && dc->debug) {
989 gen_debug_exception(dc, debug_cause);
990 return;
991 }
992
993 if (windowed_register && !gen_window_check(dc, windowed_register)) {
994 return;
995 }
996
997 if (op_flags & XTENSA_OP_UNDERFLOW) {
998 TCGv_i32 tmp = tcg_const_i32(dc->pc);
999
1000 gen_helper_test_underflow_retw(cpu_env, tmp);
1001 tcg_temp_free(tmp);
1002 }
1003
1004 if (op_flags & XTENSA_OP_ALLOCA) {
1005 TCGv_i32 tmp = tcg_const_i32(dc->pc);
1006
1007 gen_helper_movsp(cpu_env, tmp);
1008 tcg_temp_free(tmp);
1009 }
1010
1011 if (coprocessor && !gen_check_cpenable(dc, coprocessor)) {
1012 return;
1013 }
1014
1015 if (op_flags & XTENSA_OP_DIVIDE_BY_ZERO) {
1016 for (slot = 0; slot < slots; ++slot) {
1017 if (slot_prop[slot].ops->op_flags & XTENSA_OP_DIVIDE_BY_ZERO) {
1018 gen_zero_check(dc, slot_prop[slot].arg);
1019 }
1020 }
1021 }
1022
1023 for (slot = 0; slot < slots; ++slot) {
1024 XtensaOpcodeOps *ops = slot_prop[slot].ops;
1025
1026 dc->raw_arg = slot_prop[slot].raw_arg;
1027 ops->translate(dc, slot_prop[slot].arg, ops->par);
1028 }
1029
1030 if (dc->base.is_jmp == DISAS_NEXT) {
1031 if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) {
1032 gen_check_interrupts(dc);
1033 }
1034
1035 if (op_flags & XTENSA_OP_EXIT_TB_M1) {
1036 /* Change in mmu index, memory mapping or tb->flags; exit tb */
1037 gen_jumpi_check_loop_end(dc, -1);
1038 } else if (op_flags & XTENSA_OP_EXIT_TB_0) {
1039 gen_jumpi_check_loop_end(dc, 0);
1040 }
1041 }
1042
1043 if (dc->base.is_jmp == DISAS_NEXT) {
1044 gen_check_loop_end(dc, 0);
1045 }
1046 dc->pc = dc->base.pc_next;
1047 }
1048
1049 static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc)
1050 {
1051 uint8_t b0 = cpu_ldub_code(env, dc->pc);
1052 return xtensa_op0_insn_len(dc, b0);
1053 }
1054
1055 static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
1056 {
1057 unsigned i;
1058
1059 for (i = 0; i < dc->config->nibreak; ++i) {
1060 if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
1061 env->sregs[IBREAKA + i] == dc->pc) {
1062 gen_debug_exception(dc, DEBUGCAUSE_IB);
1063 break;
1064 }
1065 }
1066 }
1067
1068 static void xtensa_tr_init_disas_context(DisasContextBase *dcbase,
1069 CPUState *cpu)
1070 {
1071 DisasContext *dc = container_of(dcbase, DisasContext, base);
1072 CPUXtensaState *env = cpu->env_ptr;
1073 uint32_t tb_flags = dc->base.tb->flags;
1074
1075 dc->config = env->config;
1076 dc->pc = dc->base.pc_first;
1077 dc->ring = tb_flags & XTENSA_TBFLAG_RING_MASK;
1078 dc->cring = (tb_flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring;
1079 dc->lbeg_off = (dc->base.tb->cs_base & XTENSA_CSBASE_LBEG_OFF_MASK) >>
1080 XTENSA_CSBASE_LBEG_OFF_SHIFT;
1081 dc->lend = (dc->base.tb->cs_base & XTENSA_CSBASE_LEND_MASK) +
1082 (dc->base.pc_first & TARGET_PAGE_MASK);
1083 dc->debug = tb_flags & XTENSA_TBFLAG_DEBUG;
1084 dc->icount = tb_flags & XTENSA_TBFLAG_ICOUNT;
1085 dc->cpenable = (tb_flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
1086 XTENSA_TBFLAG_CPENABLE_SHIFT;
1087 dc->window = ((tb_flags & XTENSA_TBFLAG_WINDOW_MASK) >>
1088 XTENSA_TBFLAG_WINDOW_SHIFT);
1089 dc->cwoe = tb_flags & XTENSA_TBFLAG_CWOE;
1090 dc->callinc = ((tb_flags & XTENSA_TBFLAG_CALLINC_MASK) >>
1091 XTENSA_TBFLAG_CALLINC_SHIFT);
1092
1093 if (dc->config->isa) {
1094 dc->insnbuf = xtensa_insnbuf_alloc(dc->config->isa);
1095 dc->slotbuf = xtensa_insnbuf_alloc(dc->config->isa);
1096 }
1097 init_sar_tracker(dc);
1098 }
1099
1100 static void xtensa_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
1101 {
1102 DisasContext *dc = container_of(dcbase, DisasContext, base);
1103
1104 if (dc->icount) {
1105 dc->next_icount = tcg_temp_local_new_i32();
1106 }
1107 }
1108
1109 static void xtensa_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
1110 {
1111 tcg_gen_insn_start(dcbase->pc_next);
1112 }
1113
1114 static bool xtensa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
1115 const CPUBreakpoint *bp)
1116 {
1117 DisasContext *dc = container_of(dcbase, DisasContext, base);
1118
1119 tcg_gen_movi_i32(cpu_pc, dc->base.pc_next);
1120 gen_exception(dc, EXCP_DEBUG);
1121 dc->base.is_jmp = DISAS_NORETURN;
1122 /* The address covered by the breakpoint must be included in
1123 [tb->pc, tb->pc + tb->size) in order to for it to be
1124 properly cleared -- thus we increment the PC here so that
1125 the logic setting tb->size below does the right thing. */
1126 dc->base.pc_next += 2;
1127 return true;
1128 }
1129
1130 static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
1131 {
1132 DisasContext *dc = container_of(dcbase, DisasContext, base);
1133 CPUXtensaState *env = cpu->env_ptr;
1134 target_ulong page_start;
1135
1136 /* These two conditions only apply to the first insn in the TB,
1137 but this is the first TranslateOps hook that allows exiting. */
1138 if ((tb_cflags(dc->base.tb) & CF_USE_ICOUNT)
1139 && (dc->base.tb->flags & XTENSA_TBFLAG_YIELD)) {
1140 gen_exception(dc, EXCP_YIELD);
1141 dc->base.is_jmp = DISAS_NORETURN;
1142 return;
1143 }
1144 if (dc->base.tb->flags & XTENSA_TBFLAG_EXCEPTION) {
1145 gen_exception(dc, EXCP_DEBUG);
1146 dc->base.is_jmp = DISAS_NORETURN;
1147 return;
1148 }
1149
1150 if (dc->icount) {
1151 TCGLabel *label = gen_new_label();
1152
1153 tcg_gen_addi_i32(dc->next_icount, cpu_SR[ICOUNT], 1);
1154 tcg_gen_brcondi_i32(TCG_COND_NE, dc->next_icount, 0, label);
1155 tcg_gen_mov_i32(dc->next_icount, cpu_SR[ICOUNT]);
1156 if (dc->debug) {
1157 gen_debug_exception(dc, DEBUGCAUSE_IC);
1158 }
1159 gen_set_label(label);
1160 }
1161
1162 if (dc->debug) {
1163 gen_ibreak_check(env, dc);
1164 }
1165
1166 disas_xtensa_insn(env, dc);
1167
1168 if (dc->icount) {
1169 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
1170 }
1171
1172 /* End the TB if the next insn will cross into the next page. */
1173 page_start = dc->base.pc_first & TARGET_PAGE_MASK;
1174 if (dc->base.is_jmp == DISAS_NEXT &&
1175 (dc->pc - page_start >= TARGET_PAGE_SIZE ||
1176 dc->pc - page_start + xtensa_insn_len(env, dc) > TARGET_PAGE_SIZE)) {
1177 dc->base.is_jmp = DISAS_TOO_MANY;
1178 }
1179 }
1180
1181 static void xtensa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
1182 {
1183 DisasContext *dc = container_of(dcbase, DisasContext, base);
1184
1185 reset_sar_tracker(dc);
1186 if (dc->config->isa) {
1187 xtensa_insnbuf_free(dc->config->isa, dc->insnbuf);
1188 xtensa_insnbuf_free(dc->config->isa, dc->slotbuf);
1189 }
1190 if (dc->icount) {
1191 tcg_temp_free(dc->next_icount);
1192 }
1193
1194 switch (dc->base.is_jmp) {
1195 case DISAS_NORETURN:
1196 break;
1197 case DISAS_TOO_MANY:
1198 if (dc->base.singlestep_enabled) {
1199 tcg_gen_movi_i32(cpu_pc, dc->pc);
1200 gen_exception(dc, EXCP_DEBUG);
1201 } else {
1202 gen_jumpi(dc, dc->pc, 0);
1203 }
1204 break;
1205 default:
1206 g_assert_not_reached();
1207 }
1208 }
1209
1210 static void xtensa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
1211 {
1212 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
1213 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
1214 }
1215
1216 static const TranslatorOps xtensa_translator_ops = {
1217 .init_disas_context = xtensa_tr_init_disas_context,
1218 .tb_start = xtensa_tr_tb_start,
1219 .insn_start = xtensa_tr_insn_start,
1220 .breakpoint_check = xtensa_tr_breakpoint_check,
1221 .translate_insn = xtensa_tr_translate_insn,
1222 .tb_stop = xtensa_tr_tb_stop,
1223 .disas_log = xtensa_tr_disas_log,
1224 };
1225
1226 void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
1227 {
1228 DisasContext dc = {};
1229 translator_loop(&xtensa_translator_ops, &dc.base, cpu, tb);
1230 }
1231
1232 void xtensa_cpu_dump_state(CPUState *cs, FILE *f,
1233 fprintf_function cpu_fprintf, int flags)
1234 {
1235 XtensaCPU *cpu = XTENSA_CPU(cs);
1236 CPUXtensaState *env = &cpu->env;
1237 int i, j;
1238
1239 cpu_fprintf(f, "PC=%08x\n\n", env->pc);
1240
1241 for (i = j = 0; i < 256; ++i) {
1242 if (xtensa_option_bits_enabled(env->config, sregnames[i].opt_bits)) {
1243 cpu_fprintf(f, "%12s=%08x%c", sregnames[i].name, env->sregs[i],
1244 (j++ % 4) == 3 ? '\n' : ' ');
1245 }
1246 }
1247
1248 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
1249
1250 for (i = j = 0; i < 256; ++i) {
1251 if (xtensa_option_bits_enabled(env->config, uregnames[i].opt_bits)) {
1252 cpu_fprintf(f, "%s=%08x%c", uregnames[i].name, env->uregs[i],
1253 (j++ % 4) == 3 ? '\n' : ' ');
1254 }
1255 }
1256
1257 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
1258
1259 for (i = 0; i < 16; ++i) {
1260 cpu_fprintf(f, " A%02d=%08x%c", i, env->regs[i],
1261 (i % 4) == 3 ? '\n' : ' ');
1262 }
1263
1264 xtensa_sync_phys_from_window(env);
1265 cpu_fprintf(f, "\n");
1266
1267 for (i = 0; i < env->config->nareg; ++i) {
1268 cpu_fprintf(f, "AR%02d=%08x ", i, env->phys_regs[i]);
1269 if (i % 4 == 3) {
1270 bool ws = (env->sregs[WINDOW_START] & (1 << (i / 4))) != 0;
1271 bool cw = env->sregs[WINDOW_BASE] == i / 4;
1272
1273 cpu_fprintf(f, "%c%c\n", ws ? '<' : ' ', cw ? '=' : ' ');
1274 }
1275 }
1276
1277 if ((flags & CPU_DUMP_FPU) &&
1278 xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
1279 cpu_fprintf(f, "\n");
1280
1281 for (i = 0; i < 16; ++i) {
1282 cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i,
1283 float32_val(env->fregs[i].f32[FP_F32_LOW]),
1284 *(float *)(env->fregs[i].f32 + FP_F32_LOW),
1285 (i % 2) == 1 ? '\n' : ' ');
1286 }
1287 }
1288 }
1289
1290 void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb,
1291 target_ulong *data)
1292 {
1293 env->pc = data[0];
1294 }
1295
1296 static int compare_opcode_ops(const void *a, const void *b)
1297 {
1298 return strcmp((const char *)a,
1299 ((const XtensaOpcodeOps *)b)->name);
1300 }
1301
1302 XtensaOpcodeOps *
1303 xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t,
1304 const char *name)
1305 {
1306 return bsearch(name, t->opcode, t->num_opcodes,
1307 sizeof(XtensaOpcodeOps), compare_opcode_ops);
1308 }
1309
1310 static void translate_abs(DisasContext *dc, const uint32_t arg[],
1311 const uint32_t par[])
1312 {
1313 TCGv_i32 zero = tcg_const_i32(0);
1314 TCGv_i32 neg = tcg_temp_new_i32();
1315
1316 tcg_gen_neg_i32(neg, cpu_R[arg[1]]);
1317 tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[arg[0]],
1318 cpu_R[arg[1]], zero, cpu_R[arg[1]], neg);
1319 tcg_temp_free(neg);
1320 tcg_temp_free(zero);
1321 }
1322
1323 static void translate_add(DisasContext *dc, const uint32_t arg[],
1324 const uint32_t par[])
1325 {
1326 tcg_gen_add_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
1327 }
1328
1329 static void translate_addi(DisasContext *dc, const uint32_t arg[],
1330 const uint32_t par[])
1331 {
1332 tcg_gen_addi_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]);
1333 }
1334
1335 static void translate_addx(DisasContext *dc, const uint32_t arg[],
1336 const uint32_t par[])
1337 {
1338 TCGv_i32 tmp = tcg_temp_new_i32();
1339 tcg_gen_shli_i32(tmp, cpu_R[arg[1]], par[0]);
1340 tcg_gen_add_i32(cpu_R[arg[0]], tmp, cpu_R[arg[2]]);
1341 tcg_temp_free(tmp);
1342 }
1343
1344 static void translate_all(DisasContext *dc, const uint32_t arg[],
1345 const uint32_t par[])
1346 {
1347 uint32_t shift = par[1];
1348 TCGv_i32 mask = tcg_const_i32(((1 << shift) - 1) << arg[1]);
1349 TCGv_i32 tmp = tcg_temp_new_i32();
1350
1351 tcg_gen_and_i32(tmp, cpu_SR[BR], mask);
1352 if (par[0]) {
1353 tcg_gen_addi_i32(tmp, tmp, 1 << arg[1]);
1354 } else {
1355 tcg_gen_add_i32(tmp, tmp, mask);
1356 }
1357 tcg_gen_shri_i32(tmp, tmp, arg[1] + shift);
1358 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR],
1359 tmp, arg[0], 1);
1360 tcg_temp_free(mask);
1361 tcg_temp_free(tmp);
1362 }
1363
1364 static void translate_and(DisasContext *dc, const uint32_t arg[],
1365 const uint32_t par[])
1366 {
1367 tcg_gen_and_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
1368 }
1369
1370 static void translate_ball(DisasContext *dc, const uint32_t arg[],
1371 const uint32_t par[])
1372 {
1373 TCGv_i32 tmp = tcg_temp_new_i32();
1374 tcg_gen_and_i32(tmp, cpu_R[arg[0]], cpu_R[arg[1]]);
1375 gen_brcond(dc, par[0], tmp, cpu_R[arg[1]], arg[2]);
1376 tcg_temp_free(tmp);
1377 }
1378
1379 static void translate_bany(DisasContext *dc, const uint32_t arg[],
1380 const uint32_t par[])
1381 {
1382 TCGv_i32 tmp = tcg_temp_new_i32();
1383 tcg_gen_and_i32(tmp, cpu_R[arg[0]], cpu_R[arg[1]]);
1384 gen_brcondi(dc, par[0], tmp, 0, arg[2]);
1385 tcg_temp_free(tmp);
1386 }
1387
1388 static void translate_b(DisasContext *dc, const uint32_t arg[],
1389 const uint32_t par[])
1390 {
1391 gen_brcond(dc, par[0], cpu_R[arg[0]], cpu_R[arg[1]], arg[2]);
1392 }
1393
1394 static void translate_bb(DisasContext *dc, const uint32_t arg[],
1395 const uint32_t par[])
1396 {
1397 #ifdef TARGET_WORDS_BIGENDIAN
1398 TCGv_i32 bit = tcg_const_i32(0x80000000u);
1399 #else
1400 TCGv_i32 bit = tcg_const_i32(0x00000001u);
1401 #endif
1402 TCGv_i32 tmp = tcg_temp_new_i32();
1403 tcg_gen_andi_i32(tmp, cpu_R[arg[1]], 0x1f);
1404 #ifdef TARGET_WORDS_BIGENDIAN
1405 tcg_gen_shr_i32(bit, bit, tmp);
1406 #else
1407 tcg_gen_shl_i32(bit, bit, tmp);
1408 #endif
1409 tcg_gen_and_i32(tmp, cpu_R[arg[0]], bit);
1410 gen_brcondi(dc, par[0], tmp, 0, arg[2]);
1411 tcg_temp_free(tmp);
1412 tcg_temp_free(bit);
1413 }
1414
1415 static void translate_bbi(DisasContext *dc, const uint32_t arg[],
1416 const uint32_t par[])
1417 {
1418 TCGv_i32 tmp = tcg_temp_new_i32();
1419 #ifdef TARGET_WORDS_BIGENDIAN
1420 tcg_gen_andi_i32(tmp, cpu_R[arg[0]], 0x80000000u >> arg[1]);
1421 #else
1422 tcg_gen_andi_i32(tmp, cpu_R[arg[0]], 0x00000001u << arg[1]);
1423 #endif
1424 gen_brcondi(dc, par[0], tmp, 0, arg[2]);
1425 tcg_temp_free(tmp);
1426 }
1427
1428 static void translate_bi(DisasContext *dc, const uint32_t arg[],
1429 const uint32_t par[])
1430 {
1431 gen_brcondi(dc, par[0], cpu_R[arg[0]], arg[1], arg[2]);
1432 }
1433
1434 static void translate_bz(DisasContext *dc, const uint32_t arg[],
1435 const uint32_t par[])
1436 {
1437 gen_brcondi(dc, par[0], cpu_R[arg[0]], 0, arg[1]);
1438 }
1439
1440 enum {
1441 BOOLEAN_AND,
1442 BOOLEAN_ANDC,
1443 BOOLEAN_OR,
1444 BOOLEAN_ORC,
1445 BOOLEAN_XOR,
1446 };
1447
1448 static void translate_boolean(DisasContext *dc, const uint32_t arg[],
1449 const uint32_t par[])
1450 {
1451 static void (* const op[])(TCGv_i32, TCGv_i32, TCGv_i32) = {
1452 [BOOLEAN_AND] = tcg_gen_and_i32,
1453 [BOOLEAN_ANDC] = tcg_gen_andc_i32,
1454 [BOOLEAN_OR] = tcg_gen_or_i32,
1455 [BOOLEAN_ORC] = tcg_gen_orc_i32,
1456 [BOOLEAN_XOR] = tcg_gen_xor_i32,
1457 };
1458
1459 TCGv_i32 tmp1 = tcg_temp_new_i32();
1460 TCGv_i32 tmp2 = tcg_temp_new_i32();
1461
1462 tcg_gen_shri_i32(tmp1, cpu_SR[BR], arg[1]);
1463 tcg_gen_shri_i32(tmp2, cpu_SR[BR], arg[2]);
1464 op[par[0]](tmp1, tmp1, tmp2);
1465 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, arg[0], 1);
1466 tcg_temp_free(tmp1);
1467 tcg_temp_free(tmp2);
1468 }
1469
1470 static void translate_bp(DisasContext *dc, const uint32_t arg[],
1471 const uint32_t par[])
1472 {
1473 TCGv_i32 tmp = tcg_temp_new_i32();
1474
1475 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[0]);
1476 gen_brcondi(dc, par[0], tmp, 0, arg[1]);
1477 tcg_temp_free(tmp);
1478 }
1479
1480 static void translate_call0(DisasContext *dc, const uint32_t arg[],
1481 const uint32_t par[])
1482 {
1483 tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next);
1484 gen_jumpi(dc, arg[0], 0);
1485 }
1486
1487 static uint32_t test_overflow_callw(DisasContext *dc, const uint32_t arg[],
1488 const uint32_t par[])
1489 {
1490 return 1 << (par[0] * 4);
1491 }
1492
1493 static void translate_callw(DisasContext *dc, const uint32_t arg[],
1494 const uint32_t par[])
1495 {
1496 gen_callwi(dc, par[0], arg[0], 0);
1497 }
1498
1499 static void translate_callx0(DisasContext *dc, const uint32_t arg[],
1500 const uint32_t par[])
1501 {
1502 TCGv_i32 tmp = tcg_temp_new_i32();
1503 tcg_gen_mov_i32(tmp, cpu_R[arg[0]]);
1504 tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next);
1505 gen_jump(dc, tmp);
1506 tcg_temp_free(tmp);
1507 }
1508
1509 static void translate_callxw(DisasContext *dc, const uint32_t arg[],
1510 const uint32_t par[])
1511 {
1512 TCGv_i32 tmp = tcg_temp_new_i32();
1513
1514 tcg_gen_mov_i32(tmp, cpu_R[arg[0]]);
1515 gen_callw(dc, par[0], tmp);
1516 tcg_temp_free(tmp);
1517 }
1518
1519 static void translate_clamps(DisasContext *dc, const uint32_t arg[],
1520 const uint32_t par[])
1521 {
1522 TCGv_i32 tmp1 = tcg_const_i32(-1u << arg[2]);
1523 TCGv_i32 tmp2 = tcg_const_i32((1 << arg[2]) - 1);
1524
1525 tcg_gen_smax_i32(tmp1, tmp1, cpu_R[arg[1]]);
1526 tcg_gen_smin_i32(cpu_R[arg[0]], tmp1, tmp2);
1527 tcg_temp_free(tmp1);
1528 tcg_temp_free(tmp2);
1529 }
1530
1531 static void translate_clrb_expstate(DisasContext *dc, const uint32_t arg[],
1532 const uint32_t par[])
1533 {
1534 /* TODO: GPIO32 may be a part of coprocessor */
1535 tcg_gen_andi_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], ~(1u << arg[0]));
1536 }
1537
1538 static void translate_const16(DisasContext *dc, const uint32_t arg[],
1539 const uint32_t par[])
1540 {
1541 TCGv_i32 c = tcg_const_i32(arg[1]);
1542
1543 tcg_gen_deposit_i32(cpu_R[arg[0]], c, cpu_R[arg[0]], 16, 16);
1544 tcg_temp_free(c);
1545 }
1546
1547 static void translate_dcache(DisasContext *dc, const uint32_t arg[],
1548 const uint32_t par[])
1549 {
1550 TCGv_i32 addr = tcg_temp_new_i32();
1551 TCGv_i32 res = tcg_temp_new_i32();
1552
1553 tcg_gen_addi_i32(addr, cpu_R[arg[0]], arg[1]);
1554 tcg_gen_qemu_ld8u(res, addr, dc->cring);
1555 tcg_temp_free(addr);
1556 tcg_temp_free(res);
1557 }
1558
1559 static void translate_depbits(DisasContext *dc, const uint32_t arg[],
1560 const uint32_t par[])
1561 {
1562 tcg_gen_deposit_i32(cpu_R[arg[1]], cpu_R[arg[1]], cpu_R[arg[0]],
1563 arg[2], arg[3]);
1564 }
1565
1566 static bool test_ill_entry(DisasContext *dc, const uint32_t arg[],
1567 const uint32_t par[])
1568 {
1569 if (arg[0] > 3 || !dc->cwoe) {
1570 qemu_log_mask(LOG_GUEST_ERROR,
1571 "Illegal entry instruction(pc = %08x)\n", dc->pc);
1572 return true;
1573 } else {
1574 return false;
1575 }
1576 }
1577
1578 static uint32_t test_overflow_entry(DisasContext *dc, const uint32_t arg[],
1579 const uint32_t par[])
1580 {
1581 return 1 << (dc->callinc * 4);
1582 }
1583
1584 static void translate_entry(DisasContext *dc, const uint32_t arg[],
1585 const uint32_t par[])
1586 {
1587 TCGv_i32 pc = tcg_const_i32(dc->pc);
1588 TCGv_i32 s = tcg_const_i32(arg[0]);
1589 TCGv_i32 imm = tcg_const_i32(arg[1]);
1590 gen_helper_entry(cpu_env, pc, s, imm);
1591 tcg_temp_free(imm);
1592 tcg_temp_free(s);
1593 tcg_temp_free(pc);
1594 }
1595
1596 static void translate_extui(DisasContext *dc, const uint32_t arg[],
1597 const uint32_t par[])
1598 {
1599 int maskimm = (1 << arg[3]) - 1;
1600
1601 TCGv_i32 tmp = tcg_temp_new_i32();
1602 tcg_gen_shri_i32(tmp, cpu_R[arg[1]], arg[2]);
1603 tcg_gen_andi_i32(cpu_R[arg[0]], tmp, maskimm);
1604 tcg_temp_free(tmp);
1605 }
1606
1607 static void translate_icache(DisasContext *dc, const uint32_t arg[],
1608 const uint32_t par[])
1609 {
1610 #ifndef CONFIG_USER_ONLY
1611 TCGv_i32 addr = tcg_temp_new_i32();
1612
1613 tcg_gen_movi_i32(cpu_pc, dc->pc);
1614 tcg_gen_addi_i32(addr, cpu_R[arg[0]], arg[1]);
1615 gen_helper_itlb_hit_test(cpu_env, addr);
1616 tcg_temp_free(addr);
1617 #endif
1618 }
1619
1620 static void translate_itlb(DisasContext *dc, const uint32_t arg[],
1621 const uint32_t par[])
1622 {
1623 #ifndef CONFIG_USER_ONLY
1624 TCGv_i32 dtlb = tcg_const_i32(par[0]);
1625
1626 gen_helper_itlb(cpu_env, cpu_R[arg[0]], dtlb);
1627 tcg_temp_free(dtlb);
1628 #endif
1629 }
1630
1631 static void translate_j(DisasContext *dc, const uint32_t arg[],
1632 const uint32_t par[])
1633 {
1634 gen_jumpi(dc, arg[0], 0);
1635 }
1636
1637 static void translate_jx(DisasContext *dc, const uint32_t arg[],
1638 const uint32_t par[])
1639 {
1640 gen_jump(dc, cpu_R[arg[0]]);
1641 }
1642
1643 static void translate_l32e(DisasContext *dc, const uint32_t arg[],
1644 const uint32_t par[])
1645 {
1646 TCGv_i32 addr = tcg_temp_new_i32();
1647
1648 tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]);
1649 gen_load_store_alignment(dc, 2, addr, false);
1650 tcg_gen_qemu_ld_tl(cpu_R[arg[0]], addr, dc->ring, MO_TEUL);
1651 tcg_temp_free(addr);
1652 }
1653
1654 static void translate_ldst(DisasContext *dc, const uint32_t arg[],
1655 const uint32_t par[])
1656 {
1657 TCGv_i32 addr = tcg_temp_new_i32();
1658
1659 tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]);
1660 if (par[0] & MO_SIZE) {
1661 gen_load_store_alignment(dc, par[0] & MO_SIZE, addr, par[1]);
1662 }
1663 if (par[2]) {
1664 if (par[1]) {
1665 tcg_gen_mb(TCG_BAR_STRL | TCG_MO_ALL);
1666 }
1667 tcg_gen_qemu_st_tl(cpu_R[arg[0]], addr, dc->cring, par[0]);
1668 } else {
1669 tcg_gen_qemu_ld_tl(cpu_R[arg[0]], addr, dc->cring, par[0]);
1670 if (par[1]) {
1671 tcg_gen_mb(TCG_BAR_LDAQ | TCG_MO_ALL);
1672 }
1673 }
1674 tcg_temp_free(addr);
1675 }
1676
1677 static void translate_l32r(DisasContext *dc, const uint32_t arg[],
1678 const uint32_t par[])
1679 {
1680 TCGv_i32 tmp;
1681
1682 if (dc->base.tb->flags & XTENSA_TBFLAG_LITBASE) {
1683 tmp = tcg_const_i32(dc->raw_arg[1] - 1);
1684 tcg_gen_add_i32(tmp, cpu_SR[LITBASE], tmp);
1685 } else {
1686 tmp = tcg_const_i32(arg[1]);
1687 }
1688 tcg_gen_qemu_ld32u(cpu_R[arg[0]], tmp, dc->cring);
1689 tcg_temp_free(tmp);
1690 }
1691
1692 static void translate_loop(DisasContext *dc, const uint32_t arg[],
1693 const uint32_t par[])
1694 {
1695 uint32_t lend = arg[1];
1696
1697 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[arg[0]], 1);
1698 tcg_gen_movi_i32(cpu_SR[LBEG], dc->base.pc_next);
1699 tcg_gen_movi_i32(cpu_SR[LEND], lend);
1700
1701 if (par[0] != TCG_COND_NEVER) {
1702 TCGLabel *label = gen_new_label();
1703 tcg_gen_brcondi_i32(par[0], cpu_R[arg[0]], 0, label);
1704 gen_jumpi(dc, lend, 1);
1705 gen_set_label(label);
1706 }
1707
1708 gen_jumpi(dc, dc->base.pc_next, 0);
1709 }
1710
1711 enum {
1712 MAC16_UMUL,
1713 MAC16_MUL,
1714 MAC16_MULA,
1715 MAC16_MULS,
1716 MAC16_NONE,
1717 };
1718
1719 enum {
1720 MAC16_LL,
1721 MAC16_HL,
1722 MAC16_LH,
1723 MAC16_HH,
1724
1725 MAC16_HX = 0x1,
1726 MAC16_XH = 0x2,
1727 };
1728
1729 enum {
1730 MAC16_AA,
1731 MAC16_AD,
1732 MAC16_DA,
1733 MAC16_DD,
1734
1735 MAC16_XD = 0x1,
1736 MAC16_DX = 0x2,
1737 };
1738
1739 static void translate_mac16(DisasContext *dc, const uint32_t arg[],
1740 const uint32_t par[])
1741 {
1742 int op = par[0];
1743 bool is_m1_sr = par[1] & MAC16_DX;
1744 bool is_m2_sr = par[1] & MAC16_XD;
1745 unsigned half = par[2];
1746 uint32_t ld_offset = par[3];
1747 unsigned off = ld_offset ? 2 : 0;
1748 TCGv_i32 vaddr = tcg_temp_new_i32();
1749 TCGv_i32 mem32 = tcg_temp_new_i32();
1750
1751 if (ld_offset) {
1752 tcg_gen_addi_i32(vaddr, cpu_R[arg[1]], ld_offset);
1753 gen_load_store_alignment(dc, 2, vaddr, false);
1754 tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
1755 }
1756 if (op != MAC16_NONE) {
1757 TCGv_i32 m1 = gen_mac16_m(is_m1_sr ?
1758 cpu_SR[MR + arg[off]] :
1759 cpu_R[arg[off]],
1760 half & MAC16_HX, op == MAC16_UMUL);
1761 TCGv_i32 m2 = gen_mac16_m(is_m2_sr ?
1762 cpu_SR[MR + arg[off + 1]] :
1763 cpu_R[arg[off + 1]],
1764 half & MAC16_XH, op == MAC16_UMUL);
1765
1766 if (op == MAC16_MUL || op == MAC16_UMUL) {
1767 tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
1768 if (op == MAC16_UMUL) {
1769 tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
1770 } else {
1771 tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
1772 }
1773 } else {
1774 TCGv_i32 lo = tcg_temp_new_i32();
1775 TCGv_i32 hi = tcg_temp_new_i32();
1776
1777 tcg_gen_mul_i32(lo, m1, m2);
1778 tcg_gen_sari_i32(hi, lo, 31);
1779 if (op == MAC16_MULA) {
1780 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
1781 cpu_SR[ACCLO], cpu_SR[ACCHI],
1782 lo, hi);
1783 } else {
1784 tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
1785 cpu_SR[ACCLO], cpu_SR[ACCHI],
1786 lo, hi);
1787 }
1788 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
1789
1790 tcg_temp_free_i32(lo);
1791 tcg_temp_free_i32(hi);
1792 }
1793 tcg_temp_free(m1);
1794 tcg_temp_free(m2);
1795 }
1796 if (ld_offset) {
1797 tcg_gen_mov_i32(cpu_R[arg[1]], vaddr);
1798 tcg_gen_mov_i32(cpu_SR[MR + arg[0]], mem32);
1799 }
1800 tcg_temp_free(vaddr);
1801 tcg_temp_free(mem32);
1802 }
1803
1804 static void translate_memw(DisasContext *dc, const uint32_t arg[],
1805 const uint32_t par[])
1806 {
1807 tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);
1808 }
1809
1810 static void translate_smin(DisasContext *dc, const uint32_t arg[],
1811 const uint32_t par[])
1812 {
1813 tcg_gen_smin_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
1814 }
1815
1816 static void translate_umin(DisasContext *dc, const uint32_t arg[],
1817 const uint32_t par[])
1818 {
1819 tcg_gen_umin_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
1820 }
1821
1822 static void translate_smax(DisasContext *dc, const uint32_t arg[],
1823 const uint32_t par[])
1824 {
1825 tcg_gen_smax_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
1826 }
1827
1828 static void translate_umax(DisasContext *dc, const uint32_t arg[],
1829 const uint32_t par[])
1830 {
1831 tcg_gen_umax_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
1832 }
1833
1834 static void translate_mov(DisasContext *dc, const uint32_t arg[],
1835 const uint32_t par[])
1836 {
1837 tcg_gen_mov_i32(cpu_R[arg[0]], cpu_R[arg[1]]);
1838 }
1839
1840 static void translate_movcond(DisasContext *dc, const uint32_t arg[],
1841 const uint32_t par[])
1842 {
1843 TCGv_i32 zero = tcg_const_i32(0);
1844
1845 tcg_gen_movcond_i32(par[0], cpu_R[arg[0]],
1846 cpu_R[arg[2]], zero, cpu_R[arg[1]], cpu_R[arg[0]]);
1847 tcg_temp_free(zero);
1848 }
1849
1850 static void translate_movi(DisasContext *dc, const uint32_t arg[],
1851 const uint32_t par[])
1852 {
1853 tcg_gen_movi_i32(cpu_R[arg[0]], arg[1]);
1854 }
1855
1856 static void translate_movp(DisasContext *dc, const uint32_t arg[],
1857 const uint32_t par[])
1858 {
1859 TCGv_i32 zero = tcg_const_i32(0);
1860 TCGv_i32 tmp = tcg_temp_new_i32();
1861
1862 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2]);
1863 tcg_gen_movcond_i32(par[0],
1864 cpu_R[arg[0]], tmp, zero,
1865 cpu_R[arg[1]], cpu_R[arg[0]]);
1866 tcg_temp_free(tmp);
1867 tcg_temp_free(zero);
1868 }
1869
1870 static void translate_movsp(DisasContext *dc, const uint32_t arg[],
1871 const uint32_t par[])
1872 {
1873 tcg_gen_mov_i32(cpu_R[arg[0]], cpu_R[arg[1]]);
1874 }
1875
1876 static void translate_mul16(DisasContext *dc, const uint32_t arg[],
1877 const uint32_t par[])
1878 {
1879 TCGv_i32 v1 = tcg_temp_new_i32();
1880 TCGv_i32 v2 = tcg_temp_new_i32();
1881
1882 if (par[0]) {
1883 tcg_gen_ext16s_i32(v1, cpu_R[arg[1]]);
1884 tcg_gen_ext16s_i32(v2, cpu_R[arg[2]]);
1885 } else {
1886 tcg_gen_ext16u_i32(v1, cpu_R[arg[1]]);
1887 tcg_gen_ext16u_i32(v2, cpu_R[arg[2]]);
1888 }
1889 tcg_gen_mul_i32(cpu_R[arg[0]], v1, v2);
1890 tcg_temp_free(v2);
1891 tcg_temp_free(v1);
1892 }
1893
1894 static void translate_mull(DisasContext *dc, const uint32_t arg[],
1895 const uint32_t par[])
1896 {
1897 tcg_gen_mul_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
1898 }
1899
1900 static void translate_mulh(DisasContext *dc, const uint32_t arg[],
1901 const uint32_t par[])
1902 {
1903 TCGv_i32 lo = tcg_temp_new();
1904
1905 if (par[0]) {
1906 tcg_gen_muls2_i32(lo, cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
1907 } else {
1908 tcg_gen_mulu2_i32(lo, cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
1909 }
1910 tcg_temp_free(lo);
1911 }
1912
1913 static void translate_neg(DisasContext *dc, const uint32_t arg[],
1914 const uint32_t par[])
1915 {
1916 tcg_gen_neg_i32(cpu_R[arg[0]], cpu_R[arg[1]]);
1917 }
1918
1919 static void translate_nop(DisasContext *dc, const uint32_t arg[],
1920 const uint32_t par[])
1921 {
1922 }
1923
1924 static void translate_nsa(DisasContext *dc, const uint32_t arg[],
1925 const uint32_t par[])
1926 {
1927 tcg_gen_clrsb_i32(cpu_R[arg[0]], cpu_R[arg[1]]);
1928 }
1929
1930 static void translate_nsau(DisasContext *dc, const uint32_t arg[],
1931 const uint32_t par[])
1932 {
1933 tcg_gen_clzi_i32(cpu_R[arg[0]], cpu_R[arg[1]], 32);
1934 }
1935
1936 static void translate_or(DisasContext *dc, const uint32_t arg[],
1937 const uint32_t par[])
1938 {
1939 tcg_gen_or_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
1940 }
1941
1942 static void translate_ptlb(DisasContext *dc, const uint32_t arg[],
1943 const uint32_t par[])
1944 {
1945 #ifndef CONFIG_USER_ONLY
1946 TCGv_i32 dtlb = tcg_const_i32(par[0]);
1947
1948 tcg_gen_movi_i32(cpu_pc, dc->pc);
1949 gen_helper_ptlb(cpu_R[arg[0]], cpu_env, cpu_R[arg[1]], dtlb);
1950 tcg_temp_free(dtlb);
1951 #endif
1952 }
1953
1954 static void translate_quos(DisasContext *dc, const uint32_t arg[],
1955 const uint32_t par[])
1956 {
1957 TCGLabel *label1 = gen_new_label();
1958 TCGLabel *label2 = gen_new_label();
1959
1960 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[1]], 0x80000000,
1961 label1);
1962 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[2]], 0xffffffff,
1963 label1);
1964 tcg_gen_movi_i32(cpu_R[arg[0]],
1965 par[0] ? 0x80000000 : 0);
1966 tcg_gen_br(label2);
1967 gen_set_label(label1);
1968 if (par[0]) {
1969 tcg_gen_div_i32(cpu_R[arg[0]],
1970 cpu_R[arg[1]], cpu_R[arg[2]]);
1971 } else {
1972 tcg_gen_rem_i32(cpu_R[arg[0]],
1973 cpu_R[arg[1]], cpu_R[arg[2]]);
1974 }
1975 gen_set_label(label2);
1976 }
1977
1978 static void translate_quou(DisasContext *dc, const uint32_t arg[],
1979 const uint32_t par[])
1980 {
1981 tcg_gen_divu_i32(cpu_R[arg[0]],
1982 cpu_R[arg[1]], cpu_R[arg[2]]);
1983 }
1984
1985 static void translate_read_impwire(DisasContext *dc, const uint32_t arg[],
1986 const uint32_t par[])
1987 {
1988 /* TODO: GPIO32 may be a part of coprocessor */
1989 tcg_gen_movi_i32(cpu_R[arg[0]], 0);
1990 }
1991
1992 static void translate_remu(DisasContext *dc, const uint32_t arg[],
1993 const uint32_t par[])
1994 {
1995 tcg_gen_remu_i32(cpu_R[arg[0]],
1996 cpu_R[arg[1]], cpu_R[arg[2]]);
1997 }
1998
1999 static void translate_rer(DisasContext *dc, const uint32_t arg[],
2000 const uint32_t par[])
2001 {
2002 gen_helper_rer(cpu_R[arg[0]], cpu_env, cpu_R[arg[1]]);
2003 }
2004
2005 static void translate_ret(DisasContext *dc, const uint32_t arg[],
2006 const uint32_t par[])
2007 {
2008 gen_jump(dc, cpu_R[0]);
2009 }
2010
2011 static bool test_ill_retw(DisasContext *dc, const uint32_t arg[],
2012 const uint32_t par[])
2013 {
2014 if (!dc->cwoe) {
2015 qemu_log_mask(LOG_GUEST_ERROR,
2016 "Illegal retw instruction(pc = %08x)\n", dc->pc);
2017 return true;
2018 } else {
2019 TCGv_i32 tmp = tcg_const_i32(dc->pc);
2020
2021 gen_helper_test_ill_retw(cpu_env, tmp);
2022 tcg_temp_free(tmp);
2023 return false;
2024 }
2025 }
2026
2027 static void translate_retw(DisasContext *dc, const uint32_t arg[],
2028 const uint32_t par[])
2029 {
2030 TCGv_i32 tmp = tcg_const_i32(dc->pc);
2031 gen_helper_retw(tmp, cpu_env, tmp);
2032 gen_jump(dc, tmp);
2033 tcg_temp_free(tmp);
2034 }
2035
2036 static void translate_rfde(DisasContext *dc, const uint32_t arg[],
2037 const uint32_t par[])
2038 {
2039 gen_jump(dc, cpu_SR[dc->config->ndepc ? DEPC : EPC1]);
2040 }
2041
2042 static void translate_rfe(DisasContext *dc, const uint32_t arg[],
2043 const uint32_t par[])
2044 {
2045 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
2046 gen_jump(dc, cpu_SR[EPC1]);
2047 }
2048
2049 static void translate_rfi(DisasContext *dc, const uint32_t arg[],
2050 const uint32_t par[])
2051 {
2052 tcg_gen_mov_i32(cpu_SR[PS], cpu_SR[EPS2 + arg[0] - 2]);
2053 gen_jump(dc, cpu_SR[EPC1 + arg[0] - 1]);
2054 }
2055
2056 static void translate_rfw(DisasContext *dc, const uint32_t arg[],
2057 const uint32_t par[])
2058 {
2059 TCGv_i32 tmp = tcg_const_i32(1);
2060
2061 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
2062 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
2063
2064 if (par[0]) {
2065 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
2066 cpu_SR[WINDOW_START], tmp);
2067 } else {
2068 tcg_gen_or_i32(cpu_SR[WINDOW_START],
2069 cpu_SR[WINDOW_START], tmp);
2070 }
2071
2072 tcg_temp_free(tmp);
2073 gen_helper_restore_owb(cpu_env);
2074 gen_jump(dc, cpu_SR[EPC1]);
2075 }
2076
2077 static void translate_rotw(DisasContext *dc, const uint32_t arg[],
2078 const uint32_t par[])
2079 {
2080 TCGv_i32 tmp = tcg_const_i32(arg[0]);
2081 gen_helper_rotw(cpu_env, tmp);
2082 tcg_temp_free(tmp);
2083 }
2084
2085 static void translate_rsil(DisasContext *dc, const uint32_t arg[],
2086 const uint32_t par[])
2087 {
2088 tcg_gen_mov_i32(cpu_R[arg[0]], cpu_SR[PS]);
2089 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
2090 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], arg[1]);
2091 }
2092
2093 static bool test_ill_rsr(DisasContext *dc, const uint32_t arg[],
2094 const uint32_t par[])
2095 {
2096 return !check_sr(dc, par[0], SR_R);
2097 }
2098
2099 static void translate_rsr(DisasContext *dc, const uint32_t arg[],
2100 const uint32_t par[])
2101 {
2102 gen_rsr(dc, cpu_R[arg[0]], par[0]);
2103 }
2104
2105 static void translate_rtlb(DisasContext *dc, const uint32_t arg[],
2106 const uint32_t par[])
2107 {
2108 #ifndef CONFIG_USER_ONLY
2109 static void (* const helper[])(TCGv_i32 r, TCGv_env env, TCGv_i32 a1,
2110 TCGv_i32 a2) = {
2111 gen_helper_rtlb0,
2112 gen_helper_rtlb1,
2113 };
2114 TCGv_i32 dtlb = tcg_const_i32(par[0]);
2115
2116 helper[par[1]](cpu_R[arg[0]], cpu_env, cpu_R[arg[1]], dtlb);
2117 tcg_temp_free(dtlb);
2118 #endif
2119 }
2120
2121 static void translate_rur(DisasContext *dc, const uint32_t arg[],
2122 const uint32_t par[])
2123 {
2124 if (uregnames[par[0]].name) {
2125 tcg_gen_mov_i32(cpu_R[arg[0]], cpu_UR[par[0]]);
2126 } else {
2127 qemu_log_mask(LOG_UNIMP, "RUR %d not implemented\n", par[0]);
2128 }
2129 }
2130
2131 static void translate_setb_expstate(DisasContext *dc, const uint32_t arg[],
2132 const uint32_t par[])
2133 {
2134 /* TODO: GPIO32 may be a part of coprocessor */
2135 tcg_gen_ori_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], 1u << arg[0]);
2136 }
2137
2138 #ifdef CONFIG_USER_ONLY
2139 static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr)
2140 {
2141 }
2142 #else
2143 static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr)
2144 {
2145 TCGv_i32 tpc = tcg_const_i32(dc->pc);
2146
2147 gen_helper_check_atomctl(cpu_env, tpc, addr);
2148 tcg_temp_free(tpc);
2149 }
2150 #endif
2151
2152 static void translate_s32c1i(DisasContext *dc, const uint32_t arg[],
2153 const uint32_t par[])
2154 {
2155 TCGv_i32 tmp = tcg_temp_local_new_i32();
2156 TCGv_i32 addr = tcg_temp_local_new_i32();
2157
2158 tcg_gen_mov_i32(tmp, cpu_R[arg[0]]);
2159 tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]);
2160 gen_load_store_alignment(dc, 2, addr, true);
2161 gen_check_atomctl(dc, addr);
2162 tcg_gen_atomic_cmpxchg_i32(cpu_R[arg[0]], addr, cpu_SR[SCOMPARE1],
2163 tmp, dc->cring, MO_TEUL);
2164 tcg_temp_free(addr);
2165 tcg_temp_free(tmp);
2166 }
2167
2168 static void translate_s32e(DisasContext *dc, const uint32_t arg[],
2169 const uint32_t par[])
2170 {
2171 TCGv_i32 addr = tcg_temp_new_i32();
2172
2173 tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]);
2174 gen_load_store_alignment(dc, 2, addr, false);
2175 tcg_gen_qemu_st_tl(cpu_R[arg[0]], addr, dc->ring, MO_TEUL);
2176 tcg_temp_free(addr);
2177 }
2178
2179 static void translate_salt(DisasContext *dc, const uint32_t arg[],
2180 const uint32_t par[])
2181 {
2182 tcg_gen_setcond_i32(par[0],
2183 cpu_R[arg[0]],
2184 cpu_R[arg[1]], cpu_R[arg[2]]);
2185 }
2186
2187 static void translate_sext(DisasContext *dc, const uint32_t arg[],
2188 const uint32_t par[])
2189 {
2190 int shift = 31 - arg[2];
2191
2192 if (shift == 24) {
2193 tcg_gen_ext8s_i32(cpu_R[arg[0]], cpu_R[arg[1]]);
2194 } else if (shift == 16) {
2195 tcg_gen_ext16s_i32(cpu_R[arg[0]], cpu_R[arg[1]]);
2196 } else {
2197 TCGv_i32 tmp = tcg_temp_new_i32();
2198 tcg_gen_shli_i32(tmp, cpu_R[arg[1]], shift);
2199 tcg_gen_sari_i32(cpu_R[arg[0]], tmp, shift);
2200 tcg_temp_free(tmp);
2201 }
2202 }
2203
2204 static bool test_ill_simcall(DisasContext *dc, const uint32_t arg[],
2205 const uint32_t par[])
2206 {
2207 #ifdef CONFIG_USER_ONLY
2208 bool ill = true;
2209 #else
2210 bool ill = !semihosting_enabled();
2211 #endif
2212 if (ill) {
2213 qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n");
2214 }
2215 return ill;
2216 }
2217
2218 static void translate_simcall(DisasContext *dc, const uint32_t arg[],
2219 const uint32_t par[])
2220 {
2221 #ifndef CONFIG_USER_ONLY
2222 gen_helper_simcall(cpu_env);
2223 #endif
2224 }
2225
2226 /*
2227 * Note: 64 bit ops are used here solely because SAR values
2228 * have range 0..63
2229 */
2230 #define gen_shift_reg(cmd, reg) do { \
2231 TCGv_i64 tmp = tcg_temp_new_i64(); \
2232 tcg_gen_extu_i32_i64(tmp, reg); \
2233 tcg_gen_##cmd##_i64(v, v, tmp); \
2234 tcg_gen_extrl_i64_i32(cpu_R[arg[0]], v); \
2235 tcg_temp_free_i64(v); \
2236 tcg_temp_free_i64(tmp); \
2237 } while (0)
2238
2239 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
2240
2241 static void translate_sll(DisasContext *dc, const uint32_t arg[],
2242 const uint32_t par[])
2243 {
2244 if (dc->sar_m32_5bit) {
2245 tcg_gen_shl_i32(cpu_R[arg[0]], cpu_R[arg[1]], dc->sar_m32);
2246 } else {
2247 TCGv_i64 v = tcg_temp_new_i64();
2248 TCGv_i32 s = tcg_const_i32(32);
2249 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
2250 tcg_gen_andi_i32(s, s, 0x3f);
2251 tcg_gen_extu_i32_i64(v, cpu_R[arg[1]]);
2252 gen_shift_reg(shl, s);
2253 tcg_temp_free(s);
2254 }
2255 }
2256
2257 static void translate_slli(DisasContext *dc, const uint32_t arg[],
2258 const uint32_t par[])
2259 {
2260 if (arg[2] == 32) {
2261 qemu_log_mask(LOG_GUEST_ERROR, "slli a%d, a%d, 32 is undefined\n",
2262 arg[0], arg[1]);
2263 }
2264 tcg_gen_shli_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2] & 0x1f);
2265 }
2266
2267 static void translate_sra(DisasContext *dc, const uint32_t arg[],
2268 const uint32_t par[])
2269 {
2270 if (dc->sar_m32_5bit) {
2271 tcg_gen_sar_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_SR[SAR]);
2272 } else {
2273 TCGv_i64 v = tcg_temp_new_i64();
2274 tcg_gen_ext_i32_i64(v, cpu_R[arg[1]]);
2275 gen_shift(sar);
2276 }
2277 }
2278
2279 static void translate_srai(DisasContext *dc, const uint32_t arg[],
2280 const uint32_t par[])
2281 {
2282 tcg_gen_sari_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]);
2283 }
2284
2285 static void translate_src(DisasContext *dc, const uint32_t arg[],
2286 const uint32_t par[])
2287 {
2288 TCGv_i64 v = tcg_temp_new_i64();
2289 tcg_gen_concat_i32_i64(v, cpu_R[arg[2]], cpu_R[arg[1]]);
2290 gen_shift(shr);
2291 }
2292
2293 static void translate_srl(DisasContext *dc, const uint32_t arg[],
2294 const uint32_t par[])
2295 {
2296 if (dc->sar_m32_5bit) {
2297 tcg_gen_shr_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_SR[SAR]);
2298 } else {
2299 TCGv_i64 v = tcg_temp_new_i64();
2300 tcg_gen_extu_i32_i64(v, cpu_R[arg[1]]);
2301 gen_shift(shr);
2302 }
2303 }
2304
2305 #undef gen_shift
2306 #undef gen_shift_reg
2307
2308 static void translate_srli(DisasContext *dc, const uint32_t arg[],
2309 const uint32_t par[])
2310 {
2311 tcg_gen_shri_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]);
2312 }
2313
2314 static void translate_ssa8b(DisasContext *dc, const uint32_t arg[],
2315 const uint32_t par[])
2316 {
2317 TCGv_i32 tmp = tcg_temp_new_i32();
2318 tcg_gen_shli_i32(tmp, cpu_R[arg[0]], 3);
2319 gen_left_shift_sar(dc, tmp);
2320 tcg_temp_free(tmp);
2321 }
2322
2323 static void translate_ssa8l(DisasContext *dc, const uint32_t arg[],
2324 const uint32_t par[])
2325 {
2326 TCGv_i32 tmp = tcg_temp_new_i32();
2327 tcg_gen_shli_i32(tmp, cpu_R[arg[0]], 3);
2328 gen_right_shift_sar(dc, tmp);
2329 tcg_temp_free(tmp);
2330 }
2331
2332 static void translate_ssai(DisasContext *dc, const uint32_t arg[],
2333 const uint32_t par[])
2334 {
2335 TCGv_i32 tmp = tcg_const_i32(arg[0]);
2336 gen_right_shift_sar(dc, tmp);
2337 tcg_temp_free(tmp);
2338 }
2339
2340 static void translate_ssl(DisasContext *dc, const uint32_t arg[],
2341 const uint32_t par[])
2342 {
2343 gen_left_shift_sar(dc, cpu_R[arg[0]]);
2344 }
2345
2346 static void translate_ssr(DisasContext *dc, const uint32_t arg[],
2347 const uint32_t par[])
2348 {
2349 gen_right_shift_sar(dc, cpu_R[arg[0]]);
2350 }
2351
2352 static void translate_sub(DisasContext *dc, const uint32_t arg[],
2353 const uint32_t par[])
2354 {
2355 tcg_gen_sub_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
2356 }
2357
2358 static void translate_subx(DisasContext *dc, const uint32_t arg[],
2359 const uint32_t par[])
2360 {
2361 TCGv_i32 tmp = tcg_temp_new_i32();
2362 tcg_gen_shli_i32(tmp, cpu_R[arg[1]], par[0]);
2363 tcg_gen_sub_i32(cpu_R[arg[0]], tmp, cpu_R[arg[2]]);
2364 tcg_temp_free(tmp);
2365 }
2366
2367 static void translate_waiti(DisasContext *dc, const uint32_t arg[],
2368 const uint32_t par[])
2369 {
2370 #ifndef CONFIG_USER_ONLY
2371 gen_waiti(dc, arg[0]);
2372 #endif
2373 }
2374
2375 static void translate_wtlb(DisasContext *dc, const uint32_t arg[],
2376 const uint32_t par[])
2377 {
2378 #ifndef CONFIG_USER_ONLY
2379 TCGv_i32 dtlb = tcg_const_i32(par[0]);
2380
2381 gen_helper_wtlb(cpu_env, cpu_R[arg[0]], cpu_R[arg[1]], dtlb);
2382 tcg_temp_free(dtlb);
2383 #endif
2384 }
2385
2386 static void translate_wer(DisasContext *dc, const uint32_t arg[],
2387 const uint32_t par[])
2388 {
2389 gen_helper_wer(cpu_env, cpu_R[arg[0]], cpu_R[arg[1]]);
2390 }
2391
2392 static void translate_wrmsk_expstate(DisasContext *dc, const uint32_t arg[],
2393 const uint32_t par[])
2394 {
2395 /* TODO: GPIO32 may be a part of coprocessor */
2396 tcg_gen_and_i32(cpu_UR[EXPSTATE], cpu_R[arg[0]], cpu_R[arg[1]]);
2397 }
2398
2399 static bool test_ill_wsr(DisasContext *dc, const uint32_t arg[],
2400 const uint32_t par[])
2401 {
2402 return !check_sr(dc, par[0], SR_W);
2403 }
2404
2405 static void translate_wsr(DisasContext *dc, const uint32_t arg[],
2406 const uint32_t par[])
2407 {
2408 gen_wsr(dc, par[0], cpu_R[arg[0]]);
2409 }
2410
2411 static void translate_wur(DisasContext *dc, const uint32_t arg[],
2412 const uint32_t par[])
2413 {
2414 if (uregnames[par[0]].name) {
2415 gen_wur(par[0], cpu_R[arg[0]]);
2416 } else {
2417 qemu_log_mask(LOG_UNIMP, "WUR %d not implemented\n", par[0]);
2418 }
2419 }
2420
2421 static void translate_xor(DisasContext *dc, const uint32_t arg[],
2422 const uint32_t par[])
2423 {
2424 tcg_gen_xor_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
2425 }
2426
2427 static bool test_ill_xsr(DisasContext *dc, const uint32_t arg[],
2428 const uint32_t par[])
2429 {
2430 return !check_sr(dc, par[0], SR_X);
2431 }
2432
2433 static void translate_xsr(DisasContext *dc, const uint32_t arg[],
2434 const uint32_t par[])
2435 {
2436 TCGv_i32 tmp = tcg_temp_new_i32();
2437
2438 tcg_gen_mov_i32(tmp, cpu_R[arg[0]]);
2439 gen_rsr(dc, cpu_R[arg[0]], par[0]);
2440 gen_wsr(dc, par[0], tmp);
2441 tcg_temp_free(tmp);
2442 }
2443
2444 static const XtensaOpcodeOps core_ops[] = {
2445 {
2446 .name = "abs",
2447 .translate = translate_abs,
2448 .windowed_register_op = 0x3,
2449 }, {
2450 .name = "add",
2451 .translate = translate_add,
2452 .windowed_register_op = 0x7,
2453 }, {
2454 .name = "add.n",
2455 .translate = translate_add,
2456 .windowed_register_op = 0x7,
2457 }, {
2458 .name = "addi",
2459 .translate = translate_addi,
2460 .windowed_register_op = 0x3,
2461 }, {
2462 .name = "addi.n",
2463 .translate = translate_addi,
2464 .windowed_register_op = 0x3,
2465 }, {
2466 .name = "addmi",
2467 .translate = translate_addi,
2468 .windowed_register_op = 0x3,
2469 }, {
2470 .name = "addx2",
2471 .translate = translate_addx,
2472 .par = (const uint32_t[]){1},
2473 .windowed_register_op = 0x7,
2474 }, {
2475 .name = "addx4",
2476 .translate = translate_addx,
2477 .par = (const uint32_t[]){2},
2478 .windowed_register_op = 0x7,
2479 }, {
2480 .name = "addx8",
2481 .translate = translate_addx,
2482 .par = (const uint32_t[]){3},
2483 .windowed_register_op = 0x7,
2484 }, {
2485 .name = "all4",
2486 .translate = translate_all,
2487 .par = (const uint32_t[]){true, 4},
2488 }, {
2489 .name = "all8",
2490 .translate = translate_all,
2491 .par = (const uint32_t[]){true, 8},
2492 }, {
2493 .name = "and",
2494 .translate = translate_and,
2495 .windowed_register_op = 0x7,
2496 }, {
2497 .name = "andb",
2498 .translate = translate_boolean,
2499 .par = (const uint32_t[]){BOOLEAN_AND},
2500 }, {
2501 .name = "andbc",
2502 .translate = translate_boolean,
2503 .par = (const uint32_t[]){BOOLEAN_ANDC},
2504 }, {
2505 .name = "any4",
2506 .translate = translate_all,
2507 .par = (const uint32_t[]){false, 4},
2508 }, {
2509 .name = "any8",
2510 .translate = translate_all,
2511 .par = (const uint32_t[]){false, 8},
2512 }, {
2513 .name = "ball",
2514 .translate = translate_ball,
2515 .par = (const uint32_t[]){TCG_COND_EQ},
2516 .windowed_register_op = 0x3,
2517 }, {
2518 .name = "bany",
2519 .translate = translate_bany,
2520 .par = (const uint32_t[]){TCG_COND_NE},
2521 .windowed_register_op = 0x3,
2522 }, {
2523 .name = "bbc",
2524 .translate = translate_bb,
2525 .par = (const uint32_t[]){TCG_COND_EQ},
2526 .windowed_register_op = 0x3,
2527 }, {
2528 .name = "bbci",
2529 .translate = translate_bbi,
2530 .par = (const uint32_t[]){TCG_COND_EQ},
2531 .windowed_register_op = 0x1,
2532 }, {
2533 .name = "bbs",
2534 .translate = translate_bb,
2535 .par = (const uint32_t[]){TCG_COND_NE},
2536 .windowed_register_op = 0x3,
2537 }, {
2538 .name = "bbsi",
2539 .translate = translate_bbi,
2540 .par = (const uint32_t[]){TCG_COND_NE},
2541 .windowed_register_op = 0x1,
2542 }, {
2543 .name = "beq",
2544 .translate = translate_b,
2545 .par = (const uint32_t[]){TCG_COND_EQ},
2546 .windowed_register_op = 0x3,
2547 }, {
2548 .name = "beqi",
2549 .translate = translate_bi,
2550 .par = (const uint32_t[]){TCG_COND_EQ},
2551 .windowed_register_op = 0x1,
2552 }, {
2553 .name = "beqz",
2554 .translate = translate_bz,
2555 .par = (const uint32_t[]){TCG_COND_EQ},
2556 .windowed_register_op = 0x1,
2557 }, {
2558 .name = "beqz.n",
2559 .translate = translate_bz,
2560 .par = (const uint32_t[]){TCG_COND_EQ},
2561 .windowed_register_op = 0x1,
2562 }, {
2563 .name = "bf",
2564 .translate = translate_bp,
2565 .par = (const uint32_t[]){TCG_COND_EQ},
2566 }, {
2567 .name = "bge",
2568 .translate = translate_b,
2569 .par = (const uint32_t[]){TCG_COND_GE},
2570 .windowed_register_op = 0x3,
2571 }, {
2572 .name = "bgei",
2573 .translate = translate_bi,
2574 .par = (const uint32_t[]){TCG_COND_GE},
2575 .windowed_register_op = 0x1,
2576 }, {
2577 .name = "bgeu",
2578 .translate = translate_b,
2579 .par = (const uint32_t[]){TCG_COND_GEU},
2580 .windowed_register_op = 0x3,
2581 }, {
2582 .name = "bgeui",
2583 .translate = translate_bi,
2584 .par = (const uint32_t[]){TCG_COND_GEU},
2585 .windowed_register_op = 0x1,
2586 }, {
2587 .name = "bgez",
2588 .translate = translate_bz,
2589 .par = (const uint32_t[]){TCG_COND_GE},
2590 .windowed_register_op = 0x1,
2591 }, {
2592 .name = "blt",
2593 .translate = translate_b,
2594 .par = (const uint32_t[]){TCG_COND_LT},
2595 .windowed_register_op = 0x3,
2596 }, {
2597 .name = "blti",
2598 .translate = translate_bi,
2599 .par = (const uint32_t[]){TCG_COND_LT},
2600 .windowed_register_op = 0x1,
2601 }, {
2602 .name = "bltu",
2603 .translate = translate_b,
2604 .par = (const uint32_t[]){TCG_COND_LTU},
2605 .windowed_register_op = 0x3,
2606 }, {
2607 .name = "bltui",
2608 .translate = translate_bi,
2609 .par = (const uint32_t[]){TCG_COND_LTU},
2610 .windowed_register_op = 0x1,
2611 }, {
2612 .name = "bltz",
2613 .translate = translate_bz,
2614 .par = (const uint32_t[]){TCG_COND_LT},
2615 .windowed_register_op = 0x1,
2616 }, {
2617 .name = "bnall",
2618 .translate = translate_ball,
2619 .par = (const uint32_t[]){TCG_COND_NE},
2620 .windowed_register_op = 0x3,
2621 }, {
2622 .name = "bne",
2623 .translate = translate_b,
2624 .par = (const uint32_t[]){TCG_COND_NE},
2625 .windowed_register_op = 0x3,
2626 }, {
2627 .name = "bnei",
2628 .translate = translate_bi,
2629 .par = (const uint32_t[]){TCG_COND_NE},
2630 .windowed_register_op = 0x1,
2631 }, {
2632 .name = "bnez",
2633 .translate = translate_bz,
2634 .par = (const uint32_t[]){TCG_COND_NE},
2635 .windowed_register_op = 0x1,
2636 }, {
2637 .name = "bnez.n",
2638 .translate = translate_bz,
2639 .par = (const uint32_t[]){TCG_COND_NE},
2640 .windowed_register_op = 0x1,
2641 }, {
2642 .name = "bnone",
2643 .translate = translate_bany,
2644 .par = (const uint32_t[]){TCG_COND_EQ},
2645 .windowed_register_op = 0x3,
2646 }, {
2647 .name = "break",
2648 .translate = translate_nop,
2649 .par = (const uint32_t[]){DEBUGCAUSE_BI},
2650 .op_flags = XTENSA_OP_DEBUG_BREAK,
2651 }, {
2652 .name = "break.n",
2653 .translate = translate_nop,
2654 .par = (const uint32_t[]){DEBUGCAUSE_BN},
2655 .op_flags = XTENSA_OP_DEBUG_BREAK,
2656 }, {
2657 .name = "bt",
2658 .translate = translate_bp,
2659 .par = (const uint32_t[]){TCG_COND_NE},
2660 }, {
2661 .name = "call0",
2662 .translate = translate_call0,
2663 }, {
2664 .name = "call12",
2665 .translate = translate_callw,
2666 .test_overflow = test_overflow_callw,
2667 .par = (const uint32_t[]){3},
2668 }, {
2669 .name = "call4",
2670 .translate = translate_callw,
2671 .test_overflow = test_overflow_callw,
2672 .par = (const uint32_t[]){1},
2673 }, {
2674 .name = "call8",
2675 .translate = translate_callw,
2676 .test_overflow = test_overflow_callw,
2677 .par = (const uint32_t[]){2},
2678 }, {
2679 .name = "callx0",
2680 .translate = translate_callx0,
2681 .windowed_register_op = 0x1,
2682 }, {
2683 .name = "callx12",
2684 .translate = translate_callxw,
2685 .test_overflow = test_overflow_callw,
2686 .par = (const uint32_t[]){3},
2687 .windowed_register_op = 0x1,
2688 }, {
2689 .name = "callx4",
2690 .translate = translate_callxw,
2691 .test_overflow = test_overflow_callw,
2692 .par = (const uint32_t[]){1},
2693 .windowed_register_op = 0x1,
2694 }, {
2695 .name = "callx8",
2696 .translate = translate_callxw,
2697 .test_overflow = test_overflow_callw,
2698 .par = (const uint32_t[]){2},
2699 .windowed_register_op = 0x1,
2700 }, {
2701 .name = "clamps",
2702 .translate = translate_clamps,
2703 .windowed_register_op = 0x3,
2704 }, {
2705 .name = "clrb_expstate",
2706 .translate = translate_clrb_expstate,
2707 }, {
2708 .name = "const16",
2709 .translate = translate_const16,
2710 .windowed_register_op = 0x1,
2711 }, {
2712 .name = "depbits",
2713 .translate = translate_depbits,
2714 .windowed_register_op = 0x3,
2715 }, {
2716 .name = "dhi",
2717 .translate = translate_dcache,
2718 .op_flags = XTENSA_OP_PRIVILEGED,
2719 .windowed_register_op = 0x1,
2720 }, {
2721 .name = "dhu",
2722 .translate = translate_dcache,
2723 .op_flags = XTENSA_OP_PRIVILEGED,
2724 .windowed_register_op = 0x1,
2725 }, {
2726 .name = "dhwb",
2727 .translate = translate_dcache,
2728 .windowed_register_op = 0x1,
2729 }, {
2730 .name = "dhwbi",
2731 .translate = translate_dcache,
2732 .windowed_register_op = 0x1,
2733 }, {
2734 .name = "dii",
2735 .translate = translate_nop,
2736 .op_flags = XTENSA_OP_PRIVILEGED,
2737 .windowed_register_op = 0x1,
2738 }, {
2739 .name = "diu",
2740 .translate = translate_nop,
2741 .op_flags = XTENSA_OP_PRIVILEGED,
2742 .windowed_register_op = 0x1,
2743 }, {
2744 .name = "diwb",
2745 .translate = translate_nop,
2746 .op_flags = XTENSA_OP_PRIVILEGED,
2747 .windowed_register_op = 0x1,
2748 }, {
2749 .name = "diwbi",
2750 .translate = translate_nop,
2751 .op_flags = XTENSA_OP_PRIVILEGED,
2752 .windowed_register_op = 0x1,
2753 }, {
2754 .name = "dpfl",
2755 .translate = translate_dcache,
2756 .op_flags = XTENSA_OP_PRIVILEGED,
2757 .windowed_register_op = 0x1,
2758 }, {
2759 .name = "dpfr",
2760 .translate = translate_nop,
2761 .windowed_register_op = 0x1,
2762 }, {
2763 .name = "dpfro",
2764 .translate = translate_nop,
2765 .windowed_register_op = 0x1,
2766 }, {
2767 .name = "dpfw",
2768 .translate = translate_nop,
2769 .windowed_register_op = 0x1,
2770 }, {
2771 .name = "dpfwo",
2772 .translate = translate_nop,
2773 .windowed_register_op = 0x1,
2774 }, {
2775 .name = "dsync",
2776 .translate = translate_nop,
2777 }, {
2778 .name = "entry",
2779 .translate = translate_entry,
2780 .test_ill = test_ill_entry,
2781 .test_overflow = test_overflow_entry,
2782 .op_flags = XTENSA_OP_EXIT_TB_M1,
2783 }, {
2784 .name = "esync",
2785 .translate = translate_nop,
2786 }, {
2787 .name = "excw",
2788 .translate = translate_nop,
2789 }, {
2790 .name = "extui",
2791 .translate = translate_extui,
2792 .windowed_register_op = 0x3,
2793 }, {
2794 .name = "extw",
2795 .translate = translate_memw,
2796 }, {
2797 .name = "hwwdtlba",
2798 .op_flags = XTENSA_OP_ILL,
2799 }, {
2800 .name = "hwwitlba",
2801 .op_flags = XTENSA_OP_ILL,
2802 }, {
2803 .name = "idtlb",
2804 .translate = translate_itlb,
2805 .par = (const uint32_t[]){true},
2806 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
2807 .windowed_register_op = 0x1,
2808 }, {
2809 .name = "ihi",
2810 .translate = translate_icache,
2811 .windowed_register_op = 0x1,
2812 }, {
2813 .name = "ihu",
2814 .translate = translate_icache,
2815 .op_flags = XTENSA_OP_PRIVILEGED,
2816 .windowed_register_op = 0x1,
2817 }, {
2818 .name = "iii",
2819 .translate = translate_nop,
2820 .op_flags = XTENSA_OP_PRIVILEGED,
2821 .windowed_register_op = 0x1,
2822 }, {
2823 .name = "iitlb",
2824 .translate = translate_itlb,
2825 .par = (const uint32_t[]){false},
2826 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
2827 .windowed_register_op = 0x1,
2828 }, {
2829 .name = "iiu",
2830 .translate = translate_nop,
2831 .op_flags = XTENSA_OP_PRIVILEGED,
2832 .windowed_register_op = 0x1,
2833 }, {
2834 .name = "ill",
2835 .op_flags = XTENSA_OP_ILL,
2836 }, {
2837 .name = "ill.n",
2838 .op_flags = XTENSA_OP_ILL,
2839 }, {
2840 .name = "ipf",
2841 .translate = translate_nop,
2842 .windowed_register_op = 0x1,
2843 }, {
2844 .name = "ipfl",
2845 .translate = translate_icache,
2846 .op_flags = XTENSA_OP_PRIVILEGED,
2847 .windowed_register_op = 0x1,
2848 }, {
2849 .name = "isync",
2850 .translate = translate_nop,
2851 }, {
2852 .name = "j",
2853 .translate = translate_j,
2854 }, {
2855 .name = "jx",
2856 .translate = translate_jx,
2857 .windowed_register_op = 0x1,
2858 }, {
2859 .name = "l16si",
2860 .translate = translate_ldst,
2861 .par = (const uint32_t[]){MO_TESW, false, false},
2862 .windowed_register_op = 0x3,
2863 }, {
2864 .name = "l16ui",
2865 .translate = translate_ldst,
2866 .par = (const uint32_t[]){MO_TEUW, false, false},
2867 .windowed_register_op = 0x3,
2868 }, {
2869 .name = "l32ai",
2870 .translate = translate_ldst,
2871 .par = (const uint32_t[]){MO_TEUL, true, false},
2872 .windowed_register_op = 0x3,
2873 }, {
2874 .name = "l32e",
2875 .translate = translate_l32e,
2876 .op_flags = XTENSA_OP_PRIVILEGED,
2877 .windowed_register_op = 0x3,
2878 }, {
2879 .name = "l32i",
2880 .translate = translate_ldst,
2881 .par = (const uint32_t[]){MO_TEUL, false, false},
2882 .windowed_register_op = 0x3,
2883 }, {
2884 .name = "l32i.n",
2885 .translate = translate_ldst,
2886 .par = (const uint32_t[]){MO_TEUL, false, false},
2887 .windowed_register_op = 0x3,
2888 }, {
2889 .name = "l32r",
2890 .translate = translate_l32r,
2891 .windowed_register_op = 0x1,
2892 }, {
2893 .name = "l8ui",
2894 .translate = translate_ldst,
2895 .par = (const uint32_t[]){MO_UB, false, false},
2896 .windowed_register_op = 0x3,
2897 }, {
2898 .name = "lddec",
2899 .translate = translate_mac16,
2900 .par = (const uint32_t[]){MAC16_NONE, 0, 0, -4},
2901 .windowed_register_op = 0x2,
2902 }, {
2903 .name = "ldinc",
2904 .translate = translate_mac16,
2905 .par = (const uint32_t[]){MAC16_NONE, 0, 0, 4},
2906 .windowed_register_op = 0x2,
2907 }, {
2908 .name = "ldpte",
2909 .op_flags = XTENSA_OP_ILL,
2910 }, {
2911 .name = "loop",
2912 .translate = translate_loop,
2913 .par = (const uint32_t[]){TCG_COND_NEVER},
2914 .windowed_register_op = 0x1,
2915 }, {
2916 .name = "loopgtz",
2917 .translate = translate_loop,
2918 .par = (const uint32_t[]){TCG_COND_GT},
2919 .windowed_register_op = 0x1,
2920 }, {
2921 .name = "loopnez",
2922 .translate = translate_loop,
2923 .par = (const uint32_t[]){TCG_COND_NE},
2924 .windowed_register_op = 0x1,
2925 }, {
2926 .name = "max",
2927 .translate = translate_smax,
2928 .windowed_register_op = 0x7,
2929 }, {
2930 .name = "maxu",
2931 .translate = translate_umax,
2932 .windowed_register_op = 0x7,
2933 }, {
2934 .name = "memw",
2935 .translate = translate_memw,
2936 }, {
2937 .name = "min",
2938 .translate = translate_smin,
2939 .windowed_register_op = 0x7,
2940 }, {
2941 .name = "minu",
2942 .translate = translate_umin,
2943 .windowed_register_op = 0x7,
2944 }, {
2945 .name = "mov",
2946 .translate = translate_mov,
2947 .windowed_register_op = 0x3,
2948 }, {
2949 .name = "mov.n",
2950 .translate = translate_mov,
2951 .windowed_register_op = 0x3,
2952 }, {
2953 .name = "moveqz",
2954 .translate = translate_movcond,
2955 .par = (const uint32_t[]){TCG_COND_EQ},
2956 .windowed_register_op = 0x7,
2957 }, {
2958 .name = "movf",
2959 .translate = translate_movp,
2960 .par = (const uint32_t[]){TCG_COND_EQ},
2961 .windowed_register_op = 0x3,
2962 }, {
2963 .name = "movgez",
2964 .translate = translate_movcond,
2965 .par = (const uint32_t[]){TCG_COND_GE},
2966 .windowed_register_op = 0x7,
2967 }, {
2968 .name = "movi",
2969 .translate = translate_movi,
2970 .windowed_register_op = 0x1,
2971 }, {
2972 .name = "movi.n",
2973 .translate = translate_movi,
2974 .windowed_register_op = 0x1,
2975 }, {
2976 .name = "movltz",
2977 .translate = translate_movcond,
2978 .par = (const uint32_t[]){TCG_COND_LT},
2979 .windowed_register_op = 0x7,
2980 }, {
2981 .name = "movnez",
2982 .translate = translate_movcond,
2983 .par = (const uint32_t[]){TCG_COND_NE},
2984 .windowed_register_op = 0x7,
2985 }, {
2986 .name = "movsp",
2987 .translate = translate_movsp,
2988 .windowed_register_op = 0x3,
2989 .op_flags = XTENSA_OP_ALLOCA,
2990 }, {
2991 .name = "movt",
2992 .translate = translate_movp,
2993 .par = (const uint32_t[]){TCG_COND_NE},
2994 .windowed_register_op = 0x3,
2995 }, {
2996 .name = "mul.aa.hh",
2997 .translate = translate_mac16,
2998 .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_HH, 0},
2999 .windowed_register_op = 0x3,
3000 }, {
3001 .name = "mul.aa.hl",
3002 .translate = translate_mac16,
3003 .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_HL, 0},
3004 .windowed_register_op = 0x3,
3005 }, {
3006 .name = "mul.aa.lh",
3007 .translate = translate_mac16,
3008 .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_LH, 0},
3009 .windowed_register_op = 0x3,
3010 }, {
3011 .name = "mul.aa.ll",
3012 .translate = translate_mac16,
3013 .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_LL, 0},
3014 .windowed_register_op = 0x3,
3015 }, {
3016 .name = "mul.ad.hh",
3017 .translate = translate_mac16,
3018 .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_HH, 0},
3019 .windowed_register_op = 0x1,
3020 }, {
3021 .name = "mul.ad.hl",
3022 .translate = translate_mac16,
3023 .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_HL, 0},
3024 .windowed_register_op = 0x1,
3025 }, {
3026 .name = "mul.ad.lh",
3027 .translate = translate_mac16,
3028 .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_LH, 0},
3029 .windowed_register_op = 0x1,
3030 }, {
3031 .name = "mul.ad.ll",
3032 .translate = translate_mac16,
3033 .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_LL, 0},
3034 .windowed_register_op = 0x1,
3035 }, {
3036 .name = "mul.da.hh",
3037 .translate = translate_mac16,
3038 .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_HH, 0},
3039 .windowed_register_op = 0x2,
3040 }, {
3041 .name = "mul.da.hl",
3042 .translate = translate_mac16,
3043 .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_HL, 0},
3044 .windowed_register_op = 0x2,
3045 }, {
3046 .name = "mul.da.lh",
3047 .translate = translate_mac16,
3048 .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_LH, 0},
3049 .windowed_register_op = 0x2,
3050 }, {
3051 .name = "mul.da.ll",
3052 .translate = translate_mac16,
3053 .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_LL, 0},
3054 .windowed_register_op = 0x2,
3055 }, {
3056 .name = "mul.dd.hh",
3057 .translate = translate_mac16,
3058 .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_HH, 0},
3059 }, {
3060 .name = "mul.dd.hl",
3061 .translate = translate_mac16,
3062 .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_HL, 0},
3063 }, {
3064 .name = "mul.dd.lh",
3065 .translate = translate_mac16,
3066 .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_LH, 0},
3067 }, {
3068 .name = "mul.dd.ll",
3069 .translate = translate_mac16,
3070 .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_LL, 0},
3071 }, {
3072 .name = "mul16s",
3073 .translate = translate_mul16,
3074 .par = (const uint32_t[]){true},
3075 .windowed_register_op = 0x7,
3076 }, {
3077 .name = "mul16u",
3078 .translate = translate_mul16,
3079 .par = (const uint32_t[]){false},
3080 .windowed_register_op = 0x7,
3081 }, {
3082 .name = "mula.aa.hh",
3083 .translate = translate_mac16,
3084 .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_HH, 0},
3085 .windowed_register_op = 0x3,
3086 }, {
3087 .name = "mula.aa.hl",
3088 .translate = translate_mac16,
3089 .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_HL, 0},
3090 .windowed_register_op = 0x3,
3091 }, {
3092 .name = "mula.aa.lh",
3093 .translate = translate_mac16,
3094 .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_LH, 0},
3095 .windowed_register_op = 0x3,
3096 }, {
3097 .name = "mula.aa.ll",
3098 .translate = translate_mac16,
3099 .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_LL, 0},
3100 .windowed_register_op = 0x3,
3101 }, {
3102 .name = "mula.ad.hh",
3103 .translate = translate_mac16,
3104 .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_HH, 0},
3105 .windowed_register_op = 0x1,
3106 }, {
3107 .name = "mula.ad.hl",
3108 .translate = translate_mac16,
3109 .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_HL, 0},
3110 .windowed_register_op = 0x1,
3111 }, {
3112 .name = "mula.ad.lh",
3113 .translate = translate_mac16,
3114 .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_LH, 0},
3115 .windowed_register_op = 0x1,
3116 }, {
3117 .name = "mula.ad.ll",
3118 .translate = translate_mac16,
3119 .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_LL, 0},
3120 .windowed_register_op = 0x1,
3121 }, {
3122 .name = "mula.da.hh",
3123 .translate = translate_mac16,
3124 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, 0},
3125 .windowed_register_op = 0x2,
3126 }, {
3127 .name = "mula.da.hh.lddec",
3128 .translate = translate_mac16,
3129 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, -4},
3130 .windowed_register_op = 0xa,
3131 }, {
3132 .name = "mula.da.hh.ldinc",
3133 .translate = translate_mac16,
3134 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, 4},
3135 .windowed_register_op = 0xa,
3136 }, {
3137 .name = "mula.da.hl",
3138 .translate = translate_mac16,
3139 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, 0},
3140 .windowed_register_op = 0x2,
3141 }, {
3142 .name = "mula.da.hl.lddec",
3143 .translate = translate_mac16,
3144 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, -4},
3145 .windowed_register_op = 0xa,
3146 }, {
3147 .name = "mula.da.hl.ldinc",
3148 .translate = translate_mac16,
3149 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, 4},
3150 .windowed_register_op = 0xa,
3151 }, {
3152 .name = "mula.da.lh",
3153 .translate = translate_mac16,
3154 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, 0},
3155 .windowed_register_op = 0x2,
3156 }, {
3157 .name = "mula.da.lh.lddec",
3158 .translate = translate_mac16,
3159 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, -4},
3160 .windowed_register_op = 0xa,
3161 }, {
3162 .name = "mula.da.lh.ldinc",
3163 .translate = translate_mac16,
3164 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, 4},
3165 .windowed_register_op = 0xa,
3166 }, {
3167 .name = "mula.da.ll",
3168 .translate = translate_mac16,
3169 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, 0},
3170 .windowed_register_op = 0x2,
3171 }, {
3172 .name = "mula.da.ll.lddec",
3173 .translate = translate_mac16,
3174 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, -4},
3175 .windowed_register_op = 0xa,
3176 }, {
3177 .name = "mula.da.ll.ldinc",
3178 .translate = translate_mac16,
3179 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, 4},
3180 .windowed_register_op = 0xa,
3181 }, {
3182 .name = "mula.dd.hh",
3183 .translate = translate_mac16,
3184 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, 0},
3185 }, {
3186 .name = "mula.dd.hh.lddec",
3187 .translate = translate_mac16,
3188 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, -4},
3189 .windowed_register_op = 0x2,
3190 }, {
3191 .name = "mula.dd.hh.ldinc",
3192 .translate = translate_mac16,
3193 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, 4},
3194 .windowed_register_op = 0x2,
3195 }, {
3196 .name = "mula.dd.hl",
3197 .translate = translate_mac16,
3198 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, 0},
3199 }, {
3200 .name = "mula.dd.hl.lddec",
3201 .translate = translate_mac16,
3202 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, -4},
3203 .windowed_register_op = 0x2,
3204 }, {
3205 .name = "mula.dd.hl.ldinc",
3206 .translate = translate_mac16,
3207 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, 4},
3208 .windowed_register_op = 0x2,
3209 }, {
3210 .name = "mula.dd.lh",
3211 .translate = translate_mac16,
3212 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, 0},
3213 }, {
3214 .name = "mula.dd.lh.lddec",
3215 .translate = translate_mac16,
3216 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, -4},
3217 .windowed_register_op = 0x2,
3218 }, {
3219 .name = "mula.dd.lh.ldinc",
3220 .translate = translate_mac16,
3221 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, 4},
3222 .windowed_register_op = 0x2,
3223 }, {
3224 .name = "mula.dd.ll",
3225 .translate = translate_mac16,
3226 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, 0},
3227 }, {
3228 .name = "mula.dd.ll.lddec",
3229 .translate = translate_mac16,
3230 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, -4},
3231 .windowed_register_op = 0x2,
3232 }, {
3233 .name = "mula.dd.ll.ldinc",
3234 .translate = translate_mac16,
3235 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, 4},
3236 .windowed_register_op = 0x2,
3237 }, {
3238 .name = "mull",
3239 .translate = translate_mull,
3240 .windowed_register_op = 0x7,
3241 }, {
3242 .name = "muls.aa.hh",
3243 .translate = translate_mac16,
3244 .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_HH, 0},
3245 .windowed_register_op = 0x3,
3246 }, {
3247 .name = "muls.aa.hl",
3248 .translate = translate_mac16,
3249 .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_HL, 0},
3250 .windowed_register_op = 0x3,
3251 }, {
3252 .name = "muls.aa.lh",
3253 .translate = translate_mac16,
3254 .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_LH, 0},
3255 .windowed_register_op = 0x3,
3256 }, {
3257 .name = "muls.aa.ll",
3258 .translate = translate_mac16,
3259 .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_LL, 0},
3260 .windowed_register_op = 0x3,
3261 }, {
3262 .name = "muls.ad.hh",
3263 .translate = translate_mac16,
3264 .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_HH, 0},
3265 .windowed_register_op = 0x1,
3266 }, {
3267 .name = "muls.ad.hl",
3268 .translate = translate_mac16,
3269 .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_HL, 0},
3270 .windowed_register_op = 0x1,
3271 }, {
3272 .name = "muls.ad.lh",
3273 .translate = translate_mac16,
3274 .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_LH, 0},
3275 .windowed_register_op = 0x1,
3276 }, {
3277 .name = "muls.ad.ll",
3278 .translate = translate_mac16,
3279 .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_LL, 0},
3280 .windowed_register_op = 0x1,
3281 }, {
3282 .name = "muls.da.hh",
3283 .translate = translate_mac16,
3284 .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_HH, 0},
3285 .windowed_register_op = 0x2,
3286 }, {
3287 .name = "muls.da.hl",
3288 .translate = translate_mac16,
3289 .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_HL, 0},
3290 .windowed_register_op = 0x2,
3291 }, {
3292 .name = "muls.da.lh",
3293 .translate = translate_mac16,
3294 .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_LH, 0},
3295 .windowed_register_op = 0x2,
3296 }, {
3297 .name = "muls.da.ll",
3298 .translate = translate_mac16,
3299 .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_LL, 0},
3300 .windowed_register_op = 0x2,
3301 }, {
3302 .name = "muls.dd.hh",
3303 .translate = translate_mac16,
3304 .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_HH, 0},
3305 }, {
3306 .name = "muls.dd.hl",
3307 .translate = translate_mac16,
3308 .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_HL, 0},
3309 }, {
3310 .name = "muls.dd.lh",
3311 .translate = translate_mac16,
3312 .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_LH, 0},
3313 }, {
3314 .name = "muls.dd.ll",
3315 .translate = translate_mac16,
3316 .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_LL, 0},
3317 }, {
3318 .name = "mulsh",
3319 .translate = translate_mulh,
3320 .par = (const uint32_t[]){true},
3321 .windowed_register_op = 0x7,
3322 }, {
3323 .name = "muluh",
3324 .translate = translate_mulh,
3325 .par = (const uint32_t[]){false},
3326 .windowed_register_op = 0x7,
3327 }, {
3328 .name = "neg",
3329 .translate = translate_neg,
3330 .windowed_register_op = 0x3,
3331 }, {
3332 .name = "nop",
3333 .translate = translate_nop,
3334 }, {
3335 .name = "nop.n",
3336 .translate = translate_nop,
3337 }, {
3338 .name = "nsa",
3339 .translate = translate_nsa,
3340 .windowed_register_op = 0x3,
3341 }, {
3342 .name = "nsau",
3343 .translate = translate_nsau,
3344 .windowed_register_op = 0x3,
3345 }, {
3346 .name = "or",
3347 .translate = translate_or,
3348 .windowed_register_op = 0x7,
3349 }, {
3350 .name = "orb",
3351 .translate = translate_boolean,
3352 .par = (const uint32_t[]){BOOLEAN_OR},
3353 }, {
3354 .name = "orbc",
3355 .translate = translate_boolean,
3356 .par = (const uint32_t[]){BOOLEAN_ORC},
3357 }, {
3358 .name = "pdtlb",
3359 .translate = translate_ptlb,
3360 .par = (const uint32_t[]){true},
3361 .op_flags = XTENSA_OP_PRIVILEGED,
3362 .windowed_register_op = 0x3,
3363 }, {
3364 .name = "pitlb",
3365 .translate = translate_ptlb,
3366 .par = (const uint32_t[]){false},
3367 .op_flags = XTENSA_OP_PRIVILEGED,
3368 .windowed_register_op = 0x3,
3369 }, {
3370 .name = "quos",
3371 .translate = translate_quos,
3372 .par = (const uint32_t[]){true},
3373 .op_flags = XTENSA_OP_DIVIDE_BY_ZERO,
3374 .windowed_register_op = 0x7,
3375 }, {
3376 .name = "quou",
3377 .translate = translate_quou,
3378 .op_flags = XTENSA_OP_DIVIDE_BY_ZERO,
3379 .windowed_register_op = 0x7,
3380 }, {
3381 .name = "rdtlb0",
3382 .translate = translate_rtlb,
3383 .par = (const uint32_t[]){true, 0},
3384 .op_flags = XTENSA_OP_PRIVILEGED,
3385 .windowed_register_op = 0x3,
3386 }, {
3387 .name = "rdtlb1",
3388 .translate = translate_rtlb,
3389 .par = (const uint32_t[]){true, 1},
3390 .op_flags = XTENSA_OP_PRIVILEGED,
3391 .windowed_register_op = 0x3,
3392 }, {
3393 .name = "read_impwire",
3394 .translate = translate_read_impwire,
3395 .windowed_register_op = 0x1,
3396 }, {
3397 .name = "rems",
3398 .translate = translate_quos,
3399 .par = (const uint32_t[]){false},
3400 .op_flags = XTENSA_OP_DIVIDE_BY_ZERO,
3401 .windowed_register_op = 0x7,
3402 }, {
3403 .name = "remu",
3404 .translate = translate_remu,
3405 .op_flags = XTENSA_OP_DIVIDE_BY_ZERO,
3406 .windowed_register_op = 0x7,
3407 }, {
3408 .name = "rer",
3409 .translate = translate_rer,
3410 .op_flags = XTENSA_OP_PRIVILEGED,
3411 .windowed_register_op = 0x3,
3412 }, {
3413 .name = "ret",
3414 .translate = translate_ret,
3415 }, {
3416 .name = "ret.n",
3417 .translate = translate_ret,
3418 }, {
3419 .name = "retw",
3420 .translate = translate_retw,
3421 .test_ill = test_ill_retw,
3422 .op_flags = XTENSA_OP_UNDERFLOW,
3423 }, {
3424 .name = "retw.n",
3425 .translate = translate_retw,
3426 .test_ill = test_ill_retw,
3427 .op_flags = XTENSA_OP_UNDERFLOW,
3428 }, {
3429 .name = "rfdd",
3430 .op_flags = XTENSA_OP_ILL,
3431 }, {
3432 .name = "rfde",
3433 .translate = translate_rfde,
3434 .op_flags = XTENSA_OP_PRIVILEGED,
3435 }, {
3436 .name = "rfdo",
3437 .op_flags = XTENSA_OP_ILL,
3438 }, {
3439 .name = "rfe",
3440 .translate = translate_rfe,
3441 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,
3442 }, {
3443 .name = "rfi",
3444 .translate = translate_rfi,
3445 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,
3446 }, {
3447 .name = "rfwo",
3448 .translate = translate_rfw,
3449 .par = (const uint32_t[]){true},
3450 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,
3451 }, {
3452 .name = "rfwu",
3453 .translate = translate_rfw,
3454 .par = (const uint32_t[]){false},
3455 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,
3456 }, {
3457 .name = "ritlb0",
3458 .translate = translate_rtlb,
3459 .par = (const uint32_t[]){false, 0},
3460 .op_flags = XTENSA_OP_PRIVILEGED,
3461 .windowed_register_op = 0x3,
3462 }, {
3463 .name = "ritlb1",
3464 .translate = translate_rtlb,
3465 .par = (const uint32_t[]){false, 1},
3466 .op_flags = XTENSA_OP_PRIVILEGED,
3467 .windowed_register_op = 0x3,
3468 }, {
3469 .name = "rotw",
3470 .translate = translate_rotw,
3471 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
3472 }, {
3473 .name = "rsil",
3474 .translate = translate_rsil,
3475 .op_flags =
3476 XTENSA_OP_PRIVILEGED |
3477 XTENSA_OP_EXIT_TB_0 |
3478 XTENSA_OP_CHECK_INTERRUPTS,
3479 .windowed_register_op = 0x1,
3480 }, {
3481 .name = "rsr.176",
3482 .translate = translate_rsr,
3483 .test_ill = test_ill_rsr,
3484 .par = (const uint32_t[]){176},
3485 .op_flags = XTENSA_OP_PRIVILEGED,
3486 .windowed_register_op = 0x1,
3487 }, {
3488 .name = "rsr.208",
3489 .translate = translate_rsr,
3490 .test_ill = test_ill_rsr,
3491 .par = (const uint32_t[]){208},
3492 .op_flags = XTENSA_OP_PRIVILEGED,
3493 .windowed_register_op = 0x1,
3494 }, {
3495 .name = "rsr.acchi",
3496 .translate = translate_rsr,
3497 .test_ill = test_ill_rsr,
3498 .par = (const uint32_t[]){ACCHI},
3499 .windowed_register_op = 0x1,
3500 }, {
3501 .name = "rsr.acclo",
3502 .translate = translate_rsr,
3503 .test_ill = test_ill_rsr,
3504 .par = (const uint32_t[]){ACCLO},
3505 .windowed_register_op = 0x1,
3506 }, {
3507 .name = "rsr.atomctl",
3508 .translate = translate_rsr,
3509 .test_ill = test_ill_rsr,
3510 .par = (const uint32_t[]){ATOMCTL},
3511 .op_flags = XTENSA_OP_PRIVILEGED,
3512 .windowed_register_op = 0x1,
3513 }, {
3514 .name = "rsr.br",
3515 .translate = translate_rsr,
3516 .test_ill = test_ill_rsr,
3517 .par = (const uint32_t[]){BR},
3518 .windowed_register_op = 0x1,
3519 }, {
3520 .name = "rsr.cacheattr",
3521 .translate = translate_rsr,
3522 .test_ill = test_ill_rsr,
3523 .par = (const uint32_t[]){CACHEATTR},
3524 .op_flags = XTENSA_OP_PRIVILEGED,
3525 .windowed_register_op = 0x1,
3526 }, {
3527 .name = "rsr.ccompare0",
3528 .translate = translate_rsr,
3529 .test_ill = test_ill_rsr,
3530 .par = (const uint32_t[]){CCOMPARE},
3531 .op_flags = XTENSA_OP_PRIVILEGED,
3532 .windowed_register_op = 0x1,
3533 }, {
3534 .name = "rsr.ccompare1",
3535 .translate = translate_rsr,
3536 .test_ill = test_ill_rsr,
3537 .par = (const uint32_t[]){CCOMPARE + 1},
3538 .op_flags = XTENSA_OP_PRIVILEGED,
3539 .windowed_register_op = 0x1,
3540 }, {
3541 .name = "rsr.ccompare2",
3542 .translate = translate_rsr,
3543 .test_ill = test_ill_rsr,
3544 .par = (const uint32_t[]){CCOMPARE + 2},
3545 .op_flags = XTENSA_OP_PRIVILEGED,
3546 .windowed_register_op = 0x1,
3547 }, {
3548 .name = "rsr.ccount",
3549 .translate = translate_rsr,
3550 .test_ill = test_ill_rsr,
3551 .par = (const uint32_t[]){CCOUNT},
3552 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
3553 .windowed_register_op = 0x1,
3554 }, {
3555 .name = "rsr.configid0",
3556 .translate = translate_rsr,
3557 .test_ill = test_ill_rsr,
3558 .par = (const uint32_t[]){CONFIGID0},
3559 .op_flags = XTENSA_OP_PRIVILEGED,
3560 .windowed_register_op = 0x1,
3561 }, {
3562 .name = "rsr.configid1",
3563 .translate = translate_rsr,
3564 .test_ill = test_ill_rsr,
3565 .par = (const uint32_t[]){CONFIGID1},
3566 .op_flags = XTENSA_OP_PRIVILEGED,
3567 .windowed_register_op = 0x1,
3568 }, {
3569 .name = "rsr.cpenable",
3570 .translate = translate_rsr,
3571 .test_ill = test_ill_rsr,
3572 .par = (const uint32_t[]){CPENABLE},
3573 .op_flags = XTENSA_OP_PRIVILEGED,
3574 .windowed_register_op = 0x1,
3575 }, {
3576 .name = "rsr.dbreaka0",
3577 .translate = translate_rsr,
3578 .test_ill = test_ill_rsr,
3579 .par = (const uint32_t[]){DBREAKA},
3580 .op_flags = XTENSA_OP_PRIVILEGED,
3581 .windowed_register_op = 0x1,
3582 }, {
3583 .name = "rsr.dbreaka1",
3584 .translate = translate_rsr,
3585 .test_ill = test_ill_rsr,
3586 .par = (const uint32_t[]){DBREAKA + 1},
3587 .op_flags = XTENSA_OP_PRIVILEGED,
3588 .windowed_register_op = 0x1,
3589 }, {
3590 .name = "rsr.dbreakc0",
3591 .translate = translate_rsr,
3592 .test_ill = test_ill_rsr,
3593 .par = (const uint32_t[]){DBREAKC},
3594 .op_flags = XTENSA_OP_PRIVILEGED,
3595 .windowed_register_op = 0x1,
3596 }, {
3597 .name = "rsr.dbreakc1",
3598 .translate = translate_rsr,
3599 .test_ill = test_ill_rsr,
3600 .par = (const uint32_t[]){DBREAKC + 1},
3601 .op_flags = XTENSA_OP_PRIVILEGED,
3602 .windowed_register_op = 0x1,
3603 }, {
3604 .name = "rsr.ddr",
3605 .translate = translate_rsr,
3606 .test_ill = test_ill_rsr,
3607 .par = (const uint32_t[]){DDR},
3608 .op_flags = XTENSA_OP_PRIVILEGED,
3609 .windowed_register_op = 0x1,
3610 }, {
3611 .name = "rsr.debugcause",
3612 .translate = translate_rsr,
3613 .test_ill = test_ill_rsr,
3614 .par = (const uint32_t[]){DEBUGCAUSE},
3615 .op_flags = XTENSA_OP_PRIVILEGED,
3616 .windowed_register_op = 0x1,
3617 }, {
3618 .name = "rsr.depc",
3619 .translate = translate_rsr,
3620 .test_ill = test_ill_rsr,
3621 .par = (const uint32_t[]){DEPC},
3622 .op_flags = XTENSA_OP_PRIVILEGED,
3623 .windowed_register_op = 0x1,
3624 }, {
3625 .name = "rsr.dtlbcfg",
3626 .translate = translate_rsr,
3627 .test_ill = test_ill_rsr,
3628 .par = (const uint32_t[]){DTLBCFG},
3629 .op_flags = XTENSA_OP_PRIVILEGED,
3630 .windowed_register_op = 0x1,
3631 }, {
3632 .name = "rsr.epc1",
3633 .translate = translate_rsr,
3634 .test_ill = test_ill_rsr,
3635 .par = (const uint32_t[]){EPC1},
3636 .op_flags = XTENSA_OP_PRIVILEGED,
3637 .windowed_register_op = 0x1,
3638 }, {
3639 .name = "rsr.epc2",
3640 .translate = translate_rsr,
3641 .test_ill = test_ill_rsr,
3642 .par = (const uint32_t[]){EPC1 + 1},
3643 .op_flags = XTENSA_OP_PRIVILEGED,
3644 .windowed_register_op = 0x1,
3645 }, {
3646 .name = "rsr.epc3",
3647 .translate = translate_rsr,
3648 .test_ill = test_ill_rsr,
3649 .par = (const uint32_t[]){EPC1 + 2},
3650 .op_flags = XTENSA_OP_PRIVILEGED,
3651 .windowed_register_op = 0x1,
3652 }, {
3653 .name = "rsr.epc4",
3654 .translate = translate_rsr,
3655 .test_ill = test_ill_rsr,
3656 .par = (const uint32_t[]){EPC1 + 3},
3657 .op_flags = XTENSA_OP_PRIVILEGED,
3658 .windowed_register_op = 0x1,
3659 }, {
3660 .name = "rsr.epc5",
3661 .translate = translate_rsr,
3662 .test_ill = test_ill_rsr,
3663 .par = (const uint32_t[]){EPC1 + 4},
3664 .op_flags = XTENSA_OP_PRIVILEGED,
3665 .windowed_register_op = 0x1,
3666 }, {
3667 .name = "rsr.epc6",
3668 .translate = translate_rsr,
3669 .test_ill = test_ill_rsr,
3670 .par = (const uint32_t[]){EPC1 + 5},
3671 .op_flags = XTENSA_OP_PRIVILEGED,
3672 .windowed_register_op = 0x1,
3673 }, {
3674 .name = "rsr.epc7",
3675 .translate = translate_rsr,
3676 .test_ill = test_ill_rsr,
3677 .par = (const uint32_t[]){EPC1 + 6},
3678 .op_flags = XTENSA_OP_PRIVILEGED,
3679 .windowed_register_op = 0x1,
3680 }, {
3681 .name = "rsr.eps2",
3682 .translate = translate_rsr,
3683 .test_ill = test_ill_rsr,
3684 .par = (const uint32_t[]){EPS2},
3685 .op_flags = XTENSA_OP_PRIVILEGED,
3686 .windowed_register_op = 0x1,
3687 }, {
3688 .name = "rsr.eps3",
3689 .translate = translate_rsr,
3690 .test_ill = test_ill_rsr,
3691 .par = (const uint32_t[]){EPS2 + 1},
3692 .op_flags = XTENSA_OP_PRIVILEGED,
3693 .windowed_register_op = 0x1,
3694 }, {
3695 .name = "rsr.eps4",
3696 .translate = translate_rsr,
3697 .test_ill = test_ill_rsr,
3698 .par = (const uint32_t[]){EPS2 + 2},
3699 .op_flags = XTENSA_OP_PRIVILEGED,
3700 .windowed_register_op = 0x1,
3701 }, {
3702 .name = "rsr.eps5",
3703 .translate = translate_rsr,
3704 .test_ill = test_ill_rsr,
3705 .par = (const uint32_t[]){EPS2 + 3},
3706 .op_flags = XTENSA_OP_PRIVILEGED,
3707 .windowed_register_op = 0x1,
3708 }, {
3709 .name = "rsr.eps6",
3710 .translate = translate_rsr,
3711 .test_ill = test_ill_rsr,
3712 .par = (const uint32_t[]){EPS2 + 4},
3713 .op_flags = XTENSA_OP_PRIVILEGED,
3714 .windowed_register_op = 0x1,
3715 }, {
3716 .name = "rsr.eps7",
3717 .translate = translate_rsr,
3718 .test_ill = test_ill_rsr,
3719 .par = (const uint32_t[]){EPS2 + 5},
3720 .op_flags = XTENSA_OP_PRIVILEGED,
3721 .windowed_register_op = 0x1,
3722 }, {
3723 .name = "rsr.exccause",
3724 .translate = translate_rsr,
3725 .test_ill = test_ill_rsr,
3726 .par = (const uint32_t[]){EXCCAUSE},
3727 .op_flags = XTENSA_OP_PRIVILEGED,
3728 .windowed_register_op = 0x1,
3729 }, {
3730 .name = "rsr.excsave1",
3731 .translate = translate_rsr,
3732 .test_ill = test_ill_rsr,
3733 .par = (const uint32_t[]){EXCSAVE1},
3734 .op_flags = XTENSA_OP_PRIVILEGED,
3735 .windowed_register_op = 0x1,
3736 }, {
3737 .name = "rsr.excsave2",
3738 .translate = translate_rsr,
3739 .test_ill = test_ill_rsr,
3740 .par = (const uint32_t[]){EXCSAVE1 + 1},
3741 .op_flags = XTENSA_OP_PRIVILEGED,
3742 .windowed_register_op = 0x1,
3743 }, {
3744 .name = "rsr.excsave3",
3745 .translate = translate_rsr,
3746 .test_ill = test_ill_rsr,
3747 .par = (const uint32_t[]){EXCSAVE1 + 2},
3748 .op_flags = XTENSA_OP_PRIVILEGED,
3749 .windowed_register_op = 0x1,
3750 }, {
3751 .name = "rsr.excsave4",
3752 .translate = translate_rsr,
3753 .test_ill = test_ill_rsr,
3754 .par = (const uint32_t[]){EXCSAVE1 + 3},
3755 .op_flags = XTENSA_OP_PRIVILEGED,
3756 .windowed_register_op = 0x1,
3757 }, {
3758 .name = "rsr.excsave5",
3759 .translate = translate_rsr,
3760 .test_ill = test_ill_rsr,
3761 .par = (const uint32_t[]){EXCSAVE1 + 4},
3762 .op_flags = XTENSA_OP_PRIVILEGED,
3763 .windowed_register_op = 0x1,
3764 }, {
3765 .name = "rsr.excsave6",
3766 .translate = translate_rsr,
3767 .test_ill = test_ill_rsr,
3768 .par = (const uint32_t[]){EXCSAVE1 + 5},
3769 .op_flags = XTENSA_OP_PRIVILEGED,
3770 .windowed_register_op = 0x1,
3771 }, {
3772 .name = "rsr.excsave7",
3773 .translate = translate_rsr,
3774 .test_ill = test_ill_rsr,
3775 .par = (const uint32_t[]){EXCSAVE1 + 6},
3776 .op_flags = XTENSA_OP_PRIVILEGED,
3777 .windowed_register_op = 0x1,
3778 }, {
3779 .name = "rsr.excvaddr",
3780 .translate = translate_rsr,
3781 .test_ill = test_ill_rsr,
3782 .par = (const uint32_t[]){EXCVADDR},
3783 .op_flags = XTENSA_OP_PRIVILEGED,
3784 .windowed_register_op = 0x1,
3785 }, {
3786 .name = "rsr.ibreaka0",
3787 .translate = translate_rsr,
3788 .test_ill = test_ill_rsr,
3789 .par = (const uint32_t[]){IBREAKA},
3790 .op_flags = XTENSA_OP_PRIVILEGED,
3791 .windowed_register_op = 0x1,
3792 }, {
3793 .name = "rsr.ibreaka1",
3794 .translate = translate_rsr,
3795 .test_ill = test_ill_rsr,
3796 .par = (const uint32_t[]){IBREAKA + 1},
3797 .op_flags = XTENSA_OP_PRIVILEGED,
3798 .windowed_register_op = 0x1,
3799 }, {
3800 .name = "rsr.ibreakenable",
3801 .translate = translate_rsr,
3802 .test_ill = test_ill_rsr,
3803 .par = (const uint32_t[]){IBREAKENABLE},
3804 .op_flags = XTENSA_OP_PRIVILEGED,
3805 .windowed_register_op = 0x1,
3806 }, {
3807 .name = "rsr.icount",
3808 .translate = translate_rsr,
3809 .test_ill = test_ill_rsr,
3810 .par = (const uint32_t[]){ICOUNT},
3811 .op_flags = XTENSA_OP_PRIVILEGED,
3812 .windowed_register_op = 0x1,
3813 }, {
3814 .name = "rsr.icountlevel",
3815 .translate = translate_rsr,
3816 .test_ill = test_ill_rsr,
3817 .par = (const uint32_t[]){ICOUNTLEVEL},
3818 .op_flags = XTENSA_OP_PRIVILEGED,
3819 .windowed_register_op = 0x1,
3820 }, {
3821 .name = "rsr.intclear",
3822 .translate = translate_rsr,
3823 .test_ill = test_ill_rsr,
3824 .par = (const uint32_t[]){INTCLEAR},
3825 .op_flags = XTENSA_OP_PRIVILEGED,
3826 .windowed_register_op = 0x1,
3827 }, {
3828 .name = "rsr.intenable",
3829 .translate = translate_rsr,
3830 .test_ill = test_ill_rsr,
3831 .par = (const uint32_t[]){INTENABLE},
3832 .op_flags = XTENSA_OP_PRIVILEGED,
3833 .windowed_register_op = 0x1,
3834 }, {
3835 .name = "rsr.interrupt",
3836 .translate = translate_rsr,
3837 .test_ill = test_ill_rsr,
3838 .par = (const uint32_t[]){INTSET},
3839 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
3840 .windowed_register_op = 0x1,
3841 }, {
3842 .name = "rsr.intset",
3843 .translate = translate_rsr,
3844 .test_ill = test_ill_rsr,
3845 .par = (const uint32_t[]){INTSET},
3846 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
3847 .windowed_register_op = 0x1,
3848 }, {
3849 .name = "rsr.itlbcfg",
3850 .translate = translate_rsr,
3851 .test_ill = test_ill_rsr,
3852 .par = (const uint32_t[]){ITLBCFG},
3853 .op_flags = XTENSA_OP_PRIVILEGED,
3854 .windowed_register_op = 0x1,
3855 }, {
3856 .name = "rsr.lbeg",
3857 .translate = translate_rsr,
3858 .test_ill = test_ill_rsr,
3859 .par = (const uint32_t[]){LBEG},
3860 .windowed_register_op = 0x1,
3861 }, {
3862 .name = "rsr.lcount",
3863 .translate = translate_rsr,
3864 .test_ill = test_ill_rsr,
3865 .par = (const uint32_t[]){LCOUNT},
3866 .windowed_register_op = 0x1,
3867 }, {
3868 .name = "rsr.lend",
3869 .translate = translate_rsr,
3870 .test_ill = test_ill_rsr,
3871 .par = (const uint32_t[]){LEND},
3872 .windowed_register_op = 0x1,
3873 }, {
3874 .name = "rsr.litbase",
3875 .translate = translate_rsr,
3876 .test_ill = test_ill_rsr,
3877 .par = (const uint32_t[]){LITBASE},
3878 .windowed_register_op = 0x1,
3879 }, {
3880 .name = "rsr.m0",
3881 .translate = translate_rsr,
3882 .test_ill = test_ill_rsr,
3883 .par = (const uint32_t[]){MR},
3884 .windowed_register_op = 0x1,
3885 }, {
3886 .name = "rsr.m1",
3887 .translate = translate_rsr,
3888 .test_ill = test_ill_rsr,
3889 .par = (const uint32_t[]){MR + 1},
3890 .windowed_register_op = 0x1,
3891 }, {
3892 .name = "rsr.m2",
3893 .translate = translate_rsr,
3894 .test_ill = test_ill_rsr,
3895 .par = (const uint32_t[]){MR + 2},
3896 .windowed_register_op = 0x1,
3897 }, {
3898 .name = "rsr.m3",
3899 .translate = translate_rsr,
3900 .test_ill = test_ill_rsr,
3901 .par = (const uint32_t[]){MR + 3},
3902 .windowed_register_op = 0x1,
3903 }, {
3904 .name = "rsr.memctl",
3905 .translate = translate_rsr,
3906 .test_ill = test_ill_rsr,
3907 .par = (const uint32_t[]){MEMCTL},
3908 .op_flags = XTENSA_OP_PRIVILEGED,
3909 .windowed_register_op = 0x1,
3910 }, {
3911 .name = "rsr.misc0",
3912 .translate = translate_rsr,
3913 .test_ill = test_ill_rsr,
3914 .par = (const uint32_t[]){MISC},
3915 .op_flags = XTENSA_OP_PRIVILEGED,
3916 .windowed_register_op = 0x1,
3917 }, {
3918 .name = "rsr.misc1",
3919 .translate = translate_rsr,
3920 .test_ill = test_ill_rsr,
3921 .par = (const uint32_t[]){MISC + 1},
3922 .op_flags = XTENSA_OP_PRIVILEGED,
3923 .windowed_register_op = 0x1,
3924 }, {
3925 .name = "rsr.misc2",
3926 .translate = translate_rsr,
3927 .test_ill = test_ill_rsr,
3928 .par = (const uint32_t[]){MISC + 2},
3929 .op_flags = XTENSA_OP_PRIVILEGED,
3930 .windowed_register_op = 0x1,
3931 }, {
3932 .name = "rsr.misc3",
3933 .translate = translate_rsr,
3934 .test_ill = test_ill_rsr,
3935 .par = (const uint32_t[]){MISC + 3},
3936 .op_flags = XTENSA_OP_PRIVILEGED,
3937 .windowed_register_op = 0x1,
3938 }, {
3939 .name = "rsr.prid",
3940 .translate = translate_rsr,
3941 .test_ill = test_ill_rsr,
3942 .par = (const uint32_t[]){PRID},
3943 .op_flags = XTENSA_OP_PRIVILEGED,
3944 .windowed_register_op = 0x1,
3945 }, {
3946 .name = "rsr.ps",
3947 .translate = translate_rsr,
3948 .test_ill = test_ill_rsr,
3949 .par = (const uint32_t[]){PS},
3950 .op_flags = XTENSA_OP_PRIVILEGED,
3951 .windowed_register_op = 0x1,
3952 }, {
3953 .name = "rsr.ptevaddr",
3954 .translate = translate_rsr,
3955 .test_ill = test_ill_rsr,
3956 .par = (const uint32_t[]){PTEVADDR},
3957 .op_flags = XTENSA_OP_PRIVILEGED,
3958 .windowed_register_op = 0x1,
3959 }, {
3960 .name = "rsr.rasid",
3961 .translate = translate_rsr,
3962 .test_ill = test_ill_rsr,
3963 .par = (const uint32_t[]){RASID},
3964 .op_flags = XTENSA_OP_PRIVILEGED,
3965 .windowed_register_op = 0x1,
3966 }, {
3967 .name = "rsr.sar",
3968 .translate = translate_rsr,
3969 .test_ill = test_ill_rsr,
3970 .par = (const uint32_t[]){SAR},
3971 .windowed_register_op = 0x1,
3972 }, {
3973 .name = "rsr.scompare1",
3974 .translate = translate_rsr,
3975 .test_ill = test_ill_rsr,
3976 .par = (const uint32_t[]){SCOMPARE1},
3977 .windowed_register_op = 0x1,
3978 }, {
3979 .name = "rsr.vecbase",
3980 .translate = translate_rsr,
3981 .test_ill = test_ill_rsr,
3982 .par = (const uint32_t[]){VECBASE},
3983 .op_flags = XTENSA_OP_PRIVILEGED,
3984 .windowed_register_op = 0x1,
3985 }, {
3986 .name = "rsr.windowbase",
3987 .translate = translate_rsr,
3988 .test_ill = test_ill_rsr,
3989 .par = (const uint32_t[]){WINDOW_BASE},
3990 .op_flags = XTENSA_OP_PRIVILEGED,
3991 .windowed_register_op = 0x1,
3992 }, {
3993 .name = "rsr.windowstart",
3994 .translate = translate_rsr,
3995 .test_ill = test_ill_rsr,
3996 .par = (const uint32_t[]){WINDOW_START},
3997 .op_flags = XTENSA_OP_PRIVILEGED,
3998 .windowed_register_op = 0x1,
3999 }, {
4000 .name = "rsync",
4001 .translate = translate_nop,
4002 }, {
4003 .name = "rur.expstate",
4004 .translate = translate_rur,
4005 .par = (const uint32_t[]){EXPSTATE},
4006 .windowed_register_op = 0x1,
4007 }, {
4008 .name = "rur.fcr",
4009 .translate = translate_rur,
4010 .par = (const uint32_t[]){FCR},
4011 .windowed_register_op = 0x1,
4012 .coprocessor = 0x1,
4013 }, {
4014 .name = "rur.fsr",
4015 .translate = translate_rur,
4016 .par = (const uint32_t[]){FSR},
4017 .windowed_register_op = 0x1,
4018 .coprocessor = 0x1,
4019 }, {
4020 .name = "rur.threadptr",
4021 .translate = translate_rur,
4022 .par = (const uint32_t[]){THREADPTR},
4023 .windowed_register_op = 0x1,
4024 }, {
4025 .name = "s16i",
4026 .translate = translate_ldst,
4027 .par = (const uint32_t[]){MO_TEUW, false, true},
4028 .windowed_register_op = 0x3,
4029 }, {
4030 .name = "s32c1i",
4031 .translate = translate_s32c1i,
4032 .windowed_register_op = 0x3,
4033 }, {
4034 .name = "s32e",
4035 .translate = translate_s32e,
4036 .op_flags = XTENSA_OP_PRIVILEGED,
4037 .windowed_register_op = 0x3,
4038 }, {
4039 .name = "s32i",
4040 .translate = translate_ldst,
4041 .par = (const uint32_t[]){MO_TEUL, false, true},
4042 .windowed_register_op = 0x3,
4043 }, {
4044 .name = "s32i.n",
4045 .translate = translate_ldst,
4046 .par = (const uint32_t[]){MO_TEUL, false, true},
4047 .windowed_register_op = 0x3,
4048 }, {
4049 .name = "s32nb",
4050 .translate = translate_ldst,
4051 .par = (const uint32_t[]){MO_TEUL, false, true},
4052 .windowed_register_op = 0x3,
4053 }, {
4054 .name = "s32ri",
4055 .translate = translate_ldst,
4056 .par = (const uint32_t[]){MO_TEUL, true, true},
4057 .windowed_register_op = 0x3,
4058 }, {
4059 .name = "s8i",
4060 .translate = translate_ldst,
4061 .par = (const uint32_t[]){MO_UB, false, true},
4062 .windowed_register_op = 0x3,
4063 }, {
4064 .name = "salt",
4065 .translate = translate_salt,
4066 .par = (const uint32_t[]){TCG_COND_LT},
4067 .windowed_register_op = 0x7,
4068 }, {
4069 .name = "saltu",
4070 .translate = translate_salt,
4071 .par = (const uint32_t[]){TCG_COND_LTU},
4072 .windowed_register_op = 0x7,
4073 }, {
4074 .name = "setb_expstate",
4075 .translate = translate_setb_expstate,
4076 }, {
4077 .name = "sext",
4078 .translate = translate_sext,
4079 .windowed_register_op = 0x3,
4080 }, {
4081 .name = "simcall",
4082 .translate = translate_simcall,
4083 .test_ill = test_ill_simcall,
4084 .op_flags = XTENSA_OP_PRIVILEGED,
4085 }, {
4086 .name = "sll",
4087 .translate = translate_sll,
4088 .windowed_register_op = 0x3,
4089 }, {
4090 .name = "slli",
4091 .translate = translate_slli,
4092 .windowed_register_op = 0x3,
4093 }, {
4094 .name = "sra",
4095 .translate = translate_sra,
4096 .windowed_register_op = 0x3,
4097 }, {
4098 .name = "srai",
4099 .translate = translate_srai,
4100 .windowed_register_op = 0x3,
4101 }, {
4102 .name = "src",
4103 .translate = translate_src,
4104 .windowed_register_op = 0x7,
4105 }, {
4106 .name = "srl",
4107 .translate = translate_srl,
4108 .windowed_register_op = 0x3,
4109 }, {
4110 .name = "srli",
4111 .translate = translate_srli,
4112 .windowed_register_op = 0x3,
4113 }, {
4114 .name = "ssa8b",
4115 .translate = translate_ssa8b,
4116 .windowed_register_op = 0x1,
4117 }, {
4118 .name = "ssa8l",
4119 .translate = translate_ssa8l,
4120 .windowed_register_op = 0x1,
4121 }, {
4122 .name = "ssai",
4123 .translate = translate_ssai,
4124 }, {
4125 .name = "ssl",
4126 .translate = translate_ssl,
4127 .windowed_register_op = 0x1,
4128 }, {
4129 .name = "ssr",
4130 .translate = translate_ssr,
4131 .windowed_register_op = 0x1,
4132 }, {
4133 .name = "sub",
4134 .translate = translate_sub,
4135 .windowed_register_op = 0x7,
4136 }, {
4137 .name = "subx2",
4138 .translate = translate_subx,
4139 .par = (const uint32_t[]){1},
4140 .windowed_register_op = 0x7,
4141 }, {
4142 .name = "subx4",
4143 .translate = translate_subx,
4144 .par = (const uint32_t[]){2},
4145 .windowed_register_op = 0x7,
4146 }, {
4147 .name = "subx8",
4148 .translate = translate_subx,
4149 .par = (const uint32_t[]){3},
4150 .windowed_register_op = 0x7,
4151 }, {
4152 .name = "syscall",
4153 .op_flags = XTENSA_OP_SYSCALL,
4154 }, {
4155 .name = "umul.aa.hh",
4156 .translate = translate_mac16,
4157 .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_HH, 0},
4158 .windowed_register_op = 0x3,
4159 }, {
4160 .name = "umul.aa.hl",
4161 .translate = translate_mac16,
4162 .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_HL, 0},
4163 .windowed_register_op = 0x3,
4164 }, {
4165 .name = "umul.aa.lh",
4166 .translate = translate_mac16,
4167 .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_LH, 0},
4168 .windowed_register_op = 0x3,
4169 }, {
4170 .name = "umul.aa.ll",
4171 .translate = translate_mac16,
4172 .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_LL, 0},
4173 .windowed_register_op = 0x3,
4174 }, {
4175 .name = "waiti",
4176 .translate = translate_waiti,
4177 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4178 }, {
4179 .name = "wdtlb",
4180 .translate = translate_wtlb,
4181 .par = (const uint32_t[]){true},
4182 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
4183 .windowed_register_op = 0x3,
4184 }, {
4185 .name = "wer",
4186 .translate = translate_wer,
4187 .op_flags = XTENSA_OP_PRIVILEGED,
4188 .windowed_register_op = 0x3,
4189 }, {
4190 .name = "witlb",
4191 .translate = translate_wtlb,
4192 .par = (const uint32_t[]){false},
4193 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
4194 .windowed_register_op = 0x3,
4195 }, {
4196 .name = "wrmsk_expstate",
4197 .translate = translate_wrmsk_expstate,
4198 .windowed_register_op = 0x3,
4199 }, {
4200 .name = "wsr.176",
4201 .translate = translate_wsr,
4202 .test_ill = test_ill_wsr,
4203 .par = (const uint32_t[]){176},
4204 .op_flags = XTENSA_OP_PRIVILEGED,
4205 .windowed_register_op = 0x1,
4206 }, {
4207 .name = "wsr.208",
4208 .translate = translate_wsr,
4209 .test_ill = test_ill_wsr,
4210 .par = (const uint32_t[]){208},
4211 .op_flags = XTENSA_OP_PRIVILEGED,
4212 .windowed_register_op = 0x1,
4213 }, {
4214 .name = "wsr.acchi",
4215 .translate = translate_wsr,
4216 .test_ill = test_ill_wsr,
4217 .par = (const uint32_t[]){ACCHI},
4218 .windowed_register_op = 0x1,
4219 }, {
4220 .name = "wsr.acclo",
4221 .translate = translate_wsr,
4222 .test_ill = test_ill_wsr,
4223 .par = (const uint32_t[]){ACCLO},
4224 .windowed_register_op = 0x1,
4225 }, {
4226 .name = "wsr.atomctl",
4227 .translate = translate_wsr,
4228 .test_ill = test_ill_wsr,
4229 .par = (const uint32_t[]){ATOMCTL},
4230 .op_flags = XTENSA_OP_PRIVILEGED,
4231 .windowed_register_op = 0x1,
4232 }, {
4233 .name = "wsr.br",
4234 .translate = translate_wsr,
4235 .test_ill = test_ill_wsr,
4236 .par = (const uint32_t[]){BR},
4237 .windowed_register_op = 0x1,
4238 }, {
4239 .name = "wsr.cacheattr",
4240 .translate = translate_wsr,
4241 .test_ill = test_ill_wsr,
4242 .par = (const uint32_t[]){CACHEATTR},
4243 .op_flags = XTENSA_OP_PRIVILEGED,
4244 .windowed_register_op = 0x1,
4245 }, {
4246 .name = "wsr.ccompare0",
4247 .translate = translate_wsr,
4248 .test_ill = test_ill_wsr,
4249 .par = (const uint32_t[]){CCOMPARE},
4250 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4251 .windowed_register_op = 0x1,
4252 }, {
4253 .name = "wsr.ccompare1",
4254 .translate = translate_wsr,
4255 .test_ill = test_ill_wsr,
4256 .par = (const uint32_t[]){CCOMPARE + 1},
4257 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4258 .windowed_register_op = 0x1,
4259 }, {
4260 .name = "wsr.ccompare2",
4261 .translate = translate_wsr,
4262 .test_ill = test_ill_wsr,
4263 .par = (const uint32_t[]){CCOMPARE + 2},
4264 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4265 .windowed_register_op = 0x1,
4266 }, {
4267 .name = "wsr.ccount",
4268 .translate = translate_wsr,
4269 .test_ill = test_ill_wsr,
4270 .par = (const uint32_t[]){CCOUNT},
4271 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4272 .windowed_register_op = 0x1,
4273 }, {
4274 .name = "wsr.configid0",
4275 .translate = translate_wsr,
4276 .test_ill = test_ill_wsr,
4277 .par = (const uint32_t[]){CONFIGID0},
4278 .op_flags = XTENSA_OP_PRIVILEGED,
4279 .windowed_register_op = 0x1,
4280 }, {
4281 .name = "wsr.configid1",
4282 .translate = translate_wsr,
4283 .test_ill = test_ill_wsr,
4284 .par = (const uint32_t[]){CONFIGID1},
4285 .op_flags = XTENSA_OP_PRIVILEGED,
4286 .windowed_register_op = 0x1,
4287 }, {
4288 .name = "wsr.cpenable",
4289 .translate = translate_wsr,
4290 .test_ill = test_ill_wsr,
4291 .par = (const uint32_t[]){CPENABLE},
4292 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
4293 .windowed_register_op = 0x1,
4294 }, {
4295 .name = "wsr.dbreaka0",
4296 .translate = translate_wsr,
4297 .test_ill = test_ill_wsr,
4298 .par = (const uint32_t[]){DBREAKA},
4299 .op_flags = XTENSA_OP_PRIVILEGED,
4300 .windowed_register_op = 0x1,
4301 }, {
4302 .name = "wsr.dbreaka1",
4303 .translate = translate_wsr,
4304 .test_ill = test_ill_wsr,
4305 .par = (const uint32_t[]){DBREAKA + 1},
4306 .op_flags = XTENSA_OP_PRIVILEGED,
4307 .windowed_register_op = 0x1,
4308 }, {
4309 .name = "wsr.dbreakc0",
4310 .translate = translate_wsr,
4311 .test_ill = test_ill_wsr,
4312 .par = (const uint32_t[]){DBREAKC},
4313 .op_flags = XTENSA_OP_PRIVILEGED,
4314 .windowed_register_op = 0x1,
4315 }, {
4316 .name = "wsr.dbreakc1",
4317 .translate = translate_wsr,
4318 .test_ill = test_ill_wsr,
4319 .par = (const uint32_t[]){DBREAKC + 1},
4320 .op_flags = XTENSA_OP_PRIVILEGED,
4321 .windowed_register_op = 0x1,
4322 }, {
4323 .name = "wsr.ddr",
4324 .translate = translate_wsr,
4325 .test_ill = test_ill_wsr,
4326 .par = (const uint32_t[]){DDR},
4327 .op_flags = XTENSA_OP_PRIVILEGED,
4328 .windowed_register_op = 0x1,
4329 }, {
4330 .name = "wsr.debugcause",
4331 .translate = translate_wsr,
4332 .test_ill = test_ill_wsr,
4333 .par = (const uint32_t[]){DEBUGCAUSE},
4334 .op_flags = XTENSA_OP_PRIVILEGED,
4335 .windowed_register_op = 0x1,
4336 }, {
4337 .name = "wsr.depc",
4338 .translate = translate_wsr,
4339 .test_ill = test_ill_wsr,
4340 .par = (const uint32_t[]){DEPC},
4341 .op_flags = XTENSA_OP_PRIVILEGED,
4342 .windowed_register_op = 0x1,
4343 }, {
4344 .name = "wsr.dtlbcfg",
4345 .translate = translate_wsr,
4346 .test_ill = test_ill_wsr,
4347 .par = (const uint32_t[]){DTLBCFG},
4348 .op_flags = XTENSA_OP_PRIVILEGED,
4349 .windowed_register_op = 0x1,
4350 }, {
4351 .name = "wsr.epc1",
4352 .translate = translate_wsr,
4353 .test_ill = test_ill_wsr,
4354 .par = (const uint32_t[]){EPC1},
4355 .op_flags = XTENSA_OP_PRIVILEGED,
4356 .windowed_register_op = 0x1,
4357 }, {
4358 .name = "wsr.epc2",
4359 .translate = translate_wsr,
4360 .test_ill = test_ill_wsr,
4361 .par = (const uint32_t[]){EPC1 + 1},
4362 .op_flags = XTENSA_OP_PRIVILEGED,
4363 .windowed_register_op = 0x1,
4364 }, {
4365 .name = "wsr.epc3",
4366 .translate = translate_wsr,
4367 .test_ill = test_ill_wsr,
4368 .par = (const uint32_t[]){EPC1 + 2},
4369 .op_flags = XTENSA_OP_PRIVILEGED,
4370 .windowed_register_op = 0x1,
4371 }, {
4372 .name = "wsr.epc4",
4373 .translate = translate_wsr,
4374 .test_ill = test_ill_wsr,
4375 .par = (const uint32_t[]){EPC1 + 3},
4376 .op_flags = XTENSA_OP_PRIVILEGED,
4377 .windowed_register_op = 0x1,
4378 }, {
4379 .name = "wsr.epc5",
4380 .translate = translate_wsr,
4381 .test_ill = test_ill_wsr,
4382 .par = (const uint32_t[]){EPC1 + 4},
4383 .op_flags = XTENSA_OP_PRIVILEGED,
4384 .windowed_register_op = 0x1,
4385 }, {
4386 .name = "wsr.epc6",
4387 .translate = translate_wsr,
4388 .test_ill = test_ill_wsr,
4389 .par = (const uint32_t[]){EPC1 + 5},
4390 .op_flags = XTENSA_OP_PRIVILEGED,
4391 .windowed_register_op = 0x1,
4392 }, {
4393 .name = "wsr.epc7",
4394 .translate = translate_wsr,
4395 .test_ill = test_ill_wsr,
4396 .par = (const uint32_t[]){EPC1 + 6},
4397 .op_flags = XTENSA_OP_PRIVILEGED,
4398 .windowed_register_op = 0x1,
4399 }, {
4400 .name = "wsr.eps2",
4401 .translate = translate_wsr,
4402 .test_ill = test_ill_wsr,
4403 .par = (const uint32_t[]){EPS2},
4404 .op_flags = XTENSA_OP_PRIVILEGED,
4405 .windowed_register_op = 0x1,
4406 }, {
4407 .name = "wsr.eps3",
4408 .translate = translate_wsr,
4409 .test_ill = test_ill_wsr,
4410 .par = (const uint32_t[]){EPS2 + 1},
4411 .op_flags = XTENSA_OP_PRIVILEGED,
4412 .windowed_register_op = 0x1,
4413 }, {
4414 .name = "wsr.eps4",
4415 .translate = translate_wsr,
4416 .test_ill = test_ill_wsr,
4417 .par = (const uint32_t[]){EPS2 + 2},
4418 .op_flags = XTENSA_OP_PRIVILEGED,
4419 .windowed_register_op = 0x1,
4420 }, {
4421 .name = "wsr.eps5",
4422 .translate = translate_wsr,
4423 .test_ill = test_ill_wsr,
4424 .par = (const uint32_t[]){EPS2 + 3},
4425 .op_flags = XTENSA_OP_PRIVILEGED,
4426 .windowed_register_op = 0x1,
4427 }, {
4428 .name = "wsr.eps6",
4429 .translate = translate_wsr,
4430 .test_ill = test_ill_wsr,
4431 .par = (const uint32_t[]){EPS2 + 4},
4432 .op_flags = XTENSA_OP_PRIVILEGED,
4433 .windowed_register_op = 0x1,
4434 }, {
4435 .name = "wsr.eps7",
4436 .translate = translate_wsr,
4437 .test_ill = test_ill_wsr,
4438 .par = (const uint32_t[]){EPS2 + 5},
4439 .op_flags = XTENSA_OP_PRIVILEGED,
4440 .windowed_register_op = 0x1,
4441 }, {
4442 .name = "wsr.exccause",
4443 .translate = translate_wsr,
4444 .test_ill = test_ill_wsr,
4445 .par = (const uint32_t[]){EXCCAUSE},
4446 .op_flags = XTENSA_OP_PRIVILEGED,
4447 .windowed_register_op = 0x1,
4448 }, {
4449 .name = "wsr.excsave1",
4450 .translate = translate_wsr,
4451 .test_ill = test_ill_wsr,
4452 .par = (const uint32_t[]){EXCSAVE1},
4453 .op_flags = XTENSA_OP_PRIVILEGED,
4454 .windowed_register_op = 0x1,
4455 }, {
4456 .name = "wsr.excsave2",
4457 .translate = translate_wsr,
4458 .test_ill = test_ill_wsr,
4459 .par = (const uint32_t[]){EXCSAVE1 + 1},
4460 .op_flags = XTENSA_OP_PRIVILEGED,
4461 .windowed_register_op = 0x1,
4462 }, {
4463 .name = "wsr.excsave3",
4464 .translate = translate_wsr,
4465 .test_ill = test_ill_wsr,
4466 .par = (const uint32_t[]){EXCSAVE1 + 2},
4467 .op_flags = XTENSA_OP_PRIVILEGED,
4468 .windowed_register_op = 0x1,
4469 }, {
4470 .name = "wsr.excsave4",
4471 .translate = translate_wsr,
4472 .test_ill = test_ill_wsr,
4473 .par = (const uint32_t[]){EXCSAVE1 + 3},
4474 .op_flags = XTENSA_OP_PRIVILEGED,
4475 .windowed_register_op = 0x1,
4476 }, {
4477 .name = "wsr.excsave5",
4478 .translate = translate_wsr,
4479 .test_ill = test_ill_wsr,
4480 .par = (const uint32_t[]){EXCSAVE1 + 4},
4481 .op_flags = XTENSA_OP_PRIVILEGED,
4482 .windowed_register_op = 0x1,
4483 }, {
4484 .name = "wsr.excsave6",
4485 .translate = translate_wsr,
4486 .test_ill = test_ill_wsr,
4487 .par = (const uint32_t[]){EXCSAVE1 + 5},
4488 .op_flags = XTENSA_OP_PRIVILEGED,
4489 .windowed_register_op = 0x1,
4490 }, {
4491 .name = "wsr.excsave7",
4492 .translate = translate_wsr,
4493 .test_ill = test_ill_wsr,
4494 .par = (const uint32_t[]){EXCSAVE1 + 6},
4495 .op_flags = XTENSA_OP_PRIVILEGED,
4496 .windowed_register_op = 0x1,
4497 }, {
4498 .name = "wsr.excvaddr",
4499 .translate = translate_wsr,
4500 .test_ill = test_ill_wsr,
4501 .par = (const uint32_t[]){EXCVADDR},
4502 .op_flags = XTENSA_OP_PRIVILEGED,
4503 .windowed_register_op = 0x1,
4504 }, {
4505 .name = "wsr.ibreaka0",
4506 .translate = translate_wsr,
4507 .test_ill = test_ill_wsr,
4508 .par = (const uint32_t[]){IBREAKA},
4509 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4510 .windowed_register_op = 0x1,
4511 }, {
4512 .name = "wsr.ibreaka1",
4513 .translate = translate_wsr,
4514 .test_ill = test_ill_wsr,
4515 .par = (const uint32_t[]){IBREAKA + 1},
4516 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4517 .windowed_register_op = 0x1,
4518 }, {
4519 .name = "wsr.ibreakenable",
4520 .translate = translate_wsr,
4521 .test_ill = test_ill_wsr,
4522 .par = (const uint32_t[]){IBREAKENABLE},
4523 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4524 .windowed_register_op = 0x1,
4525 }, {
4526 .name = "wsr.icount",
4527 .translate = translate_wsr,
4528 .test_ill = test_ill_wsr,
4529 .par = (const uint32_t[]){ICOUNT},
4530 .op_flags = XTENSA_OP_PRIVILEGED,
4531 .windowed_register_op = 0x1,
4532 }, {
4533 .name = "wsr.icountlevel",
4534 .translate = translate_wsr,
4535 .test_ill = test_ill_wsr,
4536 .par = (const uint32_t[]){ICOUNTLEVEL},
4537 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
4538 .windowed_register_op = 0x1,
4539 }, {
4540 .name = "wsr.intclear",
4541 .translate = translate_wsr,
4542 .test_ill = test_ill_wsr,
4543 .par = (const uint32_t[]){INTCLEAR},
4544 .op_flags =
4545 XTENSA_OP_PRIVILEGED |
4546 XTENSA_OP_EXIT_TB_0 |
4547 XTENSA_OP_CHECK_INTERRUPTS,
4548 .windowed_register_op = 0x1,
4549 }, {
4550 .name = "wsr.intenable",
4551 .translate = translate_wsr,
4552 .test_ill = test_ill_wsr,
4553 .par = (const uint32_t[]){INTENABLE},
4554 .op_flags =
4555 XTENSA_OP_PRIVILEGED |
4556 XTENSA_OP_EXIT_TB_0 |
4557 XTENSA_OP_CHECK_INTERRUPTS,
4558 .windowed_register_op = 0x1,
4559 }, {
4560 .name = "wsr.interrupt",
4561 .translate = translate_wsr,
4562 .test_ill = test_ill_wsr,
4563 .par = (const uint32_t[]){INTSET},
4564 .op_flags =
4565 XTENSA_OP_PRIVILEGED |
4566 XTENSA_OP_EXIT_TB_0 |
4567 XTENSA_OP_CHECK_INTERRUPTS,
4568 .windowed_register_op = 0x1,
4569 }, {
4570 .name = "wsr.intset",
4571 .translate = translate_wsr,
4572 .test_ill = test_ill_wsr,
4573 .par = (const uint32_t[]){INTSET},
4574 .op_flags =
4575 XTENSA_OP_PRIVILEGED |
4576 XTENSA_OP_EXIT_TB_0 |
4577 XTENSA_OP_CHECK_INTERRUPTS,
4578 .windowed_register_op = 0x1,
4579 }, {
4580 .name = "wsr.itlbcfg",
4581 .translate = translate_wsr,
4582 .test_ill = test_ill_wsr,
4583 .par = (const uint32_t[]){ITLBCFG},
4584 .op_flags = XTENSA_OP_PRIVILEGED,
4585 .windowed_register_op = 0x1,
4586 }, {
4587 .name = "wsr.lbeg",
4588 .translate = translate_wsr,
4589 .test_ill = test_ill_wsr,
4590 .par = (const uint32_t[]){LBEG},
4591 .op_flags = XTENSA_OP_EXIT_TB_M1,
4592 .windowed_register_op = 0x1,
4593 }, {
4594 .name = "wsr.lcount",
4595 .translate = translate_wsr,
4596 .test_ill = test_ill_wsr,
4597 .par = (const uint32_t[]){LCOUNT},
4598 .windowed_register_op = 0x1,
4599 }, {
4600 .name = "wsr.lend",
4601 .translate = translate_wsr,
4602 .test_ill = test_ill_wsr,
4603 .par = (const uint32_t[]){LEND},
4604 .op_flags = XTENSA_OP_EXIT_TB_M1,
4605 .windowed_register_op = 0x1,
4606 }, {
4607 .name = "wsr.litbase",
4608 .translate = translate_wsr,
4609 .test_ill = test_ill_wsr,
4610 .par = (const uint32_t[]){LITBASE},
4611 .op_flags = XTENSA_OP_EXIT_TB_M1,
4612 .windowed_register_op = 0x1,
4613 }, {
4614 .name = "wsr.m0",
4615 .translate = translate_wsr,
4616 .test_ill = test_ill_wsr,
4617 .par = (const uint32_t[]){MR},
4618 .windowed_register_op = 0x1,
4619 }, {
4620 .name = "wsr.m1",
4621 .translate = translate_wsr,
4622 .test_ill = test_ill_wsr,
4623 .par = (const uint32_t[]){MR + 1},
4624 .windowed_register_op = 0x1,
4625 }, {
4626 .name = "wsr.m2",
4627 .translate = translate_wsr,
4628 .test_ill = test_ill_wsr,
4629 .par = (const uint32_t[]){MR + 2},
4630 .windowed_register_op = 0x1,
4631 }, {
4632 .name = "wsr.m3",
4633 .translate = translate_wsr,
4634 .test_ill = test_ill_wsr,
4635 .par = (const uint32_t[]){MR + 3},
4636 .windowed_register_op = 0x1,
4637 }, {
4638 .name = "wsr.memctl",
4639 .translate = translate_wsr,
4640 .test_ill = test_ill_wsr,
4641 .par = (const uint32_t[]){MEMCTL},
4642 .op_flags = XTENSA_OP_PRIVILEGED,
4643 .windowed_register_op = 0x1,
4644 }, {
4645 .name = "wsr.misc0",
4646 .translate = translate_wsr,
4647 .test_ill = test_ill_wsr,
4648 .par = (const uint32_t[]){MISC},
4649 .op_flags = XTENSA_OP_PRIVILEGED,
4650 .windowed_register_op = 0x1,
4651 }, {
4652 .name = "wsr.misc1",
4653 .translate = translate_wsr,
4654 .test_ill = test_ill_wsr,
4655 .par = (const uint32_t[]){MISC + 1},
4656 .op_flags = XTENSA_OP_PRIVILEGED,
4657 .windowed_register_op = 0x1,
4658 }, {
4659 .name = "wsr.misc2",
4660 .translate = translate_wsr,
4661 .test_ill = test_ill_wsr,
4662 .par = (const uint32_t[]){MISC + 2},
4663 .op_flags = XTENSA_OP_PRIVILEGED,
4664 .windowed_register_op = 0x1,
4665 }, {
4666 .name = "wsr.misc3",
4667 .translate = translate_wsr,
4668 .test_ill = test_ill_wsr,
4669 .par = (const uint32_t[]){MISC + 3},
4670 .op_flags = XTENSA_OP_PRIVILEGED,
4671 .windowed_register_op = 0x1,
4672 }, {
4673 .name = "wsr.mmid",
4674 .translate = translate_wsr,
4675 .test_ill = test_ill_wsr,
4676 .par = (const uint32_t[]){MMID},
4677 .op_flags = XTENSA_OP_PRIVILEGED,
4678 .windowed_register_op = 0x1,
4679 }, {
4680 .name = "wsr.prid",
4681 .translate = translate_wsr,
4682 .test_ill = test_ill_wsr,
4683 .par = (const uint32_t[]){PRID},
4684 .op_flags = XTENSA_OP_PRIVILEGED,
4685 .windowed_register_op = 0x1,
4686 }, {
4687 .name = "wsr.ps",
4688 .translate = translate_wsr,
4689 .test_ill = test_ill_wsr,
4690 .par = (const uint32_t[]){PS},
4691 .op_flags =
4692 XTENSA_OP_PRIVILEGED |
4693 XTENSA_OP_EXIT_TB_M1 |
4694 XTENSA_OP_CHECK_INTERRUPTS,
4695 .windowed_register_op = 0x1,
4696 }, {
4697 .name = "wsr.ptevaddr",
4698 .translate = translate_wsr,
4699 .test_ill = test_ill_wsr,
4700 .par = (const uint32_t[]){PTEVADDR},
4701 .op_flags = XTENSA_OP_PRIVILEGED,
4702 .windowed_register_op = 0x1,
4703 }, {
4704 .name = "wsr.rasid",
4705 .translate = translate_wsr,
4706 .test_ill = test_ill_wsr,
4707 .par = (const uint32_t[]){RASID},
4708 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
4709 .windowed_register_op = 0x1,
4710 }, {
4711 .name = "wsr.sar",
4712 .translate = translate_wsr,
4713 .test_ill = test_ill_wsr,
4714 .par = (const uint32_t[]){SAR},
4715 .windowed_register_op = 0x1,
4716 }, {
4717 .name = "wsr.scompare1",
4718 .translate = translate_wsr,
4719 .test_ill = test_ill_wsr,
4720 .par = (const uint32_t[]){SCOMPARE1},
4721 .windowed_register_op = 0x1,
4722 }, {
4723 .name = "wsr.vecbase",
4724 .translate = translate_wsr,
4725 .test_ill = test_ill_wsr,
4726 .par = (const uint32_t[]){VECBASE},
4727 .op_flags = XTENSA_OP_PRIVILEGED,
4728 .windowed_register_op = 0x1,
4729 }, {
4730 .name = "wsr.windowbase",
4731 .translate = translate_wsr,
4732 .test_ill = test_ill_wsr,
4733 .par = (const uint32_t[]){WINDOW_BASE},
4734 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
4735 .windowed_register_op = 0x1,
4736 }, {
4737 .name = "wsr.windowstart",
4738 .translate = translate_wsr,
4739 .test_ill = test_ill_wsr,
4740 .par = (const uint32_t[]){WINDOW_START},
4741 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
4742 .windowed_register_op = 0x1,
4743 }, {
4744 .name = "wur.expstate",
4745 .translate = translate_wur,
4746 .par = (const uint32_t[]){EXPSTATE},
4747 .windowed_register_op = 0x1,
4748 }, {
4749 .name = "wur.fcr",
4750 .translate = translate_wur,
4751 .par = (const uint32_t[]){FCR},
4752 .windowed_register_op = 0x1,
4753 .coprocessor = 0x1,
4754 }, {
4755 .name = "wur.fsr",
4756 .translate = translate_wur,
4757 .par = (const uint32_t[]){FSR},
4758 .windowed_register_op = 0x1,
4759 .coprocessor = 0x1,
4760 }, {
4761 .name = "wur.threadptr",
4762 .translate = translate_wur,
4763 .par = (const uint32_t[]){THREADPTR},
4764 .windowed_register_op = 0x1,
4765 }, {
4766 .name = "xor",
4767 .translate = translate_xor,
4768 .windowed_register_op = 0x7,
4769 }, {
4770 .name = "xorb",
4771 .translate = translate_boolean,
4772 .par = (const uint32_t[]){BOOLEAN_XOR},
4773 }, {
4774 .name = "xsr.176",
4775 .translate = translate_xsr,
4776 .test_ill = test_ill_xsr,
4777 .par = (const uint32_t[]){176},
4778 .op_flags = XTENSA_OP_PRIVILEGED,
4779 .windowed_register_op = 0x1,
4780 }, {
4781 .name = "xsr.208",
4782 .translate = translate_xsr,
4783 .test_ill = test_ill_xsr,
4784 .par = (const uint32_t[]){208},
4785 .op_flags = XTENSA_OP_PRIVILEGED,
4786 .windowed_register_op = 0x1,
4787 }, {
4788 .name = "xsr.acchi",
4789 .translate = translate_xsr,
4790 .test_ill = test_ill_xsr,
4791 .par = (const uint32_t[]){ACCHI},
4792 .windowed_register_op = 0x1,
4793 }, {
4794 .name = "xsr.acclo",
4795 .translate = translate_xsr,
4796 .test_ill = test_ill_xsr,
4797 .par = (const uint32_t[]){ACCLO},
4798 .windowed_register_op = 0x1,
4799 }, {
4800 .name = "xsr.atomctl",
4801 .translate = translate_xsr,
4802 .test_ill = test_ill_xsr,
4803 .par = (const uint32_t[]){ATOMCTL},
4804 .op_flags = XTENSA_OP_PRIVILEGED,
4805 .windowed_register_op = 0x1,
4806 }, {
4807 .name = "xsr.br",
4808 .translate = translate_xsr,
4809 .test_ill = test_ill_xsr,
4810 .par = (const uint32_t[]){BR},
4811 .windowed_register_op = 0x1,
4812 }, {
4813 .name = "xsr.cacheattr",
4814 .translate = translate_xsr,
4815 .test_ill = test_ill_xsr,
4816 .par = (const uint32_t[]){CACHEATTR},
4817 .op_flags = XTENSA_OP_PRIVILEGED,
4818 .windowed_register_op = 0x1,
4819 }, {
4820 .name = "xsr.ccompare0",
4821 .translate = translate_xsr,
4822 .test_ill = test_ill_xsr,
4823 .par = (const uint32_t[]){CCOMPARE},
4824 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4825 .windowed_register_op = 0x1,
4826 }, {
4827 .name = "xsr.ccompare1",
4828 .translate = translate_xsr,
4829 .test_ill = test_ill_xsr,
4830 .par = (const uint32_t[]){CCOMPARE + 1},
4831 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4832 .windowed_register_op = 0x1,
4833 }, {
4834 .name = "xsr.ccompare2",
4835 .translate = translate_xsr,
4836 .test_ill = test_ill_xsr,
4837 .par = (const uint32_t[]){CCOMPARE + 2},
4838 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4839 .windowed_register_op = 0x1,
4840 }, {
4841 .name = "xsr.ccount",
4842 .translate = translate_xsr,
4843 .test_ill = test_ill_xsr,
4844 .par = (const uint32_t[]){CCOUNT},
4845 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4846 .windowed_register_op = 0x1,
4847 }, {
4848 .name = "xsr.configid0",
4849 .translate = translate_xsr,
4850 .test_ill = test_ill_xsr,
4851 .par = (const uint32_t[]){CONFIGID0},
4852 .op_flags = XTENSA_OP_PRIVILEGED,
4853 .windowed_register_op = 0x1,
4854 }, {
4855 .name = "xsr.configid1",
4856 .translate = translate_xsr,
4857 .test_ill = test_ill_xsr,
4858 .par = (const uint32_t[]){CONFIGID1},
4859 .op_flags = XTENSA_OP_PRIVILEGED,
4860 .windowed_register_op = 0x1,
4861 }, {
4862 .name = "xsr.cpenable",
4863 .translate = translate_xsr,
4864 .test_ill = test_ill_xsr,
4865 .par = (const uint32_t[]){CPENABLE},
4866 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
4867 .windowed_register_op = 0x1,
4868 }, {
4869 .name = "xsr.dbreaka0",
4870 .translate = translate_xsr,
4871 .test_ill = test_ill_xsr,
4872 .par = (const uint32_t[]){DBREAKA},
4873 .op_flags = XTENSA_OP_PRIVILEGED,
4874 .windowed_register_op = 0x1,
4875 }, {
4876 .name = "xsr.dbreaka1",
4877 .translate = translate_xsr,
4878 .test_ill = test_ill_xsr,
4879 .par = (const uint32_t[]){DBREAKA + 1},
4880 .op_flags = XTENSA_OP_PRIVILEGED,
4881 .windowed_register_op = 0x1,
4882 }, {
4883 .name = "xsr.dbreakc0",
4884 .translate = translate_xsr,
4885 .test_ill = test_ill_xsr,
4886 .par = (const uint32_t[]){DBREAKC},
4887 .op_flags = XTENSA_OP_PRIVILEGED,
4888 .windowed_register_op = 0x1,
4889 }, {
4890 .name = "xsr.dbreakc1",
4891 .translate = translate_xsr,
4892 .test_ill = test_ill_xsr,
4893 .par = (const uint32_t[]){DBREAKC + 1},
4894 .op_flags = XTENSA_OP_PRIVILEGED,
4895 .windowed_register_op = 0x1,
4896 }, {
4897 .name = "xsr.ddr",
4898 .translate = translate_xsr,
4899 .test_ill = test_ill_xsr,
4900 .par = (const uint32_t[]){DDR},
4901 .op_flags = XTENSA_OP_PRIVILEGED,
4902 .windowed_register_op = 0x1,
4903 }, {
4904 .name = "xsr.debugcause",
4905 .translate = translate_xsr,
4906 .test_ill = test_ill_xsr,
4907 .par = (const uint32_t[]){DEBUGCAUSE},
4908 .op_flags = XTENSA_OP_PRIVILEGED,
4909 .windowed_register_op = 0x1,
4910 }, {
4911 .name = "xsr.depc",
4912 .translate = translate_xsr,
4913 .test_ill = test_ill_xsr,
4914 .par = (const uint32_t[]){DEPC},
4915 .op_flags = XTENSA_OP_PRIVILEGED,
4916 .windowed_register_op = 0x1,
4917 }, {
4918 .name = "xsr.dtlbcfg",
4919 .translate = translate_xsr,
4920 .test_ill = test_ill_xsr,
4921 .par = (const uint32_t[]){DTLBCFG},
4922 .op_flags = XTENSA_OP_PRIVILEGED,
4923 .windowed_register_op = 0x1,
4924 }, {
4925 .name = "xsr.epc1",
4926 .translate = translate_xsr,
4927 .test_ill = test_ill_xsr,
4928 .par = (const uint32_t[]){EPC1},
4929 .op_flags = XTENSA_OP_PRIVILEGED,
4930 .windowed_register_op = 0x1,
4931 }, {
4932 .name = "xsr.epc2",
4933 .translate = translate_xsr,
4934 .test_ill = test_ill_xsr,
4935 .par = (const uint32_t[]){EPC1 + 1},
4936 .op_flags = XTENSA_OP_PRIVILEGED,
4937 .windowed_register_op = 0x1,
4938 }, {
4939 .name = "xsr.epc3",
4940 .translate = translate_xsr,
4941 .test_ill = test_ill_xsr,
4942 .par = (const uint32_t[]){EPC1 + 2},
4943 .op_flags = XTENSA_OP_PRIVILEGED,
4944 .windowed_register_op = 0x1,
4945 }, {
4946 .name = "xsr.epc4",
4947 .translate = translate_xsr,
4948 .test_ill = test_ill_xsr,
4949 .par = (const uint32_t[]){EPC1 + 3},
4950 .op_flags = XTENSA_OP_PRIVILEGED,
4951 .windowed_register_op = 0x1,
4952 }, {
4953 .name = "xsr.epc5",
4954 .translate = translate_xsr,
4955 .test_ill = test_ill_xsr,
4956 .par = (const uint32_t[]){EPC1 + 4},
4957 .op_flags = XTENSA_OP_PRIVILEGED,
4958 .windowed_register_op = 0x1,
4959 }, {
4960 .name = "xsr.epc6",
4961 .translate = translate_xsr,
4962 .test_ill = test_ill_xsr,
4963 .par = (const uint32_t[]){EPC1 + 5},
4964 .op_flags = XTENSA_OP_PRIVILEGED,
4965 .windowed_register_op = 0x1,
4966 }, {
4967 .name = "xsr.epc7",
4968 .translate = translate_xsr,
4969 .test_ill = test_ill_xsr,
4970 .par = (const uint32_t[]){EPC1 + 6},
4971 .op_flags = XTENSA_OP_PRIVILEGED,
4972 .windowed_register_op = 0x1,
4973 }, {
4974 .name = "xsr.eps2",
4975 .translate = translate_xsr,
4976 .test_ill = test_ill_xsr,
4977 .par = (const uint32_t[]){EPS2},
4978 .op_flags = XTENSA_OP_PRIVILEGED,
4979 .windowed_register_op = 0x1,
4980 }, {
4981 .name = "xsr.eps3",
4982 .translate = translate_xsr,
4983 .test_ill = test_ill_xsr,
4984 .par = (const uint32_t[]){EPS2 + 1},
4985 .op_flags = XTENSA_OP_PRIVILEGED,
4986 .windowed_register_op = 0x1,
4987 }, {
4988 .name = "xsr.eps4",
4989 .translate = translate_xsr,
4990 .test_ill = test_ill_xsr,
4991 .par = (const uint32_t[]){EPS2 + 2},
4992 .op_flags = XTENSA_OP_PRIVILEGED,
4993 .windowed_register_op = 0x1,
4994 }, {
4995 .name = "xsr.eps5",
4996 .translate = translate_xsr,
4997 .test_ill = test_ill_xsr,
4998 .par = (const uint32_t[]){EPS2 + 3},
4999 .op_flags = XTENSA_OP_PRIVILEGED,
5000 .windowed_register_op = 0x1,
5001 }, {
5002 .name = "xsr.eps6",
5003 .translate = translate_xsr,
5004 .test_ill = test_ill_xsr,
5005 .par = (const uint32_t[]){EPS2 + 4},
5006 .op_flags = XTENSA_OP_PRIVILEGED,
5007 .windowed_register_op = 0x1,
5008 }, {
5009 .name = "xsr.eps7",
5010 .translate = translate_xsr,
5011 .test_ill = test_ill_xsr,
5012 .par = (const uint32_t[]){EPS2 + 5},
5013 .op_flags = XTENSA_OP_PRIVILEGED,
5014 .windowed_register_op = 0x1,
5015 }, {
5016 .name = "xsr.exccause",
5017 .translate = translate_xsr,
5018 .test_ill = test_ill_xsr,
5019 .par = (const uint32_t[]){EXCCAUSE},
5020 .op_flags = XTENSA_OP_PRIVILEGED,
5021 .windowed_register_op = 0x1,
5022 }, {
5023 .name = "xsr.excsave1",
5024 .translate = translate_xsr,
5025 .test_ill = test_ill_xsr,
5026 .par = (const uint32_t[]){EXCSAVE1},
5027 .op_flags = XTENSA_OP_PRIVILEGED,
5028 .windowed_register_op = 0x1,
5029 }, {
5030 .name = "xsr.excsave2",
5031 .translate = translate_xsr,
5032 .test_ill = test_ill_xsr,
5033 .par = (const uint32_t[]){EXCSAVE1 + 1},
5034 .op_flags = XTENSA_OP_PRIVILEGED,
5035 .windowed_register_op = 0x1,
5036 }, {
5037 .name = "xsr.excsave3",
5038 .translate = translate_xsr,
5039 .test_ill = test_ill_xsr,
5040 .par = (const uint32_t[]){EXCSAVE1 + 2},
5041 .op_flags = XTENSA_OP_PRIVILEGED,
5042 .windowed_register_op = 0x1,
5043 }, {
5044 .name = "xsr.excsave4",
5045 .translate = translate_xsr,
5046 .test_ill = test_ill_xsr,
5047 .par = (const uint32_t[]){EXCSAVE1 + 3},
5048 .op_flags = XTENSA_OP_PRIVILEGED,
5049 .windowed_register_op = 0x1,
5050 }, {
5051 .name = "xsr.excsave5",
5052 .translate = translate_xsr,
5053 .test_ill = test_ill_xsr,
5054 .par = (const uint32_t[]){EXCSAVE1 + 4},
5055 .op_flags = XTENSA_OP_PRIVILEGED,
5056 .windowed_register_op = 0x1,
5057 }, {
5058 .name = "xsr.excsave6",
5059 .translate = translate_xsr,
5060 .test_ill = test_ill_xsr,
5061 .par = (const uint32_t[]){EXCSAVE1 + 5},
5062 .op_flags = XTENSA_OP_PRIVILEGED,
5063 .windowed_register_op = 0x1,
5064 }, {
5065 .name = "xsr.excsave7",
5066 .translate = translate_xsr,
5067 .test_ill = test_ill_xsr,
5068 .par = (const uint32_t[]){EXCSAVE1 + 6},
5069 .op_flags = XTENSA_OP_PRIVILEGED,
5070 .windowed_register_op = 0x1,
5071 }, {
5072 .name = "xsr.excvaddr",
5073 .translate = translate_xsr,
5074 .test_ill = test_ill_xsr,
5075 .par = (const uint32_t[]){EXCVADDR},
5076 .op_flags = XTENSA_OP_PRIVILEGED,
5077 .windowed_register_op = 0x1,
5078 }, {
5079 .name = "xsr.ibreaka0",
5080 .translate = translate_xsr,
5081 .test_ill = test_ill_xsr,
5082 .par = (const uint32_t[]){IBREAKA},
5083 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5084 .windowed_register_op = 0x1,
5085 }, {
5086 .name = "xsr.ibreaka1",
5087 .translate = translate_xsr,
5088 .test_ill = test_ill_xsr,
5089 .par = (const uint32_t[]){IBREAKA + 1},
5090 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5091 .windowed_register_op = 0x1,
5092 }, {
5093 .name = "xsr.ibreakenable",
5094 .translate = translate_xsr,
5095 .test_ill = test_ill_xsr,
5096 .par = (const uint32_t[]){IBREAKENABLE},
5097 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5098 .windowed_register_op = 0x1,
5099 }, {
5100 .name = "xsr.icount",
5101 .translate = translate_xsr,
5102 .test_ill = test_ill_xsr,
5103 .par = (const uint32_t[]){ICOUNT},
5104 .op_flags = XTENSA_OP_PRIVILEGED,
5105 .windowed_register_op = 0x1,
5106 }, {
5107 .name = "xsr.icountlevel",
5108 .translate = translate_xsr,
5109 .test_ill = test_ill_xsr,
5110 .par = (const uint32_t[]){ICOUNTLEVEL},
5111 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
5112 .windowed_register_op = 0x1,
5113 }, {
5114 .name = "xsr.intclear",
5115 .translate = translate_xsr,
5116 .test_ill = test_ill_xsr,
5117 .par = (const uint32_t[]){INTCLEAR},
5118 .op_flags =
5119 XTENSA_OP_PRIVILEGED |
5120 XTENSA_OP_EXIT_TB_0 |
5121 XTENSA_OP_CHECK_INTERRUPTS,
5122 .windowed_register_op = 0x1,
5123 }, {
5124 .name = "xsr.intenable",
5125 .translate = translate_xsr,
5126 .test_ill = test_ill_xsr,
5127 .par = (const uint32_t[]){INTENABLE},
5128 .op_flags =
5129 XTENSA_OP_PRIVILEGED |
5130 XTENSA_OP_EXIT_TB_0 |
5131 XTENSA_OP_CHECK_INTERRUPTS,
5132 .windowed_register_op = 0x1,
5133 }, {
5134 .name = "xsr.interrupt",
5135 .translate = translate_xsr,
5136 .test_ill = test_ill_xsr,
5137 .par = (const uint32_t[]){INTSET},
5138 .op_flags =
5139 XTENSA_OP_PRIVILEGED |
5140 XTENSA_OP_EXIT_TB_0 |
5141 XTENSA_OP_CHECK_INTERRUPTS,
5142 .windowed_register_op = 0x1,
5143 }, {
5144 .name = "xsr.intset",
5145 .translate = translate_xsr,
5146 .test_ill = test_ill_xsr,
5147 .par = (const uint32_t[]){INTSET},
5148 .op_flags =
5149 XTENSA_OP_PRIVILEGED |
5150 XTENSA_OP_EXIT_TB_0 |
5151 XTENSA_OP_CHECK_INTERRUPTS,
5152 .windowed_register_op = 0x1,
5153 }, {
5154 .name = "xsr.itlbcfg",
5155 .translate = translate_xsr,
5156 .test_ill = test_ill_xsr,
5157 .par = (const uint32_t[]){ITLBCFG},
5158 .op_flags = XTENSA_OP_PRIVILEGED,
5159 .windowed_register_op = 0x1,
5160 }, {
5161 .name = "xsr.lbeg",
5162 .translate = translate_xsr,
5163 .test_ill = test_ill_xsr,
5164 .par = (const uint32_t[]){LBEG},
5165 .op_flags = XTENSA_OP_EXIT_TB_M1,
5166 .windowed_register_op = 0x1,
5167 }, {
5168 .name = "xsr.lcount",
5169 .translate = translate_xsr,
5170 .test_ill = test_ill_xsr,
5171 .par = (const uint32_t[]){LCOUNT},
5172 .windowed_register_op = 0x1,
5173 }, {
5174 .name = "xsr.lend",
5175 .translate = translate_xsr,
5176 .test_ill = test_ill_xsr,
5177 .par = (const uint32_t[]){LEND},
5178 .op_flags = XTENSA_OP_EXIT_TB_M1,
5179 .windowed_register_op = 0x1,
5180 }, {
5181 .name = "xsr.litbase",
5182 .translate = translate_xsr,
5183 .test_ill = test_ill_xsr,
5184 .par = (const uint32_t[]){LITBASE},
5185 .op_flags = XTENSA_OP_EXIT_TB_M1,
5186 .windowed_register_op = 0x1,
5187 }, {
5188 .name = "xsr.m0",
5189 .translate = translate_xsr,
5190 .test_ill = test_ill_xsr,
5191 .par = (const uint32_t[]){MR},
5192 .windowed_register_op = 0x1,
5193 }, {
5194 .name = "xsr.m1",
5195 .translate = translate_xsr,
5196 .test_ill = test_ill_xsr,
5197 .par = (const uint32_t[]){MR + 1},
5198 .windowed_register_op = 0x1,
5199 }, {
5200 .name = "xsr.m2",
5201 .translate = translate_xsr,
5202 .test_ill = test_ill_xsr,
5203 .par = (const uint32_t[]){MR + 2},
5204 .windowed_register_op = 0x1,
5205 }, {
5206 .name = "xsr.m3",
5207 .translate = translate_xsr,
5208 .test_ill = test_ill_xsr,
5209 .par = (const uint32_t[]){MR + 3},
5210 .windowed_register_op = 0x1,
5211 }, {
5212 .name = "xsr.memctl",
5213 .translate = translate_xsr,
5214 .test_ill = test_ill_xsr,
5215 .par = (const uint32_t[]){MEMCTL},
5216 .op_flags = XTENSA_OP_PRIVILEGED,
5217 .windowed_register_op = 0x1,
5218 }, {
5219 .name = "xsr.misc0",
5220 .translate = translate_xsr,
5221 .test_ill = test_ill_xsr,
5222 .par = (const uint32_t[]){MISC},
5223 .op_flags = XTENSA_OP_PRIVILEGED,
5224 .windowed_register_op = 0x1,
5225 }, {
5226 .name = "xsr.misc1",
5227 .translate = translate_xsr,
5228 .test_ill = test_ill_xsr,
5229 .par = (const uint32_t[]){MISC + 1},
5230 .op_flags = XTENSA_OP_PRIVILEGED,
5231 .windowed_register_op = 0x1,
5232 }, {
5233 .name = "xsr.misc2",
5234 .translate = translate_xsr,
5235 .test_ill = test_ill_xsr,
5236 .par = (const uint32_t[]){MISC + 2},
5237 .op_flags = XTENSA_OP_PRIVILEGED,
5238 .windowed_register_op = 0x1,
5239 }, {
5240 .name = "xsr.misc3",
5241 .translate = translate_xsr,
5242 .test_ill = test_ill_xsr,
5243 .par = (const uint32_t[]){MISC + 3},
5244 .op_flags = XTENSA_OP_PRIVILEGED,
5245 .windowed_register_op = 0x1,
5246 }, {
5247 .name = "xsr.prid",
5248 .translate = translate_xsr,
5249 .test_ill = test_ill_xsr,
5250 .par = (const uint32_t[]){PRID},
5251 .op_flags = XTENSA_OP_PRIVILEGED,
5252 .windowed_register_op = 0x1,
5253 }, {
5254 .name = "xsr.ps",
5255 .translate = translate_xsr,
5256 .test_ill = test_ill_xsr,
5257 .par = (const uint32_t[]){PS},
5258 .op_flags =
5259 XTENSA_OP_PRIVILEGED |
5260 XTENSA_OP_EXIT_TB_M1 |
5261 XTENSA_OP_CHECK_INTERRUPTS,
5262 .windowed_register_op = 0x1,
5263 }, {
5264 .name = "xsr.ptevaddr",
5265 .translate = translate_xsr,
5266 .test_ill = test_ill_xsr,
5267 .par = (const uint32_t[]){PTEVADDR},
5268 .op_flags = XTENSA_OP_PRIVILEGED,
5269 .windowed_register_op = 0x1,
5270 }, {
5271 .name = "xsr.rasid",
5272 .translate = translate_xsr,
5273 .test_ill = test_ill_xsr,
5274 .par = (const uint32_t[]){RASID},
5275 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
5276 .windowed_register_op = 0x1,
5277 }, {
5278 .name = "xsr.sar",
5279 .translate = translate_xsr,
5280 .test_ill = test_ill_xsr,
5281 .par = (const uint32_t[]){SAR},
5282 .windowed_register_op = 0x1,
5283 }, {
5284 .name = "xsr.scompare1",
5285 .translate = translate_xsr,
5286 .test_ill = test_ill_xsr,
5287 .par = (const uint32_t[]){SCOMPARE1},
5288 .windowed_register_op = 0x1,
5289 }, {
5290 .name = "xsr.vecbase",
5291 .translate = translate_xsr,
5292 .test_ill = test_ill_xsr,
5293 .par = (const uint32_t[]){VECBASE},
5294 .op_flags = XTENSA_OP_PRIVILEGED,
5295 .windowed_register_op = 0x1,
5296 }, {
5297 .name = "xsr.windowbase",
5298 .translate = translate_xsr,
5299 .test_ill = test_ill_xsr,
5300 .par = (const uint32_t[]){WINDOW_BASE},
5301 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
5302 .windowed_register_op = 0x1,
5303 }, {
5304 .name = "xsr.windowstart",
5305 .translate = translate_xsr,
5306 .test_ill = test_ill_xsr,
5307 .par = (const uint32_t[]){WINDOW_START},
5308 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
5309 .windowed_register_op = 0x1,
5310 },
5311 };
5312
5313 const XtensaOpcodeTranslators xtensa_core_opcodes = {
5314 .num_opcodes = ARRAY_SIZE(core_ops),
5315 .opcode = core_ops,
5316 };
5317
5318
5319 static void translate_abs_s(DisasContext *dc, const uint32_t arg[],
5320 const uint32_t par[])
5321 {
5322 gen_helper_abs_s(cpu_FR[arg[0]], cpu_FR[arg[1]]);
5323 }
5324
5325 static void translate_add_s(DisasContext *dc, const uint32_t arg[],
5326 const uint32_t par[])
5327 {
5328 gen_helper_add_s(cpu_FR[arg[0]], cpu_env,
5329 cpu_FR[arg[1]], cpu_FR[arg[2]]);
5330 }
5331
5332 enum {
5333 COMPARE_UN,
5334 COMPARE_OEQ,
5335 COMPARE_UEQ,
5336 COMPARE_OLT,
5337 COMPARE_ULT,
5338 COMPARE_OLE,
5339 COMPARE_ULE,
5340 };
5341
5342 static void translate_compare_s(DisasContext *dc, const uint32_t arg[],
5343 const uint32_t par[])
5344 {
5345 static void (* const helper[])(TCGv_env env, TCGv_i32 bit,
5346 TCGv_i32 s, TCGv_i32 t) = {
5347 [COMPARE_UN] = gen_helper_un_s,
5348 [COMPARE_OEQ] = gen_helper_oeq_s,
5349 [COMPARE_UEQ] = gen_helper_ueq_s,
5350 [COMPARE_OLT] = gen_helper_olt_s,
5351 [COMPARE_ULT] = gen_helper_ult_s,
5352 [COMPARE_OLE] = gen_helper_ole_s,
5353 [COMPARE_ULE] = gen_helper_ule_s,
5354 };
5355 TCGv_i32 bit = tcg_const_i32(1 << arg[0]);
5356
5357 helper[par[0]](cpu_env, bit, cpu_FR[arg[1]], cpu_FR[arg[2]]);
5358 tcg_temp_free(bit);
5359 }
5360
5361 static void translate_float_s(DisasContext *dc, const uint32_t arg[],
5362 const uint32_t par[])
5363 {
5364 TCGv_i32 scale = tcg_const_i32(-arg[2]);
5365
5366 if (par[0]) {
5367 gen_helper_uitof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale);
5368 } else {
5369 gen_helper_itof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale);
5370 }
5371 tcg_temp_free(scale);
5372 }
5373
5374 static void translate_ftoi_s(DisasContext *dc, const uint32_t arg[],
5375 const uint32_t par[])
5376 {
5377 TCGv_i32 rounding_mode = tcg_const_i32(par[0]);
5378 TCGv_i32 scale = tcg_const_i32(arg[2]);
5379
5380 if (par[1]) {
5381 gen_helper_ftoui(cpu_R[arg[0]], cpu_FR[arg[1]],
5382 rounding_mode, scale);
5383 } else {
5384 gen_helper_ftoi(cpu_R[arg[0]], cpu_FR[arg[1]],
5385 rounding_mode, scale);
5386 }
5387 tcg_temp_free(rounding_mode);
5388 tcg_temp_free(scale);
5389 }
5390
5391 static void translate_ldsti(DisasContext *dc, const uint32_t arg[],
5392 const uint32_t par[])
5393 {
5394 TCGv_i32 addr = tcg_temp_new_i32();
5395
5396 tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]);
5397 gen_load_store_alignment(dc, 2, addr, false);
5398 if (par[0]) {
5399 tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring);
5400 } else {
5401 tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring);
5402 }
5403 if (par[1]) {
5404 tcg_gen_mov_i32(cpu_R[arg[1]], addr);
5405 }
5406 tcg_temp_free(addr);
5407 }
5408
5409 static void translate_ldstx(DisasContext *dc, const uint32_t arg[],
5410 const uint32_t par[])
5411 {
5412 TCGv_i32 addr = tcg_temp_new_i32();
5413
5414 tcg_gen_add_i32(addr, cpu_R[arg[1]], cpu_R[arg[2]]);
5415 gen_load_store_alignment(dc, 2, addr, false);
5416 if (par[0]) {
5417 tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring);
5418 } else {
5419 tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring);
5420 }
5421 if (par[1]) {
5422 tcg_gen_mov_i32(cpu_R[arg[1]], addr);
5423 }
5424 tcg_temp_free(addr);
5425 }
5426
5427 static void translate_madd_s(DisasContext *dc, const uint32_t arg[],
5428 const uint32_t par[])
5429 {
5430 gen_helper_madd_s(cpu_FR[arg[0]], cpu_env,
5431 cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]);
5432 }
5433
5434 static void translate_mov_s(DisasContext *dc, const uint32_t arg[],
5435 const uint32_t par[])
5436 {
5437 tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_FR[arg[1]]);
5438 }
5439
5440 static void translate_movcond_s(DisasContext *dc, const uint32_t arg[],
5441 const uint32_t par[])
5442 {
5443 TCGv_i32 zero = tcg_const_i32(0);
5444
5445 tcg_gen_movcond_i32(par[0], cpu_FR[arg[0]],
5446 cpu_R[arg[2]], zero,
5447 cpu_FR[arg[1]], cpu_FR[arg[0]]);
5448 tcg_temp_free(zero);
5449 }
5450
5451 static void translate_movp_s(DisasContext *dc, const uint32_t arg[],
5452 const uint32_t par[])
5453 {
5454 TCGv_i32 zero = tcg_const_i32(0);
5455 TCGv_i32 tmp = tcg_temp_new_i32();
5456
5457 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2]);
5458 tcg_gen_movcond_i32(par[0],
5459 cpu_FR[arg[0]], tmp, zero,
5460 cpu_FR[arg[1]], cpu_FR[arg[0]]);
5461 tcg_temp_free(tmp);
5462 tcg_temp_free(zero);
5463 }
5464
5465 static void translate_mul_s(DisasContext *dc, const uint32_t arg[],
5466 const uint32_t par[])
5467 {
5468 gen_helper_mul_s(cpu_FR[arg[0]], cpu_env,
5469 cpu_FR[arg[1]], cpu_FR[arg[2]]);
5470 }
5471
5472 static void translate_msub_s(DisasContext *dc, const uint32_t arg[],
5473 const uint32_t par[])
5474 {
5475 gen_helper_msub_s(cpu_FR[arg[0]], cpu_env,
5476 cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]);
5477 }
5478
5479 static void translate_neg_s(DisasContext *dc, const uint32_t arg[],
5480 const uint32_t par[])
5481 {
5482 gen_helper_neg_s(cpu_FR[arg[0]], cpu_FR[arg[1]]);
5483 }
5484
5485 static void translate_rfr_s(DisasContext *dc, const uint32_t arg[],
5486 const uint32_t par[])
5487 {
5488 tcg_gen_mov_i32(cpu_R[arg[0]], cpu_FR[arg[1]]);
5489 }
5490
5491 static void translate_sub_s(DisasContext *dc, const uint32_t arg[],
5492 const uint32_t par[])
5493 {
5494 gen_helper_sub_s(cpu_FR[arg[0]], cpu_env,
5495 cpu_FR[arg[1]], cpu_FR[arg[2]]);
5496 }
5497
5498 static void translate_wfr_s(DisasContext *dc, const uint32_t arg[],
5499 const uint32_t par[])
5500 {
5501 tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_R[arg[1]]);
5502 }
5503
5504 static const XtensaOpcodeOps fpu2000_ops[] = {
5505 {
5506 .name = "abs.s",
5507 .translate = translate_abs_s,
5508 .coprocessor = 0x1,
5509 }, {
5510 .name = "add.s",
5511 .translate = translate_add_s,
5512 .coprocessor = 0x1,
5513 }, {
5514 .name = "ceil.s",
5515 .translate = translate_ftoi_s,
5516 .par = (const uint32_t[]){float_round_up, false},
5517 .windowed_register_op = 0x1,
5518 .coprocessor = 0x1,
5519 }, {
5520 .name = "float.s",
5521 .translate = translate_float_s,
5522 .par = (const uint32_t[]){false},
5523 .windowed_register_op = 0x2,
5524 .coprocessor = 0x1,
5525 }, {
5526 .name = "floor.s",
5527 .translate = translate_ftoi_s,
5528 .par = (const uint32_t[]){float_round_down, false},
5529 .windowed_register_op = 0x1,
5530 .coprocessor = 0x1,
5531 }, {
5532 .name = "lsi",
5533 .translate = translate_ldsti,
5534 .par = (const uint32_t[]){false, false},
5535 .windowed_register_op = 0x2,
5536 .coprocessor = 0x1,
5537 }, {
5538 .name = "lsiu",
5539 .translate = translate_ldsti,
5540 .par = (const uint32_t[]){false, true},
5541 .windowed_register_op = 0x2,
5542 .coprocessor = 0x1,
5543 }, {
5544 .name = "lsx",
5545 .translate = translate_ldstx,
5546 .par = (const uint32_t[]){false, false},
5547 .windowed_register_op = 0x6,
5548 .coprocessor = 0x1,
5549 }, {
5550 .name = "lsxu",
5551 .translate = translate_ldstx,
5552 .par = (const uint32_t[]){false, true},
5553 .windowed_register_op = 0x6,
5554 .coprocessor = 0x1,
5555 }, {
5556 .name = "madd.s",
5557 .translate = translate_madd_s,
5558 .coprocessor = 0x1,
5559 }, {
5560 .name = "mov.s",
5561 .translate = translate_mov_s,
5562 .coprocessor = 0x1,
5563 }, {
5564 .name = "moveqz.s",
5565 .translate = translate_movcond_s,
5566 .par = (const uint32_t[]){TCG_COND_EQ},
5567 .windowed_register_op = 0x4,
5568 .coprocessor = 0x1,
5569 }, {
5570 .name = "movf.s",
5571 .translate = translate_movp_s,
5572 .par = (const uint32_t[]){TCG_COND_EQ},
5573 .coprocessor = 0x1,
5574 }, {
5575 .name = "movgez.s",
5576 .translate = translate_movcond_s,
5577 .par = (const uint32_t[]){TCG_COND_GE},
5578 .windowed_register_op = 0x4,
5579 .coprocessor = 0x1,
5580 }, {
5581 .name = "movltz.s",
5582 .translate = translate_movcond_s,
5583 .par = (const uint32_t[]){TCG_COND_LT},
5584 .windowed_register_op = 0x4,
5585 .coprocessor = 0x1,
5586 }, {
5587 .name = "movnez.s",
5588 .translate = translate_movcond_s,
5589 .par = (const uint32_t[]){TCG_COND_NE},
5590 .windowed_register_op = 0x4,
5591 .coprocessor = 0x1,
5592 }, {
5593 .name = "movt.s",
5594 .translate = translate_movp_s,
5595 .par = (const uint32_t[]){TCG_COND_NE},
5596 .coprocessor = 0x1,
5597 }, {
5598 .name = "msub.s",
5599 .translate = translate_msub_s,
5600 .coprocessor = 0x1,
5601 }, {
5602 .name = "mul.s",
5603 .translate = translate_mul_s,
5604 .coprocessor = 0x1,
5605 }, {
5606 .name = "neg.s",
5607 .translate = translate_neg_s,
5608 .coprocessor = 0x1,
5609 }, {
5610 .name = "oeq.s",
5611 .translate = translate_compare_s,
5612 .par = (const uint32_t[]){COMPARE_OEQ},
5613 .coprocessor = 0x1,
5614 }, {
5615 .name = "ole.s",
5616 .translate = translate_compare_s,
5617 .par = (const uint32_t[]){COMPARE_OLE},
5618 .coprocessor = 0x1,
5619 }, {
5620 .name = "olt.s",
5621 .translate = translate_compare_s,
5622 .par = (const uint32_t[]){COMPARE_OLT},
5623 .coprocessor = 0x1,
5624 }, {
5625 .name = "rfr",
5626 .translate = translate_rfr_s,
5627 .windowed_register_op = 0x1,
5628 .coprocessor = 0x1,
5629 }, {
5630 .name = "round.s",
5631 .translate = translate_ftoi_s,
5632 .par = (const uint32_t[]){float_round_nearest_even, false},
5633 .windowed_register_op = 0x1,
5634 .coprocessor = 0x1,
5635 }, {
5636 .name = "ssi",
5637 .translate = translate_ldsti,
5638 .par = (const uint32_t[]){true, false},
5639 .windowed_register_op = 0x2,
5640 .coprocessor = 0x1,
5641 }, {
5642 .name = "ssiu",
5643 .translate = translate_ldsti,
5644 .par = (const uint32_t[]){true, true},
5645 .windowed_register_op = 0x2,
5646 .coprocessor = 0x1,
5647 }, {
5648 .name = "ssx",
5649 .translate = translate_ldstx,
5650 .par = (const uint32_t[]){true, false},
5651 .windowed_register_op = 0x6,
5652 .coprocessor = 0x1,
5653 }, {
5654 .name = "ssxu",
5655 .translate = translate_ldstx,
5656 .par = (const uint32_t[]){true, true},
5657 .windowed_register_op = 0x6,
5658 .coprocessor = 0x1,
5659 }, {
5660 .name = "sub.s",
5661 .translate = translate_sub_s,
5662 .coprocessor = 0x1,
5663 }, {
5664 .name = "trunc.s",
5665 .translate = translate_ftoi_s,
5666 .par = (const uint32_t[]){float_round_to_zero, false},
5667 .windowed_register_op = 0x1,
5668 .coprocessor = 0x1,
5669 }, {
5670 .name = "ueq.s",
5671 .translate = translate_compare_s,
5672 .par = (const uint32_t[]){COMPARE_UEQ},
5673 .coprocessor = 0x1,
5674 }, {
5675 .name = "ufloat.s",
5676 .translate = translate_float_s,
5677 .par = (const uint32_t[]){true},
5678 .windowed_register_op = 0x2,
5679 .coprocessor = 0x1,
5680 }, {
5681 .name = "ule.s",
5682 .translate = translate_compare_s,
5683 .par = (const uint32_t[]){COMPARE_ULE},
5684 .coprocessor = 0x1,
5685 }, {
5686 .name = "ult.s",
5687 .translate = translate_compare_s,
5688 .par = (const uint32_t[]){COMPARE_ULT},
5689 .coprocessor = 0x1,
5690 }, {
5691 .name = "un.s",
5692 .translate = translate_compare_s,
5693 .par = (const uint32_t[]){COMPARE_UN},
5694 .coprocessor = 0x1,
5695 }, {
5696 .name = "utrunc.s",
5697 .translate = translate_ftoi_s,
5698 .par = (const uint32_t[]){float_round_to_zero, true},
5699 .windowed_register_op = 0x1,
5700 .coprocessor = 0x1,
5701 }, {
5702 .name = "wfr",
5703 .translate = translate_wfr_s,
5704 .windowed_register_op = 0x2,
5705 .coprocessor = 0x1,
5706 },
5707 };
5708
5709 const XtensaOpcodeTranslators xtensa_fpu2000_opcodes = {
5710 .num_opcodes = ARRAY_SIZE(fpu2000_ops),
5711 .opcode = fpu2000_ops,
5712 };
AR7 emulation for QEMU