1 #include "qemu/osdep.h"
2 #include "target/arm/idau.h"
6 #include "exec/gdbstub.h"
7 #include "exec/helper-proto.h"
8 #include "qemu/host-utils.h"
9 #include "sysemu/arch_init.h"
10 #include "sysemu/sysemu.h"
11 #include "qemu/bitops.h"
12 #include "qemu/crc32c.h"
13 #include "exec/exec-all.h"
14 #include "exec/cpu_ldst.h"
16 #include <zlib.h> /* For crc32 */
17 #include "exec/semihost.h"
18 #include "sysemu/cpus.h"
19 #include "sysemu/kvm.h"
20 #include "fpu/softfloat.h"
21 #include "qemu/range.h"
23 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
25 #ifndef CONFIG_USER_ONLY
26 /* Cacheability and shareability attributes for a memory access */
27 typedef struct ARMCacheAttrs
{
28 unsigned int attrs
:8; /* as in the MAIR register encoding */
29 unsigned int shareability
:2; /* as in the SH field of the VMSAv8-64 PTEs */
32 static bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
33 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
34 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
35 target_ulong
*page_size
,
36 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
);
38 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
39 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
40 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
41 target_ulong
*page_size_ptr
,
42 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
);
44 /* Security attributes for an address, as returned by v8m_security_lookup. */
45 typedef struct V8M_SAttributes
{
46 bool subpage
; /* true if these attrs don't cover the whole TARGET_PAGE */
55 static void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
56 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
57 V8M_SAttributes
*sattrs
);
60 static void switch_mode(CPUARMState
*env
, int mode
);
62 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
66 /* VFP data registers are always little-endian. */
67 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
69 stq_le_p(buf
, *aa32_vfp_dreg(env
, reg
));
72 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
73 /* Aliases for Q regs. */
76 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
78 stq_le_p(buf
+ 8, q
[1]);
82 switch (reg
- nregs
) {
83 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
84 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
85 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
90 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
94 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
96 *aa32_vfp_dreg(env
, reg
) = ldq_le_p(buf
);
99 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
102 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
103 q
[0] = ldq_le_p(buf
);
104 q
[1] = ldq_le_p(buf
+ 8);
108 switch (reg
- nregs
) {
109 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
110 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
111 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
116 static int aarch64_fpu_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
120 /* 128 bit FP register */
122 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
124 stq_le_p(buf
+ 8, q
[1]);
129 stl_p(buf
, vfp_get_fpsr(env
));
133 stl_p(buf
, vfp_get_fpcr(env
));
140 static int aarch64_fpu_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
144 /* 128 bit FP register */
146 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
147 q
[0] = ldq_le_p(buf
);
148 q
[1] = ldq_le_p(buf
+ 8);
153 vfp_set_fpsr(env
, ldl_p(buf
));
157 vfp_set_fpcr(env
, ldl_p(buf
));
164 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
166 assert(ri
->fieldoffset
);
167 if (cpreg_field_is_64bit(ri
)) {
168 return CPREG_FIELD64(env
, ri
);
170 return CPREG_FIELD32(env
, ri
);
174 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
177 assert(ri
->fieldoffset
);
178 if (cpreg_field_is_64bit(ri
)) {
179 CPREG_FIELD64(env
, ri
) = value
;
181 CPREG_FIELD32(env
, ri
) = value
;
185 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
187 return (char *)env
+ ri
->fieldoffset
;
190 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
192 /* Raw read of a coprocessor register (as needed for migration, etc). */
193 if (ri
->type
& ARM_CP_CONST
) {
194 return ri
->resetvalue
;
195 } else if (ri
->raw_readfn
) {
196 return ri
->raw_readfn(env
, ri
);
197 } else if (ri
->readfn
) {
198 return ri
->readfn(env
, ri
);
200 return raw_read(env
, ri
);
204 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
207 /* Raw write of a coprocessor register (as needed for migration, etc).
208 * Note that constant registers are treated as write-ignored; the
209 * caller should check for success by whether a readback gives the
212 if (ri
->type
& ARM_CP_CONST
) {
214 } else if (ri
->raw_writefn
) {
215 ri
->raw_writefn(env
, ri
, v
);
216 } else if (ri
->writefn
) {
217 ri
->writefn(env
, ri
, v
);
219 raw_write(env
, ri
, v
);
223 static int arm_gdb_get_sysreg(CPUARMState
*env
, uint8_t *buf
, int reg
)
225 ARMCPU
*cpu
= arm_env_get_cpu(env
);
226 const ARMCPRegInfo
*ri
;
229 key
= cpu
->dyn_xml
.cpregs_keys
[reg
];
230 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
232 if (cpreg_field_is_64bit(ri
)) {
233 return gdb_get_reg64(buf
, (uint64_t)read_raw_cp_reg(env
, ri
));
235 return gdb_get_reg32(buf
, (uint32_t)read_raw_cp_reg(env
, ri
));
241 static int arm_gdb_set_sysreg(CPUARMState
*env
, uint8_t *buf
, int reg
)
246 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
248 /* Return true if the regdef would cause an assertion if you called
249 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
250 * program bug for it not to have the NO_RAW flag).
251 * NB that returning false here doesn't necessarily mean that calling
252 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
253 * read/write access functions which are safe for raw use" from "has
254 * read/write access functions which have side effects but has forgotten
255 * to provide raw access functions".
256 * The tests here line up with the conditions in read/write_raw_cp_reg()
257 * and assertions in raw_read()/raw_write().
259 if ((ri
->type
& ARM_CP_CONST
) ||
261 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
267 bool write_cpustate_to_list(ARMCPU
*cpu
)
269 /* Write the coprocessor state from cpu->env to the (index,value) list. */
273 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
274 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
275 const ARMCPRegInfo
*ri
;
277 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
282 if (ri
->type
& ARM_CP_NO_RAW
) {
285 cpu
->cpreg_values
[i
] = read_raw_cp_reg(&cpu
->env
, ri
);
290 bool write_list_to_cpustate(ARMCPU
*cpu
)
295 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
296 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
297 uint64_t v
= cpu
->cpreg_values
[i
];
298 const ARMCPRegInfo
*ri
;
300 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
305 if (ri
->type
& ARM_CP_NO_RAW
) {
308 /* Write value and confirm it reads back as written
309 * (to catch read-only registers and partially read-only
310 * registers where the incoming migration value doesn't match)
312 write_raw_cp_reg(&cpu
->env
, ri
, v
);
313 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
320 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
322 ARMCPU
*cpu
= opaque
;
324 const ARMCPRegInfo
*ri
;
326 regidx
= *(uint32_t *)key
;
327 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
329 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
330 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
331 /* The value array need not be initialized at this point */
332 cpu
->cpreg_array_len
++;
336 static void count_cpreg(gpointer key
, gpointer opaque
)
338 ARMCPU
*cpu
= opaque
;
340 const ARMCPRegInfo
*ri
;
342 regidx
= *(uint32_t *)key
;
343 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
345 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
346 cpu
->cpreg_array_len
++;
350 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
352 uint64_t aidx
= cpreg_to_kvm_id(*(uint32_t *)a
);
353 uint64_t bidx
= cpreg_to_kvm_id(*(uint32_t *)b
);
364 void init_cpreg_list(ARMCPU
*cpu
)
366 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
367 * Note that we require cpreg_tuples[] to be sorted by key ID.
372 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
373 keys
= g_list_sort(keys
, cpreg_key_compare
);
375 cpu
->cpreg_array_len
= 0;
377 g_list_foreach(keys
, count_cpreg
, cpu
);
379 arraylen
= cpu
->cpreg_array_len
;
380 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
381 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
382 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
383 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
384 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
385 cpu
->cpreg_array_len
= 0;
387 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
389 assert(cpu
->cpreg_array_len
== arraylen
);
395 * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
396 * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
398 * access_el3_aa32ns: Used to check AArch32 register views.
399 * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
401 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
402 const ARMCPRegInfo
*ri
,
405 bool secure
= arm_is_secure_below_el3(env
);
407 assert(!arm_el_is_aa64(env
, 3));
409 return CP_ACCESS_TRAP_UNCATEGORIZED
;
414 static CPAccessResult
access_el3_aa32ns_aa64any(CPUARMState
*env
,
415 const ARMCPRegInfo
*ri
,
418 if (!arm_el_is_aa64(env
, 3)) {
419 return access_el3_aa32ns(env
, ri
, isread
);
424 /* Some secure-only AArch32 registers trap to EL3 if used from
425 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
426 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
427 * We assume that the .access field is set to PL1_RW.
429 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
430 const ARMCPRegInfo
*ri
,
433 if (arm_current_el(env
) == 3) {
436 if (arm_is_secure_below_el3(env
)) {
437 return CP_ACCESS_TRAP_EL3
;
439 /* This will be EL1 NS and EL2 NS, which just UNDEF */
440 return CP_ACCESS_TRAP_UNCATEGORIZED
;
443 /* Check for traps to "powerdown debug" registers, which are controlled
446 static CPAccessResult
access_tdosa(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
449 int el
= arm_current_el(env
);
450 bool mdcr_el2_tdosa
= (env
->cp15
.mdcr_el2
& MDCR_TDOSA
) ||
451 (env
->cp15
.mdcr_el2
& MDCR_TDE
) ||
452 (arm_hcr_el2_eff(env
) & HCR_TGE
);
454 if (el
< 2 && mdcr_el2_tdosa
&& !arm_is_secure_below_el3(env
)) {
455 return CP_ACCESS_TRAP_EL2
;
457 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDOSA
)) {
458 return CP_ACCESS_TRAP_EL3
;
463 /* Check for traps to "debug ROM" registers, which are controlled
464 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
466 static CPAccessResult
access_tdra(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
469 int el
= arm_current_el(env
);
470 bool mdcr_el2_tdra
= (env
->cp15
.mdcr_el2
& MDCR_TDRA
) ||
471 (env
->cp15
.mdcr_el2
& MDCR_TDE
) ||
472 (arm_hcr_el2_eff(env
) & HCR_TGE
);
474 if (el
< 2 && mdcr_el2_tdra
&& !arm_is_secure_below_el3(env
)) {
475 return CP_ACCESS_TRAP_EL2
;
477 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
478 return CP_ACCESS_TRAP_EL3
;
483 /* Check for traps to general debug registers, which are controlled
484 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
486 static CPAccessResult
access_tda(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
489 int el
= arm_current_el(env
);
490 bool mdcr_el2_tda
= (env
->cp15
.mdcr_el2
& MDCR_TDA
) ||
491 (env
->cp15
.mdcr_el2
& MDCR_TDE
) ||
492 (arm_hcr_el2_eff(env
) & HCR_TGE
);
494 if (el
< 2 && mdcr_el2_tda
&& !arm_is_secure_below_el3(env
)) {
495 return CP_ACCESS_TRAP_EL2
;
497 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
498 return CP_ACCESS_TRAP_EL3
;
503 /* Check for traps to performance monitor registers, which are controlled
504 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
506 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
509 int el
= arm_current_el(env
);
511 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
512 && !arm_is_secure_below_el3(env
)) {
513 return CP_ACCESS_TRAP_EL2
;
515 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
516 return CP_ACCESS_TRAP_EL3
;
521 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
523 ARMCPU
*cpu
= arm_env_get_cpu(env
);
525 raw_write(env
, ri
, value
);
526 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
529 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
531 ARMCPU
*cpu
= arm_env_get_cpu(env
);
533 if (raw_read(env
, ri
) != value
) {
534 /* Unlike real hardware the qemu TLB uses virtual addresses,
535 * not modified virtual addresses, so this causes a TLB flush.
538 raw_write(env
, ri
, value
);
542 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
545 ARMCPU
*cpu
= arm_env_get_cpu(env
);
547 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
548 && !extended_addresses_enabled(env
)) {
549 /* For VMSA (when not using the LPAE long descriptor page table
550 * format) this register includes the ASID, so do a TLB flush.
551 * For PMSA it is purely a process ID and no action is needed.
555 raw_write(env
, ri
, value
);
558 /* IS variants of TLB operations must affect all cores */
559 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
562 CPUState
*cs
= ENV_GET_CPU(env
);
564 tlb_flush_all_cpus_synced(cs
);
567 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
570 CPUState
*cs
= ENV_GET_CPU(env
);
572 tlb_flush_all_cpus_synced(cs
);
575 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
578 CPUState
*cs
= ENV_GET_CPU(env
);
580 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
583 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
586 CPUState
*cs
= ENV_GET_CPU(env
);
588 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
592 * Non-IS variants of TLB operations are upgraded to
593 * IS versions if we are at NS EL1 and HCR_EL2.FB is set to
594 * force broadcast of these operations.
596 static bool tlb_force_broadcast(CPUARMState
*env
)
598 return (env
->cp15
.hcr_el2
& HCR_FB
) &&
599 arm_current_el(env
) == 1 && arm_is_secure_below_el3(env
);
602 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
605 /* Invalidate all (TLBIALL) */
606 ARMCPU
*cpu
= arm_env_get_cpu(env
);
608 if (tlb_force_broadcast(env
)) {
609 tlbiall_is_write(env
, NULL
, value
);
616 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
619 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
620 ARMCPU
*cpu
= arm_env_get_cpu(env
);
622 if (tlb_force_broadcast(env
)) {
623 tlbimva_is_write(env
, NULL
, value
);
627 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
630 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
633 /* Invalidate by ASID (TLBIASID) */
634 ARMCPU
*cpu
= arm_env_get_cpu(env
);
636 if (tlb_force_broadcast(env
)) {
637 tlbiasid_is_write(env
, NULL
, value
);
644 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
647 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
648 ARMCPU
*cpu
= arm_env_get_cpu(env
);
650 if (tlb_force_broadcast(env
)) {
651 tlbimvaa_is_write(env
, NULL
, value
);
655 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
658 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
661 CPUState
*cs
= ENV_GET_CPU(env
);
663 tlb_flush_by_mmuidx(cs
,
664 ARMMMUIdxBit_S12NSE1
|
665 ARMMMUIdxBit_S12NSE0
|
669 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
672 CPUState
*cs
= ENV_GET_CPU(env
);
674 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
675 ARMMMUIdxBit_S12NSE1
|
676 ARMMMUIdxBit_S12NSE0
|
680 static void tlbiipas2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
683 /* Invalidate by IPA. This has to invalidate any structures that
684 * contain only stage 2 translation information, but does not need
685 * to apply to structures that contain combined stage 1 and stage 2
686 * translation information.
687 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
689 CPUState
*cs
= ENV_GET_CPU(env
);
692 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
696 pageaddr
= sextract64(value
<< 12, 0, 40);
698 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S2NS
);
701 static void tlbiipas2_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
704 CPUState
*cs
= ENV_GET_CPU(env
);
707 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
711 pageaddr
= sextract64(value
<< 12, 0, 40);
713 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
717 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
720 CPUState
*cs
= ENV_GET_CPU(env
);
722 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E2
);
725 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
728 CPUState
*cs
= ENV_GET_CPU(env
);
730 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E2
);
733 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
736 CPUState
*cs
= ENV_GET_CPU(env
);
737 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
739 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E2
);
742 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
745 CPUState
*cs
= ENV_GET_CPU(env
);
746 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
748 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
752 static const ARMCPRegInfo cp_reginfo
[] = {
753 /* Define the secure and non-secure FCSE identifier CP registers
754 * separately because there is no secure bank in V8 (no _EL3). This allows
755 * the secure register to be properly reset and migrated. There is also no
756 * v8 EL1 version of the register so the non-secure instance stands alone.
759 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
760 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
761 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
762 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
763 { .name
= "FCSEIDR_S",
764 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
765 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
766 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
767 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
768 /* Define the secure and non-secure context identifier CP registers
769 * separately because there is no secure bank in V8 (no _EL3). This allows
770 * the secure register to be properly reset and migrated. In the
771 * non-secure case, the 32-bit register will have reset and migration
772 * disabled during registration as it is handled by the 64-bit instance.
774 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
775 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
776 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
777 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
778 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
779 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
780 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
781 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
782 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
783 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
787 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
788 /* NB: Some of these registers exist in v8 but with more precise
789 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
791 /* MMU Domain access control / MPU write buffer control */
793 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
794 .access
= PL1_RW
, .resetvalue
= 0,
795 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
796 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
797 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
798 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
799 * For v6 and v5, these mappings are overly broad.
801 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
802 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
803 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
804 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
805 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
806 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
807 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
808 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
809 /* Cache maintenance ops; some of this space may be overridden later. */
810 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
811 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
812 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
816 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
817 /* Not all pre-v6 cores implemented this WFI, so this is slightly
820 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
821 .access
= PL1_W
, .type
= ARM_CP_WFI
},
825 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
826 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
827 * is UNPREDICTABLE; we choose to NOP as most implementations do).
829 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
830 .access
= PL1_W
, .type
= ARM_CP_WFI
},
831 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
832 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
833 * OMAPCP will override this space.
835 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
836 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
838 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
839 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
841 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
842 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
843 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
845 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
846 * implementing it as RAZ means the "debug architecture version" bits
847 * will read as a reserved value, which should cause Linux to not try
848 * to use the debug hardware.
850 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
851 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
852 /* MMU TLB control. Note that the wildcarding means we cover not just
853 * the unified TLB ops but also the dside/iside/inner-shareable variants.
855 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
856 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
857 .type
= ARM_CP_NO_RAW
},
858 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
859 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
860 .type
= ARM_CP_NO_RAW
},
861 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
862 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
863 .type
= ARM_CP_NO_RAW
},
864 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
865 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
866 .type
= ARM_CP_NO_RAW
},
867 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
868 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
869 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
870 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
874 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
879 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
880 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
881 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
882 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
883 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
885 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
886 /* VFP coprocessor: cp10 & cp11 [23:20] */
887 mask
|= (1 << 31) | (1 << 30) | (0xf << 20);
889 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
890 /* ASEDIS [31] bit is RAO/WI */
894 /* VFPv3 and upwards with NEON implement 32 double precision
895 * registers (D0-D31).
897 if (!arm_feature(env
, ARM_FEATURE_NEON
) ||
898 !arm_feature(env
, ARM_FEATURE_VFP3
)) {
899 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
905 env
->cp15
.cpacr_el1
= value
;
908 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
910 /* Call cpacr_write() so that we reset with the correct RAO bits set
911 * for our CPU features.
913 cpacr_write(env
, ri
, 0);
916 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
919 if (arm_feature(env
, ARM_FEATURE_V8
)) {
920 /* Check if CPACR accesses are to be trapped to EL2 */
921 if (arm_current_el(env
) == 1 &&
922 (env
->cp15
.cptr_el
[2] & CPTR_TCPAC
) && !arm_is_secure(env
)) {
923 return CP_ACCESS_TRAP_EL2
;
924 /* Check if CPACR accesses are to be trapped to EL3 */
925 } else if (arm_current_el(env
) < 3 &&
926 (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
927 return CP_ACCESS_TRAP_EL3
;
934 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
937 /* Check if CPTR accesses are set to trap to EL3 */
938 if (arm_current_el(env
) == 2 && (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
939 return CP_ACCESS_TRAP_EL3
;
945 static const ARMCPRegInfo v6_cp_reginfo
[] = {
946 /* prefetch by MVA in v6, NOP in v7 */
947 { .name
= "MVA_prefetch",
948 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
949 .access
= PL1_W
, .type
= ARM_CP_NOP
},
950 /* We need to break the TB after ISB to execute self-modifying code
951 * correctly and also to take any pending interrupts immediately.
952 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
954 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
955 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
956 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
957 .access
= PL0_W
, .type
= ARM_CP_NOP
},
958 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
959 .access
= PL0_W
, .type
= ARM_CP_NOP
},
960 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
962 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
963 offsetof(CPUARMState
, cp15
.ifar_ns
) },
965 /* Watchpoint Fault Address Register : should actually only be present
966 * for 1136, 1176, 11MPCore.
968 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
969 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
970 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
971 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
972 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
973 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
},
977 /* Definitions for the PMU registers */
978 #define PMCRN_MASK 0xf800
979 #define PMCRN_SHIFT 11
987 #define PMXEVTYPER_P 0x80000000
988 #define PMXEVTYPER_U 0x40000000
989 #define PMXEVTYPER_NSK 0x20000000
990 #define PMXEVTYPER_NSU 0x10000000
991 #define PMXEVTYPER_NSH 0x08000000
992 #define PMXEVTYPER_M 0x04000000
993 #define PMXEVTYPER_MT 0x02000000
994 #define PMXEVTYPER_EVTCOUNT 0x0000ffff
995 #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \
996 PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
997 PMXEVTYPER_M | PMXEVTYPER_MT | \
1000 #define PMCCFILTR 0xf8000000
1001 #define PMCCFILTR_M PMXEVTYPER_M
1002 #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)
1004 static inline uint32_t pmu_num_counters(CPUARMState
*env
)
1006 return (env
->cp15
.c9_pmcr
& PMCRN_MASK
) >> PMCRN_SHIFT
;
1009 /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
1010 static inline uint64_t pmu_counter_mask(CPUARMState
*env
)
1012 return (1 << 31) | ((1 << pmu_num_counters(env
)) - 1);
1015 typedef struct pm_event
{
1016 uint16_t number
; /* PMEVTYPER.evtCount is 16 bits wide */
1017 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
1018 bool (*supported
)(CPUARMState
*);
1020 * Retrieve the current count of the underlying event. The programmed
1021 * counters hold a difference from the return value from this function
1023 uint64_t (*get_count
)(CPUARMState
*);
1025 * Return how many nanoseconds it will take (at a minimum) for count events
1026 * to occur. A negative value indicates the counter will never overflow, or
1027 * that the counter has otherwise arranged for the overflow bit to be set
1028 * and the PMU interrupt to be raised on overflow.
1030 int64_t (*ns_per_count
)(uint64_t);
1033 static bool event_always_supported(CPUARMState
*env
)
1038 static uint64_t swinc_get_count(CPUARMState
*env
)
1041 * SW_INCR events are written directly to the pmevcntr's by writes to
1042 * PMSWINC, so there is no underlying count maintained by the PMU itself
1047 static int64_t swinc_ns_per(uint64_t ignored
)
1053 * Return the underlying cycle count for the PMU cycle counters. If we're in
1054 * usermode, simply return 0.
1056 static uint64_t cycles_get_count(CPUARMState
*env
)
1058 #ifndef CONFIG_USER_ONLY
1059 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1060 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1062 return cpu_get_host_ticks();
1066 #ifndef CONFIG_USER_ONLY
1067 static int64_t cycles_ns_per(uint64_t cycles
)
1069 return (ARM_CPU_FREQ
/ NANOSECONDS_PER_SECOND
) * cycles
;
1072 static bool instructions_supported(CPUARMState
*env
)
1074 return use_icount
== 1 /* Precise instruction counting */;
1077 static uint64_t instructions_get_count(CPUARMState
*env
)
1079 return (uint64_t)cpu_get_icount_raw();
1082 static int64_t instructions_ns_per(uint64_t icount
)
1084 return cpu_icount_to_ns((int64_t)icount
);
1088 static const pm_event pm_events
[] = {
1089 { .number
= 0x000, /* SW_INCR */
1090 .supported
= event_always_supported
,
1091 .get_count
= swinc_get_count
,
1092 .ns_per_count
= swinc_ns_per
,
1094 #ifndef CONFIG_USER_ONLY
1095 { .number
= 0x008, /* INST_RETIRED, Instruction architecturally executed */
1096 .supported
= instructions_supported
,
1097 .get_count
= instructions_get_count
,
1098 .ns_per_count
= instructions_ns_per
,
1100 { .number
= 0x011, /* CPU_CYCLES, Cycle */
1101 .supported
= event_always_supported
,
1102 .get_count
= cycles_get_count
,
1103 .ns_per_count
= cycles_ns_per
,
1109 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1110 * events (i.e. the statistical profiling extension), this implementation
1111 * should first be updated to something sparse instead of the current
1112 * supported_event_map[] array.
1114 #define MAX_EVENT_ID 0x11
1115 #define UNSUPPORTED_EVENT UINT16_MAX
1116 static uint16_t supported_event_map
[MAX_EVENT_ID
+ 1];
1119 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1120 * of ARM event numbers to indices in our pm_events array.
1122 * Note: Events in the 0x40XX range are not currently supported.
1124 void pmu_init(ARMCPU
*cpu
)
1129 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1132 for (i
= 0; i
< ARRAY_SIZE(supported_event_map
); i
++) {
1133 supported_event_map
[i
] = UNSUPPORTED_EVENT
;
1138 for (i
= 0; i
< ARRAY_SIZE(pm_events
); i
++) {
1139 const pm_event
*cnt
= &pm_events
[i
];
1140 assert(cnt
->number
<= MAX_EVENT_ID
);
1141 /* We do not currently support events in the 0x40xx range */
1142 assert(cnt
->number
<= 0x3f);
1144 if (cnt
->supported(&cpu
->env
)) {
1145 supported_event_map
[cnt
->number
] = i
;
1146 uint64_t event_mask
= 1 << (cnt
->number
& 0x1f);
1147 if (cnt
->number
& 0x20) {
1148 cpu
->pmceid1
|= event_mask
;
1150 cpu
->pmceid0
|= event_mask
;
1157 * Check at runtime whether a PMU event is supported for the current machine
1159 static bool event_supported(uint16_t number
)
1161 if (number
> MAX_EVENT_ID
) {
1164 return supported_event_map
[number
] != UNSUPPORTED_EVENT
;
1167 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1170 /* Performance monitor registers user accessibility is controlled
1171 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1172 * trapping to EL2 or EL3 for other accesses.
1174 int el
= arm_current_el(env
);
1176 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
1177 return CP_ACCESS_TRAP
;
1179 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
1180 && !arm_is_secure_below_el3(env
)) {
1181 return CP_ACCESS_TRAP_EL2
;
1183 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
1184 return CP_ACCESS_TRAP_EL3
;
1187 return CP_ACCESS_OK
;
1190 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
1191 const ARMCPRegInfo
*ri
,
1194 /* ER: event counter read trap control */
1195 if (arm_feature(env
, ARM_FEATURE_V8
)
1196 && arm_current_el(env
) == 0
1197 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
1199 return CP_ACCESS_OK
;
1202 return pmreg_access(env
, ri
, isread
);
1205 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1206 const ARMCPRegInfo
*ri
,
1209 /* SW: software increment write trap control */
1210 if (arm_feature(env
, ARM_FEATURE_V8
)
1211 && arm_current_el(env
) == 0
1212 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1214 return CP_ACCESS_OK
;
1217 return pmreg_access(env
, ri
, isread
);
1220 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1221 const ARMCPRegInfo
*ri
,
1224 /* ER: event counter read trap control */
1225 if (arm_feature(env
, ARM_FEATURE_V8
)
1226 && arm_current_el(env
) == 0
1227 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1228 return CP_ACCESS_OK
;
1231 return pmreg_access(env
, ri
, isread
);
1234 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1235 const ARMCPRegInfo
*ri
,
1238 /* CR: cycle counter read trap control */
1239 if (arm_feature(env
, ARM_FEATURE_V8
)
1240 && arm_current_el(env
) == 0
1241 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1243 return CP_ACCESS_OK
;
1246 return pmreg_access(env
, ri
, isread
);
1249 /* Returns true if the counter (pass 31 for PMCCNTR) should count events using
1250 * the current EL, security state, and register configuration.
1252 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
1255 bool e
, p
, u
, nsk
, nsu
, nsh
, m
;
1256 bool enabled
, prohibited
, filtered
;
1257 bool secure
= arm_is_secure(env
);
1258 int el
= arm_current_el(env
);
1259 uint8_t hpmn
= env
->cp15
.mdcr_el2
& MDCR_HPMN
;
1261 if (!arm_feature(env
, ARM_FEATURE_EL2
) ||
1262 (counter
< hpmn
|| counter
== 31)) {
1263 e
= env
->cp15
.c9_pmcr
& PMCRE
;
1265 e
= env
->cp15
.mdcr_el2
& MDCR_HPME
;
1267 enabled
= e
&& (env
->cp15
.c9_pmcnten
& (1 << counter
));
1270 if (el
== 2 && (counter
< hpmn
|| counter
== 31)) {
1271 prohibited
= env
->cp15
.mdcr_el2
& MDCR_HPMD
;
1276 prohibited
= arm_feature(env
, ARM_FEATURE_EL3
) &&
1277 (env
->cp15
.mdcr_el3
& MDCR_SPME
);
1280 if (prohibited
&& counter
== 31) {
1281 prohibited
= env
->cp15
.c9_pmcr
& PMCRDP
;
1284 if (counter
== 31) {
1285 filter
= env
->cp15
.pmccfiltr_el0
;
1287 filter
= env
->cp15
.c14_pmevtyper
[counter
];
1290 p
= filter
& PMXEVTYPER_P
;
1291 u
= filter
& PMXEVTYPER_U
;
1292 nsk
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSK
);
1293 nsu
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSU
);
1294 nsh
= arm_feature(env
, ARM_FEATURE_EL2
) && (filter
& PMXEVTYPER_NSH
);
1295 m
= arm_el_is_aa64(env
, 1) &&
1296 arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_M
);
1299 filtered
= secure
? u
: u
!= nsu
;
1300 } else if (el
== 1) {
1301 filtered
= secure
? p
: p
!= nsk
;
1302 } else if (el
== 2) {
1308 if (counter
!= 31) {
1310 * If not checking PMCCNTR, ensure the counter is setup to an event we
1313 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
1314 if (!event_supported(event
)) {
1319 return enabled
&& !prohibited
&& !filtered
;
1322 static void pmu_update_irq(CPUARMState
*env
)
1324 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1325 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
1326 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
1330 * Ensure c15_ccnt is the guest-visible count so that operations such as
1331 * enabling/disabling the counter or filtering, modifying the count itself,
1332 * etc. can be done logically. This is essentially a no-op if the counter is
1333 * not enabled at the time of the call.
1335 void pmccntr_op_start(CPUARMState
*env
)
1337 uint64_t cycles
= cycles_get_count(env
);
1339 if (pmu_counter_enabled(env
, 31)) {
1340 uint64_t eff_cycles
= cycles
;
1341 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1342 /* Increment once every 64 processor clock cycles */
1346 uint64_t new_pmccntr
= eff_cycles
- env
->cp15
.c15_ccnt_delta
;
1348 uint64_t overflow_mask
= env
->cp15
.c9_pmcr
& PMCRLC
? \
1349 1ull << 63 : 1ull << 31;
1350 if (env
->cp15
.c15_ccnt
& ~new_pmccntr
& overflow_mask
) {
1351 env
->cp15
.c9_pmovsr
|= (1 << 31);
1352 pmu_update_irq(env
);
1355 env
->cp15
.c15_ccnt
= new_pmccntr
;
1357 env
->cp15
.c15_ccnt_delta
= cycles
;
1361 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1362 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1365 void pmccntr_op_finish(CPUARMState
*env
)
1367 if (pmu_counter_enabled(env
, 31)) {
1368 #ifndef CONFIG_USER_ONLY
1369 /* Calculate when the counter will next overflow */
1370 uint64_t remaining_cycles
= -env
->cp15
.c15_ccnt
;
1371 if (!(env
->cp15
.c9_pmcr
& PMCRLC
)) {
1372 remaining_cycles
= (uint32_t)remaining_cycles
;
1374 int64_t overflow_in
= cycles_ns_per(remaining_cycles
);
1376 if (overflow_in
> 0) {
1377 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1379 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1380 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1384 uint64_t prev_cycles
= env
->cp15
.c15_ccnt_delta
;
1385 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1386 /* Increment once every 64 processor clock cycles */
1389 env
->cp15
.c15_ccnt_delta
= prev_cycles
- env
->cp15
.c15_ccnt
;
1393 static void pmevcntr_op_start(CPUARMState
*env
, uint8_t counter
)
1396 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1398 if (event_supported(event
)) {
1399 uint16_t event_idx
= supported_event_map
[event
];
1400 count
= pm_events
[event_idx
].get_count(env
);
1403 if (pmu_counter_enabled(env
, counter
)) {
1404 uint32_t new_pmevcntr
= count
- env
->cp15
.c14_pmevcntr_delta
[counter
];
1406 if (env
->cp15
.c14_pmevcntr
[counter
] & ~new_pmevcntr
& INT32_MIN
) {
1407 env
->cp15
.c9_pmovsr
|= (1 << counter
);
1408 pmu_update_irq(env
);
1410 env
->cp15
.c14_pmevcntr
[counter
] = new_pmevcntr
;
1412 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1415 static void pmevcntr_op_finish(CPUARMState
*env
, uint8_t counter
)
1417 if (pmu_counter_enabled(env
, counter
)) {
1418 #ifndef CONFIG_USER_ONLY
1419 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1420 uint16_t event_idx
= supported_event_map
[event
];
1421 uint64_t delta
= UINT32_MAX
-
1422 (uint32_t)env
->cp15
.c14_pmevcntr
[counter
] + 1;
1423 int64_t overflow_in
= pm_events
[event_idx
].ns_per_count(delta
);
1425 if (overflow_in
> 0) {
1426 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1428 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1429 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1433 env
->cp15
.c14_pmevcntr_delta
[counter
] -=
1434 env
->cp15
.c14_pmevcntr
[counter
];
1438 void pmu_op_start(CPUARMState
*env
)
1441 pmccntr_op_start(env
);
1442 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1443 pmevcntr_op_start(env
, i
);
1447 void pmu_op_finish(CPUARMState
*env
)
1450 pmccntr_op_finish(env
);
1451 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1452 pmevcntr_op_finish(env
, i
);
1456 void pmu_pre_el_change(ARMCPU
*cpu
, void *ignored
)
1458 pmu_op_start(&cpu
->env
);
1461 void pmu_post_el_change(ARMCPU
*cpu
, void *ignored
)
1463 pmu_op_finish(&cpu
->env
);
1466 void arm_pmu_timer_cb(void *opaque
)
1468 ARMCPU
*cpu
= opaque
;
1471 * Update all the counter values based on the current underlying counts,
1472 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1473 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1474 * counter may expire.
1476 pmu_op_start(&cpu
->env
);
1477 pmu_op_finish(&cpu
->env
);
1480 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1485 if (value
& PMCRC
) {
1486 /* The counter has been reset */
1487 env
->cp15
.c15_ccnt
= 0;
1490 if (value
& PMCRP
) {
1492 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1493 env
->cp15
.c14_pmevcntr
[i
] = 0;
1497 /* only the DP, X, D and E bits are writable */
1498 env
->cp15
.c9_pmcr
&= ~0x39;
1499 env
->cp15
.c9_pmcr
|= (value
& 0x39);
1504 static void pmswinc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1508 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1509 /* Increment a counter's count iff: */
1510 if ((value
& (1 << i
)) && /* counter's bit is set */
1511 /* counter is enabled and not filtered */
1512 pmu_counter_enabled(env
, i
) &&
1513 /* counter is SW_INCR */
1514 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
1515 pmevcntr_op_start(env
, i
);
1518 * Detect if this write causes an overflow since we can't predict
1519 * PMSWINC overflows like we can for other events
1521 uint32_t new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
1523 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& INT32_MIN
) {
1524 env
->cp15
.c9_pmovsr
|= (1 << i
);
1525 pmu_update_irq(env
);
1528 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
1530 pmevcntr_op_finish(env
, i
);
1535 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1538 pmccntr_op_start(env
);
1539 ret
= env
->cp15
.c15_ccnt
;
1540 pmccntr_op_finish(env
);
1544 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1547 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1548 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1549 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1552 env
->cp15
.c9_pmselr
= value
& 0x1f;
1555 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1558 pmccntr_op_start(env
);
1559 env
->cp15
.c15_ccnt
= value
;
1560 pmccntr_op_finish(env
);
1563 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1566 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1568 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1571 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1574 pmccntr_op_start(env
);
1575 env
->cp15
.pmccfiltr_el0
= value
& PMCCFILTR_EL0
;
1576 pmccntr_op_finish(env
);
1579 static void pmccfiltr_write_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1582 pmccntr_op_start(env
);
1583 /* M is not accessible from AArch32 */
1584 env
->cp15
.pmccfiltr_el0
= (env
->cp15
.pmccfiltr_el0
& PMCCFILTR_M
) |
1585 (value
& PMCCFILTR
);
1586 pmccntr_op_finish(env
);
1589 static uint64_t pmccfiltr_read_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1591 /* M is not visible in AArch32 */
1592 return env
->cp15
.pmccfiltr_el0
& PMCCFILTR
;
1595 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1598 value
&= pmu_counter_mask(env
);
1599 env
->cp15
.c9_pmcnten
|= value
;
1602 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1605 value
&= pmu_counter_mask(env
);
1606 env
->cp15
.c9_pmcnten
&= ~value
;
1609 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1612 value
&= pmu_counter_mask(env
);
1613 env
->cp15
.c9_pmovsr
&= ~value
;
1614 pmu_update_irq(env
);
1617 static void pmovsset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1620 value
&= pmu_counter_mask(env
);
1621 env
->cp15
.c9_pmovsr
|= value
;
1622 pmu_update_irq(env
);
1625 static void pmevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1626 uint64_t value
, const uint8_t counter
)
1628 if (counter
== 31) {
1629 pmccfiltr_write(env
, ri
, value
);
1630 } else if (counter
< pmu_num_counters(env
)) {
1631 pmevcntr_op_start(env
, counter
);
1634 * If this counter's event type is changing, store the current
1635 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1636 * pmevcntr_op_finish has the correct baseline when it converts back to
1639 uint16_t old_event
= env
->cp15
.c14_pmevtyper
[counter
] &
1640 PMXEVTYPER_EVTCOUNT
;
1641 uint16_t new_event
= value
& PMXEVTYPER_EVTCOUNT
;
1642 if (old_event
!= new_event
) {
1644 if (event_supported(new_event
)) {
1645 uint16_t event_idx
= supported_event_map
[new_event
];
1646 count
= pm_events
[event_idx
].get_count(env
);
1648 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1651 env
->cp15
.c14_pmevtyper
[counter
] = value
& PMXEVTYPER_MASK
;
1652 pmevcntr_op_finish(env
, counter
);
1654 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1655 * PMSELR value is equal to or greater than the number of implemented
1656 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1660 static uint64_t pmevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1661 const uint8_t counter
)
1663 if (counter
== 31) {
1664 return env
->cp15
.pmccfiltr_el0
;
1665 } else if (counter
< pmu_num_counters(env
)) {
1666 return env
->cp15
.c14_pmevtyper
[counter
];
1669 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1670 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1676 static void pmevtyper_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1679 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1680 pmevtyper_write(env
, ri
, value
, counter
);
1683 static void pmevtyper_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1686 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1687 env
->cp15
.c14_pmevtyper
[counter
] = value
;
1690 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1691 * pmu_op_finish calls when loading saved state for a migration. Because
1692 * we're potentially updating the type of event here, the value written to
1693 * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
1694 * different counter type. Therefore, we need to set this value to the
1695 * current count for the counter type we're writing so that pmu_op_finish
1696 * has the correct count for its calculation.
1698 uint16_t event
= value
& PMXEVTYPER_EVTCOUNT
;
1699 if (event_supported(event
)) {
1700 uint16_t event_idx
= supported_event_map
[event
];
1701 env
->cp15
.c14_pmevcntr_delta
[counter
] =
1702 pm_events
[event_idx
].get_count(env
);
1706 static uint64_t pmevtyper_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1708 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1709 return pmevtyper_read(env
, ri
, counter
);
1712 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1715 pmevtyper_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1718 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1720 return pmevtyper_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1723 static void pmevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1724 uint64_t value
, uint8_t counter
)
1726 if (counter
< pmu_num_counters(env
)) {
1727 pmevcntr_op_start(env
, counter
);
1728 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1729 pmevcntr_op_finish(env
, counter
);
1732 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1733 * are CONSTRAINED UNPREDICTABLE.
1737 static uint64_t pmevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1740 if (counter
< pmu_num_counters(env
)) {
1742 pmevcntr_op_start(env
, counter
);
1743 ret
= env
->cp15
.c14_pmevcntr
[counter
];
1744 pmevcntr_op_finish(env
, counter
);
1747 /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1748 * are CONSTRAINED UNPREDICTABLE. */
1753 static void pmevcntr_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1756 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1757 pmevcntr_write(env
, ri
, value
, counter
);
1760 static uint64_t pmevcntr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1762 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1763 return pmevcntr_read(env
, ri
, counter
);
1766 static void pmevcntr_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1769 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1770 assert(counter
< pmu_num_counters(env
));
1771 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1772 pmevcntr_write(env
, ri
, value
, counter
);
1775 static uint64_t pmevcntr_rawread(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1777 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1778 assert(counter
< pmu_num_counters(env
));
1779 return env
->cp15
.c14_pmevcntr
[counter
];
1782 static void pmxevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1785 pmevcntr_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1788 static uint64_t pmxevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1790 return pmevcntr_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1793 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1796 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1797 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1799 env
->cp15
.c9_pmuserenr
= value
& 1;
1803 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1806 /* We have no event counters so only the C bit can be changed */
1807 value
&= pmu_counter_mask(env
);
1808 env
->cp15
.c9_pminten
|= value
;
1809 pmu_update_irq(env
);
1812 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1815 value
&= pmu_counter_mask(env
);
1816 env
->cp15
.c9_pminten
&= ~value
;
1817 pmu_update_irq(env
);
1820 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1823 /* Note that even though the AArch64 view of this register has bits
1824 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1825 * architectural requirements for bits which are RES0 only in some
1826 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1827 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1829 raw_write(env
, ri
, value
& ~0x1FULL
);
1832 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1834 /* Begin with base v8.0 state. */
1835 uint32_t valid_mask
= 0x3fff;
1836 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1838 if (arm_el_is_aa64(env
, 3)) {
1839 value
|= SCR_FW
| SCR_AW
; /* these two bits are RES1. */
1840 valid_mask
&= ~SCR_NET
;
1842 valid_mask
&= ~(SCR_RW
| SCR_ST
);
1845 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1846 valid_mask
&= ~SCR_HCE
;
1848 /* On ARMv7, SMD (or SCD as it is called in v7) is only
1849 * supported if EL2 exists. The bit is UNK/SBZP when
1850 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1851 * when EL2 is unavailable.
1852 * On ARMv8, this bit is always available.
1854 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1855 !arm_feature(env
, ARM_FEATURE_V8
)) {
1856 valid_mask
&= ~SCR_SMD
;
1859 if (cpu_isar_feature(aa64_lor
, cpu
)) {
1860 valid_mask
|= SCR_TLOR
;
1863 /* Clear all-context RES0 bits. */
1864 value
&= valid_mask
;
1865 raw_write(env
, ri
, value
);
1868 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1870 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1872 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1875 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1876 ri
->secure
& ARM_CP_SECSTATE_S
);
1878 return cpu
->ccsidr
[index
];
1881 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1884 raw_write(env
, ri
, value
& 0xf);
1887 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1889 CPUState
*cs
= ENV_GET_CPU(env
);
1890 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
1893 if (hcr_el2
& HCR_IMO
) {
1894 if (cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) {
1898 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
1903 if (hcr_el2
& HCR_FMO
) {
1904 if (cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) {
1908 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
1913 /* External aborts are not possible in QEMU so A bit is always clear */
1917 static const ARMCPRegInfo v7_cp_reginfo
[] = {
1918 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
1919 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
1920 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1921 /* Performance monitors are implementation defined in v7,
1922 * but with an ARM recommended set of registers, which we
1925 * Performance registers fall into three categories:
1926 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
1927 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
1928 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
1929 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
1930 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
1932 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
1933 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1934 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1935 .writefn
= pmcntenset_write
,
1936 .accessfn
= pmreg_access
,
1937 .raw_writefn
= raw_write
},
1938 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
,
1939 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
1940 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1941 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
1942 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
1943 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
1945 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1946 .accessfn
= pmreg_access
,
1947 .writefn
= pmcntenclr_write
,
1948 .type
= ARM_CP_ALIAS
},
1949 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1950 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
1951 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1952 .type
= ARM_CP_ALIAS
,
1953 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
1954 .writefn
= pmcntenclr_write
},
1955 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
1956 .access
= PL0_RW
, .type
= ARM_CP_IO
,
1957 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
1958 .accessfn
= pmreg_access
,
1959 .writefn
= pmovsr_write
,
1960 .raw_writefn
= raw_write
},
1961 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1962 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
1963 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1964 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
1965 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
1966 .writefn
= pmovsr_write
,
1967 .raw_writefn
= raw_write
},
1968 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
1969 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
1970 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1971 .writefn
= pmswinc_write
},
1972 { .name
= "PMSWINC_EL0", .state
= ARM_CP_STATE_AA64
,
1973 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 4,
1974 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
1975 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1976 .writefn
= pmswinc_write
},
1977 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
1978 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1979 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
1980 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
1981 .raw_writefn
= raw_write
},
1982 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
1983 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
1984 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
1985 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
1986 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
1987 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
1988 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
1989 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
1990 .accessfn
= pmreg_access_ccntr
},
1991 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
1992 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
1993 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
1995 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ccnt
),
1996 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
1997 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
, },
1998 { .name
= "PMCCFILTR", .cp
= 15, .opc1
= 0, .crn
= 14, .crm
= 15, .opc2
= 7,
1999 .writefn
= pmccfiltr_write_a32
, .readfn
= pmccfiltr_read_a32
,
2000 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2001 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2003 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
2004 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
2005 .writefn
= pmccfiltr_write
, .raw_writefn
= raw_write
,
2006 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2008 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
2010 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
2011 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2012 .accessfn
= pmreg_access
,
2013 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2014 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
2015 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
2016 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2017 .accessfn
= pmreg_access
,
2018 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2019 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
2020 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2021 .accessfn
= pmreg_access_xevcntr
,
2022 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2023 { .name
= "PMXEVCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2024 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 2,
2025 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2026 .accessfn
= pmreg_access_xevcntr
,
2027 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2028 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
2029 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
2030 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
2032 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2033 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
2034 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
2035 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
2036 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
2038 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2039 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
2040 .access
= PL1_RW
, .accessfn
= access_tpm
,
2041 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2042 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
2044 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
2045 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
2046 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
2047 .access
= PL1_RW
, .accessfn
= access_tpm
,
2049 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2050 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
2051 .resetvalue
= 0x0 },
2052 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
2053 .access
= PL1_RW
, .accessfn
= access_tpm
,
2054 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2055 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2056 .writefn
= pmintenclr_write
, },
2057 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
2058 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
2059 .access
= PL1_RW
, .accessfn
= access_tpm
,
2060 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2061 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2062 .writefn
= pmintenclr_write
},
2063 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
2064 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
2065 .access
= PL1_R
, .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
2066 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
2067 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
2068 .access
= PL1_RW
, .writefn
= csselr_write
, .resetvalue
= 0,
2069 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
2070 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
2071 /* Auxiliary ID register: this actually has an IMPDEF value but for now
2072 * just RAZ for all cores:
2074 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
2075 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
2076 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2077 /* Auxiliary fault status registers: these also are IMPDEF, and we
2078 * choose to RAZ/WI for all cores.
2080 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2081 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
2082 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2083 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2084 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
2085 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2086 /* MAIR can just read-as-written because we don't implement caches
2087 * and so don't need to care about memory attributes.
2089 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
2090 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2091 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
2093 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
2094 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
2095 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
2097 /* For non-long-descriptor page tables these are PRRR and NMRR;
2098 * regardless they still act as reads-as-written for QEMU.
2100 /* MAIR0/1 are defined separately from their 64-bit counterpart which
2101 * allows them to assign the correct fieldoffset based on the endianness
2102 * handled in the field definitions.
2104 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
2105 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0, .access
= PL1_RW
,
2106 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
2107 offsetof(CPUARMState
, cp15
.mair0_ns
) },
2108 .resetfn
= arm_cp_reset_ignore
},
2109 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
2110 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1, .access
= PL1_RW
,
2111 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
2112 offsetof(CPUARMState
, cp15
.mair1_ns
) },
2113 .resetfn
= arm_cp_reset_ignore
},
2114 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
2115 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
2116 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
2117 /* 32 bit ITLB invalidates */
2118 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2119 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
2120 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2121 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2122 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2123 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
2124 /* 32 bit DTLB invalidates */
2125 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2126 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
2127 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2128 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2129 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2130 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
2131 /* 32 bit TLB invalidates */
2132 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2133 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
2134 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2135 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2136 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2137 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
2138 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2139 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
2143 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
2144 /* 32 bit TLB invalidates, Inner Shareable */
2145 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2146 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_is_write
},
2147 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2148 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
2149 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2150 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
2151 .writefn
= tlbiasid_is_write
},
2152 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2153 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
2154 .writefn
= tlbimvaa_is_write
},
2158 static const ARMCPRegInfo pmovsset_cp_reginfo
[] = {
2159 /* PMOVSSET is not implemented in v7 before v7ve */
2160 { .name
= "PMOVSSET", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 3,
2161 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2162 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2163 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2164 .writefn
= pmovsset_write
,
2165 .raw_writefn
= raw_write
},
2166 { .name
= "PMOVSSET_EL0", .state
= ARM_CP_STATE_AA64
,
2167 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 3,
2168 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2169 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2170 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2171 .writefn
= pmovsset_write
,
2172 .raw_writefn
= raw_write
},
2176 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2183 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2186 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
2187 return CP_ACCESS_TRAP
;
2189 return CP_ACCESS_OK
;
2192 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
2193 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
2194 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
2196 .writefn
= teecr_write
},
2197 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
2198 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
2199 .accessfn
= teehbr_access
, .resetvalue
= 0 },
2203 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
2204 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
2205 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
2207 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
2208 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
2210 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
2211 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
2212 .resetfn
= arm_cp_reset_ignore
},
2213 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
2214 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
2215 .access
= PL0_R
|PL1_W
,
2216 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
2218 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
2219 .access
= PL0_R
|PL1_W
,
2220 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
2221 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
2222 .resetfn
= arm_cp_reset_ignore
},
2223 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2224 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
2226 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
2227 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
2229 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
2230 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
2235 #ifndef CONFIG_USER_ONLY
2237 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2240 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2241 * Writable only at the highest implemented exception level.
2243 int el
= arm_current_el(env
);
2247 if (!extract32(env
->cp15
.c14_cntkctl
, 0, 2)) {
2248 return CP_ACCESS_TRAP
;
2252 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
2253 arm_is_secure_below_el3(env
)) {
2254 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2255 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2263 if (!isread
&& el
< arm_highest_el(env
)) {
2264 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2267 return CP_ACCESS_OK
;
2270 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
2273 unsigned int cur_el
= arm_current_el(env
);
2274 bool secure
= arm_is_secure(env
);
2276 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
2278 !extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
2279 return CP_ACCESS_TRAP
;
2282 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
2283 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
2284 !extract32(env
->cp15
.cnthctl_el2
, 0, 1)) {
2285 return CP_ACCESS_TRAP_EL2
;
2287 return CP_ACCESS_OK
;
2290 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
2293 unsigned int cur_el
= arm_current_el(env
);
2294 bool secure
= arm_is_secure(env
);
2296 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
2297 * EL0[PV]TEN is zero.
2300 !extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
2301 return CP_ACCESS_TRAP
;
2304 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
2305 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
2306 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2307 return CP_ACCESS_TRAP_EL2
;
2309 return CP_ACCESS_OK
;
2312 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
2313 const ARMCPRegInfo
*ri
,
2316 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
2319 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
2320 const ARMCPRegInfo
*ri
,
2323 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
2326 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2329 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
2332 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2335 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
2338 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
2339 const ARMCPRegInfo
*ri
,
2342 /* The AArch64 register view of the secure physical timer is
2343 * always accessible from EL3, and configurably accessible from
2346 switch (arm_current_el(env
)) {
2348 if (!arm_is_secure(env
)) {
2349 return CP_ACCESS_TRAP
;
2351 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
2352 return CP_ACCESS_TRAP_EL3
;
2354 return CP_ACCESS_OK
;
2357 return CP_ACCESS_TRAP
;
2359 return CP_ACCESS_OK
;
2361 g_assert_not_reached();
2365 static uint64_t gt_get_countervalue(CPUARMState
*env
)
2367 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / GTIMER_SCALE
;
2370 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
2372 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
2375 /* Timer enabled: calculate and set current ISTATUS, irq, and
2376 * reset timer to when ISTATUS next has to change
2378 uint64_t offset
= timeridx
== GTIMER_VIRT
?
2379 cpu
->env
.cp15
.cntvoff_el2
: 0;
2380 uint64_t count
= gt_get_countervalue(&cpu
->env
);
2381 /* Note that this must be unsigned 64 bit arithmetic: */
2382 int istatus
= count
- offset
>= gt
->cval
;
2386 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
2388 irqstate
= (istatus
&& !(gt
->ctl
& 2));
2389 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2392 /* Next transition is when count rolls back over to zero */
2393 nexttick
= UINT64_MAX
;
2395 /* Next transition is when we hit cval */
2396 nexttick
= gt
->cval
+ offset
;
2398 /* Note that the desired next expiry time might be beyond the
2399 * signed-64-bit range of a QEMUTimer -- in this case we just
2400 * set the timer for as far in the future as possible. When the
2401 * timer expires we will reset the timer for any remaining period.
2403 if (nexttick
> INT64_MAX
/ GTIMER_SCALE
) {
2404 nexttick
= INT64_MAX
/ GTIMER_SCALE
;
2406 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
2407 trace_arm_gt_recalc(timeridx
, irqstate
, nexttick
);
2409 /* Timer disabled: ISTATUS and timer output always clear */
2411 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
2412 timer_del(cpu
->gt_timer
[timeridx
]);
2413 trace_arm_gt_recalc_disabled(timeridx
);
2417 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2420 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2422 timer_del(cpu
->gt_timer
[timeridx
]);
2425 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2427 return gt_get_countervalue(env
);
2430 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2432 return gt_get_countervalue(env
) - env
->cp15
.cntvoff_el2
;
2435 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2439 trace_arm_gt_cval_write(timeridx
, value
);
2440 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
2441 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
2444 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2447 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
2449 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
2450 (gt_get_countervalue(env
) - offset
));
2453 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2457 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
2459 trace_arm_gt_tval_write(timeridx
, value
);
2460 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
2461 sextract64(value
, 0, 32);
2462 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
2465 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2469 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2470 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
2472 trace_arm_gt_ctl_write(timeridx
, value
);
2473 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
2474 if ((oldval
^ value
) & 1) {
2475 /* Enable toggled */
2476 gt_recalc_timer(cpu
, timeridx
);
2477 } else if ((oldval
^ value
) & 2) {
2478 /* IMASK toggled: don't need to recalculate,
2479 * just set the interrupt line based on ISTATUS
2481 int irqstate
= (oldval
& 4) && !(value
& 2);
2483 trace_arm_gt_imask_toggle(timeridx
, irqstate
);
2484 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2488 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2490 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
2493 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2496 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
2499 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2501 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
2504 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2507 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
2510 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2513 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
2516 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2518 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
2521 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2524 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
2527 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2529 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
2532 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2535 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
2538 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2541 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
2544 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2547 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2549 trace_arm_gt_cntvoff_write(value
);
2550 raw_write(env
, ri
, value
);
2551 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2554 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2556 gt_timer_reset(env
, ri
, GTIMER_HYP
);
2559 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2562 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
2565 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2567 return gt_tval_read(env
, ri
, GTIMER_HYP
);
2570 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2573 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
2576 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2579 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
2582 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2584 gt_timer_reset(env
, ri
, GTIMER_SEC
);
2587 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2590 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
2593 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2595 return gt_tval_read(env
, ri
, GTIMER_SEC
);
2598 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2601 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
2604 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2607 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
2610 void arm_gt_ptimer_cb(void *opaque
)
2612 ARMCPU
*cpu
= opaque
;
2614 gt_recalc_timer(cpu
, GTIMER_PHYS
);
2617 void arm_gt_vtimer_cb(void *opaque
)
2619 ARMCPU
*cpu
= opaque
;
2621 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2624 void arm_gt_htimer_cb(void *opaque
)
2626 ARMCPU
*cpu
= opaque
;
2628 gt_recalc_timer(cpu
, GTIMER_HYP
);
2631 void arm_gt_stimer_cb(void *opaque
)
2633 ARMCPU
*cpu
= opaque
;
2635 gt_recalc_timer(cpu
, GTIMER_SEC
);
2638 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
2639 /* Note that CNTFRQ is purely reads-as-written for the benefit
2640 * of software; writing it doesn't actually change the timer frequency.
2641 * Our reset value matches the fixed frequency we implement the timer at.
2643 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
2644 .type
= ARM_CP_ALIAS
,
2645 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
2646 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
2648 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
2649 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
2650 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
2651 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
2652 .resetvalue
= (1000 * 1000 * 1000) / GTIMER_SCALE
,
2654 /* overall control: mostly access permissions */
2655 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
2656 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
2658 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
2661 /* per-timer control */
2662 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
2663 .secure
= ARM_CP_SECSTATE_NS
,
2664 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
2665 .accessfn
= gt_ptimer_access
,
2666 .fieldoffset
= offsetoflow32(CPUARMState
,
2667 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
2668 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
2670 { .name
= "CNTP_CTL_S",
2671 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
2672 .secure
= ARM_CP_SECSTATE_S
,
2673 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
2674 .accessfn
= gt_ptimer_access
,
2675 .fieldoffset
= offsetoflow32(CPUARMState
,
2676 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
2677 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
2679 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
2680 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
2681 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2682 .accessfn
= gt_ptimer_access
,
2683 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
2685 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
2687 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
2688 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
2689 .accessfn
= gt_vtimer_access
,
2690 .fieldoffset
= offsetoflow32(CPUARMState
,
2691 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
2692 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
2694 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
2695 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
2696 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2697 .accessfn
= gt_vtimer_access
,
2698 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
2700 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
2702 /* TimerValue views: a 32 bit downcounting view of the underlying state */
2703 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2704 .secure
= ARM_CP_SECSTATE_NS
,
2705 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2706 .accessfn
= gt_ptimer_access
,
2707 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
2709 { .name
= "CNTP_TVAL_S",
2710 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2711 .secure
= ARM_CP_SECSTATE_S
,
2712 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2713 .accessfn
= gt_ptimer_access
,
2714 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
2716 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2717 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
2718 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2719 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
2720 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
2722 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
2723 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2724 .accessfn
= gt_vtimer_access
,
2725 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
2727 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2728 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
2729 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2730 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
2731 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
2733 /* The counter itself */
2734 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
2735 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
2736 .accessfn
= gt_pct_access
,
2737 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
2739 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
2740 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
2741 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2742 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
2744 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
2745 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
2746 .accessfn
= gt_vct_access
,
2747 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
2749 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
2750 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
2751 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2752 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
2754 /* Comparison value, indicating when the timer goes off */
2755 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
2756 .secure
= ARM_CP_SECSTATE_NS
,
2757 .access
= PL1_RW
| PL0_R
,
2758 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2759 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
2760 .accessfn
= gt_ptimer_access
,
2761 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
2763 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
2764 .secure
= ARM_CP_SECSTATE_S
,
2765 .access
= PL1_RW
| PL0_R
,
2766 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2767 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
2768 .accessfn
= gt_ptimer_access
,
2769 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
2771 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2772 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
2773 .access
= PL1_RW
| PL0_R
,
2775 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
2776 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
2777 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
2779 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
2780 .access
= PL1_RW
| PL0_R
,
2781 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2782 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
2783 .accessfn
= gt_vtimer_access
,
2784 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
2786 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2787 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
2788 .access
= PL1_RW
| PL0_R
,
2790 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
2791 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
2792 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
2794 /* Secure timer -- this is actually restricted to only EL3
2795 * and configurably Secure-EL1 via the accessfn.
2797 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
2798 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
2799 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
2800 .accessfn
= gt_stimer_access
,
2801 .readfn
= gt_sec_tval_read
,
2802 .writefn
= gt_sec_tval_write
,
2803 .resetfn
= gt_sec_timer_reset
,
2805 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
2806 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
2807 .type
= ARM_CP_IO
, .access
= PL1_RW
,
2808 .accessfn
= gt_stimer_access
,
2809 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
2811 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
2813 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
2814 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
2815 .type
= ARM_CP_IO
, .access
= PL1_RW
,
2816 .accessfn
= gt_stimer_access
,
2817 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
2818 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
2825 /* In user-mode most of the generic timer registers are inaccessible
2826 * however modern kernels (4.12+) allow access to cntvct_el0
2829 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2831 /* Currently we have no support for QEMUTimer in linux-user so we
2832 * can't call gt_get_countervalue(env), instead we directly
2833 * call the lower level functions.
2835 return cpu_get_clock() / GTIMER_SCALE
;
2838 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
2839 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
2840 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
2841 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
2842 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
2843 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
2845 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
2846 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
2847 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2848 .readfn
= gt_virt_cnt_read
,
2855 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
2857 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2858 raw_write(env
, ri
, value
);
2859 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
2860 raw_write(env
, ri
, value
& 0xfffff6ff);
2862 raw_write(env
, ri
, value
& 0xfffff1ff);
2866 #ifndef CONFIG_USER_ONLY
2867 /* get_phys_addr() isn't present for user-mode-only targets */
2869 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2873 /* The ATS12NSO* operations must trap to EL3 if executed in
2874 * Secure EL1 (which can only happen if EL3 is AArch64).
2875 * They are simply UNDEF if executed from NS EL1.
2876 * They function normally from EL2 or EL3.
2878 if (arm_current_el(env
) == 1) {
2879 if (arm_is_secure_below_el3(env
)) {
2880 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3
;
2882 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2885 return CP_ACCESS_OK
;
2888 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
2889 MMUAccessType access_type
, ARMMMUIdx mmu_idx
)
2892 target_ulong page_size
;
2896 bool format64
= false;
2897 MemTxAttrs attrs
= {};
2898 ARMMMUFaultInfo fi
= {};
2899 ARMCacheAttrs cacheattrs
= {};
2901 ret
= get_phys_addr(env
, value
, access_type
, mmu_idx
, &phys_addr
, &attrs
,
2902 &prot
, &page_size
, &fi
, &cacheattrs
);
2906 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2909 * * TTBCR.EAE determines whether the result is returned using the
2910 * 32-bit or the 64-bit PAR format
2911 * * Instructions executed in Hyp mode always use the 64bit format
2913 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
2914 * * The Non-secure TTBCR.EAE bit is set to 1
2915 * * The implementation includes EL2, and the value of HCR.VM is 1
2917 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
2919 * ATS1Hx always uses the 64bit format.
2921 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
2923 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
2924 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
2925 format64
|= env
->cp15
.hcr_el2
& (HCR_VM
| HCR_DC
);
2927 format64
|= arm_current_el(env
) == 2;
2933 /* Create a 64-bit PAR */
2934 par64
= (1 << 11); /* LPAE bit always set */
2936 par64
|= phys_addr
& ~0xfffULL
;
2937 if (!attrs
.secure
) {
2938 par64
|= (1 << 9); /* NS */
2940 par64
|= (uint64_t)cacheattrs
.attrs
<< 56; /* ATTR */
2941 par64
|= cacheattrs
.shareability
<< 7; /* SH */
2943 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
2946 par64
|= (fsr
& 0x3f) << 1; /* FS */
2948 par64
|= (1 << 9); /* S */
2951 par64
|= (1 << 8); /* PTW */
2955 /* fsr is a DFSR/IFSR value for the short descriptor
2956 * translation table format (with WnR always clear).
2957 * Convert it to a 32-bit PAR.
2960 /* We do not set any attribute bits in the PAR */
2961 if (page_size
== (1 << 24)
2962 && arm_feature(env
, ARM_FEATURE_V7
)) {
2963 par64
= (phys_addr
& 0xff000000) | (1 << 1);
2965 par64
= phys_addr
& 0xfffff000;
2967 if (!attrs
.secure
) {
2968 par64
|= (1 << 9); /* NS */
2971 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
2973 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
2974 ((fsr
& 0xf) << 1) | 1;
2980 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
2982 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
2985 int el
= arm_current_el(env
);
2986 bool secure
= arm_is_secure_below_el3(env
);
2988 switch (ri
->opc2
& 6) {
2990 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
2993 mmu_idx
= ARMMMUIdx_S1E3
;
2996 mmu_idx
= ARMMMUIdx_S1NSE1
;
2999 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
3002 g_assert_not_reached();
3006 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3009 mmu_idx
= ARMMMUIdx_S1SE0
;
3012 mmu_idx
= ARMMMUIdx_S1NSE0
;
3015 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
3018 g_assert_not_reached();
3022 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3023 mmu_idx
= ARMMMUIdx_S12NSE1
;
3026 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3027 mmu_idx
= ARMMMUIdx_S12NSE0
;
3030 g_assert_not_reached();
3033 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
);
3035 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3038 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3041 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3044 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_S1E2
);
3046 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3049 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3052 if (arm_current_el(env
) == 3 && !(env
->cp15
.scr_el3
& SCR_NS
)) {
3053 return CP_ACCESS_TRAP
;
3055 return CP_ACCESS_OK
;
3058 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3061 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3063 int secure
= arm_is_secure_below_el3(env
);
3065 switch (ri
->opc2
& 6) {
3068 case 0: /* AT S1E1R, AT S1E1W */
3069 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
3071 case 4: /* AT S1E2R, AT S1E2W */
3072 mmu_idx
= ARMMMUIdx_S1E2
;
3074 case 6: /* AT S1E3R, AT S1E3W */
3075 mmu_idx
= ARMMMUIdx_S1E3
;
3078 g_assert_not_reached();
3081 case 2: /* AT S1E0R, AT S1E0W */
3082 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
3084 case 4: /* AT S12E1R, AT S12E1W */
3085 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S12NSE1
;
3087 case 6: /* AT S12E0R, AT S12E0W */
3088 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S12NSE0
;
3091 g_assert_not_reached();
3094 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
, mmu_idx
);
3098 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
3099 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
3100 .access
= PL1_RW
, .resetvalue
= 0,
3101 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
3102 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
3103 .writefn
= par_write
},
3104 #ifndef CONFIG_USER_ONLY
3105 /* This underdecoding is safe because the reginfo is NO_RAW. */
3106 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
3107 .access
= PL1_W
, .accessfn
= ats_access
,
3108 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
},
3113 /* Return basic MPU access permission bits. */
3114 static uint32_t simple_mpu_ap_bits(uint32_t val
)
3121 for (i
= 0; i
< 16; i
+= 2) {
3122 ret
|= (val
>> i
) & mask
;
3128 /* Pad basic MPU access permission bits to extended format. */
3129 static uint32_t extended_mpu_ap_bits(uint32_t val
)
3136 for (i
= 0; i
< 16; i
+= 2) {
3137 ret
|= (val
& mask
) << i
;
3143 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3146 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
3149 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3151 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
3154 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3157 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
3160 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3162 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
3165 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3167 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3173 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3177 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3180 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3181 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3187 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3188 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3192 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3195 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3196 uint32_t nrgs
= cpu
->pmsav7_dregion
;
3198 if (value
>= nrgs
) {
3199 qemu_log_mask(LOG_GUEST_ERROR
,
3200 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3201 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
3205 raw_write(env
, ri
, value
);
3208 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
3209 /* Reset for all these registers is handled in arm_cpu_reset(),
3210 * because the PMSAv7 is also used by M-profile CPUs, which do
3211 * not register cpregs but still need the state to be reset.
3213 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
3214 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3215 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
3216 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3217 .resetfn
= arm_cp_reset_ignore
},
3218 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
3219 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3220 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
3221 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3222 .resetfn
= arm_cp_reset_ignore
},
3223 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
3224 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3225 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
3226 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3227 .resetfn
= arm_cp_reset_ignore
},
3228 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
3230 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
3231 .writefn
= pmsav7_rgnr_write
,
3232 .resetfn
= arm_cp_reset_ignore
},
3236 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
3237 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3238 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3239 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3240 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
3241 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3242 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3243 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3244 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
3245 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
3247 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3249 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
3251 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3253 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
3255 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
3256 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
3258 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
3259 /* Protection region base and size registers */
3260 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
3261 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3262 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
3263 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
3264 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3265 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
3266 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
3267 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3268 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
3269 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
3270 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3271 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
3272 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
3273 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3274 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
3275 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
3276 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3277 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
3278 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
3279 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3280 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
3281 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
3282 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3283 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
3287 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3290 TCR
*tcr
= raw_ptr(env
, ri
);
3291 int maskshift
= extract32(value
, 0, 3);
3293 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
3294 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
3295 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
3296 * using Long-desciptor translation table format */
3297 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
3298 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3299 /* In an implementation that includes the Security Extensions
3300 * TTBCR has additional fields PD0 [4] and PD1 [5] for
3301 * Short-descriptor translation table format.
3303 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
3309 /* Update the masks corresponding to the TCR bank being written
3310 * Note that we always calculate mask and base_mask, but
3311 * they are only used for short-descriptor tables (ie if EAE is 0);
3312 * for long-descriptor tables the TCR fields are used differently
3313 * and the mask and base_mask values are meaningless.
3315 tcr
->raw_tcr
= value
;
3316 tcr
->mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
3317 tcr
->base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
3320 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3323 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3324 TCR
*tcr
= raw_ptr(env
, ri
);
3326 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3327 /* With LPAE the TTBCR could result in a change of ASID
3328 * via the TTBCR.A1 bit, so do a TLB flush.
3330 tlb_flush(CPU(cpu
));
3332 /* Preserve the high half of TCR_EL1, set via TTBCR2. */
3333 value
= deposit64(tcr
->raw_tcr
, 0, 32, value
);
3334 vmsa_ttbcr_raw_write(env
, ri
, value
);
3337 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3339 TCR
*tcr
= raw_ptr(env
, ri
);
3341 /* Reset both the TCR as well as the masks corresponding to the bank of
3342 * the TCR being reset.
3346 tcr
->base_mask
= 0xffffc000u
;
3349 static void vmsa_tcr_el1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3352 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3353 TCR
*tcr
= raw_ptr(env
, ri
);
3355 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
3356 tlb_flush(CPU(cpu
));
3357 tcr
->raw_tcr
= value
;
3360 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3363 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
3364 if (cpreg_field_is_64bit(ri
) &&
3365 extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
3366 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3367 tlb_flush(CPU(cpu
));
3369 raw_write(env
, ri
, value
);
3372 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3375 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3376 CPUState
*cs
= CPU(cpu
);
3378 /* Accesses to VTTBR may change the VMID so we must flush the TLB. */
3379 if (raw_read(env
, ri
) != value
) {
3380 tlb_flush_by_mmuidx(cs
,
3381 ARMMMUIdxBit_S12NSE1
|
3382 ARMMMUIdxBit_S12NSE0
|
3384 raw_write(env
, ri
, value
);
3388 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
3389 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3390 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3391 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
3392 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
3393 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3394 .access
= PL1_RW
, .resetvalue
= 0,
3395 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
3396 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
3397 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
3398 .access
= PL1_RW
, .resetvalue
= 0,
3399 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
3400 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
3401 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
3402 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
3403 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
3408 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
3409 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
3410 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
3412 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
3413 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
3414 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
3415 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
3416 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
3417 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
3418 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
3419 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
3420 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
3421 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
3422 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
3423 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
3424 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
3425 .access
= PL1_RW
, .writefn
= vmsa_tcr_el1_write
,
3426 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
3427 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
3428 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
3429 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
3430 .raw_writefn
= vmsa_ttbcr_raw_write
,
3431 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
3432 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
3436 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
3437 * qemu tlbs nor adjusting cached masks.
3439 static const ARMCPRegInfo ttbcr2_reginfo
= {
3440 .name
= "TTBCR2", .cp
= 15, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 3,
3441 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3442 .bank_fieldoffsets
= { offsetofhigh32(CPUARMState
, cp15
.tcr_el
[3]),
3443 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[1]) },
3446 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3449 env
->cp15
.c15_ticonfig
= value
& 0xe7;
3450 /* The OS_TYPE bit in this register changes the reported CPUID! */
3451 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
3452 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
3455 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3458 env
->cp15
.c15_threadid
= value
& 0xffff;
3461 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3464 /* Wait-for-interrupt (deprecated) */
3465 cpu_interrupt(CPU(arm_env_get_cpu(env
)), CPU_INTERRUPT_HALT
);
3468 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3471 /* On OMAP there are registers indicating the max/min index of dcache lines
3472 * containing a dirty line; cache flush operations have to reset these.
3474 env
->cp15
.c15_i_max
= 0x000;
3475 env
->cp15
.c15_i_min
= 0xff0;
3478 static const ARMCPRegInfo omap_cp_reginfo
[] = {
3479 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
3480 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
3481 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
3483 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
3484 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
3485 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
3487 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
3488 .writefn
= omap_ticonfig_write
},
3489 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
3491 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
3492 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
3493 .access
= PL1_RW
, .resetvalue
= 0xff0,
3494 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
3495 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
3497 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
3498 .writefn
= omap_threadid_write
},
3499 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
3500 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
3501 .type
= ARM_CP_NO_RAW
,
3502 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
3503 /* TODO: Peripheral port remap register:
3504 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
3505 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
3508 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
3509 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
3510 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
3511 .writefn
= omap_cachemaint_write
},
3512 { .name
= "C9", .cp
= 15, .crn
= 9,
3513 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
3514 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
3518 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3521 env
->cp15
.c15_cpar
= value
& 0x3fff;
3524 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
3525 { .name
= "XSCALE_CPAR",
3526 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
3527 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
3528 .writefn
= xscale_cpar_write
, },
3529 { .name
= "XSCALE_AUXCR",
3530 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
3531 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
3533 /* XScale specific cache-lockdown: since we have no cache we NOP these
3534 * and hope the guest does not really rely on cache behaviour.
3536 { .name
= "XSCALE_LOCK_ICACHE_LINE",
3537 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
3538 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3539 { .name
= "XSCALE_UNLOCK_ICACHE",
3540 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
3541 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3542 { .name
= "XSCALE_DCACHE_LOCK",
3543 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
3544 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
3545 { .name
= "XSCALE_UNLOCK_DCACHE",
3546 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
3547 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3551 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
3552 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
3553 * implementation of this implementation-defined space.
3554 * Ideally this should eventually disappear in favour of actually
3555 * implementing the correct behaviour for all cores.
3557 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
3558 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
3560 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
3565 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
3566 /* Cache status: RAZ because we have no cache so it's always clean */
3567 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
3568 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3573 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
3574 /* We never have a a block transfer operation in progress */
3575 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
3576 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3578 /* The cache ops themselves: these all NOP for QEMU */
3579 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
3580 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3581 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
3582 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3583 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
3584 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3585 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
3586 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3587 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
3588 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3589 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
3590 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3594 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
3595 /* The cache test-and-clean instructions always return (1 << 30)
3596 * to indicate that there are no dirty cache lines.
3598 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
3599 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3600 .resetvalue
= (1 << 30) },
3601 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
3602 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3603 .resetvalue
= (1 << 30) },
3607 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
3608 /* Ignore ReadBuffer accesses */
3609 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
3610 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
3611 .access
= PL1_RW
, .resetvalue
= 0,
3612 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
3616 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3618 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3619 unsigned int cur_el
= arm_current_el(env
);
3620 bool secure
= arm_is_secure(env
);
3622 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
3623 return env
->cp15
.vpidr_el2
;
3625 return raw_read(env
, ri
);
3628 static uint64_t mpidr_read_val(CPUARMState
*env
)
3630 ARMCPU
*cpu
= ARM_CPU(arm_env_get_cpu(env
));
3631 uint64_t mpidr
= cpu
->mp_affinity
;
3633 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
3634 mpidr
|= (1U << 31);
3635 /* Cores which are uniprocessor (non-coherent)
3636 * but still implement the MP extensions set
3637 * bit 30. (For instance, Cortex-R5).
3639 if (cpu
->mp_is_up
) {
3640 mpidr
|= (1u << 30);
3646 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3648 unsigned int cur_el
= arm_current_el(env
);
3649 bool secure
= arm_is_secure(env
);
3651 if (arm_feature(env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
3652 return env
->cp15
.vmpidr_el2
;
3654 return mpidr_read_val(env
);
3657 static const ARMCPRegInfo mpidr_cp_reginfo
[] = {
3658 { .name
= "MPIDR", .state
= ARM_CP_STATE_BOTH
,
3659 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
3660 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
3664 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
3666 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
3667 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
3668 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
3670 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
3671 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
3672 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
3674 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
3675 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
3676 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
3677 offsetof(CPUARMState
, cp15
.par_ns
)} },
3678 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
3679 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3680 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
3681 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
3682 .writefn
= vmsa_ttbr_write
, },
3683 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
3684 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3685 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
3686 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
3687 .writefn
= vmsa_ttbr_write
, },
3691 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3693 return vfp_get_fpcr(env
);
3696 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3699 vfp_set_fpcr(env
, value
);
3702 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3704 return vfp_get_fpsr(env
);
3707 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3710 vfp_set_fpsr(env
, value
);
3713 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3716 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UMA
)) {
3717 return CP_ACCESS_TRAP
;
3719 return CP_ACCESS_OK
;
3722 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3725 env
->daif
= value
& PSTATE_DAIF
;
3728 static CPAccessResult
aa64_cacheop_access(CPUARMState
*env
,
3729 const ARMCPRegInfo
*ri
,
3732 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
3733 * SCTLR_EL1.UCI is set.
3735 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCI
)) {
3736 return CP_ACCESS_TRAP
;
3738 return CP_ACCESS_OK
;
3741 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
3742 * Page D4-1736 (DDI0487A.b)
3745 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3748 CPUState
*cs
= ENV_GET_CPU(env
);
3749 bool sec
= arm_is_secure_below_el3(env
);
3752 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3753 ARMMMUIdxBit_S1SE1
|
3754 ARMMMUIdxBit_S1SE0
);
3756 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3757 ARMMMUIdxBit_S12NSE1
|
3758 ARMMMUIdxBit_S12NSE0
);
3762 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3765 CPUState
*cs
= ENV_GET_CPU(env
);
3767 if (tlb_force_broadcast(env
)) {
3768 tlbi_aa64_vmalle1is_write(env
, NULL
, value
);
3772 if (arm_is_secure_below_el3(env
)) {
3773 tlb_flush_by_mmuidx(cs
,
3774 ARMMMUIdxBit_S1SE1
|
3775 ARMMMUIdxBit_S1SE0
);
3777 tlb_flush_by_mmuidx(cs
,
3778 ARMMMUIdxBit_S12NSE1
|
3779 ARMMMUIdxBit_S12NSE0
);
3783 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3786 /* Note that the 'ALL' scope must invalidate both stage 1 and
3787 * stage 2 translations, whereas most other scopes only invalidate
3788 * stage 1 translations.
3790 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3791 CPUState
*cs
= CPU(cpu
);
3793 if (arm_is_secure_below_el3(env
)) {
3794 tlb_flush_by_mmuidx(cs
,
3795 ARMMMUIdxBit_S1SE1
|
3796 ARMMMUIdxBit_S1SE0
);
3798 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3799 tlb_flush_by_mmuidx(cs
,
3800 ARMMMUIdxBit_S12NSE1
|
3801 ARMMMUIdxBit_S12NSE0
|
3804 tlb_flush_by_mmuidx(cs
,
3805 ARMMMUIdxBit_S12NSE1
|
3806 ARMMMUIdxBit_S12NSE0
);
3811 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3814 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3815 CPUState
*cs
= CPU(cpu
);
3817 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E2
);
3820 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3823 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3824 CPUState
*cs
= CPU(cpu
);
3826 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E3
);
3829 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3832 /* Note that the 'ALL' scope must invalidate both stage 1 and
3833 * stage 2 translations, whereas most other scopes only invalidate
3834 * stage 1 translations.
3836 CPUState
*cs
= ENV_GET_CPU(env
);
3837 bool sec
= arm_is_secure_below_el3(env
);
3838 bool has_el2
= arm_feature(env
, ARM_FEATURE_EL2
);
3841 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3842 ARMMMUIdxBit_S1SE1
|
3843 ARMMMUIdxBit_S1SE0
);
3844 } else if (has_el2
) {
3845 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3846 ARMMMUIdxBit_S12NSE1
|
3847 ARMMMUIdxBit_S12NSE0
|
3850 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3851 ARMMMUIdxBit_S12NSE1
|
3852 ARMMMUIdxBit_S12NSE0
);
3856 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3859 CPUState
*cs
= ENV_GET_CPU(env
);
3861 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E2
);
3864 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3867 CPUState
*cs
= ENV_GET_CPU(env
);
3869 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E3
);
3872 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3875 /* Invalidate by VA, EL2
3876 * Currently handles both VAE2 and VALE2, since we don't support
3877 * flush-last-level-only.
3879 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3880 CPUState
*cs
= CPU(cpu
);
3881 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3883 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E2
);
3886 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3889 /* Invalidate by VA, EL3
3890 * Currently handles both VAE3 and VALE3, since we don't support
3891 * flush-last-level-only.
3893 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3894 CPUState
*cs
= CPU(cpu
);
3895 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3897 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E3
);
3900 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3903 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3904 CPUState
*cs
= CPU(cpu
);
3905 bool sec
= arm_is_secure_below_el3(env
);
3906 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3909 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3910 ARMMMUIdxBit_S1SE1
|
3911 ARMMMUIdxBit_S1SE0
);
3913 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3914 ARMMMUIdxBit_S12NSE1
|
3915 ARMMMUIdxBit_S12NSE0
);
3919 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3922 /* Invalidate by VA, EL1&0 (AArch64 version).
3923 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
3924 * since we don't support flush-for-specific-ASID-only or
3925 * flush-last-level-only.
3927 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3928 CPUState
*cs
= CPU(cpu
);
3929 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3931 if (tlb_force_broadcast(env
)) {
3932 tlbi_aa64_vae1is_write(env
, NULL
, value
);
3936 if (arm_is_secure_below_el3(env
)) {
3937 tlb_flush_page_by_mmuidx(cs
, pageaddr
,
3938 ARMMMUIdxBit_S1SE1
|
3939 ARMMMUIdxBit_S1SE0
);
3941 tlb_flush_page_by_mmuidx(cs
, pageaddr
,
3942 ARMMMUIdxBit_S12NSE1
|
3943 ARMMMUIdxBit_S12NSE0
);
3947 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3950 CPUState
*cs
= ENV_GET_CPU(env
);
3951 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3953 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3957 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3960 CPUState
*cs
= ENV_GET_CPU(env
);
3961 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3963 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3967 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3970 /* Invalidate by IPA. This has to invalidate any structures that
3971 * contain only stage 2 translation information, but does not need
3972 * to apply to structures that contain combined stage 1 and stage 2
3973 * translation information.
3974 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
3976 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3977 CPUState
*cs
= CPU(cpu
);
3980 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
3984 pageaddr
= sextract64(value
<< 12, 0, 48);
3986 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S2NS
);
3989 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3992 CPUState
*cs
= ENV_GET_CPU(env
);
3995 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
3999 pageaddr
= sextract64(value
<< 12, 0, 48);
4001 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4005 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4008 /* We don't implement EL2, so the only control on DC ZVA is the
4009 * bit in the SCTLR which can prohibit access for EL0.
4011 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
4012 return CP_ACCESS_TRAP
;
4014 return CP_ACCESS_OK
;
4017 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4019 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4020 int dzp_bit
= 1 << 4;
4022 /* DZP indicates whether DC ZVA access is allowed */
4023 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
4026 return cpu
->dcz_blocksize
| dzp_bit
;
4029 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4032 if (!(env
->pstate
& PSTATE_SP
)) {
4033 /* Access to SP_EL0 is undefined if it's being used as
4034 * the stack pointer.
4036 return CP_ACCESS_TRAP_UNCATEGORIZED
;
4038 return CP_ACCESS_OK
;
4041 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4043 return env
->pstate
& PSTATE_SP
;
4046 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
4048 update_spsel(env
, val
);
4051 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4054 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4056 if (raw_read(env
, ri
) == value
) {
4057 /* Skip the TLB flush if nothing actually changed; Linux likes
4058 * to do a lot of pointless SCTLR writes.
4063 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
4064 /* M bit is RAZ/WI for PMSA with no MPU implemented */
4068 raw_write(env
, ri
, value
);
4069 /* ??? Lots of these bits are not implemented. */
4070 /* This may enable/disable the MMU, so do a TLB flush. */
4071 tlb_flush(CPU(cpu
));
4074 static CPAccessResult
fpexc32_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4077 if ((env
->cp15
.cptr_el
[2] & CPTR_TFP
) && arm_current_el(env
) == 2) {
4078 return CP_ACCESS_TRAP_FP_EL2
;
4080 if (env
->cp15
.cptr_el
[3] & CPTR_TFP
) {
4081 return CP_ACCESS_TRAP_FP_EL3
;
4083 return CP_ACCESS_OK
;
4086 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4089 env
->cp15
.mdcr_el3
= value
& SDCR_VALID_MASK
;
4092 static const ARMCPRegInfo v8_cp_reginfo
[] = {
4093 /* Minimal set of EL0-visible registers. This will need to be expanded
4094 * significantly for system emulation of AArch64 CPUs.
4096 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
4097 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
4098 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
4099 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
4100 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
4101 .type
= ARM_CP_NO_RAW
,
4102 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
4103 .fieldoffset
= offsetof(CPUARMState
, daif
),
4104 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
4105 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
4106 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
4107 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4108 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
4109 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
4110 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
4111 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4112 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
4113 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
4114 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
4115 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
4116 .readfn
= aa64_dczid_read
},
4117 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
4118 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
4119 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
4120 #ifndef CONFIG_USER_ONLY
4121 /* Avoid overhead of an access check that always passes in user-mode */
4122 .accessfn
= aa64_zva_access
,
4125 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
4126 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
4127 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
4128 /* Cache ops: all NOPs since we don't emulate caches */
4129 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
4130 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
4131 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4132 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
4133 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
4134 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4135 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
4136 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
4137 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4138 .accessfn
= aa64_cacheop_access
},
4139 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
4140 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
4141 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4142 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
4143 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
4144 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4145 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
4146 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
4147 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4148 .accessfn
= aa64_cacheop_access
},
4149 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
4150 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
4151 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4152 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
4153 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
4154 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4155 .accessfn
= aa64_cacheop_access
},
4156 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
4157 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
4158 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4159 .accessfn
= aa64_cacheop_access
},
4160 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
4161 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
4162 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4163 /* TLBI operations */
4164 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
4165 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
4166 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4167 .writefn
= tlbi_aa64_vmalle1is_write
},
4168 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
4169 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
4170 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4171 .writefn
= tlbi_aa64_vae1is_write
},
4172 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
4173 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
4174 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4175 .writefn
= tlbi_aa64_vmalle1is_write
},
4176 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
4177 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
4178 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4179 .writefn
= tlbi_aa64_vae1is_write
},
4180 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
4181 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
4182 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4183 .writefn
= tlbi_aa64_vae1is_write
},
4184 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
4185 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
4186 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4187 .writefn
= tlbi_aa64_vae1is_write
},
4188 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
4189 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
4190 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4191 .writefn
= tlbi_aa64_vmalle1_write
},
4192 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
4193 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
4194 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4195 .writefn
= tlbi_aa64_vae1_write
},
4196 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
4197 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
4198 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4199 .writefn
= tlbi_aa64_vmalle1_write
},
4200 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
4201 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
4202 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4203 .writefn
= tlbi_aa64_vae1_write
},
4204 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
4205 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
4206 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4207 .writefn
= tlbi_aa64_vae1_write
},
4208 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
4209 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
4210 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4211 .writefn
= tlbi_aa64_vae1_write
},
4212 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
4213 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
4214 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4215 .writefn
= tlbi_aa64_ipas2e1is_write
},
4216 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
4217 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
4218 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4219 .writefn
= tlbi_aa64_ipas2e1is_write
},
4220 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
4221 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
4222 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4223 .writefn
= tlbi_aa64_alle1is_write
},
4224 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
4225 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
4226 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4227 .writefn
= tlbi_aa64_alle1is_write
},
4228 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
4229 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
4230 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4231 .writefn
= tlbi_aa64_ipas2e1_write
},
4232 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
4233 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
4234 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4235 .writefn
= tlbi_aa64_ipas2e1_write
},
4236 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
4237 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
4238 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4239 .writefn
= tlbi_aa64_alle1_write
},
4240 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
4241 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
4242 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4243 .writefn
= tlbi_aa64_alle1is_write
},
4244 #ifndef CONFIG_USER_ONLY
4245 /* 64 bit address translation operations */
4246 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
4247 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
4248 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4249 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
4250 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
4251 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4252 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
4253 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
4254 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4255 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
4256 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
4257 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4258 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
4259 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
4260 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4261 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
4262 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
4263 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4264 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
4265 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
4266 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4267 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
4268 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
4269 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4270 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
4271 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
4272 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
4273 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4274 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
4275 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
4276 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4277 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
4278 .type
= ARM_CP_ALIAS
,
4279 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
4280 .access
= PL1_RW
, .resetvalue
= 0,
4281 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
4282 .writefn
= par_write
},
4284 /* TLB invalidate last level of translation table walk */
4285 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
4286 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
4287 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
4288 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
4289 .writefn
= tlbimvaa_is_write
},
4290 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
4291 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
4292 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
4293 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
4294 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
4295 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4296 .writefn
= tlbimva_hyp_write
},
4297 { .name
= "TLBIMVALHIS",
4298 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
4299 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4300 .writefn
= tlbimva_hyp_is_write
},
4301 { .name
= "TLBIIPAS2",
4302 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
4303 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4304 .writefn
= tlbiipas2_write
},
4305 { .name
= "TLBIIPAS2IS",
4306 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
4307 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4308 .writefn
= tlbiipas2_is_write
},
4309 { .name
= "TLBIIPAS2L",
4310 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
4311 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4312 .writefn
= tlbiipas2_write
},
4313 { .name
= "TLBIIPAS2LIS",
4314 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
4315 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4316 .writefn
= tlbiipas2_is_write
},
4317 /* 32 bit cache operations */
4318 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
4319 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4320 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
4321 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4322 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
4323 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4324 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
4325 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4326 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
4327 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4328 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
4329 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4330 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
4331 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4332 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
4333 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4334 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
4335 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4336 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
4337 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4338 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
4339 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4340 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
4341 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4342 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
4343 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4344 /* MMU Domain access control / MPU write buffer control */
4345 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
4346 .access
= PL1_RW
, .resetvalue
= 0,
4347 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
4348 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
4349 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
4350 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
4351 .type
= ARM_CP_ALIAS
,
4352 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
4354 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
4355 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
4356 .type
= ARM_CP_ALIAS
,
4357 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
4359 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
4360 /* We rely on the access checks not allowing the guest to write to the
4361 * state field when SPSel indicates that it's being used as the stack
4364 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
4365 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
4366 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
4367 .type
= ARM_CP_ALIAS
,
4368 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
4369 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
4370 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
4371 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
4372 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
4373 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
4374 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
4375 .type
= ARM_CP_NO_RAW
,
4376 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
4377 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
4378 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
4379 .type
= ARM_CP_ALIAS
,
4380 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]),
4381 .access
= PL2_RW
, .accessfn
= fpexc32_access
},
4382 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
4383 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
4384 .access
= PL2_RW
, .resetvalue
= 0,
4385 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
4386 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
4387 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
4388 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
4389 .access
= PL2_RW
, .resetvalue
= 0,
4390 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
4391 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
4392 .type
= ARM_CP_ALIAS
,
4393 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
4395 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
4396 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
4397 .type
= ARM_CP_ALIAS
,
4398 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
4400 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
4401 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
4402 .type
= ARM_CP_ALIAS
,
4403 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
4405 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
4406 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
4407 .type
= ARM_CP_ALIAS
,
4408 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
4410 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
4411 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
4412 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
4414 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
4415 { .name
= "SDCR", .type
= ARM_CP_ALIAS
,
4416 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
4417 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
4418 .writefn
= sdcr_write
,
4419 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
4423 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
4424 static const ARMCPRegInfo el3_no_el2_cp_reginfo
[] = {
4425 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
4426 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
4428 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
4429 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4430 .type
= ARM_CP_NO_RAW
,
4431 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
4433 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4434 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
4435 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
4437 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4438 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
4439 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
4440 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4441 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
4442 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
4443 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4445 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
4446 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
4447 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4448 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
4449 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
4450 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4452 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
4453 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
4454 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4456 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
4457 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
4458 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4460 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
4461 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
4462 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4464 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4465 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
4466 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4467 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4468 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
4469 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
4470 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4471 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
4472 .cp
= 15, .opc1
= 6, .crm
= 2,
4473 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4474 .type
= ARM_CP_CONST
| ARM_CP_64BIT
, .resetvalue
= 0 },
4475 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
4476 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
4477 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4478 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
4479 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
4480 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4481 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
4482 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
4483 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4484 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
4485 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
4486 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4487 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
4488 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
4490 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
4491 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
4492 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4493 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
4494 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
4495 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4496 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
4497 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
4499 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
4500 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
4501 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4502 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
4503 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
4505 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
4506 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
4507 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4508 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
4509 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
4510 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4511 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4512 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
4513 .access
= PL2_RW
, .accessfn
= access_tda
,
4514 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4515 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_BOTH
,
4516 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
4517 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
4518 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4519 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
4520 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
4521 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4522 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
4523 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
4524 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4525 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
4526 .type
= ARM_CP_CONST
,
4527 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
4528 .access
= PL2_RW
, .resetvalue
= 0 },
4532 /* Ditto, but for registers which exist in ARMv8 but not v7 */
4533 static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo
[] = {
4534 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
4535 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
4537 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4541 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
4543 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4544 uint64_t valid_mask
= HCR_MASK
;
4546 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4547 valid_mask
&= ~HCR_HCD
;
4548 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
4549 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
4550 * However, if we're using the SMC PSCI conduit then QEMU is
4551 * effectively acting like EL3 firmware and so the guest at
4552 * EL2 should retain the ability to prevent EL1 from being
4553 * able to make SMC calls into the ersatz firmware, so in
4554 * that case HCR.TSC should be read/write.
4556 valid_mask
&= ~HCR_TSC
;
4558 if (cpu_isar_feature(aa64_lor
, cpu
)) {
4559 valid_mask
|= HCR_TLOR
;
4562 /* Clear RES0 bits. */
4563 value
&= valid_mask
;
4565 /* These bits change the MMU setup:
4566 * HCR_VM enables stage 2 translation
4567 * HCR_PTW forbids certain page-table setups
4568 * HCR_DC Disables stage1 and enables stage2 translation
4570 if ((env
->cp15
.hcr_el2
^ value
) & (HCR_VM
| HCR_PTW
| HCR_DC
)) {
4571 tlb_flush(CPU(cpu
));
4573 env
->cp15
.hcr_el2
= value
;
4576 * Updates to VI and VF require us to update the status of
4577 * virtual interrupts, which are the logical OR of these bits
4578 * and the state of the input lines from the GIC. (This requires
4579 * that we have the iothread lock, which is done by marking the
4580 * reginfo structs as ARM_CP_IO.)
4581 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
4582 * possible for it to be taken immediately, because VIRQ and
4583 * VFIQ are masked unless running at EL0 or EL1, and HCR
4584 * can only be written at EL2.
4586 g_assert(qemu_mutex_iothread_locked());
4587 arm_cpu_update_virq(cpu
);
4588 arm_cpu_update_vfiq(cpu
);
4591 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4594 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
4595 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
4596 hcr_write(env
, NULL
, value
);
4599 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4602 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
4603 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
4604 hcr_write(env
, NULL
, value
);
4608 * Return the effective value of HCR_EL2.
4609 * Bits that are not included here:
4610 * RW (read from SCR_EL3.RW as needed)
4612 uint64_t arm_hcr_el2_eff(CPUARMState
*env
)
4614 uint64_t ret
= env
->cp15
.hcr_el2
;
4616 if (arm_is_secure_below_el3(env
)) {
4618 * "This register has no effect if EL2 is not enabled in the
4619 * current Security state". This is ARMv8.4-SecEL2 speak for
4620 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
4622 * Prior to that, the language was "In an implementation that
4623 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
4624 * as if this field is 0 for all purposes other than a direct
4625 * read or write access of HCR_EL2". With lots of enumeration
4626 * on a per-field basis. In current QEMU, this is condition
4627 * is arm_is_secure_below_el3.
4629 * Since the v8.4 language applies to the entire register, and
4630 * appears to be backward compatible, use that.
4633 } else if (ret
& HCR_TGE
) {
4634 /* These bits are up-to-date as of ARMv8.4. */
4635 if (ret
& HCR_E2H
) {
4636 ret
&= ~(HCR_VM
| HCR_FMO
| HCR_IMO
| HCR_AMO
|
4637 HCR_BSU_MASK
| HCR_DC
| HCR_TWI
| HCR_TWE
|
4638 HCR_TID0
| HCR_TID2
| HCR_TPCP
| HCR_TPU
|
4639 HCR_TDZ
| HCR_CD
| HCR_ID
| HCR_MIOCNCE
);
4641 ret
|= HCR_FMO
| HCR_IMO
| HCR_AMO
;
4643 ret
&= ~(HCR_SWIO
| HCR_PTW
| HCR_VF
| HCR_VI
| HCR_VSE
|
4644 HCR_FB
| HCR_TID1
| HCR_TID3
| HCR_TSC
| HCR_TACR
|
4645 HCR_TSW
| HCR_TTLB
| HCR_TVM
| HCR_HCD
| HCR_TRVM
|
4652 static const ARMCPRegInfo el2_cp_reginfo
[] = {
4653 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
4655 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
4656 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
4657 .writefn
= hcr_write
},
4658 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
4659 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
4660 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
4661 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
4662 .writefn
= hcr_writelow
},
4663 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
4664 .type
= ARM_CP_ALIAS
,
4665 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
4667 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
4668 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
4669 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
4670 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
4671 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
4672 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
4673 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
4674 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
4675 .type
= ARM_CP_ALIAS
,
4676 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
4678 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
4679 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
4680 .type
= ARM_CP_ALIAS
,
4681 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
4683 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
4684 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
4685 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
4686 .access
= PL2_RW
, .writefn
= vbar_write
,
4687 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
4689 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
4690 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
4691 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
4692 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
4693 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
4694 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
4695 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
4696 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]) },
4697 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
4698 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
4699 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
4701 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
4702 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
4703 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
4704 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
4705 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
4706 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
4707 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4709 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
4710 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
4711 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
4712 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4714 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
4715 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
4716 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4718 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
4719 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
4720 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4722 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4723 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
4725 /* no .writefn needed as this can't cause an ASID change;
4726 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
4728 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
4729 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
4730 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
4731 .type
= ARM_CP_ALIAS
,
4732 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4733 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
4734 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
4735 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
4737 /* no .writefn needed as this can't cause an ASID change;
4738 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
4740 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
4741 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
4742 .cp
= 15, .opc1
= 6, .crm
= 2,
4743 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4744 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4745 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
4746 .writefn
= vttbr_write
},
4747 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
4748 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
4749 .access
= PL2_RW
, .writefn
= vttbr_write
,
4750 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
4751 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
4752 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
4753 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
4754 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
4755 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
4756 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
4757 .access
= PL2_RW
, .resetvalue
= 0,
4758 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
4759 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
4760 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
4761 .access
= PL2_RW
, .resetvalue
= 0,
4762 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
4763 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
4764 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4765 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
4766 { .name
= "TLBIALLNSNH",
4767 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
4768 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4769 .writefn
= tlbiall_nsnh_write
},
4770 { .name
= "TLBIALLNSNHIS",
4771 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
4772 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4773 .writefn
= tlbiall_nsnh_is_write
},
4774 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
4775 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4776 .writefn
= tlbiall_hyp_write
},
4777 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
4778 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4779 .writefn
= tlbiall_hyp_is_write
},
4780 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
4781 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4782 .writefn
= tlbimva_hyp_write
},
4783 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
4784 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4785 .writefn
= tlbimva_hyp_is_write
},
4786 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
4787 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
4788 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4789 .writefn
= tlbi_aa64_alle2_write
},
4790 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
4791 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
4792 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4793 .writefn
= tlbi_aa64_vae2_write
},
4794 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
4795 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
4796 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4797 .writefn
= tlbi_aa64_vae2_write
},
4798 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
4799 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
4800 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4801 .writefn
= tlbi_aa64_alle2is_write
},
4802 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
4803 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
4804 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4805 .writefn
= tlbi_aa64_vae2is_write
},
4806 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
4807 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
4808 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4809 .writefn
= tlbi_aa64_vae2is_write
},
4810 #ifndef CONFIG_USER_ONLY
4811 /* Unlike the other EL2-related AT operations, these must
4812 * UNDEF from EL3 if EL2 is not implemented, which is why we
4813 * define them here rather than with the rest of the AT ops.
4815 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
4816 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
4817 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
4818 .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4819 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
4820 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
4821 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
4822 .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4823 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
4824 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
4825 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
4826 * to behave as if SCR.NS was 1.
4828 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
4830 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
},
4831 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
4833 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
},
4834 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
4835 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
4836 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
4837 * reset values as IMPDEF. We choose to reset to 3 to comply with
4838 * both ARMv7 and ARMv8.
4840 .access
= PL2_RW
, .resetvalue
= 3,
4841 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
4842 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
4843 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
4844 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
4845 .writefn
= gt_cntvoff_write
,
4846 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
4847 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
4848 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
4849 .writefn
= gt_cntvoff_write
,
4850 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
4851 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
4852 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
4853 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
4854 .type
= ARM_CP_IO
, .access
= PL2_RW
,
4855 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
4856 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
4857 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
4858 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
4859 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
4860 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
4861 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
4862 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
4863 .resetfn
= gt_hyp_timer_reset
,
4864 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
4865 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
4867 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
4869 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
4871 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
4873 /* The only field of MDCR_EL2 that has a defined architectural reset value
4874 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
4875 * don't implement any PMU event counters, so using zero as a reset
4876 * value for MDCR_EL2 is okay
4878 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4879 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
4880 .access
= PL2_RW
, .resetvalue
= 0,
4881 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
), },
4882 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
4883 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
4884 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4885 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
4886 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
4887 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
4889 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
4890 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
4891 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
4893 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
4897 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
4898 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
4899 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
4900 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
4902 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
4903 .writefn
= hcr_writehigh
},
4907 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4910 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
4911 * At Secure EL1 it traps to EL3.
4913 if (arm_current_el(env
) == 3) {
4914 return CP_ACCESS_OK
;
4916 if (arm_is_secure_below_el3(env
)) {
4917 return CP_ACCESS_TRAP_EL3
;
4919 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
4921 return CP_ACCESS_OK
;
4923 return CP_ACCESS_TRAP_UNCATEGORIZED
;
4926 static const ARMCPRegInfo el3_cp_reginfo
[] = {
4927 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
4928 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
4929 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
4930 .resetvalue
= 0, .writefn
= scr_write
},
4931 { .name
= "SCR", .type
= ARM_CP_ALIAS
,
4932 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
4933 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
4934 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
4935 .writefn
= scr_write
},
4936 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
4937 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
4938 .access
= PL3_RW
, .resetvalue
= 0,
4939 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
4941 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
4942 .access
= PL3_RW
, .resetvalue
= 0,
4943 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
4944 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
4945 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
4946 .writefn
= vbar_write
, .resetvalue
= 0,
4947 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
4948 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
4949 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
4950 .access
= PL3_RW
, .resetvalue
= 0,
4951 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
4952 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
4953 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
4955 /* no .writefn needed as this can't cause an ASID change;
4956 * we must provide a .raw_writefn and .resetfn because we handle
4957 * reset and migration for the AArch32 TTBCR(S), which might be
4958 * using mask and base_mask.
4960 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= vmsa_ttbcr_raw_write
,
4961 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
4962 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
4963 .type
= ARM_CP_ALIAS
,
4964 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
4966 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
4967 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
4968 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
4969 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
4970 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
4971 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
4972 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
4973 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
4974 .type
= ARM_CP_ALIAS
,
4975 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
4977 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
4978 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
4979 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
4980 .access
= PL3_RW
, .writefn
= vbar_write
,
4981 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
4983 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
4984 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
4985 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
4986 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
4987 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
4988 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
4989 .access
= PL3_RW
, .resetvalue
= 0,
4990 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
4991 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
4992 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
4993 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
4995 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
4996 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
4997 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
4999 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
5000 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
5001 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5003 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
5004 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
5005 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5006 .writefn
= tlbi_aa64_alle3is_write
},
5007 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
5008 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
5009 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5010 .writefn
= tlbi_aa64_vae3is_write
},
5011 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
5012 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
5013 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5014 .writefn
= tlbi_aa64_vae3is_write
},
5015 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
5016 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
5017 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5018 .writefn
= tlbi_aa64_alle3_write
},
5019 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
5020 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
5021 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5022 .writefn
= tlbi_aa64_vae3_write
},
5023 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
5024 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
5025 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5026 .writefn
= tlbi_aa64_vae3_write
},
5030 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5033 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
5034 * but the AArch32 CTR has its own reginfo struct)
5036 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
5037 return CP_ACCESS_TRAP
;
5039 return CP_ACCESS_OK
;
5042 static void oslar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5045 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
5046 * read via a bit in OSLSR_EL1.
5050 if (ri
->state
== ARM_CP_STATE_AA32
) {
5051 oslock
= (value
== 0xC5ACCE55);
5056 env
->cp15
.oslsr_el1
= deposit32(env
->cp15
.oslsr_el1
, 1, 1, oslock
);
5059 static const ARMCPRegInfo debug_cp_reginfo
[] = {
5060 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
5061 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
5062 * unlike DBGDRAR it is never accessible from EL0.
5063 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
5066 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
5067 .access
= PL0_R
, .accessfn
= access_tdra
,
5068 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5069 { .name
= "MDRAR_EL1", .state
= ARM_CP_STATE_AA64
,
5070 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
5071 .access
= PL1_R
, .accessfn
= access_tdra
,
5072 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5073 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
5074 .access
= PL0_R
, .accessfn
= access_tdra
,
5075 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5076 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
5077 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_BOTH
,
5078 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
5079 .access
= PL1_RW
, .accessfn
= access_tda
,
5080 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
),
5082 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
5083 * We don't implement the configurable EL0 access.
5085 { .name
= "MDCCSR_EL0", .state
= ARM_CP_STATE_BOTH
,
5086 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
5087 .type
= ARM_CP_ALIAS
,
5088 .access
= PL1_R
, .accessfn
= access_tda
,
5089 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
), },
5090 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_BOTH
,
5091 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
5092 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
5093 .accessfn
= access_tdosa
,
5094 .writefn
= oslar_write
},
5095 { .name
= "OSLSR_EL1", .state
= ARM_CP_STATE_BOTH
,
5096 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 4,
5097 .access
= PL1_R
, .resetvalue
= 10,
5098 .accessfn
= access_tdosa
,
5099 .fieldoffset
= offsetof(CPUARMState
, cp15
.oslsr_el1
) },
5100 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
5101 { .name
= "OSDLR_EL1", .state
= ARM_CP_STATE_BOTH
,
5102 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 4,
5103 .access
= PL1_RW
, .accessfn
= access_tdosa
,
5104 .type
= ARM_CP_NOP
},
5105 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
5106 * implement vector catch debug events yet.
5109 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
5110 .access
= PL1_RW
, .accessfn
= access_tda
,
5111 .type
= ARM_CP_NOP
},
5112 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
5113 * to save and restore a 32-bit guest's DBGVCR)
5115 { .name
= "DBGVCR32_EL2", .state
= ARM_CP_STATE_AA64
,
5116 .opc0
= 2, .opc1
= 4, .crn
= 0, .crm
= 7, .opc2
= 0,
5117 .access
= PL2_RW
, .accessfn
= access_tda
,
5118 .type
= ARM_CP_NOP
},
5119 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
5120 * Channel but Linux may try to access this register. The 32-bit
5121 * alias is DBGDCCINT.
5123 { .name
= "MDCCINT_EL1", .state
= ARM_CP_STATE_BOTH
,
5124 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
5125 .access
= PL1_RW
, .accessfn
= access_tda
,
5126 .type
= ARM_CP_NOP
},
5130 static const ARMCPRegInfo debug_lpae_cp_reginfo
[] = {
5131 /* 64 bit access versions of the (dummy) debug registers */
5132 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
5133 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
5134 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
5135 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
5139 /* Return the exception level to which exceptions should be taken
5140 * via SVEAccessTrap. If an exception should be routed through
5141 * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
5142 * take care of raising that exception.
5143 * C.f. the ARM pseudocode function CheckSVEEnabled.
5145 int sve_exception_el(CPUARMState
*env
, int el
)
5147 #ifndef CONFIG_USER_ONLY
5149 bool disabled
= false;
5151 /* The CPACR.ZEN controls traps to EL1:
5152 * 0, 2 : trap EL0 and EL1 accesses
5153 * 1 : trap only EL0 accesses
5154 * 3 : trap no accesses
5156 if (!extract32(env
->cp15
.cpacr_el1
, 16, 1)) {
5158 } else if (!extract32(env
->cp15
.cpacr_el1
, 17, 1)) {
5163 return (arm_feature(env
, ARM_FEATURE_EL2
)
5164 && (arm_hcr_el2_eff(env
) & HCR_TGE
) ? 2 : 1);
5167 /* Check CPACR.FPEN. */
5168 if (!extract32(env
->cp15
.cpacr_el1
, 20, 1)) {
5170 } else if (!extract32(env
->cp15
.cpacr_el1
, 21, 1)) {
5178 /* CPTR_EL2. Since TZ and TFP are positive,
5179 * they will be zero when EL2 is not present.
5181 if (el
<= 2 && !arm_is_secure_below_el3(env
)) {
5182 if (env
->cp15
.cptr_el
[2] & CPTR_TZ
) {
5185 if (env
->cp15
.cptr_el
[2] & CPTR_TFP
) {
5190 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
5191 if (arm_feature(env
, ARM_FEATURE_EL3
)
5192 && !(env
->cp15
.cptr_el
[3] & CPTR_EZ
)) {
5200 * Given that SVE is enabled, return the vector length for EL.
5202 uint32_t sve_zcr_len_for_el(CPUARMState
*env
, int el
)
5204 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5205 uint32_t zcr_len
= cpu
->sve_max_vq
- 1;
5208 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[1]);
5210 if (el
< 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
5211 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[2]);
5213 if (el
< 3 && arm_feature(env
, ARM_FEATURE_EL3
)) {
5214 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[3]);
5219 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5222 int cur_el
= arm_current_el(env
);
5223 int old_len
= sve_zcr_len_for_el(env
, cur_el
);
5226 /* Bits other than [3:0] are RAZ/WI. */
5227 raw_write(env
, ri
, value
& 0xf);
5230 * Because we arrived here, we know both FP and SVE are enabled;
5231 * otherwise we would have trapped access to the ZCR_ELn register.
5233 new_len
= sve_zcr_len_for_el(env
, cur_el
);
5234 if (new_len
< old_len
) {
5235 aarch64_sve_narrow_vq(env
, new_len
+ 1);
5239 static const ARMCPRegInfo zcr_el1_reginfo
= {
5240 .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
5241 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
5242 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
5243 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
5244 .writefn
= zcr_write
, .raw_writefn
= raw_write
5247 static const ARMCPRegInfo zcr_el2_reginfo
= {
5248 .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
5249 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
5250 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
5251 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
5252 .writefn
= zcr_write
, .raw_writefn
= raw_write
5255 static const ARMCPRegInfo zcr_no_el2_reginfo
= {
5256 .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
5257 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
5258 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
5259 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
5262 static const ARMCPRegInfo zcr_el3_reginfo
= {
5263 .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
5264 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
5265 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
5266 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
5267 .writefn
= zcr_write
, .raw_writefn
= raw_write
5270 void hw_watchpoint_update(ARMCPU
*cpu
, int n
)
5272 CPUARMState
*env
= &cpu
->env
;
5274 vaddr wvr
= env
->cp15
.dbgwvr
[n
];
5275 uint64_t wcr
= env
->cp15
.dbgwcr
[n
];
5277 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
5279 if (env
->cpu_watchpoint
[n
]) {
5280 cpu_watchpoint_remove_by_ref(CPU(cpu
), env
->cpu_watchpoint
[n
]);
5281 env
->cpu_watchpoint
[n
] = NULL
;
5284 if (!extract64(wcr
, 0, 1)) {
5285 /* E bit clear : watchpoint disabled */
5289 switch (extract64(wcr
, 3, 2)) {
5291 /* LSC 00 is reserved and must behave as if the wp is disabled */
5294 flags
|= BP_MEM_READ
;
5297 flags
|= BP_MEM_WRITE
;
5300 flags
|= BP_MEM_ACCESS
;
5304 /* Attempts to use both MASK and BAS fields simultaneously are
5305 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
5306 * thus generating a watchpoint for every byte in the masked region.
5308 mask
= extract64(wcr
, 24, 4);
5309 if (mask
== 1 || mask
== 2) {
5310 /* Reserved values of MASK; we must act as if the mask value was
5311 * some non-reserved value, or as if the watchpoint were disabled.
5312 * We choose the latter.
5316 /* Watchpoint covers an aligned area up to 2GB in size */
5318 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
5319 * whether the watchpoint fires when the unmasked bits match; we opt
5320 * to generate the exceptions.
5324 /* Watchpoint covers bytes defined by the byte address select bits */
5325 int bas
= extract64(wcr
, 5, 8);
5329 /* This must act as if the watchpoint is disabled */
5333 if (extract64(wvr
, 2, 1)) {
5334 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
5335 * ignored, and BAS[3:0] define which bytes to watch.
5339 /* The BAS bits are supposed to be programmed to indicate a contiguous
5340 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
5341 * we fire for each byte in the word/doubleword addressed by the WVR.
5342 * We choose to ignore any non-zero bits after the first range of 1s.
5344 basstart
= ctz32(bas
);
5345 len
= cto32(bas
>> basstart
);
5349 cpu_watchpoint_insert(CPU(cpu
), wvr
, len
, flags
,
5350 &env
->cpu_watchpoint
[n
]);
5353 void hw_watchpoint_update_all(ARMCPU
*cpu
)
5356 CPUARMState
*env
= &cpu
->env
;
5358 /* Completely clear out existing QEMU watchpoints and our array, to
5359 * avoid possible stale entries following migration load.
5361 cpu_watchpoint_remove_all(CPU(cpu
), BP_CPU
);
5362 memset(env
->cpu_watchpoint
, 0, sizeof(env
->cpu_watchpoint
));
5364 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_watchpoint
); i
++) {
5365 hw_watchpoint_update(cpu
, i
);
5369 static void dbgwvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5372 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5375 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
5376 * register reads and behaves as if values written are sign extended.
5377 * Bits [1:0] are RES0.
5379 value
= sextract64(value
, 0, 49) & ~3ULL;
5381 raw_write(env
, ri
, value
);
5382 hw_watchpoint_update(cpu
, i
);
5385 static void dbgwcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5388 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5391 raw_write(env
, ri
, value
);
5392 hw_watchpoint_update(cpu
, i
);
5395 void hw_breakpoint_update(ARMCPU
*cpu
, int n
)
5397 CPUARMState
*env
= &cpu
->env
;
5398 uint64_t bvr
= env
->cp15
.dbgbvr
[n
];
5399 uint64_t bcr
= env
->cp15
.dbgbcr
[n
];
5404 if (env
->cpu_breakpoint
[n
]) {
5405 cpu_breakpoint_remove_by_ref(CPU(cpu
), env
->cpu_breakpoint
[n
]);
5406 env
->cpu_breakpoint
[n
] = NULL
;
5409 if (!extract64(bcr
, 0, 1)) {
5410 /* E bit clear : watchpoint disabled */
5414 bt
= extract64(bcr
, 20, 4);
5417 case 4: /* unlinked address mismatch (reserved if AArch64) */
5418 case 5: /* linked address mismatch (reserved if AArch64) */
5419 qemu_log_mask(LOG_UNIMP
,
5420 "arm: address mismatch breakpoint types not implemented\n");
5422 case 0: /* unlinked address match */
5423 case 1: /* linked address match */
5425 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
5426 * we behave as if the register was sign extended. Bits [1:0] are
5427 * RES0. The BAS field is used to allow setting breakpoints on 16
5428 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
5429 * a bp will fire if the addresses covered by the bp and the addresses
5430 * covered by the insn overlap but the insn doesn't start at the
5431 * start of the bp address range. We choose to require the insn and
5432 * the bp to have the same address. The constraints on writing to
5433 * BAS enforced in dbgbcr_write mean we have only four cases:
5434 * 0b0000 => no breakpoint
5435 * 0b0011 => breakpoint on addr
5436 * 0b1100 => breakpoint on addr + 2
5437 * 0b1111 => breakpoint on addr
5438 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
5440 int bas
= extract64(bcr
, 5, 4);
5441 addr
= sextract64(bvr
, 0, 49) & ~3ULL;
5450 case 2: /* unlinked context ID match */
5451 case 8: /* unlinked VMID match (reserved if no EL2) */
5452 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
5453 qemu_log_mask(LOG_UNIMP
,
5454 "arm: unlinked context breakpoint types not implemented\n");
5456 case 9: /* linked VMID match (reserved if no EL2) */
5457 case 11: /* linked context ID and VMID match (reserved if no EL2) */
5458 case 3: /* linked context ID match */
5460 /* We must generate no events for Linked context matches (unless
5461 * they are linked to by some other bp/wp, which is handled in
5462 * updates for the linking bp/wp). We choose to also generate no events
5463 * for reserved values.
5468 cpu_breakpoint_insert(CPU(cpu
), addr
, flags
, &env
->cpu_breakpoint
[n
]);
5471 void hw_breakpoint_update_all(ARMCPU
*cpu
)
5474 CPUARMState
*env
= &cpu
->env
;
5476 /* Completely clear out existing QEMU breakpoints and our array, to
5477 * avoid possible stale entries following migration load.
5479 cpu_breakpoint_remove_all(CPU(cpu
), BP_CPU
);
5480 memset(env
->cpu_breakpoint
, 0, sizeof(env
->cpu_breakpoint
));
5482 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_breakpoint
); i
++) {
5483 hw_breakpoint_update(cpu
, i
);
5487 static void dbgbvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5490 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5493 raw_write(env
, ri
, value
);
5494 hw_breakpoint_update(cpu
, i
);
5497 static void dbgbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5500 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5503 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
5506 value
= deposit64(value
, 6, 1, extract64(value
, 5, 1));
5507 value
= deposit64(value
, 8, 1, extract64(value
, 7, 1));
5509 raw_write(env
, ri
, value
);
5510 hw_breakpoint_update(cpu
, i
);
5513 static void define_debug_regs(ARMCPU
*cpu
)
5515 /* Define v7 and v8 architectural debug registers.
5516 * These are just dummy implementations for now.
5519 int wrps
, brps
, ctx_cmps
;
5520 ARMCPRegInfo dbgdidr
= {
5521 .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
5522 .access
= PL0_R
, .accessfn
= access_tda
,
5523 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->dbgdidr
,
5526 /* Note that all these register fields hold "number of Xs minus 1". */
5527 brps
= extract32(cpu
->dbgdidr
, 24, 4);
5528 wrps
= extract32(cpu
->dbgdidr
, 28, 4);
5529 ctx_cmps
= extract32(cpu
->dbgdidr
, 20, 4);
5531 assert(ctx_cmps
<= brps
);
5533 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
5534 * of the debug registers such as number of breakpoints;
5535 * check that if they both exist then they agree.
5537 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
5538 assert(extract32(cpu
->id_aa64dfr0
, 12, 4) == brps
);
5539 assert(extract32(cpu
->id_aa64dfr0
, 20, 4) == wrps
);
5540 assert(extract32(cpu
->id_aa64dfr0
, 28, 4) == ctx_cmps
);
5543 define_one_arm_cp_reg(cpu
, &dbgdidr
);
5544 define_arm_cp_regs(cpu
, debug_cp_reginfo
);
5546 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
)) {
5547 define_arm_cp_regs(cpu
, debug_lpae_cp_reginfo
);
5550 for (i
= 0; i
< brps
+ 1; i
++) {
5551 ARMCPRegInfo dbgregs
[] = {
5552 { .name
= "DBGBVR", .state
= ARM_CP_STATE_BOTH
,
5553 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
5554 .access
= PL1_RW
, .accessfn
= access_tda
,
5555 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]),
5556 .writefn
= dbgbvr_write
, .raw_writefn
= raw_write
5558 { .name
= "DBGBCR", .state
= ARM_CP_STATE_BOTH
,
5559 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
5560 .access
= PL1_RW
, .accessfn
= access_tda
,
5561 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]),
5562 .writefn
= dbgbcr_write
, .raw_writefn
= raw_write
5566 define_arm_cp_regs(cpu
, dbgregs
);
5569 for (i
= 0; i
< wrps
+ 1; i
++) {
5570 ARMCPRegInfo dbgregs
[] = {
5571 { .name
= "DBGWVR", .state
= ARM_CP_STATE_BOTH
,
5572 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
5573 .access
= PL1_RW
, .accessfn
= access_tda
,
5574 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]),
5575 .writefn
= dbgwvr_write
, .raw_writefn
= raw_write
5577 { .name
= "DBGWCR", .state
= ARM_CP_STATE_BOTH
,
5578 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
5579 .access
= PL1_RW
, .accessfn
= access_tda
,
5580 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]),
5581 .writefn
= dbgwcr_write
, .raw_writefn
= raw_write
5585 define_arm_cp_regs(cpu
, dbgregs
);
5589 /* We don't know until after realize whether there's a GICv3
5590 * attached, and that is what registers the gicv3 sysregs.
5591 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
5594 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5596 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5597 uint64_t pfr1
= cpu
->id_pfr1
;
5599 if (env
->gicv3state
) {
5605 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5607 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5608 uint64_t pfr0
= cpu
->isar
.id_aa64pfr0
;
5610 if (env
->gicv3state
) {
5616 /* Shared logic between LORID and the rest of the LOR* registers.
5617 * Secure state has already been delt with.
5619 static CPAccessResult
access_lor_ns(CPUARMState
*env
)
5621 int el
= arm_current_el(env
);
5623 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TLOR
)) {
5624 return CP_ACCESS_TRAP_EL2
;
5626 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TLOR
)) {
5627 return CP_ACCESS_TRAP_EL3
;
5629 return CP_ACCESS_OK
;
5632 static CPAccessResult
access_lorid(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5635 if (arm_is_secure_below_el3(env
)) {
5636 /* Access ok in secure mode. */
5637 return CP_ACCESS_OK
;
5639 return access_lor_ns(env
);
5642 static CPAccessResult
access_lor_other(CPUARMState
*env
,
5643 const ARMCPRegInfo
*ri
, bool isread
)
5645 if (arm_is_secure_below_el3(env
)) {
5646 /* Access denied in secure mode. */
5647 return CP_ACCESS_TRAP
;
5649 return access_lor_ns(env
);
5652 #ifdef TARGET_AARCH64
5653 static CPAccessResult
access_pauth(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5656 int el
= arm_current_el(env
);
5659 arm_feature(env
, ARM_FEATURE_EL2
) &&
5660 !(arm_hcr_el2_eff(env
) & HCR_APK
)) {
5661 return CP_ACCESS_TRAP_EL2
;
5664 arm_feature(env
, ARM_FEATURE_EL3
) &&
5665 !(env
->cp15
.scr_el3
& SCR_APK
)) {
5666 return CP_ACCESS_TRAP_EL3
;
5668 return CP_ACCESS_OK
;
5671 static const ARMCPRegInfo pauth_reginfo
[] = {
5672 { .name
= "APDAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
5673 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 0,
5674 .access
= PL1_RW
, .accessfn
= access_pauth
,
5675 .fieldoffset
= offsetof(CPUARMState
, apda_key
.lo
) },
5676 { .name
= "APDAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
5677 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 1,
5678 .access
= PL1_RW
, .accessfn
= access_pauth
,
5679 .fieldoffset
= offsetof(CPUARMState
, apda_key
.hi
) },
5680 { .name
= "APDBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
5681 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 2,
5682 .access
= PL1_RW
, .accessfn
= access_pauth
,
5683 .fieldoffset
= offsetof(CPUARMState
, apdb_key
.lo
) },
5684 { .name
= "APDBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
5685 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 3,
5686 .access
= PL1_RW
, .accessfn
= access_pauth
,
5687 .fieldoffset
= offsetof(CPUARMState
, apdb_key
.hi
) },
5688 { .name
= "APGAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
5689 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 0,
5690 .access
= PL1_RW
, .accessfn
= access_pauth
,
5691 .fieldoffset
= offsetof(CPUARMState
, apga_key
.lo
) },
5692 { .name
= "APGAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
5693 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 1,
5694 .access
= PL1_RW
, .accessfn
= access_pauth
,
5695 .fieldoffset
= offsetof(CPUARMState
, apga_key
.hi
) },
5696 { .name
= "APIAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
5697 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 0,
5698 .access
= PL1_RW
, .accessfn
= access_pauth
,
5699 .fieldoffset
= offsetof(CPUARMState
, apia_key
.lo
) },
5700 { .name
= "APIAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
5701 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 1,
5702 .access
= PL1_RW
, .accessfn
= access_pauth
,
5703 .fieldoffset
= offsetof(CPUARMState
, apia_key
.hi
) },
5704 { .name
= "APIBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
5705 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 2,
5706 .access
= PL1_RW
, .accessfn
= access_pauth
,
5707 .fieldoffset
= offsetof(CPUARMState
, apib_key
.lo
) },
5708 { .name
= "APIBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
5709 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 3,
5710 .access
= PL1_RW
, .accessfn
= access_pauth
,
5711 .fieldoffset
= offsetof(CPUARMState
, apib_key
.hi
) },
5716 void register_cp_regs_for_features(ARMCPU
*cpu
)
5718 /* Register all the coprocessor registers based on feature bits */
5719 CPUARMState
*env
= &cpu
->env
;
5720 if (arm_feature(env
, ARM_FEATURE_M
)) {
5721 /* M profile has no coprocessor registers */
5725 define_arm_cp_regs(cpu
, cp_reginfo
);
5726 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
5727 /* Must go early as it is full of wildcards that may be
5728 * overridden by later definitions.
5730 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
5733 if (arm_feature(env
, ARM_FEATURE_V6
)) {
5734 /* The ID registers all have impdef reset values */
5735 ARMCPRegInfo v6_idregs
[] = {
5736 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
5737 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
5738 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5739 .resetvalue
= cpu
->id_pfr0
},
5740 /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
5741 * the value of the GIC field until after we define these regs.
5743 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
5744 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
5745 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
5746 .readfn
= id_pfr1_read
,
5747 .writefn
= arm_cp_write_ignore
},
5748 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
5749 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
5750 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5751 .resetvalue
= cpu
->id_dfr0
},
5752 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
5753 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
5754 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5755 .resetvalue
= cpu
->id_afr0
},
5756 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
5757 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
5758 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5759 .resetvalue
= cpu
->id_mmfr0
},
5760 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
5761 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
5762 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5763 .resetvalue
= cpu
->id_mmfr1
},
5764 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
5765 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
5766 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5767 .resetvalue
= cpu
->id_mmfr2
},
5768 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
5769 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
5770 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5771 .resetvalue
= cpu
->id_mmfr3
},
5772 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
5773 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
5774 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5775 .resetvalue
= cpu
->isar
.id_isar0
},
5776 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
5777 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
5778 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5779 .resetvalue
= cpu
->isar
.id_isar1
},
5780 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
5781 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
5782 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5783 .resetvalue
= cpu
->isar
.id_isar2
},
5784 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
5785 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
5786 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5787 .resetvalue
= cpu
->isar
.id_isar3
},
5788 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
5789 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
5790 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5791 .resetvalue
= cpu
->isar
.id_isar4
},
5792 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
5793 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
5794 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5795 .resetvalue
= cpu
->isar
.id_isar5
},
5796 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
5797 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
5798 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5799 .resetvalue
= cpu
->id_mmfr4
},
5800 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
5801 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
5802 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5803 .resetvalue
= cpu
->isar
.id_isar6
},
5806 define_arm_cp_regs(cpu
, v6_idregs
);
5807 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
5809 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
5811 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
5812 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
5814 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
5815 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
5816 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
5818 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
5819 define_arm_cp_regs(cpu
, pmovsset_cp_reginfo
);
5821 if (arm_feature(env
, ARM_FEATURE_V7
)) {
5822 /* v7 performance monitor control register: same implementor
5823 * field as main ID register, and we implement four counters in
5824 * addition to the cycle count register.
5826 unsigned int i
, pmcrn
= 4;
5827 ARMCPRegInfo pmcr
= {
5828 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
5830 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
5831 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
5832 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
5833 .raw_writefn
= raw_write
,
5835 ARMCPRegInfo pmcr64
= {
5836 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
5837 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
5838 .access
= PL0_RW
, .accessfn
= pmreg_access
,
5840 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
5841 .resetvalue
= (cpu
->midr
& 0xff000000) | (pmcrn
<< PMCRN_SHIFT
),
5842 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
5844 define_one_arm_cp_reg(cpu
, &pmcr
);
5845 define_one_arm_cp_reg(cpu
, &pmcr64
);
5846 for (i
= 0; i
< pmcrn
; i
++) {
5847 char *pmevcntr_name
= g_strdup_printf("PMEVCNTR%d", i
);
5848 char *pmevcntr_el0_name
= g_strdup_printf("PMEVCNTR%d_EL0", i
);
5849 char *pmevtyper_name
= g_strdup_printf("PMEVTYPER%d", i
);
5850 char *pmevtyper_el0_name
= g_strdup_printf("PMEVTYPER%d_EL0", i
);
5851 ARMCPRegInfo pmev_regs
[] = {
5852 { .name
= pmevcntr_name
, .cp
= 15, .crn
= 15,
5853 .crm
= 8 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
5854 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
5855 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
5856 .accessfn
= pmreg_access
},
5857 { .name
= pmevcntr_el0_name
, .state
= ARM_CP_STATE_AA64
,
5858 .opc0
= 3, .opc1
= 3, .crn
= 15, .crm
= 8 | (3 & (i
>> 3)),
5859 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
5861 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
5862 .raw_readfn
= pmevcntr_rawread
,
5863 .raw_writefn
= pmevcntr_rawwrite
},
5864 { .name
= pmevtyper_name
, .cp
= 15, .crn
= 15,
5865 .crm
= 12 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
5866 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
5867 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
5868 .accessfn
= pmreg_access
},
5869 { .name
= pmevtyper_el0_name
, .state
= ARM_CP_STATE_AA64
,
5870 .opc0
= 3, .opc1
= 3, .crn
= 15, .crm
= 12 | (3 & (i
>> 3)),
5871 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
5873 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
5874 .raw_writefn
= pmevtyper_rawwrite
},
5877 define_arm_cp_regs(cpu
, pmev_regs
);
5878 g_free(pmevcntr_name
);
5879 g_free(pmevcntr_el0_name
);
5880 g_free(pmevtyper_name
);
5881 g_free(pmevtyper_el0_name
);
5883 ARMCPRegInfo clidr
= {
5884 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
5885 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
5886 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->clidr
5888 define_one_arm_cp_reg(cpu
, &clidr
);
5889 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
5890 define_debug_regs(cpu
);
5892 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
5894 if (FIELD_EX32(cpu
->id_dfr0
, ID_DFR0
, PERFMON
) >= 4 &&
5895 FIELD_EX32(cpu
->id_dfr0
, ID_DFR0
, PERFMON
) != 0xf) {
5896 ARMCPRegInfo v81_pmu_regs
[] = {
5897 { .name
= "PMCEID2", .state
= ARM_CP_STATE_AA32
,
5898 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 4,
5899 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
5900 .resetvalue
= extract64(cpu
->pmceid0
, 32, 32) },
5901 { .name
= "PMCEID3", .state
= ARM_CP_STATE_AA32
,
5902 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 5,
5903 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
5904 .resetvalue
= extract64(cpu
->pmceid1
, 32, 32) },
5907 define_arm_cp_regs(cpu
, v81_pmu_regs
);
5909 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5910 /* AArch64 ID registers, which all have impdef reset values.
5911 * Note that within the ID register ranges the unused slots
5912 * must all RAZ, not UNDEF; future architecture versions may
5913 * define new registers here.
5915 ARMCPRegInfo v8_idregs
[] = {
5916 /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't
5917 * know the right value for the GIC field until after we
5918 * define these regs.
5920 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
5921 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
5922 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
5923 .readfn
= id_aa64pfr0_read
,
5924 .writefn
= arm_cp_write_ignore
},
5925 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
5926 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
5927 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5928 .resetvalue
= cpu
->isar
.id_aa64pfr1
},
5929 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5930 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
5931 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5933 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5934 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
5935 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5937 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
5938 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
5939 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5940 /* At present, only SVEver == 0 is defined anyway. */
5942 { .name
= "ID_AA64PFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5943 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
5944 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5946 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5947 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
5948 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5950 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5951 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
5952 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5954 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
5955 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
5956 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5957 .resetvalue
= cpu
->id_aa64dfr0
},
5958 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
5959 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
5960 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5961 .resetvalue
= cpu
->id_aa64dfr1
},
5962 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5963 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
5964 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5966 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5967 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
5968 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5970 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
5971 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
5972 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5973 .resetvalue
= cpu
->id_aa64afr0
},
5974 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
5975 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
5976 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5977 .resetvalue
= cpu
->id_aa64afr1
},
5978 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5979 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
5980 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5982 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5983 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
5984 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5986 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
5987 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
5988 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5989 .resetvalue
= cpu
->isar
.id_aa64isar0
},
5990 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
5991 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
5992 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5993 .resetvalue
= cpu
->isar
.id_aa64isar1
},
5994 { .name
= "ID_AA64ISAR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5995 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
5996 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5998 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5999 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
6000 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6002 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6003 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
6004 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6006 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6007 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
6008 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6010 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6011 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
6012 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6014 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6015 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
6016 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6018 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
6019 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
6020 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6021 .resetvalue
= cpu
->isar
.id_aa64mmfr0
},
6022 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
6023 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
6024 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6025 .resetvalue
= cpu
->isar
.id_aa64mmfr1
},
6026 { .name
= "ID_AA64MMFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6027 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
6028 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6030 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6031 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
6032 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6034 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6035 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
6036 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6038 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6039 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
6040 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6042 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6043 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
6044 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6046 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6047 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
6048 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6050 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
6051 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
6052 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6053 .resetvalue
= cpu
->isar
.mvfr0
},
6054 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
6055 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
6056 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6057 .resetvalue
= cpu
->isar
.mvfr1
},
6058 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
6059 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
6060 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6061 .resetvalue
= cpu
->isar
.mvfr2
},
6062 { .name
= "MVFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6063 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
6064 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6066 { .name
= "MVFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6067 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
6068 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6070 { .name
= "MVFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6071 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
6072 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6074 { .name
= "MVFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6075 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
6076 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6078 { .name
= "MVFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6079 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
6080 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6082 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
6083 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
6084 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6085 .resetvalue
= extract64(cpu
->pmceid0
, 0, 32) },
6086 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
6087 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
6088 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6089 .resetvalue
= cpu
->pmceid0
},
6090 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
6091 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
6092 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6093 .resetvalue
= extract64(cpu
->pmceid1
, 0, 32) },
6094 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
6095 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
6096 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6097 .resetvalue
= cpu
->pmceid1
},
6100 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
6101 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
6102 !arm_feature(env
, ARM_FEATURE_EL2
)) {
6103 ARMCPRegInfo rvbar
= {
6104 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
6105 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
6106 .type
= ARM_CP_CONST
, .access
= PL1_R
, .resetvalue
= cpu
->rvbar
6108 define_one_arm_cp_reg(cpu
, &rvbar
);
6110 define_arm_cp_regs(cpu
, v8_idregs
);
6111 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
6113 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
6114 uint64_t vmpidr_def
= mpidr_read_val(env
);
6115 ARMCPRegInfo vpidr_regs
[] = {
6116 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
6117 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
6118 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6119 .resetvalue
= cpu
->midr
, .type
= ARM_CP_ALIAS
,
6120 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
6121 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
6122 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
6123 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
6124 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
6125 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
6126 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
6127 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6128 .resetvalue
= vmpidr_def
, .type
= ARM_CP_ALIAS
,
6129 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
6130 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
6131 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
6133 .resetvalue
= vmpidr_def
,
6134 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
6137 define_arm_cp_regs(cpu
, vpidr_regs
);
6138 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
6139 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6140 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
6142 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
6143 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
6144 ARMCPRegInfo rvbar
= {
6145 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
6146 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
6147 .type
= ARM_CP_CONST
, .access
= PL2_R
, .resetvalue
= cpu
->rvbar
6149 define_one_arm_cp_reg(cpu
, &rvbar
);
6152 /* If EL2 is missing but higher ELs are enabled, we need to
6153 * register the no_el2 reginfos.
6155 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6156 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
6157 * of MIDR_EL1 and MPIDR_EL1.
6159 ARMCPRegInfo vpidr_regs
[] = {
6160 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
6161 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
6162 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
6163 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->midr
,
6164 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
6165 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
6166 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
6167 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
6168 .type
= ARM_CP_NO_RAW
,
6169 .writefn
= arm_cp_write_ignore
, .readfn
= mpidr_read
},
6172 define_arm_cp_regs(cpu
, vpidr_regs
);
6173 define_arm_cp_regs(cpu
, el3_no_el2_cp_reginfo
);
6174 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6175 define_arm_cp_regs(cpu
, el3_no_el2_v8_cp_reginfo
);
6179 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6180 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
6181 ARMCPRegInfo el3_regs
[] = {
6182 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
6183 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
6184 .type
= ARM_CP_CONST
, .access
= PL3_R
, .resetvalue
= cpu
->rvbar
},
6185 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
6186 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
6188 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
6189 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
6190 .resetvalue
= cpu
->reset_sctlr
},
6194 define_arm_cp_regs(cpu
, el3_regs
);
6196 /* The behaviour of NSACR is sufficiently various that we don't
6197 * try to describe it in a single reginfo:
6198 * if EL3 is 64 bit, then trap to EL3 from S EL1,
6199 * reads as constant 0xc00 from NS EL1 and NS EL2
6200 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
6201 * if v7 without EL3, register doesn't exist
6202 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
6204 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6205 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
6206 ARMCPRegInfo nsacr
= {
6207 .name
= "NSACR", .type
= ARM_CP_CONST
,
6208 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
6209 .access
= PL1_RW
, .accessfn
= nsacr_access
,
6212 define_one_arm_cp_reg(cpu
, &nsacr
);
6214 ARMCPRegInfo nsacr
= {
6216 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
6217 .access
= PL3_RW
| PL1_R
,
6219 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
6221 define_one_arm_cp_reg(cpu
, &nsacr
);
6224 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6225 ARMCPRegInfo nsacr
= {
6226 .name
= "NSACR", .type
= ARM_CP_CONST
,
6227 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
6231 define_one_arm_cp_reg(cpu
, &nsacr
);
6235 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
6236 if (arm_feature(env
, ARM_FEATURE_V6
)) {
6237 /* PMSAv6 not implemented */
6238 assert(arm_feature(env
, ARM_FEATURE_V7
));
6239 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
6240 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
6242 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
6245 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
6246 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
6247 /* TTCBR2 is introduced with ARMv8.2-A32HPD. */
6248 if (FIELD_EX32(cpu
->id_mmfr4
, ID_MMFR4
, HPDS
) != 0) {
6249 define_one_arm_cp_reg(cpu
, &ttbcr2_reginfo
);
6252 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
6253 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
6255 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
6256 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
6258 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
6259 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
6261 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
6262 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
6264 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
6265 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
6267 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
6268 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
6270 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
6271 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
6273 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
6274 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
6276 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
6277 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
6279 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
6280 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
6282 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
6283 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
6285 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
6286 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
6287 * be read-only (ie write causes UNDEF exception).
6290 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
6291 /* Pre-v8 MIDR space.
6292 * Note that the MIDR isn't a simple constant register because
6293 * of the TI925 behaviour where writes to another register can
6294 * cause the MIDR value to change.
6296 * Unimplemented registers in the c15 0 0 0 space default to
6297 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
6298 * and friends override accordingly.
6301 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
6302 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
6303 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
6304 .readfn
= midr_read
,
6305 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
6306 .type
= ARM_CP_OVERRIDE
},
6307 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
6309 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
6310 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6312 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
6313 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6315 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
6316 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6318 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
6319 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6321 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
6322 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6325 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
6326 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6327 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
6328 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
6329 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
6330 .readfn
= midr_read
},
6331 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
6332 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
6333 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
6334 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
6335 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
6336 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
6337 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
6338 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6339 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
6340 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
6343 ARMCPRegInfo id_cp_reginfo
[] = {
6344 /* These are common to v8 and pre-v8 */
6346 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
6347 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
6348 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
6349 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
6350 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
6351 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
6352 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
6354 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
6355 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6358 /* TLBTR is specific to VMSA */
6359 ARMCPRegInfo id_tlbtr_reginfo
= {
6361 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
6362 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
6364 /* MPUIR is specific to PMSA V6+ */
6365 ARMCPRegInfo id_mpuir_reginfo
= {
6367 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
6368 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6369 .resetvalue
= cpu
->pmsav7_dregion
<< 8
6371 ARMCPRegInfo crn0_wi_reginfo
= {
6372 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
6373 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
6374 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
6376 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
6377 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
6379 /* Register the blanket "writes ignored" value first to cover the
6380 * whole space. Then update the specific ID registers to allow write
6381 * access, so that they ignore writes rather than causing them to
6384 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
6385 for (r
= id_pre_v8_midr_cp_reginfo
;
6386 r
->type
!= ARM_CP_SENTINEL
; r
++) {
6389 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
6392 id_mpuir_reginfo
.access
= PL1_RW
;
6393 id_tlbtr_reginfo
.access
= PL1_RW
;
6395 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6396 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
6398 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
6400 define_arm_cp_regs(cpu
, id_cp_reginfo
);
6401 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
6402 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
6403 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
6404 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
6408 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
6409 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
6412 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
6413 ARMCPRegInfo auxcr_reginfo
[] = {
6414 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
6415 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
6416 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
6417 .resetvalue
= cpu
->reset_auxcr
},
6418 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
6419 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
6420 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6422 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
6423 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
6424 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6428 define_arm_cp_regs(cpu
, auxcr_reginfo
);
6429 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6430 /* HACTLR2 maps to ACTLR_EL2[63:32] and is not in ARMv7 */
6431 ARMCPRegInfo hactlr2_reginfo
= {
6432 .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
6433 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
6434 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6437 define_one_arm_cp_reg(cpu
, &hactlr2_reginfo
);
6441 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
6442 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
6443 /* 32 bit view is [31:18] 0...0 [43:32]. */
6444 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
6445 | extract64(cpu
->reset_cbar
, 32, 12);
6446 ARMCPRegInfo cbar_reginfo
[] = {
6448 .type
= ARM_CP_CONST
,
6449 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
6450 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
6451 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
6452 .type
= ARM_CP_CONST
,
6453 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
6454 .access
= PL1_R
, .resetvalue
= cbar32
},
6457 /* We don't implement a r/w 64 bit CBAR currently */
6458 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
6459 define_arm_cp_regs(cpu
, cbar_reginfo
);
6461 ARMCPRegInfo cbar
= {
6463 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
6464 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
6465 .fieldoffset
= offsetof(CPUARMState
,
6466 cp15
.c15_config_base_address
)
6468 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
6469 cbar
.access
= PL1_R
;
6470 cbar
.fieldoffset
= 0;
6471 cbar
.type
= ARM_CP_CONST
;
6473 define_one_arm_cp_reg(cpu
, &cbar
);
6477 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
6478 ARMCPRegInfo vbar_cp_reginfo
[] = {
6479 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
6480 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
6481 .access
= PL1_RW
, .writefn
= vbar_write
,
6482 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
6483 offsetof(CPUARMState
, cp15
.vbar_ns
) },
6487 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
6490 /* Generic registers whose values depend on the implementation */
6492 ARMCPRegInfo sctlr
= {
6493 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
6494 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
6496 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
6497 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
6498 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
6499 .raw_writefn
= raw_write
,
6501 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
6502 /* Normally we would always end the TB on an SCTLR write, but Linux
6503 * arch/arm/mach-pxa/sleep.S expects two instructions following
6504 * an MMU enable to execute from cache. Imitate this behaviour.
6506 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
6508 define_one_arm_cp_reg(cpu
, &sctlr
);
6511 if (cpu_isar_feature(aa64_lor
, cpu
)) {
6513 * A trivial implementation of ARMv8.1-LOR leaves all of these
6514 * registers fixed at 0, which indicates that there are zero
6515 * supported Limited Ordering regions.
6517 static const ARMCPRegInfo lor_reginfo
[] = {
6518 { .name
= "LORSA_EL1", .state
= ARM_CP_STATE_AA64
,
6519 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 0,
6520 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6521 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6522 { .name
= "LOREA_EL1", .state
= ARM_CP_STATE_AA64
,
6523 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 1,
6524 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6525 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6526 { .name
= "LORN_EL1", .state
= ARM_CP_STATE_AA64
,
6527 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 2,
6528 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6529 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6530 { .name
= "LORC_EL1", .state
= ARM_CP_STATE_AA64
,
6531 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 3,
6532 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6533 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6534 { .name
= "LORID_EL1", .state
= ARM_CP_STATE_AA64
,
6535 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 7,
6536 .access
= PL1_R
, .accessfn
= access_lorid
,
6537 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6540 define_arm_cp_regs(cpu
, lor_reginfo
);
6543 if (cpu_isar_feature(aa64_sve
, cpu
)) {
6544 define_one_arm_cp_reg(cpu
, &zcr_el1_reginfo
);
6545 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
6546 define_one_arm_cp_reg(cpu
, &zcr_el2_reginfo
);
6548 define_one_arm_cp_reg(cpu
, &zcr_no_el2_reginfo
);
6550 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6551 define_one_arm_cp_reg(cpu
, &zcr_el3_reginfo
);
6555 #ifdef TARGET_AARCH64
6556 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
6557 define_arm_cp_regs(cpu
, pauth_reginfo
);
6562 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
6564 CPUState
*cs
= CPU(cpu
);
6565 CPUARMState
*env
= &cpu
->env
;
6567 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
6568 gdb_register_coprocessor(cs
, aarch64_fpu_gdb_get_reg
,
6569 aarch64_fpu_gdb_set_reg
,
6570 34, "aarch64-fpu.xml", 0);
6571 } else if (arm_feature(env
, ARM_FEATURE_NEON
)) {
6572 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
6573 51, "arm-neon.xml", 0);
6574 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
6575 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
6576 35, "arm-vfp3.xml", 0);
6577 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
6578 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
6579 19, "arm-vfp.xml", 0);
6581 gdb_register_coprocessor(cs
, arm_gdb_get_sysreg
, arm_gdb_set_sysreg
,
6582 arm_gen_dynamic_xml(cs
),
6583 "system-registers.xml", 0);
6586 /* Sort alphabetically by type name, except for "any". */
6587 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
6589 ObjectClass
*class_a
= (ObjectClass
*)a
;
6590 ObjectClass
*class_b
= (ObjectClass
*)b
;
6591 const char *name_a
, *name_b
;
6593 name_a
= object_class_get_name(class_a
);
6594 name_b
= object_class_get_name(class_b
);
6595 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
6597 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
6600 return strcmp(name_a
, name_b
);
6604 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
6606 ObjectClass
*oc
= data
;
6607 CPUListState
*s
= user_data
;
6608 const char *typename
;
6611 typename
= object_class_get_name(oc
);
6612 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
6613 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
6618 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
6622 .cpu_fprintf
= cpu_fprintf
,
6626 list
= object_class_get_list(TYPE_ARM_CPU
, false);
6627 list
= g_slist_sort(list
, arm_cpu_list_compare
);
6628 (*cpu_fprintf
)(f
, "Available CPUs:\n");
6629 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
6633 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
6635 ObjectClass
*oc
= data
;
6636 CpuDefinitionInfoList
**cpu_list
= user_data
;
6637 CpuDefinitionInfoList
*entry
;
6638 CpuDefinitionInfo
*info
;
6639 const char *typename
;
6641 typename
= object_class_get_name(oc
);
6642 info
= g_malloc0(sizeof(*info
));
6643 info
->name
= g_strndup(typename
,
6644 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
6645 info
->q_typename
= g_strdup(typename
);
6647 entry
= g_malloc0(sizeof(*entry
));
6648 entry
->value
= info
;
6649 entry
->next
= *cpu_list
;
6653 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
6655 CpuDefinitionInfoList
*cpu_list
= NULL
;
6658 list
= object_class_get_list(TYPE_ARM_CPU
, false);
6659 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
6665 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
6666 void *opaque
, int state
, int secstate
,
6667 int crm
, int opc1
, int opc2
,
6670 /* Private utility function for define_one_arm_cp_reg_with_opaque():
6671 * add a single reginfo struct to the hash table.
6673 uint32_t *key
= g_new(uint32_t, 1);
6674 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
6675 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
6676 int ns
= (secstate
& ARM_CP_SECSTATE_NS
) ? 1 : 0;
6678 r2
->name
= g_strdup(name
);
6679 /* Reset the secure state to the specific incoming state. This is
6680 * necessary as the register may have been defined with both states.
6682 r2
->secure
= secstate
;
6684 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
6685 /* Register is banked (using both entries in array).
6686 * Overwriting fieldoffset as the array is only used to define
6687 * banked registers but later only fieldoffset is used.
6689 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
6692 if (state
== ARM_CP_STATE_AA32
) {
6693 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
6694 /* If the register is banked then we don't need to migrate or
6695 * reset the 32-bit instance in certain cases:
6697 * 1) If the register has both 32-bit and 64-bit instances then we
6698 * can count on the 64-bit instance taking care of the
6700 * 2) If ARMv8 is enabled then we can count on a 64-bit version
6701 * taking care of the secure bank. This requires that separate
6702 * 32 and 64-bit definitions are provided.
6704 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
6705 (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) && !ns
)) {
6706 r2
->type
|= ARM_CP_ALIAS
;
6708 } else if ((secstate
!= r
->secure
) && !ns
) {
6709 /* The register is not banked so we only want to allow migration of
6710 * the non-secure instance.
6712 r2
->type
|= ARM_CP_ALIAS
;
6715 if (r
->state
== ARM_CP_STATE_BOTH
) {
6716 /* We assume it is a cp15 register if the .cp field is left unset.
6722 #ifdef HOST_WORDS_BIGENDIAN
6723 if (r2
->fieldoffset
) {
6724 r2
->fieldoffset
+= sizeof(uint32_t);
6729 if (state
== ARM_CP_STATE_AA64
) {
6730 /* To allow abbreviation of ARMCPRegInfo
6731 * definitions, we treat cp == 0 as equivalent to
6732 * the value for "standard guest-visible sysreg".
6733 * STATE_BOTH definitions are also always "standard
6734 * sysreg" in their AArch64 view (the .cp value may
6735 * be non-zero for the benefit of the AArch32 view).
6737 if (r
->cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
6738 r2
->cp
= CP_REG_ARM64_SYSREG_CP
;
6740 *key
= ENCODE_AA64_CP_REG(r2
->cp
, r2
->crn
, crm
,
6741 r2
->opc0
, opc1
, opc2
);
6743 *key
= ENCODE_CP_REG(r2
->cp
, is64
, ns
, r2
->crn
, crm
, opc1
, opc2
);
6746 r2
->opaque
= opaque
;
6748 /* reginfo passed to helpers is correct for the actual access,
6749 * and is never ARM_CP_STATE_BOTH:
6752 /* Make sure reginfo passed to helpers for wildcarded regs
6753 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
6758 /* By convention, for wildcarded registers only the first
6759 * entry is used for migration; the others are marked as
6760 * ALIAS so we don't try to transfer the register
6761 * multiple times. Special registers (ie NOP/WFI) are
6762 * never migratable and not even raw-accessible.
6764 if ((r
->type
& ARM_CP_SPECIAL
)) {
6765 r2
->type
|= ARM_CP_NO_RAW
;
6767 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
6768 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
6769 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
6770 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
6773 /* Check that raw accesses are either forbidden or handled. Note that
6774 * we can't assert this earlier because the setup of fieldoffset for
6775 * banked registers has to be done first.
6777 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
6778 assert(!raw_accessors_invalid(r2
));
6781 /* Overriding of an existing definition must be explicitly
6784 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
6785 ARMCPRegInfo
*oldreg
;
6786 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
6787 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
6788 fprintf(stderr
, "Register redefined: cp=%d %d bit "
6789 "crn=%d crm=%d opc1=%d opc2=%d, "
6790 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
6791 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
6792 oldreg
->name
, r2
->name
);
6793 g_assert_not_reached();
6796 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
6800 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
6801 const ARMCPRegInfo
*r
, void *opaque
)
6803 /* Define implementations of coprocessor registers.
6804 * We store these in a hashtable because typically
6805 * there are less than 150 registers in a space which
6806 * is 16*16*16*8*8 = 262144 in size.
6807 * Wildcarding is supported for the crm, opc1 and opc2 fields.
6808 * If a register is defined twice then the second definition is
6809 * used, so this can be used to define some generic registers and
6810 * then override them with implementation specific variations.
6811 * At least one of the original and the second definition should
6812 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
6813 * against accidental use.
6815 * The state field defines whether the register is to be
6816 * visible in the AArch32 or AArch64 execution state. If the
6817 * state is set to ARM_CP_STATE_BOTH then we synthesise a
6818 * reginfo structure for the AArch32 view, which sees the lower
6819 * 32 bits of the 64 bit register.
6821 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
6822 * be wildcarded. AArch64 registers are always considered to be 64
6823 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
6824 * the register, if any.
6826 int crm
, opc1
, opc2
, state
;
6827 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
6828 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
6829 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
6830 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
6831 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
6832 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
6833 /* 64 bit registers have only CRm and Opc1 fields */
6834 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
6835 /* op0 only exists in the AArch64 encodings */
6836 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
6837 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
6838 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
6839 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
6840 * encodes a minimum access level for the register. We roll this
6841 * runtime check into our general permission check code, so check
6842 * here that the reginfo's specified permissions are strict enough
6843 * to encompass the generic architectural permission check.
6845 if (r
->state
!= ARM_CP_STATE_AA32
) {
6848 case 0: case 1: case 2:
6861 /* unallocated encoding, so not possible */
6869 /* min_EL EL1, secure mode only (we don't check the latter) */
6873 /* broken reginfo with out-of-range opc1 */
6877 /* assert our permissions are not too lax (stricter is fine) */
6878 assert((r
->access
& ~mask
) == 0);
6881 /* Check that the register definition has enough info to handle
6882 * reads and writes if they are permitted.
6884 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
6885 if (r
->access
& PL3_R
) {
6886 assert((r
->fieldoffset
||
6887 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
6890 if (r
->access
& PL3_W
) {
6891 assert((r
->fieldoffset
||
6892 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
6896 /* Bad type field probably means missing sentinel at end of reg list */
6897 assert(cptype_valid(r
->type
));
6898 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
6899 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
6900 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
6901 for (state
= ARM_CP_STATE_AA32
;
6902 state
<= ARM_CP_STATE_AA64
; state
++) {
6903 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
6906 if (state
== ARM_CP_STATE_AA32
) {
6907 /* Under AArch32 CP registers can be common
6908 * (same for secure and non-secure world) or banked.
6912 switch (r
->secure
) {
6913 case ARM_CP_SECSTATE_S
:
6914 case ARM_CP_SECSTATE_NS
:
6915 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
6916 r
->secure
, crm
, opc1
, opc2
,
6920 name
= g_strdup_printf("%s_S", r
->name
);
6921 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
6923 crm
, opc1
, opc2
, name
);
6925 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
6927 crm
, opc1
, opc2
, r
->name
);
6931 /* AArch64 registers get mapped to non-secure instance
6933 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
6935 crm
, opc1
, opc2
, r
->name
);
6943 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
6944 const ARMCPRegInfo
*regs
, void *opaque
)
6946 /* Define a whole list of registers */
6947 const ARMCPRegInfo
*r
;
6948 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
6949 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
6953 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
6955 return g_hash_table_lookup(cpregs
, &encoded_cp
);
6958 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6961 /* Helper coprocessor write function for write-ignore registers */
6964 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6966 /* Helper coprocessor write function for read-as-zero registers */
6970 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
6972 /* Helper coprocessor reset function for do-nothing-on-reset registers */
6975 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
6977 /* Return true if it is not valid for us to switch to
6978 * this CPU mode (ie all the UNPREDICTABLE cases in
6979 * the ARM ARM CPSRWriteByInstr pseudocode).
6982 /* Changes to or from Hyp via MSR and CPS are illegal. */
6983 if (write_type
== CPSRWriteByInstr
&&
6984 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
6985 mode
== ARM_CPU_MODE_HYP
)) {
6990 case ARM_CPU_MODE_USR
:
6992 case ARM_CPU_MODE_SYS
:
6993 case ARM_CPU_MODE_SVC
:
6994 case ARM_CPU_MODE_ABT
:
6995 case ARM_CPU_MODE_UND
:
6996 case ARM_CPU_MODE_IRQ
:
6997 case ARM_CPU_MODE_FIQ
:
6998 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
6999 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
7001 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
7002 * and CPS are treated as illegal mode changes.
7004 if (write_type
== CPSRWriteByInstr
&&
7005 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
7006 (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
7010 case ARM_CPU_MODE_HYP
:
7011 return !arm_feature(env
, ARM_FEATURE_EL2
)
7012 || arm_current_el(env
) < 2 || arm_is_secure_below_el3(env
);
7013 case ARM_CPU_MODE_MON
:
7014 return arm_current_el(env
) < 3;
7020 uint32_t cpsr_read(CPUARMState
*env
)
7023 ZF
= (env
->ZF
== 0);
7024 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
7025 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
7026 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
7027 | ((env
->condexec_bits
& 0xfc) << 8)
7028 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
7031 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
7032 CPSRWriteType write_type
)
7034 uint32_t changed_daif
;
7036 if (mask
& CPSR_NZCV
) {
7037 env
->ZF
= (~val
) & CPSR_Z
;
7039 env
->CF
= (val
>> 29) & 1;
7040 env
->VF
= (val
<< 3) & 0x80000000;
7043 env
->QF
= ((val
& CPSR_Q
) != 0);
7045 env
->thumb
= ((val
& CPSR_T
) != 0);
7046 if (mask
& CPSR_IT_0_1
) {
7047 env
->condexec_bits
&= ~3;
7048 env
->condexec_bits
|= (val
>> 25) & 3;
7050 if (mask
& CPSR_IT_2_7
) {
7051 env
->condexec_bits
&= 3;
7052 env
->condexec_bits
|= (val
>> 8) & 0xfc;
7054 if (mask
& CPSR_GE
) {
7055 env
->GE
= (val
>> 16) & 0xf;
7058 /* In a V7 implementation that includes the security extensions but does
7059 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
7060 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
7061 * bits respectively.
7063 * In a V8 implementation, it is permitted for privileged software to
7064 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
7066 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
7067 arm_feature(env
, ARM_FEATURE_EL3
) &&
7068 !arm_feature(env
, ARM_FEATURE_EL2
) &&
7069 !arm_is_secure(env
)) {
7071 changed_daif
= (env
->daif
^ val
) & mask
;
7073 if (changed_daif
& CPSR_A
) {
7074 /* Check to see if we are allowed to change the masking of async
7075 * abort exceptions from a non-secure state.
7077 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
7078 qemu_log_mask(LOG_GUEST_ERROR
,
7079 "Ignoring attempt to switch CPSR_A flag from "
7080 "non-secure world with SCR.AW bit clear\n");
7085 if (changed_daif
& CPSR_F
) {
7086 /* Check to see if we are allowed to change the masking of FIQ
7087 * exceptions from a non-secure state.
7089 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
7090 qemu_log_mask(LOG_GUEST_ERROR
,
7091 "Ignoring attempt to switch CPSR_F flag from "
7092 "non-secure world with SCR.FW bit clear\n");
7096 /* Check whether non-maskable FIQ (NMFI) support is enabled.
7097 * If this bit is set software is not allowed to mask
7098 * FIQs, but is allowed to set CPSR_F to 0.
7100 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
7102 qemu_log_mask(LOG_GUEST_ERROR
,
7103 "Ignoring attempt to enable CPSR_F flag "
7104 "(non-maskable FIQ [NMFI] support enabled)\n");
7110 env
->daif
&= ~(CPSR_AIF
& mask
);
7111 env
->daif
|= val
& CPSR_AIF
& mask
;
7113 if (write_type
!= CPSRWriteRaw
&&
7114 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
7115 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
7116 /* Note that we can only get here in USR mode if this is a
7117 * gdb stub write; for this case we follow the architectural
7118 * behaviour for guest writes in USR mode of ignoring an attempt
7119 * to switch mode. (Those are caught by translate.c for writes
7120 * triggered by guest instructions.)
7123 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
7124 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
7125 * v7, and has defined behaviour in v8:
7126 * + leave CPSR.M untouched
7127 * + allow changes to the other CPSR fields
7129 * For user changes via the GDB stub, we don't set PSTATE.IL,
7130 * as this would be unnecessarily harsh for a user error.
7133 if (write_type
!= CPSRWriteByGDBStub
&&
7134 arm_feature(env
, ARM_FEATURE_V8
)) {
7138 qemu_log_mask(LOG_GUEST_ERROR
,
7139 "Illegal AArch32 mode switch attempt from %s to %s\n",
7140 aarch32_mode_name(env
->uncached_cpsr
),
7141 aarch32_mode_name(val
));
7143 qemu_log_mask(CPU_LOG_INT
, "%s %s to %s PC 0x%" PRIx32
"\n",
7144 write_type
== CPSRWriteExceptionReturn
?
7145 "Exception return from AArch32" :
7146 "AArch32 mode switch from",
7147 aarch32_mode_name(env
->uncached_cpsr
),
7148 aarch32_mode_name(val
), env
->regs
[15]);
7149 switch_mode(env
, val
& CPSR_M
);
7152 mask
&= ~CACHED_CPSR_BITS
;
7153 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
7156 /* Sign/zero extend */
7157 uint32_t HELPER(sxtb16
)(uint32_t x
)
7160 res
= (uint16_t)(int8_t)x
;
7161 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
7165 uint32_t HELPER(uxtb16
)(uint32_t x
)
7168 res
= (uint16_t)(uint8_t)x
;
7169 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
7173 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
7177 if (num
== INT_MIN
&& den
== -1)
7182 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
7189 uint32_t HELPER(rbit
)(uint32_t x
)
7194 #if defined(CONFIG_USER_ONLY)
7196 /* These should probably raise undefined insn exceptions. */
7197 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
7199 ARMCPU
*cpu
= arm_env_get_cpu(env
);
7201 cpu_abort(CPU(cpu
), "v7m_msr %d\n", reg
);
7204 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
7206 ARMCPU
*cpu
= arm_env_get_cpu(env
);
7208 cpu_abort(CPU(cpu
), "v7m_mrs %d\n", reg
);
7212 void HELPER(v7m_bxns
)(CPUARMState
*env
, uint32_t dest
)
7214 /* translate.c should never generate calls here in user-only mode */
7215 g_assert_not_reached();
7218 void HELPER(v7m_blxns
)(CPUARMState
*env
, uint32_t dest
)
7220 /* translate.c should never generate calls here in user-only mode */
7221 g_assert_not_reached();
7224 uint32_t HELPER(v7m_tt
)(CPUARMState
*env
, uint32_t addr
, uint32_t op
)
7226 /* The TT instructions can be used by unprivileged code, but in
7227 * user-only emulation we don't have the MPU.
7228 * Luckily since we know we are NonSecure unprivileged (and that in
7229 * turn means that the A flag wasn't specified), all the bits in the
7230 * register must be zero:
7231 * IREGION: 0 because IRVALID is 0
7232 * IRVALID: 0 because NS
7234 * NSRW: 0 because NS
7236 * RW: 0 because unpriv and A flag not set
7237 * R: 0 because unpriv and A flag not set
7238 * SRVALID: 0 because NS
7239 * MRVALID: 0 because unpriv and A flag not set
7240 * SREGION: 0 becaus SRVALID is 0
7241 * MREGION: 0 because MRVALID is 0
7246 static void switch_mode(CPUARMState
*env
, int mode
)
7248 ARMCPU
*cpu
= arm_env_get_cpu(env
);
7250 if (mode
!= ARM_CPU_MODE_USR
) {
7251 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
7255 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
7256 uint32_t cur_el
, bool secure
)
7261 void aarch64_sync_64_to_32(CPUARMState
*env
)
7263 g_assert_not_reached();
7268 static void switch_mode(CPUARMState
*env
, int mode
)
7273 old_mode
= env
->uncached_cpsr
& CPSR_M
;
7274 if (mode
== old_mode
)
7277 if (old_mode
== ARM_CPU_MODE_FIQ
) {
7278 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
7279 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
7280 } else if (mode
== ARM_CPU_MODE_FIQ
) {
7281 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
7282 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
7285 i
= bank_number(old_mode
);
7286 env
->banked_r13
[i
] = env
->regs
[13];
7287 env
->banked_spsr
[i
] = env
->spsr
;
7289 i
= bank_number(mode
);
7290 env
->regs
[13] = env
->banked_r13
[i
];
7291 env
->spsr
= env
->banked_spsr
[i
];
7293 env
->banked_r14
[r14_bank_number(old_mode
)] = env
->regs
[14];
7294 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
7297 /* Physical Interrupt Target EL Lookup Table
7299 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
7301 * The below multi-dimensional table is used for looking up the target
7302 * exception level given numerous condition criteria. Specifically, the
7303 * target EL is based on SCR and HCR routing controls as well as the
7304 * currently executing EL and secure state.
7307 * target_el_table[2][2][2][2][2][4]
7308 * | | | | | +--- Current EL
7309 * | | | | +------ Non-secure(0)/Secure(1)
7310 * | | | +--------- HCR mask override
7311 * | | +------------ SCR exec state control
7312 * | +--------------- SCR mask override
7313 * +------------------ 32-bit(0)/64-bit(1) EL3
7315 * The table values are as such:
7319 * The ARM ARM target EL table includes entries indicating that an "exception
7320 * is not taken". The two cases where this is applicable are:
7321 * 1) An exception is taken from EL3 but the SCR does not have the exception
7323 * 2) An exception is taken from EL2 but the HCR does not have the exception
7325 * In these two cases, the below table contain a target of EL1. This value is
7326 * returned as it is expected that the consumer of the table data will check
7327 * for "target EL >= current EL" to ensure the exception is not taken.
7331 * BIT IRQ IMO Non-secure Secure
7332 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
7334 static const int8_t target_el_table
[2][2][2][2][2][4] = {
7335 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
7336 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
7337 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
7338 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
7339 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
7340 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
7341 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
7342 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
7343 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
7344 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
7345 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
7346 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
7347 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
7348 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
7349 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
7350 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
7354 * Determine the target EL for physical exceptions
7356 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
7357 uint32_t cur_el
, bool secure
)
7359 CPUARMState
*env
= cs
->env_ptr
;
7364 /* Is the highest EL AArch64? */
7365 bool is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
7368 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7369 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
7371 /* Either EL2 is the highest EL (and so the EL2 register width
7372 * is given by is64); or there is no EL2 or EL3, in which case
7373 * the value of 'rw' does not affect the table lookup anyway.
7378 hcr_el2
= arm_hcr_el2_eff(env
);
7381 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
7382 hcr
= hcr_el2
& HCR_IMO
;
7385 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
7386 hcr
= hcr_el2
& HCR_FMO
;
7389 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
7390 hcr
= hcr_el2
& HCR_AMO
;
7394 /* Perform a table-lookup for the target EL given the current state */
7395 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
7397 assert(target_el
> 0);
7402 static bool v7m_stack_write(ARMCPU
*cpu
, uint32_t addr
, uint32_t value
,
7403 ARMMMUIdx mmu_idx
, bool ignfault
)
7405 CPUState
*cs
= CPU(cpu
);
7406 CPUARMState
*env
= &cpu
->env
;
7407 MemTxAttrs attrs
= {};
7409 target_ulong page_size
;
7412 ARMMMUFaultInfo fi
= {};
7413 bool secure
= mmu_idx
& ARM_MMU_IDX_M_S
;
7417 if (get_phys_addr(env
, addr
, MMU_DATA_STORE
, mmu_idx
, &physaddr
,
7418 &attrs
, &prot
, &page_size
, &fi
, NULL
)) {
7419 /* MPU/SAU lookup failed */
7420 if (fi
.type
== ARMFault_QEMU_SFault
) {
7421 qemu_log_mask(CPU_LOG_INT
,
7422 "...SecureFault with SFSR.AUVIOL during stacking\n");
7423 env
->v7m
.sfsr
|= R_V7M_SFSR_AUVIOL_MASK
| R_V7M_SFSR_SFARVALID_MASK
;
7424 env
->v7m
.sfar
= addr
;
7425 exc
= ARMV7M_EXCP_SECURE
;
7428 qemu_log_mask(CPU_LOG_INT
, "...MemManageFault with CFSR.MSTKERR\n");
7429 env
->v7m
.cfsr
[secure
] |= R_V7M_CFSR_MSTKERR_MASK
;
7430 exc
= ARMV7M_EXCP_MEM
;
7431 exc_secure
= secure
;
7435 address_space_stl_le(arm_addressspace(cs
, attrs
), physaddr
, value
,
7437 if (txres
!= MEMTX_OK
) {
7438 /* BusFault trying to write the data */
7439 qemu_log_mask(CPU_LOG_INT
, "...BusFault with BFSR.STKERR\n");
7440 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_STKERR_MASK
;
7441 exc
= ARMV7M_EXCP_BUS
;
7448 /* By pending the exception at this point we are making
7449 * the IMPDEF choice "overridden exceptions pended" (see the
7450 * MergeExcInfo() pseudocode). The other choice would be to not
7451 * pend them now and then make a choice about which to throw away
7452 * later if we have two derived exceptions.
7453 * The only case when we must not pend the exception but instead
7454 * throw it away is if we are doing the push of the callee registers
7455 * and we've already generated a derived exception. Even in this
7456 * case we will still update the fault status registers.
7459 armv7m_nvic_set_pending_derived(env
->nvic
, exc
, exc_secure
);
7464 static bool v7m_stack_read(ARMCPU
*cpu
, uint32_t *dest
, uint32_t addr
,
7467 CPUState
*cs
= CPU(cpu
);
7468 CPUARMState
*env
= &cpu
->env
;
7469 MemTxAttrs attrs
= {};
7471 target_ulong page_size
;
7474 ARMMMUFaultInfo fi
= {};
7475 bool secure
= mmu_idx
& ARM_MMU_IDX_M_S
;
7480 if (get_phys_addr(env
, addr
, MMU_DATA_LOAD
, mmu_idx
, &physaddr
,
7481 &attrs
, &prot
, &page_size
, &fi
, NULL
)) {
7482 /* MPU/SAU lookup failed */
7483 if (fi
.type
== ARMFault_QEMU_SFault
) {
7484 qemu_log_mask(CPU_LOG_INT
,
7485 "...SecureFault with SFSR.AUVIOL during unstack\n");
7486 env
->v7m
.sfsr
|= R_V7M_SFSR_AUVIOL_MASK
| R_V7M_SFSR_SFARVALID_MASK
;
7487 env
->v7m
.sfar
= addr
;
7488 exc
= ARMV7M_EXCP_SECURE
;
7491 qemu_log_mask(CPU_LOG_INT
,
7492 "...MemManageFault with CFSR.MUNSTKERR\n");
7493 env
->v7m
.cfsr
[secure
] |= R_V7M_CFSR_MUNSTKERR_MASK
;
7494 exc
= ARMV7M_EXCP_MEM
;
7495 exc_secure
= secure
;
7500 value
= address_space_ldl(arm_addressspace(cs
, attrs
), physaddr
,
7502 if (txres
!= MEMTX_OK
) {
7503 /* BusFault trying to read the data */
7504 qemu_log_mask(CPU_LOG_INT
, "...BusFault with BFSR.UNSTKERR\n");
7505 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_UNSTKERR_MASK
;
7506 exc
= ARMV7M_EXCP_BUS
;
7515 /* By pending the exception at this point we are making
7516 * the IMPDEF choice "overridden exceptions pended" (see the
7517 * MergeExcInfo() pseudocode). The other choice would be to not
7518 * pend them now and then make a choice about which to throw away
7519 * later if we have two derived exceptions.
7521 armv7m_nvic_set_pending(env
->nvic
, exc
, exc_secure
);
7525 /* Write to v7M CONTROL.SPSEL bit for the specified security bank.
7526 * This may change the current stack pointer between Main and Process
7527 * stack pointers if it is done for the CONTROL register for the current
7530 static void write_v7m_control_spsel_for_secstate(CPUARMState
*env
,
7534 bool old_is_psp
= v7m_using_psp(env
);
7536 env
->v7m
.control
[secstate
] =
7537 deposit32(env
->v7m
.control
[secstate
],
7538 R_V7M_CONTROL_SPSEL_SHIFT
,
7539 R_V7M_CONTROL_SPSEL_LENGTH
, new_spsel
);
7541 if (secstate
== env
->v7m
.secure
) {
7542 bool new_is_psp
= v7m_using_psp(env
);
7545 if (old_is_psp
!= new_is_psp
) {
7546 tmp
= env
->v7m
.other_sp
;
7547 env
->v7m
.other_sp
= env
->regs
[13];
7548 env
->regs
[13] = tmp
;
7553 /* Write to v7M CONTROL.SPSEL bit. This may change the current
7554 * stack pointer between Main and Process stack pointers.
7556 static void write_v7m_control_spsel(CPUARMState
*env
, bool new_spsel
)
7558 write_v7m_control_spsel_for_secstate(env
, new_spsel
, env
->v7m
.secure
);
7561 void write_v7m_exception(CPUARMState
*env
, uint32_t new_exc
)
7563 /* Write a new value to v7m.exception, thus transitioning into or out
7564 * of Handler mode; this may result in a change of active stack pointer.
7566 bool new_is_psp
, old_is_psp
= v7m_using_psp(env
);
7569 env
->v7m
.exception
= new_exc
;
7571 new_is_psp
= v7m_using_psp(env
);
7573 if (old_is_psp
!= new_is_psp
) {
7574 tmp
= env
->v7m
.other_sp
;
7575 env
->v7m
.other_sp
= env
->regs
[13];
7576 env
->regs
[13] = tmp
;
7580 /* Switch M profile security state between NS and S */
7581 static void switch_v7m_security_state(CPUARMState
*env
, bool new_secstate
)
7583 uint32_t new_ss_msp
, new_ss_psp
;
7585 if (env
->v7m
.secure
== new_secstate
) {
7589 /* All the banked state is accessed by looking at env->v7m.secure
7590 * except for the stack pointer; rearrange the SP appropriately.
7592 new_ss_msp
= env
->v7m
.other_ss_msp
;
7593 new_ss_psp
= env
->v7m
.other_ss_psp
;
7595 if (v7m_using_psp(env
)) {
7596 env
->v7m
.other_ss_psp
= env
->regs
[13];
7597 env
->v7m
.other_ss_msp
= env
->v7m
.other_sp
;
7599 env
->v7m
.other_ss_msp
= env
->regs
[13];
7600 env
->v7m
.other_ss_psp
= env
->v7m
.other_sp
;
7603 env
->v7m
.secure
= new_secstate
;
7605 if (v7m_using_psp(env
)) {
7606 env
->regs
[13] = new_ss_psp
;
7607 env
->v7m
.other_sp
= new_ss_msp
;
7609 env
->regs
[13] = new_ss_msp
;
7610 env
->v7m
.other_sp
= new_ss_psp
;
7614 void HELPER(v7m_bxns
)(CPUARMState
*env
, uint32_t dest
)
7617 * - if the return value is a magic value, do exception return (like BX)
7618 * - otherwise bit 0 of the return value is the target security state
7622 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
7623 /* Covers FNC_RETURN and EXC_RETURN magic */
7624 min_magic
= FNC_RETURN_MIN_MAGIC
;
7626 /* EXC_RETURN magic only */
7627 min_magic
= EXC_RETURN_MIN_MAGIC
;
7630 if (dest
>= min_magic
) {
7631 /* This is an exception return magic value; put it where
7632 * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT.
7633 * Note that if we ever add gen_ss_advance() singlestep support to
7634 * M profile this should count as an "instruction execution complete"
7635 * event (compare gen_bx_excret_final_code()).
7637 env
->regs
[15] = dest
& ~1;
7638 env
->thumb
= dest
& 1;
7639 HELPER(exception_internal
)(env
, EXCP_EXCEPTION_EXIT
);
7643 /* translate.c should have made BXNS UNDEF unless we're secure */
7644 assert(env
->v7m
.secure
);
7646 switch_v7m_security_state(env
, dest
& 1);
7648 env
->regs
[15] = dest
& ~1;
7651 void HELPER(v7m_blxns
)(CPUARMState
*env
, uint32_t dest
)
7653 /* Handle v7M BLXNS:
7654 * - bit 0 of the destination address is the target security state
7657 /* At this point regs[15] is the address just after the BLXNS */
7658 uint32_t nextinst
= env
->regs
[15] | 1;
7659 uint32_t sp
= env
->regs
[13] - 8;
7662 /* translate.c will have made BLXNS UNDEF unless we're secure */
7663 assert(env
->v7m
.secure
);
7666 /* target is Secure, so this is just a normal BLX,
7667 * except that the low bit doesn't indicate Thumb/not.
7669 env
->regs
[14] = nextinst
;
7671 env
->regs
[15] = dest
& ~1;
7675 /* Target is non-secure: first push a stack frame */
7676 if (!QEMU_IS_ALIGNED(sp
, 8)) {
7677 qemu_log_mask(LOG_GUEST_ERROR
,
7678 "BLXNS with misaligned SP is UNPREDICTABLE\n");
7681 if (sp
< v7m_sp_limit(env
)) {
7682 raise_exception(env
, EXCP_STKOF
, 0, 1);
7685 saved_psr
= env
->v7m
.exception
;
7686 if (env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
) {
7687 saved_psr
|= XPSR_SFPA
;
7690 /* Note that these stores can throw exceptions on MPU faults */
7691 cpu_stl_data(env
, sp
, nextinst
);
7692 cpu_stl_data(env
, sp
+ 4, saved_psr
);
7695 env
->regs
[14] = 0xfeffffff;
7696 if (arm_v7m_is_handler_mode(env
)) {
7697 /* Write a dummy value to IPSR, to avoid leaking the current secure
7698 * exception number to non-secure code. This is guaranteed not
7699 * to cause write_v7m_exception() to actually change stacks.
7701 write_v7m_exception(env
, 1);
7703 switch_v7m_security_state(env
, 0);
7705 env
->regs
[15] = dest
;
7708 static uint32_t *get_v7m_sp_ptr(CPUARMState
*env
, bool secure
, bool threadmode
,
7711 /* Return a pointer to the location where we currently store the
7712 * stack pointer for the requested security state and thread mode.
7713 * This pointer will become invalid if the CPU state is updated
7714 * such that the stack pointers are switched around (eg changing
7715 * the SPSEL control bit).
7716 * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
7717 * Unlike that pseudocode, we require the caller to pass us in the
7718 * SPSEL control bit value; this is because we also use this
7719 * function in handling of pushing of the callee-saves registers
7720 * part of the v8M stack frame (pseudocode PushCalleeStack()),
7721 * and in the tailchain codepath the SPSEL bit comes from the exception
7722 * return magic LR value from the previous exception. The pseudocode
7723 * opencodes the stack-selection in PushCalleeStack(), but we prefer
7724 * to make this utility function generic enough to do the job.
7726 bool want_psp
= threadmode
&& spsel
;
7728 if (secure
== env
->v7m
.secure
) {
7729 if (want_psp
== v7m_using_psp(env
)) {
7730 return &env
->regs
[13];
7732 return &env
->v7m
.other_sp
;
7736 return &env
->v7m
.other_ss_psp
;
7738 return &env
->v7m
.other_ss_msp
;
7743 static bool arm_v7m_load_vector(ARMCPU
*cpu
, int exc
, bool targets_secure
,
7746 CPUState
*cs
= CPU(cpu
);
7747 CPUARMState
*env
= &cpu
->env
;
7749 uint32_t addr
= env
->v7m
.vecbase
[targets_secure
] + exc
* 4;
7750 uint32_t vector_entry
;
7751 MemTxAttrs attrs
= {};
7755 mmu_idx
= arm_v7m_mmu_idx_for_secstate_and_priv(env
, targets_secure
, true);
7757 /* We don't do a get_phys_addr() here because the rules for vector
7758 * loads are special: they always use the default memory map, and
7759 * the default memory map permits reads from all addresses.
7760 * Since there's no easy way to pass through to pmsav8_mpu_lookup()
7761 * that we want this special case which would always say "yes",
7762 * we just do the SAU lookup here followed by a direct physical load.
7764 attrs
.secure
= targets_secure
;
7767 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
7768 V8M_SAttributes sattrs
= {};
7770 v8m_security_lookup(env
, addr
, MMU_DATA_LOAD
, mmu_idx
, &sattrs
);
7772 attrs
.secure
= false;
7773 } else if (!targets_secure
) {
7774 /* NS access to S memory */
7779 vector_entry
= address_space_ldl(arm_addressspace(cs
, attrs
), addr
,
7781 if (result
!= MEMTX_OK
) {
7784 *pvec
= vector_entry
;
7788 /* All vector table fetch fails are reported as HardFault, with
7789 * HFSR.VECTTBL and .FORCED set. (FORCED is set because
7790 * technically the underlying exception is a MemManage or BusFault
7791 * that is escalated to HardFault.) This is a terminal exception,
7792 * so we will either take the HardFault immediately or else enter
7793 * lockup (the latter case is handled in armv7m_nvic_set_pending_derived()).
7795 exc_secure
= targets_secure
||
7796 !(cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
);
7797 env
->v7m
.hfsr
|= R_V7M_HFSR_VECTTBL_MASK
| R_V7M_HFSR_FORCED_MASK
;
7798 armv7m_nvic_set_pending_derived(env
->nvic
, ARMV7M_EXCP_HARD
, exc_secure
);
7802 static bool v7m_push_callee_stack(ARMCPU
*cpu
, uint32_t lr
, bool dotailchain
,
7805 /* For v8M, push the callee-saves register part of the stack frame.
7806 * Compare the v8M pseudocode PushCalleeStack().
7807 * In the tailchaining case this may not be the current stack.
7809 CPUARMState
*env
= &cpu
->env
;
7810 uint32_t *frame_sp_p
;
7818 bool mode
= lr
& R_V7M_EXCRET_MODE_MASK
;
7819 bool priv
= !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_NPRIV_MASK
) ||
7822 mmu_idx
= arm_v7m_mmu_idx_for_secstate_and_priv(env
, M_REG_S
, priv
);
7823 frame_sp_p
= get_v7m_sp_ptr(env
, M_REG_S
, mode
,
7824 lr
& R_V7M_EXCRET_SPSEL_MASK
);
7825 want_psp
= mode
&& (lr
& R_V7M_EXCRET_SPSEL_MASK
);
7827 limit
= env
->v7m
.psplim
[M_REG_S
];
7829 limit
= env
->v7m
.msplim
[M_REG_S
];
7832 mmu_idx
= arm_mmu_idx(env
);
7833 frame_sp_p
= &env
->regs
[13];
7834 limit
= v7m_sp_limit(env
);
7837 frameptr
= *frame_sp_p
- 0x28;
7838 if (frameptr
< limit
) {
7840 * Stack limit failure: set SP to the limit value, and generate
7841 * STKOF UsageFault. Stack pushes below the limit must not be
7842 * performed. It is IMPDEF whether pushes above the limit are
7843 * performed; we choose not to.
7845 qemu_log_mask(CPU_LOG_INT
,
7846 "...STKOF during callee-saves register stacking\n");
7847 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_STKOF_MASK
;
7848 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
7850 *frame_sp_p
= limit
;
7854 /* Write as much of the stack frame as we can. A write failure may
7855 * cause us to pend a derived exception.
7858 v7m_stack_write(cpu
, frameptr
, 0xfefa125b, mmu_idx
, ignore_faults
) &&
7859 v7m_stack_write(cpu
, frameptr
+ 0x8, env
->regs
[4], mmu_idx
,
7861 v7m_stack_write(cpu
, frameptr
+ 0xc, env
->regs
[5], mmu_idx
,
7863 v7m_stack_write(cpu
, frameptr
+ 0x10, env
->regs
[6], mmu_idx
,
7865 v7m_stack_write(cpu
, frameptr
+ 0x14, env
->regs
[7], mmu_idx
,
7867 v7m_stack_write(cpu
, frameptr
+ 0x18, env
->regs
[8], mmu_idx
,
7869 v7m_stack_write(cpu
, frameptr
+ 0x1c, env
->regs
[9], mmu_idx
,
7871 v7m_stack_write(cpu
, frameptr
+ 0x20, env
->regs
[10], mmu_idx
,
7873 v7m_stack_write(cpu
, frameptr
+ 0x24, env
->regs
[11], mmu_idx
,
7876 /* Update SP regardless of whether any of the stack accesses failed. */
7877 *frame_sp_p
= frameptr
;
7882 static void v7m_exception_taken(ARMCPU
*cpu
, uint32_t lr
, bool dotailchain
,
7883 bool ignore_stackfaults
)
7885 /* Do the "take the exception" parts of exception entry,
7886 * but not the pushing of state to the stack. This is
7887 * similar to the pseudocode ExceptionTaken() function.
7889 CPUARMState
*env
= &cpu
->env
;
7891 bool targets_secure
;
7893 bool push_failed
= false;
7895 armv7m_nvic_get_pending_irq_info(env
->nvic
, &exc
, &targets_secure
);
7896 qemu_log_mask(CPU_LOG_INT
, "...taking pending %s exception %d\n",
7897 targets_secure
? "secure" : "nonsecure", exc
);
7899 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7900 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
7901 (lr
& R_V7M_EXCRET_S_MASK
)) {
7902 /* The background code (the owner of the registers in the
7903 * exception frame) is Secure. This means it may either already
7904 * have or now needs to push callee-saves registers.
7906 if (targets_secure
) {
7907 if (dotailchain
&& !(lr
& R_V7M_EXCRET_ES_MASK
)) {
7908 /* We took an exception from Secure to NonSecure
7909 * (which means the callee-saved registers got stacked)
7910 * and are now tailchaining to a Secure exception.
7911 * Clear DCRS so eventual return from this Secure
7912 * exception unstacks the callee-saved registers.
7914 lr
&= ~R_V7M_EXCRET_DCRS_MASK
;
7917 /* We're going to a non-secure exception; push the
7918 * callee-saves registers to the stack now, if they're
7919 * not already saved.
7921 if (lr
& R_V7M_EXCRET_DCRS_MASK
&&
7922 !(dotailchain
&& !(lr
& R_V7M_EXCRET_ES_MASK
))) {
7923 push_failed
= v7m_push_callee_stack(cpu
, lr
, dotailchain
,
7924 ignore_stackfaults
);
7926 lr
|= R_V7M_EXCRET_DCRS_MASK
;
7930 lr
&= ~R_V7M_EXCRET_ES_MASK
;
7931 if (targets_secure
|| !arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
7932 lr
|= R_V7M_EXCRET_ES_MASK
;
7934 lr
&= ~R_V7M_EXCRET_SPSEL_MASK
;
7935 if (env
->v7m
.control
[targets_secure
] & R_V7M_CONTROL_SPSEL_MASK
) {
7936 lr
|= R_V7M_EXCRET_SPSEL_MASK
;
7939 /* Clear registers if necessary to prevent non-secure exception
7940 * code being able to see register values from secure code.
7941 * Where register values become architecturally UNKNOWN we leave
7942 * them with their previous values.
7944 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
7945 if (!targets_secure
) {
7946 /* Always clear the caller-saved registers (they have been
7947 * pushed to the stack earlier in v7m_push_stack()).
7948 * Clear callee-saved registers if the background code is
7949 * Secure (in which case these regs were saved in
7950 * v7m_push_callee_stack()).
7954 for (i
= 0; i
< 13; i
++) {
7955 /* r4..r11 are callee-saves, zero only if EXCRET.S == 1 */
7956 if (i
< 4 || i
> 11 || (lr
& R_V7M_EXCRET_S_MASK
)) {
7961 xpsr_write(env
, 0, XPSR_NZCV
| XPSR_Q
| XPSR_GE
| XPSR_IT
);
7966 if (push_failed
&& !ignore_stackfaults
) {
7967 /* Derived exception on callee-saves register stacking:
7968 * we might now want to take a different exception which
7969 * targets a different security state, so try again from the top.
7971 qemu_log_mask(CPU_LOG_INT
,
7972 "...derived exception on callee-saves register stacking");
7973 v7m_exception_taken(cpu
, lr
, true, true);
7977 if (!arm_v7m_load_vector(cpu
, exc
, targets_secure
, &addr
)) {
7978 /* Vector load failed: derived exception */
7979 qemu_log_mask(CPU_LOG_INT
, "...derived exception on vector table load");
7980 v7m_exception_taken(cpu
, lr
, true, true);
7984 /* Now we've done everything that might cause a derived exception
7985 * we can go ahead and activate whichever exception we're going to
7986 * take (which might now be the derived exception).
7988 armv7m_nvic_acknowledge_irq(env
->nvic
);
7990 /* Switch to target security state -- must do this before writing SPSEL */
7991 switch_v7m_security_state(env
, targets_secure
);
7992 write_v7m_control_spsel(env
, 0);
7993 arm_clear_exclusive(env
);
7995 env
->condexec_bits
= 0;
7997 env
->regs
[15] = addr
& 0xfffffffe;
7998 env
->thumb
= addr
& 1;
8001 static bool v7m_push_stack(ARMCPU
*cpu
)
8003 /* Do the "set up stack frame" part of exception entry,
8004 * similar to pseudocode PushStack().
8005 * Return true if we generate a derived exception (and so
8006 * should ignore further stack faults trying to process
8007 * that derived exception.)
8010 CPUARMState
*env
= &cpu
->env
;
8011 uint32_t xpsr
= xpsr_read(env
);
8012 uint32_t frameptr
= env
->regs
[13];
8013 ARMMMUIdx mmu_idx
= arm_mmu_idx(env
);
8015 /* Align stack pointer if the guest wants that */
8016 if ((frameptr
& 4) &&
8017 (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_STKALIGN_MASK
)) {
8019 xpsr
|= XPSR_SPREALIGN
;
8024 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8025 uint32_t limit
= v7m_sp_limit(env
);
8027 if (frameptr
< limit
) {
8029 * Stack limit failure: set SP to the limit value, and generate
8030 * STKOF UsageFault. Stack pushes below the limit must not be
8031 * performed. It is IMPDEF whether pushes above the limit are
8032 * performed; we choose not to.
8034 qemu_log_mask(CPU_LOG_INT
,
8035 "...STKOF during stacking\n");
8036 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_STKOF_MASK
;
8037 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
8039 env
->regs
[13] = limit
;
8044 /* Write as much of the stack frame as we can. If we fail a stack
8045 * write this will result in a derived exception being pended
8046 * (which may be taken in preference to the one we started with
8047 * if it has higher priority).
8050 v7m_stack_write(cpu
, frameptr
, env
->regs
[0], mmu_idx
, false) &&
8051 v7m_stack_write(cpu
, frameptr
+ 4, env
->regs
[1], mmu_idx
, false) &&
8052 v7m_stack_write(cpu
, frameptr
+ 8, env
->regs
[2], mmu_idx
, false) &&
8053 v7m_stack_write(cpu
, frameptr
+ 12, env
->regs
[3], mmu_idx
, false) &&
8054 v7m_stack_write(cpu
, frameptr
+ 16, env
->regs
[12], mmu_idx
, false) &&
8055 v7m_stack_write(cpu
, frameptr
+ 20, env
->regs
[14], mmu_idx
, false) &&
8056 v7m_stack_write(cpu
, frameptr
+ 24, env
->regs
[15], mmu_idx
, false) &&
8057 v7m_stack_write(cpu
, frameptr
+ 28, xpsr
, mmu_idx
, false);
8059 /* Update SP regardless of whether any of the stack accesses failed. */
8060 env
->regs
[13] = frameptr
;
8065 static void do_v7m_exception_exit(ARMCPU
*cpu
)
8067 CPUARMState
*env
= &cpu
->env
;
8070 bool ufault
= false;
8071 bool sfault
= false;
8072 bool return_to_sp_process
;
8073 bool return_to_handler
;
8074 bool rettobase
= false;
8075 bool exc_secure
= false;
8076 bool return_to_secure
;
8078 /* If we're not in Handler mode then jumps to magic exception-exit
8079 * addresses don't have magic behaviour. However for the v8M
8080 * security extensions the magic secure-function-return has to
8081 * work in thread mode too, so to avoid doing an extra check in
8082 * the generated code we allow exception-exit magic to also cause the
8083 * internal exception and bring us here in thread mode. Correct code
8084 * will never try to do this (the following insn fetch will always
8085 * fault) so we the overhead of having taken an unnecessary exception
8088 if (!arm_v7m_is_handler_mode(env
)) {
8092 /* In the spec pseudocode ExceptionReturn() is called directly
8093 * from BXWritePC() and gets the full target PC value including
8094 * bit zero. In QEMU's implementation we treat it as a normal
8095 * jump-to-register (which is then caught later on), and so split
8096 * the target value up between env->regs[15] and env->thumb in
8097 * gen_bx(). Reconstitute it.
8099 excret
= env
->regs
[15];
8104 qemu_log_mask(CPU_LOG_INT
, "Exception return: magic PC %" PRIx32
8105 " previous exception %d\n",
8106 excret
, env
->v7m
.exception
);
8108 if ((excret
& R_V7M_EXCRET_RES1_MASK
) != R_V7M_EXCRET_RES1_MASK
) {
8109 qemu_log_mask(LOG_GUEST_ERROR
, "M profile: zero high bits in exception "
8110 "exit PC value 0x%" PRIx32
" are UNPREDICTABLE\n",
8114 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
8115 /* EXC_RETURN.ES validation check (R_SMFL). We must do this before
8116 * we pick which FAULTMASK to clear.
8118 if (!env
->v7m
.secure
&&
8119 ((excret
& R_V7M_EXCRET_ES_MASK
) ||
8120 !(excret
& R_V7M_EXCRET_DCRS_MASK
))) {
8122 /* For all other purposes, treat ES as 0 (R_HXSR) */
8123 excret
&= ~R_V7M_EXCRET_ES_MASK
;
8125 exc_secure
= excret
& R_V7M_EXCRET_ES_MASK
;
8128 if (env
->v7m
.exception
!= ARMV7M_EXCP_NMI
) {
8129 /* Auto-clear FAULTMASK on return from other than NMI.
8130 * If the security extension is implemented then this only
8131 * happens if the raw execution priority is >= 0; the
8132 * value of the ES bit in the exception return value indicates
8133 * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.)
8135 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
8136 if (armv7m_nvic_raw_execution_priority(env
->nvic
) >= 0) {
8137 env
->v7m
.faultmask
[exc_secure
] = 0;
8140 env
->v7m
.faultmask
[M_REG_NS
] = 0;
8144 switch (armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
,
8147 /* attempt to exit an exception that isn't active */
8151 /* still an irq active now */
8154 /* we returned to base exception level, no nesting.
8155 * (In the pseudocode this is written using "NestedActivation != 1"
8156 * where we have 'rettobase == false'.)
8161 g_assert_not_reached();
8164 return_to_handler
= !(excret
& R_V7M_EXCRET_MODE_MASK
);
8165 return_to_sp_process
= excret
& R_V7M_EXCRET_SPSEL_MASK
;
8166 return_to_secure
= arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
8167 (excret
& R_V7M_EXCRET_S_MASK
);
8169 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8170 if (!arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
8171 /* UNPREDICTABLE if S == 1 or DCRS == 0 or ES == 1 (R_XLCP);
8172 * we choose to take the UsageFault.
8174 if ((excret
& R_V7M_EXCRET_S_MASK
) ||
8175 (excret
& R_V7M_EXCRET_ES_MASK
) ||
8176 !(excret
& R_V7M_EXCRET_DCRS_MASK
)) {
8180 if (excret
& R_V7M_EXCRET_RES0_MASK
) {
8184 /* For v7M we only recognize certain combinations of the low bits */
8185 switch (excret
& 0xf) {
8186 case 1: /* Return to Handler */
8188 case 13: /* Return to Thread using Process stack */
8189 case 9: /* Return to Thread using Main stack */
8190 /* We only need to check NONBASETHRDENA for v7M, because in
8191 * v8M this bit does not exist (it is RES1).
8194 !(env
->v7m
.ccr
[env
->v7m
.secure
] &
8195 R_V7M_CCR_NONBASETHRDENA_MASK
)) {
8205 * Set CONTROL.SPSEL from excret.SPSEL. Since we're still in
8206 * Handler mode (and will be until we write the new XPSR.Interrupt
8207 * field) this does not switch around the current stack pointer.
8208 * We must do this before we do any kind of tailchaining, including
8209 * for the derived exceptions on integrity check failures, or we will
8210 * give the guest an incorrect EXCRET.SPSEL value on exception entry.
8212 write_v7m_control_spsel_for_secstate(env
, return_to_sp_process
, exc_secure
);
8215 env
->v7m
.sfsr
|= R_V7M_SFSR_INVER_MASK
;
8216 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
8217 qemu_log_mask(CPU_LOG_INT
, "...taking SecureFault on existing "
8218 "stackframe: failed EXC_RETURN.ES validity check\n");
8219 v7m_exception_taken(cpu
, excret
, true, false);
8224 /* Bad exception return: instead of popping the exception
8225 * stack, directly take a usage fault on the current stack.
8227 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
8228 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
8229 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on existing "
8230 "stackframe: failed exception return integrity check\n");
8231 v7m_exception_taken(cpu
, excret
, true, false);
8236 * Tailchaining: if there is currently a pending exception that
8237 * is high enough priority to preempt execution at the level we're
8238 * about to return to, then just directly take that exception now,
8239 * avoiding an unstack-and-then-stack. Note that now we have
8240 * deactivated the previous exception by calling armv7m_nvic_complete_irq()
8241 * our current execution priority is already the execution priority we are
8242 * returning to -- none of the state we would unstack or set based on
8243 * the EXCRET value affects it.
8245 if (armv7m_nvic_can_take_pending_exception(env
->nvic
)) {
8246 qemu_log_mask(CPU_LOG_INT
, "...tailchaining to pending exception\n");
8247 v7m_exception_taken(cpu
, excret
, true, false);
8251 switch_v7m_security_state(env
, return_to_secure
);
8254 /* The stack pointer we should be reading the exception frame from
8255 * depends on bits in the magic exception return type value (and
8256 * for v8M isn't necessarily the stack pointer we will eventually
8257 * end up resuming execution with). Get a pointer to the location
8258 * in the CPU state struct where the SP we need is currently being
8259 * stored; we will use and modify it in place.
8260 * We use this limited C variable scope so we don't accidentally
8261 * use 'frame_sp_p' after we do something that makes it invalid.
8263 uint32_t *frame_sp_p
= get_v7m_sp_ptr(env
,
8266 return_to_sp_process
);
8267 uint32_t frameptr
= *frame_sp_p
;
8270 bool return_to_priv
= return_to_handler
||
8271 !(env
->v7m
.control
[return_to_secure
] & R_V7M_CONTROL_NPRIV_MASK
);
8273 mmu_idx
= arm_v7m_mmu_idx_for_secstate_and_priv(env
, return_to_secure
,
8276 if (!QEMU_IS_ALIGNED(frameptr
, 8) &&
8277 arm_feature(env
, ARM_FEATURE_V8
)) {
8278 qemu_log_mask(LOG_GUEST_ERROR
,
8279 "M profile exception return with non-8-aligned SP "
8280 "for destination state is UNPREDICTABLE\n");
8283 /* Do we need to pop callee-saved registers? */
8284 if (return_to_secure
&&
8285 ((excret
& R_V7M_EXCRET_ES_MASK
) == 0 ||
8286 (excret
& R_V7M_EXCRET_DCRS_MASK
) == 0)) {
8287 uint32_t expected_sig
= 0xfefa125b;
8288 uint32_t actual_sig
;
8290 pop_ok
= v7m_stack_read(cpu
, &actual_sig
, frameptr
, mmu_idx
);
8292 if (pop_ok
&& expected_sig
!= actual_sig
) {
8293 /* Take a SecureFault on the current stack */
8294 env
->v7m
.sfsr
|= R_V7M_SFSR_INVIS_MASK
;
8295 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
8296 qemu_log_mask(CPU_LOG_INT
, "...taking SecureFault on existing "
8297 "stackframe: failed exception return integrity "
8298 "signature check\n");
8299 v7m_exception_taken(cpu
, excret
, true, false);
8304 v7m_stack_read(cpu
, &env
->regs
[4], frameptr
+ 0x8, mmu_idx
) &&
8305 v7m_stack_read(cpu
, &env
->regs
[5], frameptr
+ 0xc, mmu_idx
) &&
8306 v7m_stack_read(cpu
, &env
->regs
[6], frameptr
+ 0x10, mmu_idx
) &&
8307 v7m_stack_read(cpu
, &env
->regs
[7], frameptr
+ 0x14, mmu_idx
) &&
8308 v7m_stack_read(cpu
, &env
->regs
[8], frameptr
+ 0x18, mmu_idx
) &&
8309 v7m_stack_read(cpu
, &env
->regs
[9], frameptr
+ 0x1c, mmu_idx
) &&
8310 v7m_stack_read(cpu
, &env
->regs
[10], frameptr
+ 0x20, mmu_idx
) &&
8311 v7m_stack_read(cpu
, &env
->regs
[11], frameptr
+ 0x24, mmu_idx
);
8318 v7m_stack_read(cpu
, &env
->regs
[0], frameptr
, mmu_idx
) &&
8319 v7m_stack_read(cpu
, &env
->regs
[1], frameptr
+ 0x4, mmu_idx
) &&
8320 v7m_stack_read(cpu
, &env
->regs
[2], frameptr
+ 0x8, mmu_idx
) &&
8321 v7m_stack_read(cpu
, &env
->regs
[3], frameptr
+ 0xc, mmu_idx
) &&
8322 v7m_stack_read(cpu
, &env
->regs
[12], frameptr
+ 0x10, mmu_idx
) &&
8323 v7m_stack_read(cpu
, &env
->regs
[14], frameptr
+ 0x14, mmu_idx
) &&
8324 v7m_stack_read(cpu
, &env
->regs
[15], frameptr
+ 0x18, mmu_idx
) &&
8325 v7m_stack_read(cpu
, &xpsr
, frameptr
+ 0x1c, mmu_idx
);
8328 /* v7m_stack_read() pended a fault, so take it (as a tail
8329 * chained exception on the same stack frame)
8331 qemu_log_mask(CPU_LOG_INT
, "...derived exception on unstacking\n");
8332 v7m_exception_taken(cpu
, excret
, true, false);
8336 /* Returning from an exception with a PC with bit 0 set is defined
8337 * behaviour on v8M (bit 0 is ignored), but for v7M it was specified
8338 * to be UNPREDICTABLE. In practice actual v7M hardware seems to ignore
8339 * the lsbit, and there are several RTOSes out there which incorrectly
8340 * assume the r15 in the stack frame should be a Thumb-style "lsbit
8341 * indicates ARM/Thumb" value, so ignore the bit on v7M as well, but
8342 * complain about the badly behaved guest.
8344 if (env
->regs
[15] & 1) {
8345 env
->regs
[15] &= ~1U;
8346 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
8347 qemu_log_mask(LOG_GUEST_ERROR
,
8348 "M profile return from interrupt with misaligned "
8349 "PC is UNPREDICTABLE on v7M\n");
8353 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8354 /* For v8M we have to check whether the xPSR exception field
8355 * matches the EXCRET value for return to handler/thread
8356 * before we commit to changing the SP and xPSR.
8358 bool will_be_handler
= (xpsr
& XPSR_EXCP
) != 0;
8359 if (return_to_handler
!= will_be_handler
) {
8360 /* Take an INVPC UsageFault on the current stack.
8361 * By this point we will have switched to the security state
8362 * for the background state, so this UsageFault will target
8365 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
8367 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
8368 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on existing "
8369 "stackframe: failed exception return integrity "
8371 v7m_exception_taken(cpu
, excret
, true, false);
8376 /* Commit to consuming the stack frame */
8378 /* Undo stack alignment (the SPREALIGN bit indicates that the original
8379 * pre-exception SP was not 8-aligned and we added a padding word to
8380 * align it, so we undo this by ORing in the bit that increases it
8381 * from the current 8-aligned value to the 8-unaligned value. (Adding 4
8382 * would work too but a logical OR is how the pseudocode specifies it.)
8384 if (xpsr
& XPSR_SPREALIGN
) {
8387 *frame_sp_p
= frameptr
;
8389 /* This xpsr_write() will invalidate frame_sp_p as it may switch stack */
8390 xpsr_write(env
, xpsr
, ~XPSR_SPREALIGN
);
8392 /* The restored xPSR exception field will be zero if we're
8393 * resuming in Thread mode. If that doesn't match what the
8394 * exception return excret specified then this is a UsageFault.
8395 * v7M requires we make this check here; v8M did it earlier.
8397 if (return_to_handler
!= arm_v7m_is_handler_mode(env
)) {
8398 /* Take an INVPC UsageFault by pushing the stack again;
8399 * we know we're v7M so this is never a Secure UsageFault.
8401 bool ignore_stackfaults
;
8403 assert(!arm_feature(env
, ARM_FEATURE_V8
));
8404 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, false);
8405 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
8406 ignore_stackfaults
= v7m_push_stack(cpu
);
8407 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on new stackframe: "
8408 "failed exception return integrity check\n");
8409 v7m_exception_taken(cpu
, excret
, false, ignore_stackfaults
);
8413 /* Otherwise, we have a successful exception exit. */
8414 arm_clear_exclusive(env
);
8415 qemu_log_mask(CPU_LOG_INT
, "...successful exception return\n");
8418 static bool do_v7m_function_return(ARMCPU
*cpu
)
8420 /* v8M security extensions magic function return.
8422 * (1) throw an exception (longjump)
8423 * (2) return true if we successfully handled the function return
8424 * (3) return false if we failed a consistency check and have
8425 * pended a UsageFault that needs to be taken now
8427 * At this point the magic return value is split between env->regs[15]
8428 * and env->thumb. We don't bother to reconstitute it because we don't
8429 * need it (all values are handled the same way).
8431 CPUARMState
*env
= &cpu
->env
;
8432 uint32_t newpc
, newpsr
, newpsr_exc
;
8434 qemu_log_mask(CPU_LOG_INT
, "...really v7M secure function return\n");
8437 bool threadmode
, spsel
;
8440 uint32_t *frame_sp_p
;
8443 /* Pull the return address and IPSR from the Secure stack */
8444 threadmode
= !arm_v7m_is_handler_mode(env
);
8445 spsel
= env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SPSEL_MASK
;
8447 frame_sp_p
= get_v7m_sp_ptr(env
, true, threadmode
, spsel
);
8448 frameptr
= *frame_sp_p
;
8450 /* These loads may throw an exception (for MPU faults). We want to
8451 * do them as secure, so work out what MMU index that is.
8453 mmu_idx
= arm_v7m_mmu_idx_for_secstate(env
, true);
8454 oi
= make_memop_idx(MO_LE
, arm_to_core_mmu_idx(mmu_idx
));
8455 newpc
= helper_le_ldul_mmu(env
, frameptr
, oi
, 0);
8456 newpsr
= helper_le_ldul_mmu(env
, frameptr
+ 4, oi
, 0);
8458 /* Consistency checks on new IPSR */
8459 newpsr_exc
= newpsr
& XPSR_EXCP
;
8460 if (!((env
->v7m
.exception
== 0 && newpsr_exc
== 0) ||
8461 (env
->v7m
.exception
== 1 && newpsr_exc
!= 0))) {
8462 /* Pend the fault and tell our caller to take it */
8463 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
8464 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
8466 qemu_log_mask(CPU_LOG_INT
,
8467 "...taking INVPC UsageFault: "
8468 "IPSR consistency check failed\n");
8472 *frame_sp_p
= frameptr
+ 8;
8475 /* This invalidates frame_sp_p */
8476 switch_v7m_security_state(env
, true);
8477 env
->v7m
.exception
= newpsr_exc
;
8478 env
->v7m
.control
[M_REG_S
] &= ~R_V7M_CONTROL_SFPA_MASK
;
8479 if (newpsr
& XPSR_SFPA
) {
8480 env
->v7m
.control
[M_REG_S
] |= R_V7M_CONTROL_SFPA_MASK
;
8482 xpsr_write(env
, 0, XPSR_IT
);
8483 env
->thumb
= newpc
& 1;
8484 env
->regs
[15] = newpc
& ~1;
8486 qemu_log_mask(CPU_LOG_INT
, "...function return successful\n");
8490 static void arm_log_exception(int idx
)
8492 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
8493 const char *exc
= NULL
;
8494 static const char * const excnames
[] = {
8495 [EXCP_UDEF
] = "Undefined Instruction",
8497 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
8498 [EXCP_DATA_ABORT
] = "Data Abort",
8501 [EXCP_BKPT
] = "Breakpoint",
8502 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
8503 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
8504 [EXCP_HVC
] = "Hypervisor Call",
8505 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
8506 [EXCP_SMC
] = "Secure Monitor Call",
8507 [EXCP_VIRQ
] = "Virtual IRQ",
8508 [EXCP_VFIQ
] = "Virtual FIQ",
8509 [EXCP_SEMIHOST
] = "Semihosting call",
8510 [EXCP_NOCP
] = "v7M NOCP UsageFault",
8511 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
8512 [EXCP_STKOF
] = "v8M STKOF UsageFault",
8515 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
8516 exc
= excnames
[idx
];
8521 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s]\n", idx
, exc
);
8525 static bool v7m_read_half_insn(ARMCPU
*cpu
, ARMMMUIdx mmu_idx
,
8526 uint32_t addr
, uint16_t *insn
)
8528 /* Load a 16-bit portion of a v7M instruction, returning true on success,
8529 * or false on failure (in which case we will have pended the appropriate
8531 * We need to do the instruction fetch's MPU and SAU checks
8532 * like this because there is no MMU index that would allow
8533 * doing the load with a single function call. Instead we must
8534 * first check that the security attributes permit the load
8535 * and that they don't mismatch on the two halves of the instruction,
8536 * and then we do the load as a secure load (ie using the security
8537 * attributes of the address, not the CPU, as architecturally required).
8539 CPUState
*cs
= CPU(cpu
);
8540 CPUARMState
*env
= &cpu
->env
;
8541 V8M_SAttributes sattrs
= {};
8542 MemTxAttrs attrs
= {};
8543 ARMMMUFaultInfo fi
= {};
8545 target_ulong page_size
;
8549 v8m_security_lookup(env
, addr
, MMU_INST_FETCH
, mmu_idx
, &sattrs
);
8550 if (!sattrs
.nsc
|| sattrs
.ns
) {
8551 /* This must be the second half of the insn, and it straddles a
8552 * region boundary with the second half not being S&NSC.
8554 env
->v7m
.sfsr
|= R_V7M_SFSR_INVEP_MASK
;
8555 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
8556 qemu_log_mask(CPU_LOG_INT
,
8557 "...really SecureFault with SFSR.INVEP\n");
8560 if (get_phys_addr(env
, addr
, MMU_INST_FETCH
, mmu_idx
,
8561 &physaddr
, &attrs
, &prot
, &page_size
, &fi
, NULL
)) {
8562 /* the MPU lookup failed */
8563 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_IACCVIOL_MASK
;
8564 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
, env
->v7m
.secure
);
8565 qemu_log_mask(CPU_LOG_INT
, "...really MemManage with CFSR.IACCVIOL\n");
8568 *insn
= address_space_lduw_le(arm_addressspace(cs
, attrs
), physaddr
,
8570 if (txres
!= MEMTX_OK
) {
8571 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_IBUSERR_MASK
;
8572 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_BUS
, false);
8573 qemu_log_mask(CPU_LOG_INT
, "...really BusFault with CFSR.IBUSERR\n");
8579 static bool v7m_handle_execute_nsc(ARMCPU
*cpu
)
8581 /* Check whether this attempt to execute code in a Secure & NS-Callable
8582 * memory region is for an SG instruction; if so, then emulate the
8583 * effect of the SG instruction and return true. Otherwise pend
8584 * the correct kind of exception and return false.
8586 CPUARMState
*env
= &cpu
->env
;
8590 /* We should never get here unless get_phys_addr_pmsav8() caused
8591 * an exception for NS executing in S&NSC memory.
8593 assert(!env
->v7m
.secure
);
8594 assert(arm_feature(env
, ARM_FEATURE_M_SECURITY
));
8596 /* We want to do the MPU lookup as secure; work out what mmu_idx that is */
8597 mmu_idx
= arm_v7m_mmu_idx_for_secstate(env
, true);
8599 if (!v7m_read_half_insn(cpu
, mmu_idx
, env
->regs
[15], &insn
)) {
8607 if (insn
!= 0xe97f) {
8608 /* Not an SG instruction first half (we choose the IMPDEF
8609 * early-SG-check option).
8614 if (!v7m_read_half_insn(cpu
, mmu_idx
, env
->regs
[15] + 2, &insn
)) {
8618 if (insn
!= 0xe97f) {
8619 /* Not an SG instruction second half (yes, both halves of the SG
8620 * insn have the same hex value)
8625 /* OK, we have confirmed that we really have an SG instruction.
8626 * We know we're NS in S memory so don't need to repeat those checks.
8628 qemu_log_mask(CPU_LOG_INT
, "...really an SG instruction at 0x%08" PRIx32
8629 ", executing it\n", env
->regs
[15]);
8630 env
->regs
[14] &= ~1;
8631 switch_v7m_security_state(env
, true);
8632 xpsr_write(env
, 0, XPSR_IT
);
8637 env
->v7m
.sfsr
|= R_V7M_SFSR_INVEP_MASK
;
8638 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
8639 qemu_log_mask(CPU_LOG_INT
,
8640 "...really SecureFault with SFSR.INVEP\n");
8644 void arm_v7m_cpu_do_interrupt(CPUState
*cs
)
8646 ARMCPU
*cpu
= ARM_CPU(cs
);
8647 CPUARMState
*env
= &cpu
->env
;
8649 bool ignore_stackfaults
;
8651 arm_log_exception(cs
->exception_index
);
8653 /* For exceptions we just mark as pending on the NVIC, and let that
8655 switch (cs
->exception_index
) {
8657 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
8658 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_UNDEFINSTR_MASK
;
8661 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
8662 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_NOCP_MASK
;
8665 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
8666 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVSTATE_MASK
;
8669 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
8670 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_STKOF_MASK
;
8673 /* The PC already points to the next instruction. */
8674 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
, env
->v7m
.secure
);
8676 case EXCP_PREFETCH_ABORT
:
8677 case EXCP_DATA_ABORT
:
8678 /* Note that for M profile we don't have a guest facing FSR, but
8679 * the env->exception.fsr will be populated by the code that
8680 * raises the fault, in the A profile short-descriptor format.
8682 switch (env
->exception
.fsr
& 0xf) {
8683 case M_FAKE_FSR_NSC_EXEC
:
8684 /* Exception generated when we try to execute code at an address
8685 * which is marked as Secure & Non-Secure Callable and the CPU
8686 * is in the Non-Secure state. The only instruction which can
8687 * be executed like this is SG (and that only if both halves of
8688 * the SG instruction have the same security attributes.)
8689 * Everything else must generate an INVEP SecureFault, so we
8690 * emulate the SG instruction here.
8692 if (v7m_handle_execute_nsc(cpu
)) {
8696 case M_FAKE_FSR_SFAULT
:
8697 /* Various flavours of SecureFault for attempts to execute or
8698 * access data in the wrong security state.
8700 switch (cs
->exception_index
) {
8701 case EXCP_PREFETCH_ABORT
:
8702 if (env
->v7m
.secure
) {
8703 env
->v7m
.sfsr
|= R_V7M_SFSR_INVTRAN_MASK
;
8704 qemu_log_mask(CPU_LOG_INT
,
8705 "...really SecureFault with SFSR.INVTRAN\n");
8707 env
->v7m
.sfsr
|= R_V7M_SFSR_INVEP_MASK
;
8708 qemu_log_mask(CPU_LOG_INT
,
8709 "...really SecureFault with SFSR.INVEP\n");
8712 case EXCP_DATA_ABORT
:
8713 /* This must be an NS access to S memory */
8714 env
->v7m
.sfsr
|= R_V7M_SFSR_AUVIOL_MASK
;
8715 qemu_log_mask(CPU_LOG_INT
,
8716 "...really SecureFault with SFSR.AUVIOL\n");
8719 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
8721 case 0x8: /* External Abort */
8722 switch (cs
->exception_index
) {
8723 case EXCP_PREFETCH_ABORT
:
8724 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_IBUSERR_MASK
;
8725 qemu_log_mask(CPU_LOG_INT
, "...with CFSR.IBUSERR\n");
8727 case EXCP_DATA_ABORT
:
8728 env
->v7m
.cfsr
[M_REG_NS
] |=
8729 (R_V7M_CFSR_PRECISERR_MASK
| R_V7M_CFSR_BFARVALID_MASK
);
8730 env
->v7m
.bfar
= env
->exception
.vaddress
;
8731 qemu_log_mask(CPU_LOG_INT
,
8732 "...with CFSR.PRECISERR and BFAR 0x%x\n",
8736 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_BUS
, false);
8739 /* All other FSR values are either MPU faults or "can't happen
8740 * for M profile" cases.
8742 switch (cs
->exception_index
) {
8743 case EXCP_PREFETCH_ABORT
:
8744 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_IACCVIOL_MASK
;
8745 qemu_log_mask(CPU_LOG_INT
, "...with CFSR.IACCVIOL\n");
8747 case EXCP_DATA_ABORT
:
8748 env
->v7m
.cfsr
[env
->v7m
.secure
] |=
8749 (R_V7M_CFSR_DACCVIOL_MASK
| R_V7M_CFSR_MMARVALID_MASK
);
8750 env
->v7m
.mmfar
[env
->v7m
.secure
] = env
->exception
.vaddress
;
8751 qemu_log_mask(CPU_LOG_INT
,
8752 "...with CFSR.DACCVIOL and MMFAR 0x%x\n",
8753 env
->v7m
.mmfar
[env
->v7m
.secure
]);
8756 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
,
8762 if (semihosting_enabled()) {
8764 nr
= arm_lduw_code(env
, env
->regs
[15], arm_sctlr_b(env
)) & 0xff;
8767 qemu_log_mask(CPU_LOG_INT
,
8768 "...handling as semihosting call 0x%x\n",
8770 env
->regs
[0] = do_arm_semihosting(env
);
8774 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
, false);
8778 case EXCP_EXCEPTION_EXIT
:
8779 if (env
->regs
[15] < EXC_RETURN_MIN_MAGIC
) {
8780 /* Must be v8M security extension function return */
8781 assert(env
->regs
[15] >= FNC_RETURN_MIN_MAGIC
);
8782 assert(arm_feature(env
, ARM_FEATURE_M_SECURITY
));
8783 if (do_v7m_function_return(cpu
)) {
8787 do_v7m_exception_exit(cpu
);
8792 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
8793 return; /* Never happens. Keep compiler happy. */
8796 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8797 lr
= R_V7M_EXCRET_RES1_MASK
|
8798 R_V7M_EXCRET_DCRS_MASK
|
8799 R_V7M_EXCRET_FTYPE_MASK
;
8800 /* The S bit indicates whether we should return to Secure
8801 * or NonSecure (ie our current state).
8802 * The ES bit indicates whether we're taking this exception
8803 * to Secure or NonSecure (ie our target state). We set it
8804 * later, in v7m_exception_taken().
8805 * The SPSEL bit is also set in v7m_exception_taken() for v8M.
8806 * This corresponds to the ARM ARM pseudocode for v8M setting
8807 * some LR bits in PushStack() and some in ExceptionTaken();
8808 * the distinction matters for the tailchain cases where we
8809 * can take an exception without pushing the stack.
8811 if (env
->v7m
.secure
) {
8812 lr
|= R_V7M_EXCRET_S_MASK
;
8815 lr
= R_V7M_EXCRET_RES1_MASK
|
8816 R_V7M_EXCRET_S_MASK
|
8817 R_V7M_EXCRET_DCRS_MASK
|
8818 R_V7M_EXCRET_FTYPE_MASK
|
8819 R_V7M_EXCRET_ES_MASK
;
8820 if (env
->v7m
.control
[M_REG_NS
] & R_V7M_CONTROL_SPSEL_MASK
) {
8821 lr
|= R_V7M_EXCRET_SPSEL_MASK
;
8824 if (!arm_v7m_is_handler_mode(env
)) {
8825 lr
|= R_V7M_EXCRET_MODE_MASK
;
8828 ignore_stackfaults
= v7m_push_stack(cpu
);
8829 v7m_exception_taken(cpu
, lr
, false, ignore_stackfaults
);
8832 /* Function used to synchronize QEMU's AArch64 register set with AArch32
8833 * register set. This is necessary when switching between AArch32 and AArch64
8836 void aarch64_sync_32_to_64(CPUARMState
*env
)
8839 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
8841 /* We can blanket copy R[0:7] to X[0:7] */
8842 for (i
= 0; i
< 8; i
++) {
8843 env
->xregs
[i
] = env
->regs
[i
];
8846 /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
8847 * Otherwise, they come from the banked user regs.
8849 if (mode
== ARM_CPU_MODE_FIQ
) {
8850 for (i
= 8; i
< 13; i
++) {
8851 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
8854 for (i
= 8; i
< 13; i
++) {
8855 env
->xregs
[i
] = env
->regs
[i
];
8859 /* Registers x13-x23 are the various mode SP and FP registers. Registers
8860 * r13 and r14 are only copied if we are in that mode, otherwise we copy
8861 * from the mode banked register.
8863 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
8864 env
->xregs
[13] = env
->regs
[13];
8865 env
->xregs
[14] = env
->regs
[14];
8867 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
8868 /* HYP is an exception in that it is copied from r14 */
8869 if (mode
== ARM_CPU_MODE_HYP
) {
8870 env
->xregs
[14] = env
->regs
[14];
8872 env
->xregs
[14] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)];
8876 if (mode
== ARM_CPU_MODE_HYP
) {
8877 env
->xregs
[15] = env
->regs
[13];
8879 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
8882 if (mode
== ARM_CPU_MODE_IRQ
) {
8883 env
->xregs
[16] = env
->regs
[14];
8884 env
->xregs
[17] = env
->regs
[13];
8886 env
->xregs
[16] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)];
8887 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
8890 if (mode
== ARM_CPU_MODE_SVC
) {
8891 env
->xregs
[18] = env
->regs
[14];
8892 env
->xregs
[19] = env
->regs
[13];
8894 env
->xregs
[18] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)];
8895 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
8898 if (mode
== ARM_CPU_MODE_ABT
) {
8899 env
->xregs
[20] = env
->regs
[14];
8900 env
->xregs
[21] = env
->regs
[13];
8902 env
->xregs
[20] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)];
8903 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
8906 if (mode
== ARM_CPU_MODE_UND
) {
8907 env
->xregs
[22] = env
->regs
[14];
8908 env
->xregs
[23] = env
->regs
[13];
8910 env
->xregs
[22] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)];
8911 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
8914 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
8915 * mode, then we can copy from r8-r14. Otherwise, we copy from the
8916 * FIQ bank for r8-r14.
8918 if (mode
== ARM_CPU_MODE_FIQ
) {
8919 for (i
= 24; i
< 31; i
++) {
8920 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
8923 for (i
= 24; i
< 29; i
++) {
8924 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
8926 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
8927 env
->xregs
[30] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)];
8930 env
->pc
= env
->regs
[15];
8933 /* Function used to synchronize QEMU's AArch32 register set with AArch64
8934 * register set. This is necessary when switching between AArch32 and AArch64
8937 void aarch64_sync_64_to_32(CPUARMState
*env
)
8940 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
8942 /* We can blanket copy X[0:7] to R[0:7] */
8943 for (i
= 0; i
< 8; i
++) {
8944 env
->regs
[i
] = env
->xregs
[i
];
8947 /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
8948 * Otherwise, we copy x8-x12 into the banked user regs.
8950 if (mode
== ARM_CPU_MODE_FIQ
) {
8951 for (i
= 8; i
< 13; i
++) {
8952 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
8955 for (i
= 8; i
< 13; i
++) {
8956 env
->regs
[i
] = env
->xregs
[i
];
8960 /* Registers r13 & r14 depend on the current mode.
8961 * If we are in a given mode, we copy the corresponding x registers to r13
8962 * and r14. Otherwise, we copy the x register to the banked r13 and r14
8965 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
8966 env
->regs
[13] = env
->xregs
[13];
8967 env
->regs
[14] = env
->xregs
[14];
8969 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
8971 /* HYP is an exception in that it does not have its own banked r14 but
8972 * shares the USR r14
8974 if (mode
== ARM_CPU_MODE_HYP
) {
8975 env
->regs
[14] = env
->xregs
[14];
8977 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
8981 if (mode
== ARM_CPU_MODE_HYP
) {
8982 env
->regs
[13] = env
->xregs
[15];
8984 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
8987 if (mode
== ARM_CPU_MODE_IRQ
) {
8988 env
->regs
[14] = env
->xregs
[16];
8989 env
->regs
[13] = env
->xregs
[17];
8991 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
8992 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
8995 if (mode
== ARM_CPU_MODE_SVC
) {
8996 env
->regs
[14] = env
->xregs
[18];
8997 env
->regs
[13] = env
->xregs
[19];
8999 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
9000 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
9003 if (mode
== ARM_CPU_MODE_ABT
) {
9004 env
->regs
[14] = env
->xregs
[20];
9005 env
->regs
[13] = env
->xregs
[21];
9007 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
9008 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
9011 if (mode
== ARM_CPU_MODE_UND
) {
9012 env
->regs
[14] = env
->xregs
[22];
9013 env
->regs
[13] = env
->xregs
[23];
9015 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
9016 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
9019 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
9020 * mode, then we can copy to r8-r14. Otherwise, we copy to the
9021 * FIQ bank for r8-r14.
9023 if (mode
== ARM_CPU_MODE_FIQ
) {
9024 for (i
= 24; i
< 31; i
++) {
9025 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
9028 for (i
= 24; i
< 29; i
++) {
9029 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
9031 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
9032 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
9035 env
->regs
[15] = env
->pc
;
9038 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
9039 uint32_t mask
, uint32_t offset
,
9042 /* Change the CPU state so as to actually take the exception. */
9043 switch_mode(env
, new_mode
);
9045 * For exceptions taken to AArch32 we must clear the SS bit in both
9046 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
9048 env
->uncached_cpsr
&= ~PSTATE_SS
;
9049 env
->spsr
= cpsr_read(env
);
9050 /* Clear IT bits. */
9051 env
->condexec_bits
= 0;
9052 /* Switch to the new mode, and to the correct instruction set. */
9053 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
9054 /* Set new mode endianness */
9055 env
->uncached_cpsr
&= ~CPSR_E
;
9056 if (env
->cp15
.sctlr_el
[arm_current_el(env
)] & SCTLR_EE
) {
9057 env
->uncached_cpsr
|= CPSR_E
;
9059 /* J and IL must always be cleared for exception entry */
9060 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
9063 if (new_mode
== ARM_CPU_MODE_HYP
) {
9064 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
9065 env
->elr_el
[2] = env
->regs
[15];
9068 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
9069 * and we should just guard the thumb mode on V4
9071 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
9073 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
9075 env
->regs
[14] = env
->regs
[15] + offset
;
9077 env
->regs
[15] = newpc
;
9080 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
9083 * Handle exception entry to Hyp mode; this is sufficiently
9084 * different to entry to other AArch32 modes that we handle it
9087 * The vector table entry used is always the 0x14 Hyp mode entry point,
9088 * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp.
9089 * The offset applied to the preferred return address is always zero
9090 * (see DDI0487C.a section G1.12.3).
9091 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
9093 uint32_t addr
, mask
;
9094 ARMCPU
*cpu
= ARM_CPU(cs
);
9095 CPUARMState
*env
= &cpu
->env
;
9097 switch (cs
->exception_index
) {
9105 /* Fall through to prefetch abort. */
9106 case EXCP_PREFETCH_ABORT
:
9107 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
9108 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
9109 (uint32_t)env
->exception
.vaddress
);
9112 case EXCP_DATA_ABORT
:
9113 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
9114 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
9115 (uint32_t)env
->exception
.vaddress
);
9130 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9133 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
9134 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
9136 * QEMU syndrome values are v8-style. v7 has the IL bit
9137 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
9138 * If this is a v7 CPU, squash the IL bit in those cases.
9140 if (cs
->exception_index
== EXCP_PREFETCH_ABORT
||
9141 (cs
->exception_index
== EXCP_DATA_ABORT
&&
9142 !(env
->exception
.syndrome
& ARM_EL_ISV
)) ||
9143 syn_get_ec(env
->exception
.syndrome
) == EC_UNCATEGORIZED
) {
9144 env
->exception
.syndrome
&= ~ARM_EL_IL
;
9147 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
9150 if (arm_current_el(env
) != 2 && addr
< 0x14) {
9155 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
9158 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
9161 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
9165 addr
+= env
->cp15
.hvbar
;
9167 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
9170 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
9172 ARMCPU
*cpu
= ARM_CPU(cs
);
9173 CPUARMState
*env
= &cpu
->env
;
9180 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
9181 switch (syn_get_ec(env
->exception
.syndrome
)) {
9183 case EC_BREAKPOINT_SAME_EL
:
9187 case EC_WATCHPOINT_SAME_EL
:
9193 case EC_VECTORCATCH
:
9202 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
9205 if (env
->exception
.target_el
== 2) {
9206 arm_cpu_do_interrupt_aarch32_hyp(cs
);
9210 switch (cs
->exception_index
) {
9212 new_mode
= ARM_CPU_MODE_UND
;
9221 new_mode
= ARM_CPU_MODE_SVC
;
9224 /* The PC already points to the next instruction. */
9228 /* Fall through to prefetch abort. */
9229 case EXCP_PREFETCH_ABORT
:
9230 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
9231 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
9232 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
9233 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
9234 new_mode
= ARM_CPU_MODE_ABT
;
9236 mask
= CPSR_A
| CPSR_I
;
9239 case EXCP_DATA_ABORT
:
9240 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
9241 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
9242 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
9244 (uint32_t)env
->exception
.vaddress
);
9245 new_mode
= ARM_CPU_MODE_ABT
;
9247 mask
= CPSR_A
| CPSR_I
;
9251 new_mode
= ARM_CPU_MODE_IRQ
;
9253 /* Disable IRQ and imprecise data aborts. */
9254 mask
= CPSR_A
| CPSR_I
;
9256 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
9257 /* IRQ routed to monitor mode */
9258 new_mode
= ARM_CPU_MODE_MON
;
9263 new_mode
= ARM_CPU_MODE_FIQ
;
9265 /* Disable FIQ, IRQ and imprecise data aborts. */
9266 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9267 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
9268 /* FIQ routed to monitor mode */
9269 new_mode
= ARM_CPU_MODE_MON
;
9274 new_mode
= ARM_CPU_MODE_IRQ
;
9276 /* Disable IRQ and imprecise data aborts. */
9277 mask
= CPSR_A
| CPSR_I
;
9281 new_mode
= ARM_CPU_MODE_FIQ
;
9283 /* Disable FIQ, IRQ and imprecise data aborts. */
9284 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9288 new_mode
= ARM_CPU_MODE_MON
;
9290 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9294 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9295 return; /* Never happens. Keep compiler happy. */
9298 if (new_mode
== ARM_CPU_MODE_MON
) {
9299 addr
+= env
->cp15
.mvbar
;
9300 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
9301 /* High vectors. When enabled, base address cannot be remapped. */
9304 /* ARM v7 architectures provide a vector base address register to remap
9305 * the interrupt vector table.
9306 * This register is only followed in non-monitor mode, and is banked.
9307 * Note: only bits 31:5 are valid.
9309 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
9312 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
9313 env
->cp15
.scr_el3
&= ~SCR_NS
;
9316 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
9319 /* Handle exception entry to a target EL which is using AArch64 */
9320 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
9322 ARMCPU
*cpu
= ARM_CPU(cs
);
9323 CPUARMState
*env
= &cpu
->env
;
9324 unsigned int new_el
= env
->exception
.target_el
;
9325 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
9326 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
9327 unsigned int cur_el
= arm_current_el(env
);
9330 * Note that new_el can never be 0. If cur_el is 0, then
9331 * el0_a64 is is_a64(), else el0_a64 is ignored.
9333 aarch64_sve_change_el(env
, cur_el
, new_el
, is_a64(env
));
9335 if (cur_el
< new_el
) {
9336 /* Entry vector offset depends on whether the implemented EL
9337 * immediately lower than the target level is using AArch32 or AArch64
9343 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
9346 is_aa64
= (env
->cp15
.hcr_el2
& HCR_RW
) != 0;
9349 is_aa64
= is_a64(env
);
9352 g_assert_not_reached();
9360 } else if (pstate_read(env
) & PSTATE_SP
) {
9364 switch (cs
->exception_index
) {
9365 case EXCP_PREFETCH_ABORT
:
9366 case EXCP_DATA_ABORT
:
9367 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
9368 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
9369 env
->cp15
.far_el
[new_el
]);
9377 if (syn_get_ec(env
->exception
.syndrome
) == EC_ADVSIMDFPACCESSTRAP
) {
9379 * QEMU internal FP/SIMD syndromes from AArch32 include the
9380 * TA and coproc fields which are only exposed if the exception
9381 * is taken to AArch32 Hyp mode. Mask them out to get a valid
9382 * AArch64 format syndrome.
9384 env
->exception
.syndrome
&= ~MAKE_64BIT_MASK(0, 20);
9386 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
9397 qemu_log_mask(CPU_LOG_INT
,
9398 "...handling as semihosting call 0x%" PRIx64
"\n",
9400 env
->xregs
[0] = do_arm_semihosting(env
);
9403 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9407 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = pstate_read(env
);
9408 aarch64_save_sp(env
, arm_current_el(env
));
9409 env
->elr_el
[new_el
] = env
->pc
;
9411 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = cpsr_read(env
);
9412 env
->elr_el
[new_el
] = env
->regs
[15];
9414 aarch64_sync_32_to_64(env
);
9416 env
->condexec_bits
= 0;
9418 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
9419 env
->elr_el
[new_el
]);
9421 pstate_write(env
, PSTATE_DAIF
| new_mode
);
9423 aarch64_restore_sp(env
, new_el
);
9427 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
9428 new_el
, env
->pc
, pstate_read(env
));
9431 static inline bool check_for_semihosting(CPUState
*cs
)
9433 /* Check whether this exception is a semihosting call; if so
9434 * then handle it and return true; otherwise return false.
9436 ARMCPU
*cpu
= ARM_CPU(cs
);
9437 CPUARMState
*env
= &cpu
->env
;
9440 if (cs
->exception_index
== EXCP_SEMIHOST
) {
9441 /* This is always the 64-bit semihosting exception.
9442 * The "is this usermode" and "is semihosting enabled"
9443 * checks have been done at translate time.
9445 qemu_log_mask(CPU_LOG_INT
,
9446 "...handling as semihosting call 0x%" PRIx64
"\n",
9448 env
->xregs
[0] = do_arm_semihosting(env
);
9455 /* Only intercept calls from privileged modes, to provide some
9456 * semblance of security.
9458 if (cs
->exception_index
!= EXCP_SEMIHOST
&&
9459 (!semihosting_enabled() ||
9460 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
))) {
9464 switch (cs
->exception_index
) {
9466 /* This is always a semihosting call; the "is this usermode"
9467 * and "is semihosting enabled" checks have been done at
9472 /* Check for semihosting interrupt. */
9474 imm
= arm_lduw_code(env
, env
->regs
[15] - 2, arm_sctlr_b(env
))
9480 imm
= arm_ldl_code(env
, env
->regs
[15] - 4, arm_sctlr_b(env
))
9482 if (imm
== 0x123456) {
9488 /* See if this is a semihosting syscall. */
9490 imm
= arm_lduw_code(env
, env
->regs
[15], arm_sctlr_b(env
))
9502 qemu_log_mask(CPU_LOG_INT
,
9503 "...handling as semihosting call 0x%x\n",
9505 env
->regs
[0] = do_arm_semihosting(env
);
9510 /* Handle a CPU exception for A and R profile CPUs.
9511 * Do any appropriate logging, handle PSCI calls, and then hand off
9512 * to the AArch64-entry or AArch32-entry function depending on the
9513 * target exception level's register width.
9515 void arm_cpu_do_interrupt(CPUState
*cs
)
9517 ARMCPU
*cpu
= ARM_CPU(cs
);
9518 CPUARMState
*env
= &cpu
->env
;
9519 unsigned int new_el
= env
->exception
.target_el
;
9521 assert(!arm_feature(env
, ARM_FEATURE_M
));
9523 arm_log_exception(cs
->exception_index
);
9524 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
9526 if (qemu_loglevel_mask(CPU_LOG_INT
)
9527 && !excp_is_internal(cs
->exception_index
)) {
9528 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
9529 syn_get_ec(env
->exception
.syndrome
),
9530 env
->exception
.syndrome
);
9533 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
9534 arm_handle_psci_call(cpu
);
9535 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
9539 /* Semihosting semantics depend on the register width of the
9540 * code that caused the exception, not the target exception level,
9541 * so must be handled here.
9543 if (check_for_semihosting(cs
)) {
9547 /* Hooks may change global state so BQL should be held, also the
9548 * BQL needs to be held for any modification of
9549 * cs->interrupt_request.
9551 g_assert(qemu_mutex_iothread_locked());
9553 arm_call_pre_el_change_hook(cpu
);
9555 assert(!excp_is_internal(cs
->exception_index
));
9556 if (arm_el_is_aa64(env
, new_el
)) {
9557 arm_cpu_do_interrupt_aarch64(cs
);
9559 arm_cpu_do_interrupt_aarch32(cs
);
9562 arm_call_el_change_hook(cpu
);
9564 if (!kvm_enabled()) {
9565 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
9569 /* Return the exception level which controls this address translation regime */
9570 static inline uint32_t regime_el(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
9573 case ARMMMUIdx_S2NS
:
9574 case ARMMMUIdx_S1E2
:
9576 case ARMMMUIdx_S1E3
:
9578 case ARMMMUIdx_S1SE0
:
9579 return arm_el_is_aa64(env
, 3) ? 1 : 3;
9580 case ARMMMUIdx_S1SE1
:
9581 case ARMMMUIdx_S1NSE0
:
9582 case ARMMMUIdx_S1NSE1
:
9583 case ARMMMUIdx_MPrivNegPri
:
9584 case ARMMMUIdx_MUserNegPri
:
9585 case ARMMMUIdx_MPriv
:
9586 case ARMMMUIdx_MUser
:
9587 case ARMMMUIdx_MSPrivNegPri
:
9588 case ARMMMUIdx_MSUserNegPri
:
9589 case ARMMMUIdx_MSPriv
:
9590 case ARMMMUIdx_MSUser
:
9593 g_assert_not_reached();
9597 /* Return the SCTLR value which controls this address translation regime */
9598 static inline uint32_t regime_sctlr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
9600 return env
->cp15
.sctlr_el
[regime_el(env
, mmu_idx
)];
9603 /* Return true if the specified stage of address translation is disabled */
9604 static inline bool regime_translation_disabled(CPUARMState
*env
,
9607 if (arm_feature(env
, ARM_FEATURE_M
)) {
9608 switch (env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)] &
9609 (R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
)) {
9610 case R_V7M_MPU_CTRL_ENABLE_MASK
:
9611 /* Enabled, but not for HardFault and NMI */
9612 return mmu_idx
& ARM_MMU_IDX_M_NEGPRI
;
9613 case R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
:
9614 /* Enabled for all cases */
9618 /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
9619 * we warned about that in armv7m_nvic.c when the guest set it.
9625 if (mmu_idx
== ARMMMUIdx_S2NS
) {
9626 /* HCR.DC means HCR.VM behaves as 1 */
9627 return (env
->cp15
.hcr_el2
& (HCR_DC
| HCR_VM
)) == 0;
9630 if (env
->cp15
.hcr_el2
& HCR_TGE
) {
9631 /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
9632 if (!regime_is_secure(env
, mmu_idx
) && regime_el(env
, mmu_idx
) == 1) {
9637 if ((env
->cp15
.hcr_el2
& HCR_DC
) &&
9638 (mmu_idx
== ARMMMUIdx_S1NSE0
|| mmu_idx
== ARMMMUIdx_S1NSE1
)) {
9639 /* HCR.DC means SCTLR_EL1.M behaves as 0 */
9643 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
9646 static inline bool regime_translation_big_endian(CPUARMState
*env
,
9649 return (regime_sctlr(env
, mmu_idx
) & SCTLR_EE
) != 0;
9652 /* Return the TCR controlling this translation regime */
9653 static inline TCR
*regime_tcr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
9655 if (mmu_idx
== ARMMMUIdx_S2NS
) {
9656 return &env
->cp15
.vtcr_el2
;
9658 return &env
->cp15
.tcr_el
[regime_el(env
, mmu_idx
)];
9661 /* Convert a possible stage1+2 MMU index into the appropriate
9664 static inline ARMMMUIdx
stage_1_mmu_idx(ARMMMUIdx mmu_idx
)
9666 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
9667 mmu_idx
+= (ARMMMUIdx_S1NSE0
- ARMMMUIdx_S12NSE0
);
9672 /* Return the TTBR associated with this translation regime */
9673 static inline uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
9676 if (mmu_idx
== ARMMMUIdx_S2NS
) {
9677 return env
->cp15
.vttbr_el2
;
9680 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
9682 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
9686 /* Return true if the translation regime is using LPAE format page tables */
9687 static inline bool regime_using_lpae_format(CPUARMState
*env
,
9690 int el
= regime_el(env
, mmu_idx
);
9691 if (el
== 2 || arm_el_is_aa64(env
, el
)) {
9694 if (arm_feature(env
, ARM_FEATURE_LPAE
)
9695 && (regime_tcr(env
, mmu_idx
)->raw_tcr
& TTBCR_EAE
)) {
9701 /* Returns true if the stage 1 translation regime is using LPAE format page
9702 * tables. Used when raising alignment exceptions, whose FSR changes depending
9703 * on whether the long or short descriptor format is in use. */
9704 bool arm_s1_regime_using_lpae_format(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
9706 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
9708 return regime_using_lpae_format(env
, mmu_idx
);
9711 static inline bool regime_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
9714 case ARMMMUIdx_S1SE0
:
9715 case ARMMMUIdx_S1NSE0
:
9716 case ARMMMUIdx_MUser
:
9717 case ARMMMUIdx_MSUser
:
9718 case ARMMMUIdx_MUserNegPri
:
9719 case ARMMMUIdx_MSUserNegPri
:
9723 case ARMMMUIdx_S12NSE0
:
9724 case ARMMMUIdx_S12NSE1
:
9725 g_assert_not_reached();
9729 /* Translate section/page access permissions to page
9730 * R/W protection flags
9733 * @mmu_idx: MMU index indicating required translation regime
9734 * @ap: The 3-bit access permissions (AP[2:0])
9735 * @domain_prot: The 2-bit domain access permissions
9737 static inline int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
9738 int ap
, int domain_prot
)
9740 bool is_user
= regime_is_user(env
, mmu_idx
);
9742 if (domain_prot
== 3) {
9743 return PAGE_READ
| PAGE_WRITE
;
9748 if (arm_feature(env
, ARM_FEATURE_V7
)) {
9751 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
9753 return is_user
? 0 : PAGE_READ
;
9760 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
9765 return PAGE_READ
| PAGE_WRITE
;
9768 return PAGE_READ
| PAGE_WRITE
;
9769 case 4: /* Reserved. */
9772 return is_user
? 0 : PAGE_READ
;
9776 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
9781 g_assert_not_reached();
9785 /* Translate section/page access permissions to page
9786 * R/W protection flags.
9788 * @ap: The 2-bit simple AP (AP[2:1])
9789 * @is_user: TRUE if accessing from PL0
9791 static inline int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
9795 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
9797 return PAGE_READ
| PAGE_WRITE
;
9799 return is_user
? 0 : PAGE_READ
;
9803 g_assert_not_reached();
9808 simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
9810 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
9813 /* Translate S2 section/page access permissions to protection flags
9816 * @s2ap: The 2-bit stage2 access permissions (S2AP)
9817 * @xn: XN (execute-never) bit
9819 static int get_S2prot(CPUARMState
*env
, int s2ap
, int xn
)
9830 if (arm_el_is_aa64(env
, 2) || prot
& PAGE_READ
) {
9837 /* Translate section/page access permissions to protection flags
9840 * @mmu_idx: MMU index indicating required translation regime
9841 * @is_aa64: TRUE if AArch64
9842 * @ap: The 2-bit simple AP (AP[2:1])
9843 * @ns: NS (non-secure) bit
9844 * @xn: XN (execute-never) bit
9845 * @pxn: PXN (privileged execute-never) bit
9847 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
9848 int ap
, int ns
, int xn
, int pxn
)
9850 bool is_user
= regime_is_user(env
, mmu_idx
);
9851 int prot_rw
, user_rw
;
9855 assert(mmu_idx
!= ARMMMUIdx_S2NS
);
9857 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
9861 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
9864 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
9868 /* TODO have_wxn should be replaced with
9869 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
9870 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
9871 * compatible processors have EL2, which is required for [U]WXN.
9873 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
9876 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
9880 switch (regime_el(env
, mmu_idx
)) {
9883 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
9890 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
9891 switch (regime_el(env
, mmu_idx
)) {
9895 xn
= xn
|| !(user_rw
& PAGE_READ
);
9899 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
9901 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
9902 (uwxn
&& (user_rw
& PAGE_WRITE
));
9912 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
9915 return prot_rw
| PAGE_EXEC
;
9918 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
9919 uint32_t *table
, uint32_t address
)
9921 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
9922 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
9924 if (address
& tcr
->mask
) {
9925 if (tcr
->raw_tcr
& TTBCR_PD1
) {
9926 /* Translation table walk disabled for TTBR1 */
9929 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
9931 if (tcr
->raw_tcr
& TTBCR_PD0
) {
9932 /* Translation table walk disabled for TTBR0 */
9935 *table
= regime_ttbr(env
, mmu_idx
, 0) & tcr
->base_mask
;
9937 *table
|= (address
>> 18) & 0x3ffc;
9941 /* Translate a S1 pagetable walk through S2 if needed. */
9942 static hwaddr
S1_ptw_translate(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
9943 hwaddr addr
, MemTxAttrs txattrs
,
9944 ARMMMUFaultInfo
*fi
)
9946 if ((mmu_idx
== ARMMMUIdx_S1NSE0
|| mmu_idx
== ARMMMUIdx_S1NSE1
) &&
9947 !regime_translation_disabled(env
, ARMMMUIdx_S2NS
)) {
9948 target_ulong s2size
;
9952 ARMCacheAttrs cacheattrs
= {};
9953 ARMCacheAttrs
*pcacheattrs
= NULL
;
9955 if (env
->cp15
.hcr_el2
& HCR_PTW
) {
9957 * PTW means we must fault if this S1 walk touches S2 Device
9958 * memory; otherwise we don't care about the attributes and can
9959 * save the S2 translation the effort of computing them.
9961 pcacheattrs
= &cacheattrs
;
9964 ret
= get_phys_addr_lpae(env
, addr
, 0, ARMMMUIdx_S2NS
, &s2pa
,
9965 &txattrs
, &s2prot
, &s2size
, fi
, pcacheattrs
);
9967 assert(fi
->type
!= ARMFault_None
);
9973 if (pcacheattrs
&& (pcacheattrs
->attrs
& 0xf0) == 0) {
9974 /* Access was to Device memory: generate Permission fault */
9975 fi
->type
= ARMFault_Permission
;
9986 /* All loads done in the course of a page table walk go through here. */
9987 static uint32_t arm_ldl_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
9988 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
9990 ARMCPU
*cpu
= ARM_CPU(cs
);
9991 CPUARMState
*env
= &cpu
->env
;
9992 MemTxAttrs attrs
= {};
9993 MemTxResult result
= MEMTX_OK
;
9997 attrs
.secure
= is_secure
;
9998 as
= arm_addressspace(cs
, attrs
);
9999 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fi
);
10003 if (regime_translation_big_endian(env
, mmu_idx
)) {
10004 data
= address_space_ldl_be(as
, addr
, attrs
, &result
);
10006 data
= address_space_ldl_le(as
, addr
, attrs
, &result
);
10008 if (result
== MEMTX_OK
) {
10011 fi
->type
= ARMFault_SyncExternalOnWalk
;
10012 fi
->ea
= arm_extabort_type(result
);
10016 static uint64_t arm_ldq_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
10017 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
10019 ARMCPU
*cpu
= ARM_CPU(cs
);
10020 CPUARMState
*env
= &cpu
->env
;
10021 MemTxAttrs attrs
= {};
10022 MemTxResult result
= MEMTX_OK
;
10026 attrs
.secure
= is_secure
;
10027 as
= arm_addressspace(cs
, attrs
);
10028 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fi
);
10032 if (regime_translation_big_endian(env
, mmu_idx
)) {
10033 data
= address_space_ldq_be(as
, addr
, attrs
, &result
);
10035 data
= address_space_ldq_le(as
, addr
, attrs
, &result
);
10037 if (result
== MEMTX_OK
) {
10040 fi
->type
= ARMFault_SyncExternalOnWalk
;
10041 fi
->ea
= arm_extabort_type(result
);
10045 static bool get_phys_addr_v5(CPUARMState
*env
, uint32_t address
,
10046 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10047 hwaddr
*phys_ptr
, int *prot
,
10048 target_ulong
*page_size
,
10049 ARMMMUFaultInfo
*fi
)
10051 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
10062 /* Pagetable walk. */
10063 /* Lookup l1 descriptor. */
10064 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
10065 /* Section translation fault if page walk is disabled by PD0 or PD1 */
10066 fi
->type
= ARMFault_Translation
;
10069 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
10071 if (fi
->type
!= ARMFault_None
) {
10075 domain
= (desc
>> 5) & 0x0f;
10076 if (regime_el(env
, mmu_idx
) == 1) {
10077 dacr
= env
->cp15
.dacr_ns
;
10079 dacr
= env
->cp15
.dacr_s
;
10081 domain_prot
= (dacr
>> (domain
* 2)) & 3;
10083 /* Section translation fault. */
10084 fi
->type
= ARMFault_Translation
;
10090 if (domain_prot
== 0 || domain_prot
== 2) {
10091 fi
->type
= ARMFault_Domain
;
10096 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
10097 ap
= (desc
>> 10) & 3;
10098 *page_size
= 1024 * 1024;
10100 /* Lookup l2 entry. */
10102 /* Coarse pagetable. */
10103 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
10105 /* Fine pagetable. */
10106 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
10108 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
10110 if (fi
->type
!= ARMFault_None
) {
10113 switch (desc
& 3) {
10114 case 0: /* Page translation fault. */
10115 fi
->type
= ARMFault_Translation
;
10117 case 1: /* 64k page. */
10118 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
10119 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
10120 *page_size
= 0x10000;
10122 case 2: /* 4k page. */
10123 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
10124 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
10125 *page_size
= 0x1000;
10127 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
10129 /* ARMv6/XScale extended small page format */
10130 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
10131 || arm_feature(env
, ARM_FEATURE_V6
)) {
10132 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
10133 *page_size
= 0x1000;
10135 /* UNPREDICTABLE in ARMv5; we choose to take a
10136 * page translation fault.
10138 fi
->type
= ARMFault_Translation
;
10142 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
10143 *page_size
= 0x400;
10145 ap
= (desc
>> 4) & 3;
10148 /* Never happens, but compiler isn't smart enough to tell. */
10152 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
10153 *prot
|= *prot
? PAGE_EXEC
: 0;
10154 if (!(*prot
& (1 << access_type
))) {
10155 /* Access permission fault. */
10156 fi
->type
= ARMFault_Permission
;
10159 *phys_ptr
= phys_addr
;
10162 fi
->domain
= domain
;
10167 static bool get_phys_addr_v6(CPUARMState
*env
, uint32_t address
,
10168 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10169 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
10170 target_ulong
*page_size
, ARMMMUFaultInfo
*fi
)
10172 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
10186 /* Pagetable walk. */
10187 /* Lookup l1 descriptor. */
10188 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
10189 /* Section translation fault if page walk is disabled by PD0 or PD1 */
10190 fi
->type
= ARMFault_Translation
;
10193 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
10195 if (fi
->type
!= ARMFault_None
) {
10199 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
10200 /* Section translation fault, or attempt to use the encoding
10201 * which is Reserved on implementations without PXN.
10203 fi
->type
= ARMFault_Translation
;
10206 if ((type
== 1) || !(desc
& (1 << 18))) {
10207 /* Page or Section. */
10208 domain
= (desc
>> 5) & 0x0f;
10210 if (regime_el(env
, mmu_idx
) == 1) {
10211 dacr
= env
->cp15
.dacr_ns
;
10213 dacr
= env
->cp15
.dacr_s
;
10218 domain_prot
= (dacr
>> (domain
* 2)) & 3;
10219 if (domain_prot
== 0 || domain_prot
== 2) {
10220 /* Section or Page domain fault */
10221 fi
->type
= ARMFault_Domain
;
10225 if (desc
& (1 << 18)) {
10226 /* Supersection. */
10227 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
10228 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
10229 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
10230 *page_size
= 0x1000000;
10233 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
10234 *page_size
= 0x100000;
10236 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
10237 xn
= desc
& (1 << 4);
10239 ns
= extract32(desc
, 19, 1);
10241 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
10242 pxn
= (desc
>> 2) & 1;
10244 ns
= extract32(desc
, 3, 1);
10245 /* Lookup l2 entry. */
10246 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
10247 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
10249 if (fi
->type
!= ARMFault_None
) {
10252 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
10253 switch (desc
& 3) {
10254 case 0: /* Page translation fault. */
10255 fi
->type
= ARMFault_Translation
;
10257 case 1: /* 64k page. */
10258 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
10259 xn
= desc
& (1 << 15);
10260 *page_size
= 0x10000;
10262 case 2: case 3: /* 4k page. */
10263 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
10265 *page_size
= 0x1000;
10268 /* Never happens, but compiler isn't smart enough to tell. */
10272 if (domain_prot
== 3) {
10273 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
10275 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
10278 if (xn
&& access_type
== MMU_INST_FETCH
) {
10279 fi
->type
= ARMFault_Permission
;
10283 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
10284 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
10285 /* The simplified model uses AP[0] as an access control bit. */
10286 if ((ap
& 1) == 0) {
10287 /* Access flag fault. */
10288 fi
->type
= ARMFault_AccessFlag
;
10291 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
10293 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
10295 if (*prot
&& !xn
) {
10296 *prot
|= PAGE_EXEC
;
10298 if (!(*prot
& (1 << access_type
))) {
10299 /* Access permission fault. */
10300 fi
->type
= ARMFault_Permission
;
10305 /* The NS bit will (as required by the architecture) have no effect if
10306 * the CPU doesn't support TZ or this is a non-secure translation
10307 * regime, because the attribute will already be non-secure.
10309 attrs
->secure
= false;
10311 *phys_ptr
= phys_addr
;
10314 fi
->domain
= domain
;
10320 * check_s2_mmu_setup
10322 * @is_aa64: True if the translation regime is in AArch64 state
10323 * @startlevel: Suggested starting level
10324 * @inputsize: Bitsize of IPAs
10325 * @stride: Page-table stride (See the ARM ARM)
10327 * Returns true if the suggested S2 translation parameters are OK and
10330 static bool check_s2_mmu_setup(ARMCPU
*cpu
, bool is_aa64
, int level
,
10331 int inputsize
, int stride
)
10333 const int grainsize
= stride
+ 3;
10334 int startsizecheck
;
10336 /* Negative levels are never allowed. */
10341 startsizecheck
= inputsize
- ((3 - level
) * stride
+ grainsize
);
10342 if (startsizecheck
< 1 || startsizecheck
> stride
+ 4) {
10347 CPUARMState
*env
= &cpu
->env
;
10348 unsigned int pamax
= arm_pamax(cpu
);
10351 case 13: /* 64KB Pages. */
10352 if (level
== 0 || (level
== 1 && pamax
<= 42)) {
10356 case 11: /* 16KB Pages. */
10357 if (level
== 0 || (level
== 1 && pamax
<= 40)) {
10361 case 9: /* 4KB Pages. */
10362 if (level
== 0 && pamax
<= 42) {
10367 g_assert_not_reached();
10370 /* Inputsize checks. */
10371 if (inputsize
> pamax
&&
10372 (arm_el_is_aa64(env
, 1) || inputsize
> 40)) {
10373 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
10377 /* AArch32 only supports 4KB pages. Assert on that. */
10378 assert(stride
== 9);
10387 /* Translate from the 4-bit stage 2 representation of
10388 * memory attributes (without cache-allocation hints) to
10389 * the 8-bit representation of the stage 1 MAIR registers
10390 * (which includes allocation hints).
10392 * ref: shared/translation/attrs/S2AttrDecode()
10393 * .../S2ConvertAttrsHints()
10395 static uint8_t convert_stage2_attrs(CPUARMState
*env
, uint8_t s2attrs
)
10397 uint8_t hiattr
= extract32(s2attrs
, 2, 2);
10398 uint8_t loattr
= extract32(s2attrs
, 0, 2);
10399 uint8_t hihint
= 0, lohint
= 0;
10401 if (hiattr
!= 0) { /* normal memory */
10402 if ((env
->cp15
.hcr_el2
& HCR_CD
) != 0) { /* cache disabled */
10403 hiattr
= loattr
= 1; /* non-cacheable */
10405 if (hiattr
!= 1) { /* Write-through or write-back */
10406 hihint
= 3; /* RW allocate */
10408 if (loattr
!= 1) { /* Write-through or write-back */
10409 lohint
= 3; /* RW allocate */
10414 return (hiattr
<< 6) | (hihint
<< 4) | (loattr
<< 2) | lohint
;
10417 ARMVAParameters
aa64_va_parameters_both(CPUARMState
*env
, uint64_t va
,
10420 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
10421 uint32_t el
= regime_el(env
, mmu_idx
);
10422 bool tbi
, tbid
, epd
, hpd
, using16k
, using64k
;
10426 * Bit 55 is always between the two regions, and is canonical for
10427 * determining if address tagging is enabled.
10429 select
= extract64(va
, 55, 1);
10432 tsz
= extract32(tcr
, 0, 6);
10433 using64k
= extract32(tcr
, 14, 1);
10434 using16k
= extract32(tcr
, 15, 1);
10435 if (mmu_idx
== ARMMMUIdx_S2NS
) {
10437 tbi
= tbid
= hpd
= false;
10439 tbi
= extract32(tcr
, 20, 1);
10440 hpd
= extract32(tcr
, 24, 1);
10441 tbid
= extract32(tcr
, 29, 1);
10444 } else if (!select
) {
10445 tsz
= extract32(tcr
, 0, 6);
10446 epd
= extract32(tcr
, 7, 1);
10447 using64k
= extract32(tcr
, 14, 1);
10448 using16k
= extract32(tcr
, 15, 1);
10449 tbi
= extract64(tcr
, 37, 1);
10450 hpd
= extract64(tcr
, 41, 1);
10451 tbid
= extract64(tcr
, 51, 1);
10453 int tg
= extract32(tcr
, 30, 2);
10454 using16k
= tg
== 1;
10455 using64k
= tg
== 3;
10456 tsz
= extract32(tcr
, 16, 6);
10457 epd
= extract32(tcr
, 23, 1);
10458 tbi
= extract64(tcr
, 38, 1);
10459 hpd
= extract64(tcr
, 42, 1);
10460 tbid
= extract64(tcr
, 52, 1);
10462 tsz
= MIN(tsz
, 39); /* TODO: ARMv8.4-TTST */
10463 tsz
= MAX(tsz
, 16); /* TODO: ARMv8.2-LVA */
10465 return (ARMVAParameters
) {
10472 .using16k
= using16k
,
10473 .using64k
= using64k
,
10477 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
10478 ARMMMUIdx mmu_idx
, bool data
)
10480 ARMVAParameters ret
= aa64_va_parameters_both(env
, va
, mmu_idx
);
10482 /* Present TBI as a composite with TBID. */
10483 ret
.tbi
&= (data
|| !ret
.tbid
);
10487 static ARMVAParameters
aa32_va_parameters(CPUARMState
*env
, uint32_t va
,
10490 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
10491 uint32_t el
= regime_el(env
, mmu_idx
);
10495 if (mmu_idx
== ARMMMUIdx_S2NS
) {
10497 bool sext
= extract32(tcr
, 4, 1);
10498 bool sign
= extract32(tcr
, 3, 1);
10501 * If the sign-extend bit is not the same as t0sz[3], the result
10502 * is unpredictable. Flag this as a guest error.
10504 if (sign
!= sext
) {
10505 qemu_log_mask(LOG_GUEST_ERROR
,
10506 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
10508 tsz
= sextract32(tcr
, 0, 4) + 8;
10512 } else if (el
== 2) {
10514 tsz
= extract32(tcr
, 0, 3);
10516 hpd
= extract64(tcr
, 24, 1);
10519 int t0sz
= extract32(tcr
, 0, 3);
10520 int t1sz
= extract32(tcr
, 16, 3);
10523 select
= va
> (0xffffffffu
>> t0sz
);
10525 /* Note that we will detect errors later. */
10526 select
= va
>= ~(0xffffffffu
>> t1sz
);
10530 epd
= extract32(tcr
, 7, 1);
10531 hpd
= extract64(tcr
, 41, 1);
10534 epd
= extract32(tcr
, 23, 1);
10535 hpd
= extract64(tcr
, 42, 1);
10537 /* For aarch32, hpd0 is not enabled without t2e as well. */
10538 hpd
&= extract32(tcr
, 6, 1);
10541 return (ARMVAParameters
) {
10549 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
10550 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10551 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
10552 target_ulong
*page_size_ptr
,
10553 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
10555 ARMCPU
*cpu
= arm_env_get_cpu(env
);
10556 CPUState
*cs
= CPU(cpu
);
10557 /* Read an LPAE long-descriptor translation table. */
10558 ARMFaultType fault_type
= ARMFault_Translation
;
10560 ARMVAParameters param
;
10562 hwaddr descaddr
, indexmask
, indexmask_grainsize
;
10563 uint32_t tableattrs
;
10564 target_ulong page_size
;
10567 int addrsize
, inputsize
;
10568 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
10569 int ap
, ns
, xn
, pxn
;
10570 uint32_t el
= regime_el(env
, mmu_idx
);
10572 uint64_t descaddrmask
;
10573 bool aarch64
= arm_el_is_aa64(env
, el
);
10576 * This code does not handle the different format TCR for VTCR_EL2.
10577 * This code also does not support shareability levels.
10578 * Attribute and permission bit handling should also be checked when adding
10579 * support for those page table walks.
10582 param
= aa64_va_parameters(env
, address
, mmu_idx
,
10583 access_type
!= MMU_INST_FETCH
);
10585 /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
10588 ttbr1_valid
= (el
< 2);
10589 addrsize
= 64 - 8 * param
.tbi
;
10590 inputsize
= 64 - param
.tsz
;
10592 param
= aa32_va_parameters(env
, address
, mmu_idx
);
10594 /* There is no TTBR1 for EL2 */
10595 ttbr1_valid
= (el
!= 2);
10596 addrsize
= (mmu_idx
== ARMMMUIdx_S2NS
? 40 : 32);
10597 inputsize
= addrsize
- param
.tsz
;
10601 * We determined the region when collecting the parameters, but we
10602 * have not yet validated that the address is valid for the region.
10603 * Extract the top bits and verify that they all match select.
10605 * For aa32, if inputsize == addrsize, then we have selected the
10606 * region by exclusion in aa32_va_parameters and there is no more
10607 * validation to do here.
10609 if (inputsize
< addrsize
) {
10610 target_ulong top_bits
= sextract64(address
, inputsize
,
10611 addrsize
- inputsize
);
10612 if (-top_bits
!= param
.select
|| (param
.select
&& !ttbr1_valid
)) {
10613 /* The gap between the two regions is a Translation fault */
10614 fault_type
= ARMFault_Translation
;
10619 if (param
.using64k
) {
10621 } else if (param
.using16k
) {
10627 /* Note that QEMU ignores shareability and cacheability attributes,
10628 * so we don't need to do anything with the SH, ORGN, IRGN fields
10629 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
10630 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
10631 * implement any ASID-like capability so we can ignore it (instead
10632 * we will always flush the TLB any time the ASID is changed).
10634 ttbr
= regime_ttbr(env
, mmu_idx
, param
.select
);
10636 /* Here we should have set up all the parameters for the translation:
10637 * inputsize, ttbr, epd, stride, tbi
10641 /* Translation table walk disabled => Translation fault on TLB miss
10642 * Note: This is always 0 on 64-bit EL2 and EL3.
10647 if (mmu_idx
!= ARMMMUIdx_S2NS
) {
10648 /* The starting level depends on the virtual address size (which can
10649 * be up to 48 bits) and the translation granule size. It indicates
10650 * the number of strides (stride bits at a time) needed to
10651 * consume the bits of the input address. In the pseudocode this is:
10652 * level = 4 - RoundUp((inputsize - grainsize) / stride)
10653 * where their 'inputsize' is our 'inputsize', 'grainsize' is
10654 * our 'stride + 3' and 'stride' is our 'stride'.
10655 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
10656 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
10657 * = 4 - (inputsize - 4) / stride;
10659 level
= 4 - (inputsize
- 4) / stride
;
10661 /* For stage 2 translations the starting level is specified by the
10662 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
10664 uint32_t sl0
= extract32(tcr
->raw_tcr
, 6, 2);
10665 uint32_t startlevel
;
10668 if (!aarch64
|| stride
== 9) {
10669 /* AArch32 or 4KB pages */
10670 startlevel
= 2 - sl0
;
10672 /* 16KB or 64KB pages */
10673 startlevel
= 3 - sl0
;
10676 /* Check that the starting level is valid. */
10677 ok
= check_s2_mmu_setup(cpu
, aarch64
, startlevel
,
10678 inputsize
, stride
);
10680 fault_type
= ARMFault_Translation
;
10683 level
= startlevel
;
10686 indexmask_grainsize
= (1ULL << (stride
+ 3)) - 1;
10687 indexmask
= (1ULL << (inputsize
- (stride
* (4 - level
)))) - 1;
10689 /* Now we can extract the actual base address from the TTBR */
10690 descaddr
= extract64(ttbr
, 0, 48);
10691 descaddr
&= ~indexmask
;
10693 /* The address field in the descriptor goes up to bit 39 for ARMv7
10694 * but up to bit 47 for ARMv8, but we use the descaddrmask
10695 * up to bit 39 for AArch32, because we don't need other bits in that case
10696 * to construct next descriptor address (anyway they should be all zeroes).
10698 descaddrmask
= ((1ull << (aarch64
? 48 : 40)) - 1) &
10699 ~indexmask_grainsize
;
10701 /* Secure accesses start with the page table in secure memory and
10702 * can be downgraded to non-secure at any step. Non-secure accesses
10703 * remain non-secure. We implement this by just ORing in the NSTable/NS
10704 * bits at each step.
10706 tableattrs
= regime_is_secure(env
, mmu_idx
) ? 0 : (1 << 4);
10708 uint64_t descriptor
;
10711 descaddr
|= (address
>> (stride
* (4 - level
))) & indexmask
;
10713 nstable
= extract32(tableattrs
, 4, 1);
10714 descriptor
= arm_ldq_ptw(cs
, descaddr
, !nstable
, mmu_idx
, fi
);
10715 if (fi
->type
!= ARMFault_None
) {
10719 if (!(descriptor
& 1) ||
10720 (!(descriptor
& 2) && (level
== 3))) {
10721 /* Invalid, or the Reserved level 3 encoding */
10724 descaddr
= descriptor
& descaddrmask
;
10726 if ((descriptor
& 2) && (level
< 3)) {
10727 /* Table entry. The top five bits are attributes which may
10728 * propagate down through lower levels of the table (and
10729 * which are all arranged so that 0 means "no effect", so
10730 * we can gather them up by ORing in the bits at each level).
10732 tableattrs
|= extract64(descriptor
, 59, 5);
10734 indexmask
= indexmask_grainsize
;
10737 /* Block entry at level 1 or 2, or page entry at level 3.
10738 * These are basically the same thing, although the number
10739 * of bits we pull in from the vaddr varies.
10741 page_size
= (1ULL << ((stride
* (4 - level
)) + 3));
10742 descaddr
|= (address
& (page_size
- 1));
10743 /* Extract attributes from the descriptor */
10744 attrs
= extract64(descriptor
, 2, 10)
10745 | (extract64(descriptor
, 52, 12) << 10);
10747 if (mmu_idx
== ARMMMUIdx_S2NS
) {
10748 /* Stage 2 table descriptors do not include any attribute fields */
10751 /* Merge in attributes from table descriptors */
10752 attrs
|= nstable
<< 3; /* NS */
10754 /* HPD disables all the table attributes except NSTable. */
10757 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
10758 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
10759 * means "force PL1 access only", which means forcing AP[1] to 0.
10761 attrs
&= ~(extract32(tableattrs
, 2, 1) << 4); /* !APT[0] => AP[1] */
10762 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APT[1] => AP[2] */
10765 /* Here descaddr is the final physical address, and attributes
10766 * are all in attrs.
10768 fault_type
= ARMFault_AccessFlag
;
10769 if ((attrs
& (1 << 8)) == 0) {
10774 ap
= extract32(attrs
, 4, 2);
10775 xn
= extract32(attrs
, 12, 1);
10777 if (mmu_idx
== ARMMMUIdx_S2NS
) {
10779 *prot
= get_S2prot(env
, ap
, xn
);
10781 ns
= extract32(attrs
, 3, 1);
10782 pxn
= extract32(attrs
, 11, 1);
10783 *prot
= get_S1prot(env
, mmu_idx
, aarch64
, ap
, ns
, xn
, pxn
);
10786 fault_type
= ARMFault_Permission
;
10787 if (!(*prot
& (1 << access_type
))) {
10792 /* The NS bit will (as required by the architecture) have no effect if
10793 * the CPU doesn't support TZ or this is a non-secure translation
10794 * regime, because the attribute will already be non-secure.
10796 txattrs
->secure
= false;
10799 if (cacheattrs
!= NULL
) {
10800 if (mmu_idx
== ARMMMUIdx_S2NS
) {
10801 cacheattrs
->attrs
= convert_stage2_attrs(env
,
10802 extract32(attrs
, 0, 4));
10804 /* Index into MAIR registers for cache attributes */
10805 uint8_t attrindx
= extract32(attrs
, 0, 3);
10806 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
10807 assert(attrindx
<= 7);
10808 cacheattrs
->attrs
= extract64(mair
, attrindx
* 8, 8);
10810 cacheattrs
->shareability
= extract32(attrs
, 6, 2);
10813 *phys_ptr
= descaddr
;
10814 *page_size_ptr
= page_size
;
10818 fi
->type
= fault_type
;
10820 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
10821 fi
->stage2
= fi
->s1ptw
|| (mmu_idx
== ARMMMUIdx_S2NS
);
10825 static inline void get_phys_addr_pmsav7_default(CPUARMState
*env
,
10827 int32_t address
, int *prot
)
10829 if (!arm_feature(env
, ARM_FEATURE_M
)) {
10830 *prot
= PAGE_READ
| PAGE_WRITE
;
10832 case 0xF0000000 ... 0xFFFFFFFF:
10833 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) {
10834 /* hivecs execing is ok */
10835 *prot
|= PAGE_EXEC
;
10838 case 0x00000000 ... 0x7FFFFFFF:
10839 *prot
|= PAGE_EXEC
;
10843 /* Default system address map for M profile cores.
10844 * The architecture specifies which regions are execute-never;
10845 * at the MPU level no other checks are defined.
10848 case 0x00000000 ... 0x1fffffff: /* ROM */
10849 case 0x20000000 ... 0x3fffffff: /* SRAM */
10850 case 0x60000000 ... 0x7fffffff: /* RAM */
10851 case 0x80000000 ... 0x9fffffff: /* RAM */
10852 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
10854 case 0x40000000 ... 0x5fffffff: /* Peripheral */
10855 case 0xa0000000 ... 0xbfffffff: /* Device */
10856 case 0xc0000000 ... 0xdfffffff: /* Device */
10857 case 0xe0000000 ... 0xffffffff: /* System */
10858 *prot
= PAGE_READ
| PAGE_WRITE
;
10861 g_assert_not_reached();
10866 static bool pmsav7_use_background_region(ARMCPU
*cpu
,
10867 ARMMMUIdx mmu_idx
, bool is_user
)
10869 /* Return true if we should use the default memory map as a
10870 * "background" region if there are no hits against any MPU regions.
10872 CPUARMState
*env
= &cpu
->env
;
10878 if (arm_feature(env
, ARM_FEATURE_M
)) {
10879 return env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)]
10880 & R_V7M_MPU_CTRL_PRIVDEFENA_MASK
;
10882 return regime_sctlr(env
, mmu_idx
) & SCTLR_BR
;
10886 static inline bool m_is_ppb_region(CPUARMState
*env
, uint32_t address
)
10888 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
10889 return arm_feature(env
, ARM_FEATURE_M
) &&
10890 extract32(address
, 20, 12) == 0xe00;
10893 static inline bool m_is_system_region(CPUARMState
*env
, uint32_t address
)
10895 /* True if address is in the M profile system region
10896 * 0xe0000000 - 0xffffffff
10898 return arm_feature(env
, ARM_FEATURE_M
) && extract32(address
, 29, 3) == 0x7;
10901 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
10902 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10903 hwaddr
*phys_ptr
, int *prot
,
10904 target_ulong
*page_size
,
10905 ARMMMUFaultInfo
*fi
)
10907 ARMCPU
*cpu
= arm_env_get_cpu(env
);
10909 bool is_user
= regime_is_user(env
, mmu_idx
);
10911 *phys_ptr
= address
;
10912 *page_size
= TARGET_PAGE_SIZE
;
10915 if (regime_translation_disabled(env
, mmu_idx
) ||
10916 m_is_ppb_region(env
, address
)) {
10917 /* MPU disabled or M profile PPB access: use default memory map.
10918 * The other case which uses the default memory map in the
10919 * v7M ARM ARM pseudocode is exception vector reads from the vector
10920 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
10921 * which always does a direct read using address_space_ldl(), rather
10922 * than going via this function, so we don't need to check that here.
10924 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
10925 } else { /* MPU enabled */
10926 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
10927 /* region search */
10928 uint32_t base
= env
->pmsav7
.drbar
[n
];
10929 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
10931 bool srdis
= false;
10933 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
10938 qemu_log_mask(LOG_GUEST_ERROR
,
10939 "DRSR[%d]: Rsize field cannot be 0\n", n
);
10943 rmask
= (1ull << rsize
) - 1;
10945 if (base
& rmask
) {
10946 qemu_log_mask(LOG_GUEST_ERROR
,
10947 "DRBAR[%d]: 0x%" PRIx32
" misaligned "
10948 "to DRSR region size, mask = 0x%" PRIx32
"\n",
10953 if (address
< base
|| address
> base
+ rmask
) {
10955 * Address not in this region. We must check whether the
10956 * region covers addresses in the same page as our address.
10957 * In that case we must not report a size that covers the
10958 * whole page for a subsequent hit against a different MPU
10959 * region or the background region, because it would result in
10960 * incorrect TLB hits for subsequent accesses to addresses that
10961 * are in this MPU region.
10963 if (ranges_overlap(base
, rmask
,
10964 address
& TARGET_PAGE_MASK
,
10965 TARGET_PAGE_SIZE
)) {
10971 /* Region matched */
10973 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
10975 uint32_t srdis_mask
;
10977 rsize
-= 3; /* sub region size (power of 2) */
10978 snd
= ((address
- base
) >> rsize
) & 0x7;
10979 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
10981 srdis_mask
= srdis
? 0x3 : 0x0;
10982 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
10983 /* This will check in groups of 2, 4 and then 8, whether
10984 * the subregion bits are consistent. rsize is incremented
10985 * back up to give the region size, considering consistent
10986 * adjacent subregions as one region. Stop testing if rsize
10987 * is already big enough for an entire QEMU page.
10989 int snd_rounded
= snd
& ~(i
- 1);
10990 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
10991 snd_rounded
+ 8, i
);
10992 if (srdis_mask
^ srdis_multi
) {
10995 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
11002 if (rsize
< TARGET_PAGE_BITS
) {
11003 *page_size
= 1 << rsize
;
11008 if (n
== -1) { /* no hits */
11009 if (!pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
11010 /* background fault */
11011 fi
->type
= ARMFault_Background
;
11014 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
11015 } else { /* a MPU hit! */
11016 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
11017 uint32_t xn
= extract32(env
->pmsav7
.dracr
[n
], 12, 1);
11019 if (m_is_system_region(env
, address
)) {
11020 /* System space is always execute never */
11024 if (is_user
) { /* User mode AP bit decoding */
11029 break; /* no access */
11031 *prot
|= PAGE_WRITE
;
11035 *prot
|= PAGE_READ
| PAGE_EXEC
;
11038 /* for v7M, same as 6; for R profile a reserved value */
11039 if (arm_feature(env
, ARM_FEATURE_M
)) {
11040 *prot
|= PAGE_READ
| PAGE_EXEC
;
11045 qemu_log_mask(LOG_GUEST_ERROR
,
11046 "DRACR[%d]: Bad value for AP bits: 0x%"
11047 PRIx32
"\n", n
, ap
);
11049 } else { /* Priv. mode AP bits decoding */
11052 break; /* no access */
11056 *prot
|= PAGE_WRITE
;
11060 *prot
|= PAGE_READ
| PAGE_EXEC
;
11063 /* for v7M, same as 6; for R profile a reserved value */
11064 if (arm_feature(env
, ARM_FEATURE_M
)) {
11065 *prot
|= PAGE_READ
| PAGE_EXEC
;
11070 qemu_log_mask(LOG_GUEST_ERROR
,
11071 "DRACR[%d]: Bad value for AP bits: 0x%"
11072 PRIx32
"\n", n
, ap
);
11076 /* execute never */
11078 *prot
&= ~PAGE_EXEC
;
11083 fi
->type
= ARMFault_Permission
;
11085 return !(*prot
& (1 << access_type
));
11088 static bool v8m_is_sau_exempt(CPUARMState
*env
,
11089 uint32_t address
, MMUAccessType access_type
)
11091 /* The architecture specifies that certain address ranges are
11092 * exempt from v8M SAU/IDAU checks.
11095 (access_type
== MMU_INST_FETCH
&& m_is_system_region(env
, address
)) ||
11096 (address
>= 0xe0000000 && address
<= 0xe0002fff) ||
11097 (address
>= 0xe000e000 && address
<= 0xe000efff) ||
11098 (address
>= 0xe002e000 && address
<= 0xe002efff) ||
11099 (address
>= 0xe0040000 && address
<= 0xe0041fff) ||
11100 (address
>= 0xe00ff000 && address
<= 0xe00fffff);
11103 static void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
11104 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11105 V8M_SAttributes
*sattrs
)
11107 /* Look up the security attributes for this address. Compare the
11108 * pseudocode SecurityCheck() function.
11109 * We assume the caller has zero-initialized *sattrs.
11111 ARMCPU
*cpu
= arm_env_get_cpu(env
);
11113 bool idau_exempt
= false, idau_ns
= true, idau_nsc
= true;
11114 int idau_region
= IREGION_NOTVALID
;
11115 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
11116 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
11119 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_GET_CLASS(cpu
->idau
);
11120 IDAUInterface
*ii
= IDAU_INTERFACE(cpu
->idau
);
11122 iic
->check(ii
, address
, &idau_region
, &idau_exempt
, &idau_ns
,
11126 if (access_type
== MMU_INST_FETCH
&& extract32(address
, 28, 4) == 0xf) {
11127 /* 0xf0000000..0xffffffff is always S for insn fetches */
11131 if (idau_exempt
|| v8m_is_sau_exempt(env
, address
, access_type
)) {
11132 sattrs
->ns
= !regime_is_secure(env
, mmu_idx
);
11136 if (idau_region
!= IREGION_NOTVALID
) {
11137 sattrs
->irvalid
= true;
11138 sattrs
->iregion
= idau_region
;
11141 switch (env
->sau
.ctrl
& 3) {
11142 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
11144 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
11147 default: /* SAU.ENABLE == 1 */
11148 for (r
= 0; r
< cpu
->sau_sregion
; r
++) {
11149 if (env
->sau
.rlar
[r
] & 1) {
11150 uint32_t base
= env
->sau
.rbar
[r
] & ~0x1f;
11151 uint32_t limit
= env
->sau
.rlar
[r
] | 0x1f;
11153 if (base
<= address
&& limit
>= address
) {
11154 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
11155 sattrs
->subpage
= true;
11157 if (sattrs
->srvalid
) {
11158 /* If we hit in more than one region then we must report
11159 * as Secure, not NS-Callable, with no valid region
11162 sattrs
->ns
= false;
11163 sattrs
->nsc
= false;
11164 sattrs
->sregion
= 0;
11165 sattrs
->srvalid
= false;
11168 if (env
->sau
.rlar
[r
] & 2) {
11169 sattrs
->nsc
= true;
11173 sattrs
->srvalid
= true;
11174 sattrs
->sregion
= r
;
11178 * Address not in this region. We must check whether the
11179 * region covers addresses in the same page as our address.
11180 * In that case we must not report a size that covers the
11181 * whole page for a subsequent hit against a different MPU
11182 * region or the background region, because it would result
11183 * in incorrect TLB hits for subsequent accesses to
11184 * addresses that are in this MPU region.
11186 if (limit
>= base
&&
11187 ranges_overlap(base
, limit
- base
+ 1,
11189 TARGET_PAGE_SIZE
)) {
11190 sattrs
->subpage
= true;
11199 * The IDAU will override the SAU lookup results if it specifies
11200 * higher security than the SAU does.
11203 if (sattrs
->ns
|| (!idau_nsc
&& sattrs
->nsc
)) {
11204 sattrs
->ns
= false;
11205 sattrs
->nsc
= idau_nsc
;
11210 static bool pmsav8_mpu_lookup(CPUARMState
*env
, uint32_t address
,
11211 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11212 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
11213 int *prot
, bool *is_subpage
,
11214 ARMMMUFaultInfo
*fi
, uint32_t *mregion
)
11216 /* Perform a PMSAv8 MPU lookup (without also doing the SAU check
11217 * that a full phys-to-virt translation does).
11218 * mregion is (if not NULL) set to the region number which matched,
11219 * or -1 if no region number is returned (MPU off, address did not
11220 * hit a region, address hit in multiple regions).
11221 * We set is_subpage to true if the region hit doesn't cover the
11222 * entire TARGET_PAGE the address is within.
11224 ARMCPU
*cpu
= arm_env_get_cpu(env
);
11225 bool is_user
= regime_is_user(env
, mmu_idx
);
11226 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
11228 int matchregion
= -1;
11230 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
11231 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
11233 *is_subpage
= false;
11234 *phys_ptr
= address
;
11240 /* Unlike the ARM ARM pseudocode, we don't need to check whether this
11241 * was an exception vector read from the vector table (which is always
11242 * done using the default system address map), because those accesses
11243 * are done in arm_v7m_load_vector(), which always does a direct
11244 * read using address_space_ldl(), rather than going via this function.
11246 if (regime_translation_disabled(env
, mmu_idx
)) { /* MPU disabled */
11248 } else if (m_is_ppb_region(env
, address
)) {
11250 } else if (pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
11253 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
11254 /* region search */
11255 /* Note that the base address is bits [31:5] from the register
11256 * with bits [4:0] all zeroes, but the limit address is bits
11257 * [31:5] from the register with bits [4:0] all ones.
11259 uint32_t base
= env
->pmsav8
.rbar
[secure
][n
] & ~0x1f;
11260 uint32_t limit
= env
->pmsav8
.rlar
[secure
][n
] | 0x1f;
11262 if (!(env
->pmsav8
.rlar
[secure
][n
] & 0x1)) {
11263 /* Region disabled */
11267 if (address
< base
|| address
> limit
) {
11269 * Address not in this region. We must check whether the
11270 * region covers addresses in the same page as our address.
11271 * In that case we must not report a size that covers the
11272 * whole page for a subsequent hit against a different MPU
11273 * region or the background region, because it would result in
11274 * incorrect TLB hits for subsequent accesses to addresses that
11275 * are in this MPU region.
11277 if (limit
>= base
&&
11278 ranges_overlap(base
, limit
- base
+ 1,
11280 TARGET_PAGE_SIZE
)) {
11281 *is_subpage
= true;
11286 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
11287 *is_subpage
= true;
11291 /* Multiple regions match -- always a failure (unlike
11292 * PMSAv7 where highest-numbered-region wins)
11294 fi
->type
= ARMFault_Permission
;
11305 /* background fault */
11306 fi
->type
= ARMFault_Background
;
11310 if (matchregion
== -1) {
11311 /* hit using the background region */
11312 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
11314 uint32_t ap
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 1, 2);
11315 uint32_t xn
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 0, 1);
11317 if (m_is_system_region(env
, address
)) {
11318 /* System space is always execute never */
11322 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
);
11323 if (*prot
&& !xn
) {
11324 *prot
|= PAGE_EXEC
;
11326 /* We don't need to look the attribute up in the MAIR0/MAIR1
11327 * registers because that only tells us about cacheability.
11330 *mregion
= matchregion
;
11334 fi
->type
= ARMFault_Permission
;
11336 return !(*prot
& (1 << access_type
));
11340 static bool get_phys_addr_pmsav8(CPUARMState
*env
, uint32_t address
,
11341 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11342 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
11343 int *prot
, target_ulong
*page_size
,
11344 ARMMMUFaultInfo
*fi
)
11346 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
11347 V8M_SAttributes sattrs
= {};
11349 bool mpu_is_subpage
;
11351 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
11352 v8m_security_lookup(env
, address
, access_type
, mmu_idx
, &sattrs
);
11353 if (access_type
== MMU_INST_FETCH
) {
11354 /* Instruction fetches always use the MMU bank and the
11355 * transaction attribute determined by the fetch address,
11356 * regardless of CPU state. This is painful for QEMU
11357 * to handle, because it would mean we need to encode
11358 * into the mmu_idx not just the (user, negpri) information
11359 * for the current security state but also that for the
11360 * other security state, which would balloon the number
11361 * of mmu_idx values needed alarmingly.
11362 * Fortunately we can avoid this because it's not actually
11363 * possible to arbitrarily execute code from memory with
11364 * the wrong security attribute: it will always generate
11365 * an exception of some kind or another, apart from the
11366 * special case of an NS CPU executing an SG instruction
11367 * in S&NSC memory. So we always just fail the translation
11368 * here and sort things out in the exception handler
11369 * (including possibly emulating an SG instruction).
11371 if (sattrs
.ns
!= !secure
) {
11373 fi
->type
= ARMFault_QEMU_NSCExec
;
11375 fi
->type
= ARMFault_QEMU_SFault
;
11377 *page_size
= sattrs
.subpage
? 1 : TARGET_PAGE_SIZE
;
11378 *phys_ptr
= address
;
11383 /* For data accesses we always use the MMU bank indicated
11384 * by the current CPU state, but the security attributes
11385 * might downgrade a secure access to nonsecure.
11388 txattrs
->secure
= false;
11389 } else if (!secure
) {
11390 /* NS access to S memory must fault.
11391 * Architecturally we should first check whether the
11392 * MPU information for this address indicates that we
11393 * are doing an unaligned access to Device memory, which
11394 * should generate a UsageFault instead. QEMU does not
11395 * currently check for that kind of unaligned access though.
11396 * If we added it we would need to do so as a special case
11397 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
11399 fi
->type
= ARMFault_QEMU_SFault
;
11400 *page_size
= sattrs
.subpage
? 1 : TARGET_PAGE_SIZE
;
11401 *phys_ptr
= address
;
11408 ret
= pmsav8_mpu_lookup(env
, address
, access_type
, mmu_idx
, phys_ptr
,
11409 txattrs
, prot
, &mpu_is_subpage
, fi
, NULL
);
11410 *page_size
= sattrs
.subpage
|| mpu_is_subpage
? 1 : TARGET_PAGE_SIZE
;
11414 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
11415 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11416 hwaddr
*phys_ptr
, int *prot
,
11417 ARMMMUFaultInfo
*fi
)
11422 bool is_user
= regime_is_user(env
, mmu_idx
);
11424 if (regime_translation_disabled(env
, mmu_idx
)) {
11425 /* MPU disabled. */
11426 *phys_ptr
= address
;
11427 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
11431 *phys_ptr
= address
;
11432 for (n
= 7; n
>= 0; n
--) {
11433 base
= env
->cp15
.c6_region
[n
];
11434 if ((base
& 1) == 0) {
11437 mask
= 1 << ((base
>> 1) & 0x1f);
11438 /* Keep this shift separate from the above to avoid an
11439 (undefined) << 32. */
11440 mask
= (mask
<< 1) - 1;
11441 if (((base
^ address
) & ~mask
) == 0) {
11446 fi
->type
= ARMFault_Background
;
11450 if (access_type
== MMU_INST_FETCH
) {
11451 mask
= env
->cp15
.pmsav5_insn_ap
;
11453 mask
= env
->cp15
.pmsav5_data_ap
;
11455 mask
= (mask
>> (n
* 4)) & 0xf;
11458 fi
->type
= ARMFault_Permission
;
11463 fi
->type
= ARMFault_Permission
;
11467 *prot
= PAGE_READ
| PAGE_WRITE
;
11472 *prot
|= PAGE_WRITE
;
11476 *prot
= PAGE_READ
| PAGE_WRITE
;
11480 fi
->type
= ARMFault_Permission
;
11490 /* Bad permission. */
11491 fi
->type
= ARMFault_Permission
;
11495 *prot
|= PAGE_EXEC
;
11499 /* Combine either inner or outer cacheability attributes for normal
11500 * memory, according to table D4-42 and pseudocode procedure
11501 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
11503 * NB: only stage 1 includes allocation hints (RW bits), leading to
11506 static uint8_t combine_cacheattr_nibble(uint8_t s1
, uint8_t s2
)
11508 if (s1
== 4 || s2
== 4) {
11509 /* non-cacheable has precedence */
11511 } else if (extract32(s1
, 2, 2) == 0 || extract32(s1
, 2, 2) == 2) {
11512 /* stage 1 write-through takes precedence */
11514 } else if (extract32(s2
, 2, 2) == 2) {
11515 /* stage 2 write-through takes precedence, but the allocation hint
11516 * is still taken from stage 1
11518 return (2 << 2) | extract32(s1
, 0, 2);
11519 } else { /* write-back */
11524 /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
11525 * and CombineS1S2Desc()
11527 * @s1: Attributes from stage 1 walk
11528 * @s2: Attributes from stage 2 walk
11530 static ARMCacheAttrs
combine_cacheattrs(ARMCacheAttrs s1
, ARMCacheAttrs s2
)
11532 uint8_t s1lo
= extract32(s1
.attrs
, 0, 4), s2lo
= extract32(s2
.attrs
, 0, 4);
11533 uint8_t s1hi
= extract32(s1
.attrs
, 4, 4), s2hi
= extract32(s2
.attrs
, 4, 4);
11536 /* Combine shareability attributes (table D4-43) */
11537 if (s1
.shareability
== 2 || s2
.shareability
== 2) {
11538 /* if either are outer-shareable, the result is outer-shareable */
11539 ret
.shareability
= 2;
11540 } else if (s1
.shareability
== 3 || s2
.shareability
== 3) {
11541 /* if either are inner-shareable, the result is inner-shareable */
11542 ret
.shareability
= 3;
11544 /* both non-shareable */
11545 ret
.shareability
= 0;
11548 /* Combine memory type and cacheability attributes */
11549 if (s1hi
== 0 || s2hi
== 0) {
11550 /* Device has precedence over normal */
11551 if (s1lo
== 0 || s2lo
== 0) {
11552 /* nGnRnE has precedence over anything */
11554 } else if (s1lo
== 4 || s2lo
== 4) {
11555 /* non-Reordering has precedence over Reordering */
11556 ret
.attrs
= 4; /* nGnRE */
11557 } else if (s1lo
== 8 || s2lo
== 8) {
11558 /* non-Gathering has precedence over Gathering */
11559 ret
.attrs
= 8; /* nGRE */
11561 ret
.attrs
= 0xc; /* GRE */
11564 /* Any location for which the resultant memory type is any
11565 * type of Device memory is always treated as Outer Shareable.
11567 ret
.shareability
= 2;
11568 } else { /* Normal memory */
11569 /* Outer/inner cacheability combine independently */
11570 ret
.attrs
= combine_cacheattr_nibble(s1hi
, s2hi
) << 4
11571 | combine_cacheattr_nibble(s1lo
, s2lo
);
11573 if (ret
.attrs
== 0x44) {
11574 /* Any location for which the resultant memory type is Normal
11575 * Inner Non-cacheable, Outer Non-cacheable is always treated
11576 * as Outer Shareable.
11578 ret
.shareability
= 2;
11586 /* get_phys_addr - get the physical address for this virtual address
11588 * Find the physical address corresponding to the given virtual address,
11589 * by doing a translation table walk on MMU based systems or using the
11590 * MPU state on MPU based systems.
11592 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
11593 * prot and page_size may not be filled in, and the populated fsr value provides
11594 * information on why the translation aborted, in the format of a
11595 * DFSR/IFSR fault register, with the following caveats:
11596 * * we honour the short vs long DFSR format differences.
11597 * * the WnR bit is never set (the caller must do this).
11598 * * for PSMAv5 based systems we don't bother to return a full FSR format
11601 * @env: CPUARMState
11602 * @address: virtual address to get physical address for
11603 * @access_type: 0 for read, 1 for write, 2 for execute
11604 * @mmu_idx: MMU index indicating required translation regime
11605 * @phys_ptr: set to the physical address corresponding to the virtual address
11606 * @attrs: set to the memory transaction attributes to use
11607 * @prot: set to the permissions for the page containing phys_ptr
11608 * @page_size: set to the size of the page containing phys_ptr
11609 * @fi: set to fault info if the translation fails
11610 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
11612 static bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
11613 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11614 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
11615 target_ulong
*page_size
,
11616 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
11618 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
11619 /* Call ourselves recursively to do the stage 1 and then stage 2
11622 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
11626 ARMCacheAttrs cacheattrs2
= {};
11628 ret
= get_phys_addr(env
, address
, access_type
,
11629 stage_1_mmu_idx(mmu_idx
), &ipa
, attrs
,
11630 prot
, page_size
, fi
, cacheattrs
);
11632 /* If S1 fails or S2 is disabled, return early. */
11633 if (ret
|| regime_translation_disabled(env
, ARMMMUIdx_S2NS
)) {
11638 /* S1 is done. Now do S2 translation. */
11639 ret
= get_phys_addr_lpae(env
, ipa
, access_type
, ARMMMUIdx_S2NS
,
11640 phys_ptr
, attrs
, &s2_prot
,
11642 cacheattrs
!= NULL
? &cacheattrs2
: NULL
);
11644 /* Combine the S1 and S2 perms. */
11647 /* Combine the S1 and S2 cache attributes, if needed */
11648 if (!ret
&& cacheattrs
!= NULL
) {
11649 if (env
->cp15
.hcr_el2
& HCR_DC
) {
11651 * HCR.DC forces the first stage attributes to
11652 * Normal Non-Shareable,
11653 * Inner Write-Back Read-Allocate Write-Allocate,
11654 * Outer Write-Back Read-Allocate Write-Allocate.
11656 cacheattrs
->attrs
= 0xff;
11657 cacheattrs
->shareability
= 0;
11659 *cacheattrs
= combine_cacheattrs(*cacheattrs
, cacheattrs2
);
11665 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
11667 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
11671 /* The page table entries may downgrade secure to non-secure, but
11672 * cannot upgrade an non-secure translation regime's attributes
11675 attrs
->secure
= regime_is_secure(env
, mmu_idx
);
11676 attrs
->user
= regime_is_user(env
, mmu_idx
);
11678 /* Fast Context Switch Extension. This doesn't exist at all in v8.
11679 * In v7 and earlier it affects all stage 1 translations.
11681 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_S2NS
11682 && !arm_feature(env
, ARM_FEATURE_V8
)) {
11683 if (regime_el(env
, mmu_idx
) == 3) {
11684 address
+= env
->cp15
.fcseidr_s
;
11686 address
+= env
->cp15
.fcseidr_ns
;
11690 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
11692 *page_size
= TARGET_PAGE_SIZE
;
11694 if (arm_feature(env
, ARM_FEATURE_V8
)) {
11696 ret
= get_phys_addr_pmsav8(env
, address
, access_type
, mmu_idx
,
11697 phys_ptr
, attrs
, prot
, page_size
, fi
);
11698 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
11700 ret
= get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
11701 phys_ptr
, prot
, page_size
, fi
);
11704 ret
= get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
11705 phys_ptr
, prot
, fi
);
11707 qemu_log_mask(CPU_LOG_MMU
, "PMSA MPU lookup for %s at 0x%08" PRIx32
11708 " mmu_idx %u -> %s (prot %c%c%c)\n",
11709 access_type
== MMU_DATA_LOAD
? "reading" :
11710 (access_type
== MMU_DATA_STORE
? "writing" : "execute"),
11711 (uint32_t)address
, mmu_idx
,
11712 ret
? "Miss" : "Hit",
11713 *prot
& PAGE_READ
? 'r' : '-',
11714 *prot
& PAGE_WRITE
? 'w' : '-',
11715 *prot
& PAGE_EXEC
? 'x' : '-');
11720 /* Definitely a real MMU, not an MPU */
11722 if (regime_translation_disabled(env
, mmu_idx
)) {
11723 /* MMU disabled. */
11724 *phys_ptr
= address
;
11725 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
11726 *page_size
= TARGET_PAGE_SIZE
;
11730 if (regime_using_lpae_format(env
, mmu_idx
)) {
11731 return get_phys_addr_lpae(env
, address
, access_type
, mmu_idx
,
11732 phys_ptr
, attrs
, prot
, page_size
,
11734 } else if (regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
11735 return get_phys_addr_v6(env
, address
, access_type
, mmu_idx
,
11736 phys_ptr
, attrs
, prot
, page_size
, fi
);
11738 return get_phys_addr_v5(env
, address
, access_type
, mmu_idx
,
11739 phys_ptr
, prot
, page_size
, fi
);
11743 /* Walk the page table and (if the mapping exists) add the page
11744 * to the TLB. Return false on success, or true on failure. Populate
11745 * fsr with ARM DFSR/IFSR fault register format value on failure.
11747 bool arm_tlb_fill(CPUState
*cs
, vaddr address
,
11748 MMUAccessType access_type
, int mmu_idx
,
11749 ARMMMUFaultInfo
*fi
)
11751 ARMCPU
*cpu
= ARM_CPU(cs
);
11752 CPUARMState
*env
= &cpu
->env
;
11754 target_ulong page_size
;
11757 MemTxAttrs attrs
= {};
11759 ret
= get_phys_addr(env
, address
, access_type
,
11760 core_to_arm_mmu_idx(env
, mmu_idx
), &phys_addr
,
11761 &attrs
, &prot
, &page_size
, fi
, NULL
);
11764 * Map a single [sub]page. Regions smaller than our declared
11765 * target page size are handled specially, so for those we
11766 * pass in the exact addresses.
11768 if (page_size
>= TARGET_PAGE_SIZE
) {
11769 phys_addr
&= TARGET_PAGE_MASK
;
11770 address
&= TARGET_PAGE_MASK
;
11772 tlb_set_page_with_attrs(cs
, address
, phys_addr
, attrs
,
11773 prot
, mmu_idx
, page_size
);
11780 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cs
, vaddr addr
,
11783 ARMCPU
*cpu
= ARM_CPU(cs
);
11784 CPUARMState
*env
= &cpu
->env
;
11786 target_ulong page_size
;
11789 ARMMMUFaultInfo fi
= {};
11790 ARMMMUIdx mmu_idx
= arm_mmu_idx(env
);
11792 *attrs
= (MemTxAttrs
) {};
11794 ret
= get_phys_addr(env
, addr
, 0, mmu_idx
, &phys_addr
,
11795 attrs
, &prot
, &page_size
, &fi
, NULL
);
11803 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
11806 unsigned el
= arm_current_el(env
);
11808 /* First handle registers which unprivileged can read */
11811 case 0 ... 7: /* xPSR sub-fields */
11813 if ((reg
& 1) && el
) {
11814 mask
|= XPSR_EXCP
; /* IPSR (unpriv. reads as zero) */
11817 mask
|= XPSR_NZCV
| XPSR_Q
; /* APSR */
11819 /* EPSR reads as zero */
11820 return xpsr_read(env
) & mask
;
11822 case 20: /* CONTROL */
11823 return env
->v7m
.control
[env
->v7m
.secure
];
11824 case 0x94: /* CONTROL_NS */
11825 /* We have to handle this here because unprivileged Secure code
11826 * can read the NS CONTROL register.
11828 if (!env
->v7m
.secure
) {
11831 return env
->v7m
.control
[M_REG_NS
];
11835 return 0; /* unprivileged reads others as zero */
11838 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
11840 case 0x88: /* MSP_NS */
11841 if (!env
->v7m
.secure
) {
11844 return env
->v7m
.other_ss_msp
;
11845 case 0x89: /* PSP_NS */
11846 if (!env
->v7m
.secure
) {
11849 return env
->v7m
.other_ss_psp
;
11850 case 0x8a: /* MSPLIM_NS */
11851 if (!env
->v7m
.secure
) {
11854 return env
->v7m
.msplim
[M_REG_NS
];
11855 case 0x8b: /* PSPLIM_NS */
11856 if (!env
->v7m
.secure
) {
11859 return env
->v7m
.psplim
[M_REG_NS
];
11860 case 0x90: /* PRIMASK_NS */
11861 if (!env
->v7m
.secure
) {
11864 return env
->v7m
.primask
[M_REG_NS
];
11865 case 0x91: /* BASEPRI_NS */
11866 if (!env
->v7m
.secure
) {
11869 return env
->v7m
.basepri
[M_REG_NS
];
11870 case 0x93: /* FAULTMASK_NS */
11871 if (!env
->v7m
.secure
) {
11874 return env
->v7m
.faultmask
[M_REG_NS
];
11875 case 0x98: /* SP_NS */
11877 /* This gives the non-secure SP selected based on whether we're
11878 * currently in handler mode or not, using the NS CONTROL.SPSEL.
11880 bool spsel
= env
->v7m
.control
[M_REG_NS
] & R_V7M_CONTROL_SPSEL_MASK
;
11882 if (!env
->v7m
.secure
) {
11885 if (!arm_v7m_is_handler_mode(env
) && spsel
) {
11886 return env
->v7m
.other_ss_psp
;
11888 return env
->v7m
.other_ss_msp
;
11898 return v7m_using_psp(env
) ? env
->v7m
.other_sp
: env
->regs
[13];
11900 return v7m_using_psp(env
) ? env
->regs
[13] : env
->v7m
.other_sp
;
11901 case 10: /* MSPLIM */
11902 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
11905 return env
->v7m
.msplim
[env
->v7m
.secure
];
11906 case 11: /* PSPLIM */
11907 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
11910 return env
->v7m
.psplim
[env
->v7m
.secure
];
11911 case 16: /* PRIMASK */
11912 return env
->v7m
.primask
[env
->v7m
.secure
];
11913 case 17: /* BASEPRI */
11914 case 18: /* BASEPRI_MAX */
11915 return env
->v7m
.basepri
[env
->v7m
.secure
];
11916 case 19: /* FAULTMASK */
11917 return env
->v7m
.faultmask
[env
->v7m
.secure
];
11920 qemu_log_mask(LOG_GUEST_ERROR
, "Attempt to read unknown special"
11921 " register %d\n", reg
);
11926 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t maskreg
, uint32_t val
)
11928 /* We're passed bits [11..0] of the instruction; extract
11929 * SYSm and the mask bits.
11930 * Invalid combinations of SYSm and mask are UNPREDICTABLE;
11931 * we choose to treat them as if the mask bits were valid.
11932 * NB that the pseudocode 'mask' variable is bits [11..10],
11933 * whereas ours is [11..8].
11935 uint32_t mask
= extract32(maskreg
, 8, 4);
11936 uint32_t reg
= extract32(maskreg
, 0, 8);
11938 if (arm_current_el(env
) == 0 && reg
> 7) {
11939 /* only xPSR sub-fields may be written by unprivileged */
11943 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
11945 case 0x88: /* MSP_NS */
11946 if (!env
->v7m
.secure
) {
11949 env
->v7m
.other_ss_msp
= val
;
11951 case 0x89: /* PSP_NS */
11952 if (!env
->v7m
.secure
) {
11955 env
->v7m
.other_ss_psp
= val
;
11957 case 0x8a: /* MSPLIM_NS */
11958 if (!env
->v7m
.secure
) {
11961 env
->v7m
.msplim
[M_REG_NS
] = val
& ~7;
11963 case 0x8b: /* PSPLIM_NS */
11964 if (!env
->v7m
.secure
) {
11967 env
->v7m
.psplim
[M_REG_NS
] = val
& ~7;
11969 case 0x90: /* PRIMASK_NS */
11970 if (!env
->v7m
.secure
) {
11973 env
->v7m
.primask
[M_REG_NS
] = val
& 1;
11975 case 0x91: /* BASEPRI_NS */
11976 if (!env
->v7m
.secure
|| !arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
11979 env
->v7m
.basepri
[M_REG_NS
] = val
& 0xff;
11981 case 0x93: /* FAULTMASK_NS */
11982 if (!env
->v7m
.secure
|| !arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
11985 env
->v7m
.faultmask
[M_REG_NS
] = val
& 1;
11987 case 0x94: /* CONTROL_NS */
11988 if (!env
->v7m
.secure
) {
11991 write_v7m_control_spsel_for_secstate(env
,
11992 val
& R_V7M_CONTROL_SPSEL_MASK
,
11994 if (arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
11995 env
->v7m
.control
[M_REG_NS
] &= ~R_V7M_CONTROL_NPRIV_MASK
;
11996 env
->v7m
.control
[M_REG_NS
] |= val
& R_V7M_CONTROL_NPRIV_MASK
;
11999 case 0x98: /* SP_NS */
12001 /* This gives the non-secure SP selected based on whether we're
12002 * currently in handler mode or not, using the NS CONTROL.SPSEL.
12004 bool spsel
= env
->v7m
.control
[M_REG_NS
] & R_V7M_CONTROL_SPSEL_MASK
;
12005 bool is_psp
= !arm_v7m_is_handler_mode(env
) && spsel
;
12008 if (!env
->v7m
.secure
) {
12012 limit
= is_psp
? env
->v7m
.psplim
[false] : env
->v7m
.msplim
[false];
12015 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
12017 cpu_restore_state(cs
, GETPC(), true);
12018 raise_exception(env
, EXCP_STKOF
, 0, 1);
12022 env
->v7m
.other_ss_psp
= val
;
12024 env
->v7m
.other_ss_msp
= val
;
12034 case 0 ... 7: /* xPSR sub-fields */
12035 /* only APSR is actually writable */
12037 uint32_t apsrmask
= 0;
12040 apsrmask
|= XPSR_NZCV
| XPSR_Q
;
12042 if ((mask
& 4) && arm_feature(env
, ARM_FEATURE_THUMB_DSP
)) {
12043 apsrmask
|= XPSR_GE
;
12045 xpsr_write(env
, val
, apsrmask
);
12049 if (v7m_using_psp(env
)) {
12050 env
->v7m
.other_sp
= val
;
12052 env
->regs
[13] = val
;
12056 if (v7m_using_psp(env
)) {
12057 env
->regs
[13] = val
;
12059 env
->v7m
.other_sp
= val
;
12062 case 10: /* MSPLIM */
12063 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
12066 env
->v7m
.msplim
[env
->v7m
.secure
] = val
& ~7;
12068 case 11: /* PSPLIM */
12069 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
12072 env
->v7m
.psplim
[env
->v7m
.secure
] = val
& ~7;
12074 case 16: /* PRIMASK */
12075 env
->v7m
.primask
[env
->v7m
.secure
] = val
& 1;
12077 case 17: /* BASEPRI */
12078 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
12081 env
->v7m
.basepri
[env
->v7m
.secure
] = val
& 0xff;
12083 case 18: /* BASEPRI_MAX */
12084 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
12088 if (val
!= 0 && (val
< env
->v7m
.basepri
[env
->v7m
.secure
]
12089 || env
->v7m
.basepri
[env
->v7m
.secure
] == 0)) {
12090 env
->v7m
.basepri
[env
->v7m
.secure
] = val
;
12093 case 19: /* FAULTMASK */
12094 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
12097 env
->v7m
.faultmask
[env
->v7m
.secure
] = val
& 1;
12099 case 20: /* CONTROL */
12100 /* Writing to the SPSEL bit only has an effect if we are in
12101 * thread mode; other bits can be updated by any privileged code.
12102 * write_v7m_control_spsel() deals with updating the SPSEL bit in
12103 * env->v7m.control, so we only need update the others.
12104 * For v7M, we must just ignore explicit writes to SPSEL in handler
12105 * mode; for v8M the write is permitted but will have no effect.
12107 if (arm_feature(env
, ARM_FEATURE_V8
) ||
12108 !arm_v7m_is_handler_mode(env
)) {
12109 write_v7m_control_spsel(env
, (val
& R_V7M_CONTROL_SPSEL_MASK
) != 0);
12111 if (arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
12112 env
->v7m
.control
[env
->v7m
.secure
] &= ~R_V7M_CONTROL_NPRIV_MASK
;
12113 env
->v7m
.control
[env
->v7m
.secure
] |= val
& R_V7M_CONTROL_NPRIV_MASK
;
12118 qemu_log_mask(LOG_GUEST_ERROR
, "Attempt to write unknown special"
12119 " register %d\n", reg
);
12124 uint32_t HELPER(v7m_tt
)(CPUARMState
*env
, uint32_t addr
, uint32_t op
)
12126 /* Implement the TT instruction. op is bits [7:6] of the insn. */
12127 bool forceunpriv
= op
& 1;
12129 V8M_SAttributes sattrs
= {};
12131 bool r
, rw
, nsr
, nsrw
, mrvalid
;
12133 ARMMMUFaultInfo fi
= {};
12134 MemTxAttrs attrs
= {};
12139 bool targetsec
= env
->v7m
.secure
;
12142 /* Work out what the security state and privilege level we're
12143 * interested in is...
12146 targetsec
= !targetsec
;
12150 targetpriv
= false;
12152 targetpriv
= arm_v7m_is_handler_mode(env
) ||
12153 !(env
->v7m
.control
[targetsec
] & R_V7M_CONTROL_NPRIV_MASK
);
12156 /* ...and then figure out which MMU index this is */
12157 mmu_idx
= arm_v7m_mmu_idx_for_secstate_and_priv(env
, targetsec
, targetpriv
);
12159 /* We know that the MPU and SAU don't care about the access type
12160 * for our purposes beyond that we don't want to claim to be
12161 * an insn fetch, so we arbitrarily call this a read.
12164 /* MPU region info only available for privileged or if
12165 * inspecting the other MPU state.
12167 if (arm_current_el(env
) != 0 || alt
) {
12168 /* We can ignore the return value as prot is always set */
12169 pmsav8_mpu_lookup(env
, addr
, MMU_DATA_LOAD
, mmu_idx
,
12170 &phys_addr
, &attrs
, &prot
, &is_subpage
,
12172 if (mregion
== -1) {
12178 r
= prot
& PAGE_READ
;
12179 rw
= prot
& PAGE_WRITE
;
12187 if (env
->v7m
.secure
) {
12188 v8m_security_lookup(env
, addr
, MMU_DATA_LOAD
, mmu_idx
, &sattrs
);
12189 nsr
= sattrs
.ns
&& r
;
12190 nsrw
= sattrs
.ns
&& rw
;
12197 tt_resp
= (sattrs
.iregion
<< 24) |
12198 (sattrs
.irvalid
<< 23) |
12199 ((!sattrs
.ns
) << 22) |
12204 (sattrs
.srvalid
<< 17) |
12206 (sattrs
.sregion
<< 8) |
12214 void HELPER(dc_zva
)(CPUARMState
*env
, uint64_t vaddr_in
)
12216 /* Implement DC ZVA, which zeroes a fixed-length block of memory.
12217 * Note that we do not implement the (architecturally mandated)
12218 * alignment fault for attempts to use this on Device memory
12219 * (which matches the usual QEMU behaviour of not implementing either
12220 * alignment faults or any memory attribute handling).
12223 ARMCPU
*cpu
= arm_env_get_cpu(env
);
12224 uint64_t blocklen
= 4 << cpu
->dcz_blocksize
;
12225 uint64_t vaddr
= vaddr_in
& ~(blocklen
- 1);
12227 #ifndef CONFIG_USER_ONLY
12229 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
12230 * the block size so we might have to do more than one TLB lookup.
12231 * We know that in fact for any v8 CPU the page size is at least 4K
12232 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
12233 * 1K as an artefact of legacy v5 subpage support being present in the
12234 * same QEMU executable.
12236 int maxidx
= DIV_ROUND_UP(blocklen
, TARGET_PAGE_SIZE
);
12237 void *hostaddr
[maxidx
];
12239 unsigned mmu_idx
= cpu_mmu_index(env
, false);
12240 TCGMemOpIdx oi
= make_memop_idx(MO_UB
, mmu_idx
);
12242 for (try = 0; try < 2; try++) {
12244 for (i
= 0; i
< maxidx
; i
++) {
12245 hostaddr
[i
] = tlb_vaddr_to_host(env
,
12246 vaddr
+ TARGET_PAGE_SIZE
* i
,
12248 if (!hostaddr
[i
]) {
12253 /* If it's all in the TLB it's fair game for just writing to;
12254 * we know we don't need to update dirty status, etc.
12256 for (i
= 0; i
< maxidx
- 1; i
++) {
12257 memset(hostaddr
[i
], 0, TARGET_PAGE_SIZE
);
12259 memset(hostaddr
[i
], 0, blocklen
- (i
* TARGET_PAGE_SIZE
));
12262 /* OK, try a store and see if we can populate the tlb. This
12263 * might cause an exception if the memory isn't writable,
12264 * in which case we will longjmp out of here. We must for
12265 * this purpose use the actual register value passed to us
12266 * so that we get the fault address right.
12268 helper_ret_stb_mmu(env
, vaddr_in
, 0, oi
, GETPC());
12269 /* Now we can populate the other TLB entries, if any */
12270 for (i
= 0; i
< maxidx
; i
++) {
12271 uint64_t va
= vaddr
+ TARGET_PAGE_SIZE
* i
;
12272 if (va
!= (vaddr_in
& TARGET_PAGE_MASK
)) {
12273 helper_ret_stb_mmu(env
, va
, 0, oi
, GETPC());
12278 /* Slow path (probably attempt to do this to an I/O device or
12279 * similar, or clearing of a block of code we have translations
12280 * cached for). Just do a series of byte writes as the architecture
12281 * demands. It's not worth trying to use a cpu_physical_memory_map(),
12282 * memset(), unmap() sequence here because:
12283 * + we'd need to account for the blocksize being larger than a page
12284 * + the direct-RAM access case is almost always going to be dealt
12285 * with in the fastpath code above, so there's no speed benefit
12286 * + we would have to deal with the map returning NULL because the
12287 * bounce buffer was in use
12289 for (i
= 0; i
< blocklen
; i
++) {
12290 helper_ret_stb_mmu(env
, vaddr
+ i
, 0, oi
, GETPC());
12294 memset(g2h(vaddr
), 0, blocklen
);
12298 /* Note that signed overflow is undefined in C. The following routines are
12299 careful to use unsigned types where modulo arithmetic is required.
12300 Failure to do so _will_ break on newer gcc. */
12302 /* Signed saturating arithmetic. */
12304 /* Perform 16-bit signed saturating addition. */
12305 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
12310 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
12319 /* Perform 8-bit signed saturating addition. */
12320 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
12325 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
12334 /* Perform 16-bit signed saturating subtraction. */
12335 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
12340 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
12349 /* Perform 8-bit signed saturating subtraction. */
12350 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
12355 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
12364 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
12365 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
12366 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
12367 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
12370 #include "op_addsub.h"
12372 /* Unsigned saturating arithmetic. */
12373 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
12382 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
12390 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
12399 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
12407 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
12408 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
12409 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
12410 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
12413 #include "op_addsub.h"
12415 /* Signed modulo arithmetic. */
12416 #define SARITH16(a, b, n, op) do { \
12418 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
12419 RESULT(sum, n, 16); \
12421 ge |= 3 << (n * 2); \
12424 #define SARITH8(a, b, n, op) do { \
12426 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
12427 RESULT(sum, n, 8); \
12433 #define ADD16(a, b, n) SARITH16(a, b, n, +)
12434 #define SUB16(a, b, n) SARITH16(a, b, n, -)
12435 #define ADD8(a, b, n) SARITH8(a, b, n, +)
12436 #define SUB8(a, b, n) SARITH8(a, b, n, -)
12440 #include "op_addsub.h"
12442 /* Unsigned modulo arithmetic. */
12443 #define ADD16(a, b, n) do { \
12445 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
12446 RESULT(sum, n, 16); \
12447 if ((sum >> 16) == 1) \
12448 ge |= 3 << (n * 2); \
12451 #define ADD8(a, b, n) do { \
12453 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
12454 RESULT(sum, n, 8); \
12455 if ((sum >> 8) == 1) \
12459 #define SUB16(a, b, n) do { \
12461 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
12462 RESULT(sum, n, 16); \
12463 if ((sum >> 16) == 0) \
12464 ge |= 3 << (n * 2); \
12467 #define SUB8(a, b, n) do { \
12469 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
12470 RESULT(sum, n, 8); \
12471 if ((sum >> 8) == 0) \
12478 #include "op_addsub.h"
12480 /* Halved signed arithmetic. */
12481 #define ADD16(a, b, n) \
12482 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
12483 #define SUB16(a, b, n) \
12484 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
12485 #define ADD8(a, b, n) \
12486 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
12487 #define SUB8(a, b, n) \
12488 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
12491 #include "op_addsub.h"
12493 /* Halved unsigned arithmetic. */
12494 #define ADD16(a, b, n) \
12495 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
12496 #define SUB16(a, b, n) \
12497 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
12498 #define ADD8(a, b, n) \
12499 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
12500 #define SUB8(a, b, n) \
12501 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
12504 #include "op_addsub.h"
12506 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
12514 /* Unsigned sum of absolute byte differences. */
12515 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
12518 sum
= do_usad(a
, b
);
12519 sum
+= do_usad(a
>> 8, b
>> 8);
12520 sum
+= do_usad(a
>> 16, b
>>16);
12521 sum
+= do_usad(a
>> 24, b
>> 24);
12525 /* For ARMv6 SEL instruction. */
12526 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
12538 mask
|= 0xff000000;
12539 return (a
& mask
) | (b
& ~mask
);
12542 /* VFP support. We follow the convention used for VFP instructions:
12543 Single precision routines have a "s" suffix, double precision a
12546 /* Convert host exception flags to vfp form. */
12547 static inline int vfp_exceptbits_from_host(int host_bits
)
12549 int target_bits
= 0;
12551 if (host_bits
& float_flag_invalid
)
12553 if (host_bits
& float_flag_divbyzero
)
12555 if (host_bits
& float_flag_overflow
)
12557 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
12559 if (host_bits
& float_flag_inexact
)
12560 target_bits
|= 0x10;
12561 if (host_bits
& float_flag_input_denormal
)
12562 target_bits
|= 0x80;
12563 return target_bits
;
12566 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
12571 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
12572 | (env
->vfp
.vec_len
<< 16)
12573 | (env
->vfp
.vec_stride
<< 20);
12575 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
12576 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
12577 /* FZ16 does not generate an input denormal exception. */
12578 i
|= (get_float_exception_flags(&env
->vfp
.fp_status_f16
)
12579 & ~float_flag_input_denormal
);
12581 fpscr
|= vfp_exceptbits_from_host(i
);
12585 uint32_t vfp_get_fpscr(CPUARMState
*env
)
12587 return HELPER(vfp_get_fpscr
)(env
);
12590 /* Convert vfp exception flags to target form. */
12591 static inline int vfp_exceptbits_to_host(int target_bits
)
12595 if (target_bits
& 1)
12596 host_bits
|= float_flag_invalid
;
12597 if (target_bits
& 2)
12598 host_bits
|= float_flag_divbyzero
;
12599 if (target_bits
& 4)
12600 host_bits
|= float_flag_overflow
;
12601 if (target_bits
& 8)
12602 host_bits
|= float_flag_underflow
;
12603 if (target_bits
& 0x10)
12604 host_bits
|= float_flag_inexact
;
12605 if (target_bits
& 0x80)
12606 host_bits
|= float_flag_input_denormal
;
12610 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
12615 /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
12616 if (!cpu_isar_feature(aa64_fp16
, arm_env_get_cpu(env
))) {
12620 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
12621 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
12622 env
->vfp
.vec_len
= (val
>> 16) & 7;
12623 env
->vfp
.vec_stride
= (val
>> 20) & 3;
12626 if (changed
& (3 << 22)) {
12627 i
= (val
>> 22) & 3;
12629 case FPROUNDING_TIEEVEN
:
12630 i
= float_round_nearest_even
;
12632 case FPROUNDING_POSINF
:
12633 i
= float_round_up
;
12635 case FPROUNDING_NEGINF
:
12636 i
= float_round_down
;
12638 case FPROUNDING_ZERO
:
12639 i
= float_round_to_zero
;
12642 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
12643 set_float_rounding_mode(i
, &env
->vfp
.fp_status_f16
);
12645 if (changed
& FPCR_FZ16
) {
12646 bool ftz_enabled
= val
& FPCR_FZ16
;
12647 set_flush_to_zero(ftz_enabled
, &env
->vfp
.fp_status_f16
);
12648 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.fp_status_f16
);
12650 if (changed
& FPCR_FZ
) {
12651 bool ftz_enabled
= val
& FPCR_FZ
;
12652 set_flush_to_zero(ftz_enabled
, &env
->vfp
.fp_status
);
12653 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.fp_status
);
12655 if (changed
& FPCR_DN
) {
12656 bool dnan_enabled
= val
& FPCR_DN
;
12657 set_default_nan_mode(dnan_enabled
, &env
->vfp
.fp_status
);
12658 set_default_nan_mode(dnan_enabled
, &env
->vfp
.fp_status_f16
);
12661 /* The exception flags are ORed together when we read fpscr so we
12662 * only need to preserve the current state in one of our
12663 * float_status values.
12665 i
= vfp_exceptbits_to_host(val
);
12666 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
12667 set_float_exception_flags(0, &env
->vfp
.fp_status_f16
);
12668 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
12671 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
12673 HELPER(vfp_set_fpscr
)(env
, val
);
12676 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
12678 #define VFP_BINOP(name) \
12679 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
12681 float_status *fpst = fpstp; \
12682 return float32_ ## name(a, b, fpst); \
12684 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
12686 float_status *fpst = fpstp; \
12687 return float64_ ## name(a, b, fpst); \
12699 float32
VFP_HELPER(neg
, s
)(float32 a
)
12701 return float32_chs(a
);
12704 float64
VFP_HELPER(neg
, d
)(float64 a
)
12706 return float64_chs(a
);
12709 float32
VFP_HELPER(abs
, s
)(float32 a
)
12711 return float32_abs(a
);
12714 float64
VFP_HELPER(abs
, d
)(float64 a
)
12716 return float64_abs(a
);
12719 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
12721 return float32_sqrt(a
, &env
->vfp
.fp_status
);
12724 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
12726 return float64_sqrt(a
, &env
->vfp
.fp_status
);
12729 /* XXX: check quiet/signaling case */
12730 #define DO_VFP_cmp(p, type) \
12731 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
12734 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
12735 case 0: flags = 0x6; break; \
12736 case -1: flags = 0x8; break; \
12737 case 1: flags = 0x2; break; \
12738 default: case 2: flags = 0x3; break; \
12740 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
12741 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
12743 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
12746 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
12747 case 0: flags = 0x6; break; \
12748 case -1: flags = 0x8; break; \
12749 case 1: flags = 0x2; break; \
12750 default: case 2: flags = 0x3; break; \
12752 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
12753 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
12755 DO_VFP_cmp(s
, float32
)
12756 DO_VFP_cmp(d
, float64
)
12759 /* Integer to float and float to integer conversions */
12761 #define CONV_ITOF(name, ftype, fsz, sign) \
12762 ftype HELPER(name)(uint32_t x, void *fpstp) \
12764 float_status *fpst = fpstp; \
12765 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
12768 #define CONV_FTOI(name, ftype, fsz, sign, round) \
12769 sign##int32_t HELPER(name)(ftype x, void *fpstp) \
12771 float_status *fpst = fpstp; \
12772 if (float##fsz##_is_any_nan(x)) { \
12773 float_raise(float_flag_invalid, fpst); \
12776 return float##fsz##_to_##sign##int32##round(x, fpst); \
12779 #define FLOAT_CONVS(name, p, ftype, fsz, sign) \
12780 CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \
12781 CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
12782 CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
12784 FLOAT_CONVS(si
, h
, uint32_t, 16, )
12785 FLOAT_CONVS(si
, s
, float32
, 32, )
12786 FLOAT_CONVS(si
, d
, float64
, 64, )
12787 FLOAT_CONVS(ui
, h
, uint32_t, 16, u
)
12788 FLOAT_CONVS(ui
, s
, float32
, 32, u
)
12789 FLOAT_CONVS(ui
, d
, float64
, 64, u
)
12795 /* floating point conversion */
12796 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
12798 return float32_to_float64(x
, &env
->vfp
.fp_status
);
12801 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
12803 return float64_to_float32(x
, &env
->vfp
.fp_status
);
12806 /* VFP3 fixed point conversion. */
12807 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
12808 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
12810 { return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); }
12812 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ROUND, suff) \
12813 uint##isz##_t HELPER(vfp_to##name##p##suff)(float##fsz x, uint32_t shift, \
12816 if (unlikely(float##fsz##_is_any_nan(x))) { \
12817 float_raise(float_flag_invalid, fpst); \
12820 return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \
12823 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
12824 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
12825 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
12826 float_round_to_zero, _round_to_zero) \
12827 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
12828 get_float_rounding_mode(fpst), )
12830 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
12831 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
12832 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
12833 get_float_rounding_mode(fpst), )
12835 VFP_CONV_FIX(sh
, d
, 64, 64, int16
)
12836 VFP_CONV_FIX(sl
, d
, 64, 64, int32
)
12837 VFP_CONV_FIX_A64(sq
, d
, 64, 64, int64
)
12838 VFP_CONV_FIX(uh
, d
, 64, 64, uint16
)
12839 VFP_CONV_FIX(ul
, d
, 64, 64, uint32
)
12840 VFP_CONV_FIX_A64(uq
, d
, 64, 64, uint64
)
12841 VFP_CONV_FIX(sh
, s
, 32, 32, int16
)
12842 VFP_CONV_FIX(sl
, s
, 32, 32, int32
)
12843 VFP_CONV_FIX_A64(sq
, s
, 32, 64, int64
)
12844 VFP_CONV_FIX(uh
, s
, 32, 32, uint16
)
12845 VFP_CONV_FIX(ul
, s
, 32, 32, uint32
)
12846 VFP_CONV_FIX_A64(uq
, s
, 32, 64, uint64
)
12848 #undef VFP_CONV_FIX
12849 #undef VFP_CONV_FIX_FLOAT
12850 #undef VFP_CONV_FLOAT_FIX_ROUND
12851 #undef VFP_CONV_FIX_A64
12853 uint32_t HELPER(vfp_sltoh
)(uint32_t x
, uint32_t shift
, void *fpst
)
12855 return int32_to_float16_scalbn(x
, -shift
, fpst
);
12858 uint32_t HELPER(vfp_ultoh
)(uint32_t x
, uint32_t shift
, void *fpst
)
12860 return uint32_to_float16_scalbn(x
, -shift
, fpst
);
12863 uint32_t HELPER(vfp_sqtoh
)(uint64_t x
, uint32_t shift
, void *fpst
)
12865 return int64_to_float16_scalbn(x
, -shift
, fpst
);
12868 uint32_t HELPER(vfp_uqtoh
)(uint64_t x
, uint32_t shift
, void *fpst
)
12870 return uint64_to_float16_scalbn(x
, -shift
, fpst
);
12873 uint32_t HELPER(vfp_toshh
)(uint32_t x
, uint32_t shift
, void *fpst
)
12875 if (unlikely(float16_is_any_nan(x
))) {
12876 float_raise(float_flag_invalid
, fpst
);
12879 return float16_to_int16_scalbn(x
, get_float_rounding_mode(fpst
),
12883 uint32_t HELPER(vfp_touhh
)(uint32_t x
, uint32_t shift
, void *fpst
)
12885 if (unlikely(float16_is_any_nan(x
))) {
12886 float_raise(float_flag_invalid
, fpst
);
12889 return float16_to_uint16_scalbn(x
, get_float_rounding_mode(fpst
),
12893 uint32_t HELPER(vfp_toslh
)(uint32_t x
, uint32_t shift
, void *fpst
)
12895 if (unlikely(float16_is_any_nan(x
))) {
12896 float_raise(float_flag_invalid
, fpst
);
12899 return float16_to_int32_scalbn(x
, get_float_rounding_mode(fpst
),
12903 uint32_t HELPER(vfp_toulh
)(uint32_t x
, uint32_t shift
, void *fpst
)
12905 if (unlikely(float16_is_any_nan(x
))) {
12906 float_raise(float_flag_invalid
, fpst
);
12909 return float16_to_uint32_scalbn(x
, get_float_rounding_mode(fpst
),
12913 uint64_t HELPER(vfp_tosqh
)(uint32_t x
, uint32_t shift
, void *fpst
)
12915 if (unlikely(float16_is_any_nan(x
))) {
12916 float_raise(float_flag_invalid
, fpst
);
12919 return float16_to_int64_scalbn(x
, get_float_rounding_mode(fpst
),
12923 uint64_t HELPER(vfp_touqh
)(uint32_t x
, uint32_t shift
, void *fpst
)
12925 if (unlikely(float16_is_any_nan(x
))) {
12926 float_raise(float_flag_invalid
, fpst
);
12929 return float16_to_uint64_scalbn(x
, get_float_rounding_mode(fpst
),
12933 /* Set the current fp rounding mode and return the old one.
12934 * The argument is a softfloat float_round_ value.
12936 uint32_t HELPER(set_rmode
)(uint32_t rmode
, void *fpstp
)
12938 float_status
*fp_status
= fpstp
;
12940 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
12941 set_float_rounding_mode(rmode
, fp_status
);
12946 /* Set the current fp rounding mode in the standard fp status and return
12947 * the old one. This is for NEON instructions that need to change the
12948 * rounding mode but wish to use the standard FPSCR values for everything
12949 * else. Always set the rounding mode back to the correct value after
12951 * The argument is a softfloat float_round_ value.
12953 uint32_t HELPER(set_neon_rmode
)(uint32_t rmode
, CPUARMState
*env
)
12955 float_status
*fp_status
= &env
->vfp
.standard_fp_status
;
12957 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
12958 set_float_rounding_mode(rmode
, fp_status
);
12963 /* Half precision conversions. */
12964 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, void *fpstp
, uint32_t ahp_mode
)
12966 /* Squash FZ16 to 0 for the duration of conversion. In this case,
12967 * it would affect flushing input denormals.
12969 float_status
*fpst
= fpstp
;
12970 flag save
= get_flush_inputs_to_zero(fpst
);
12971 set_flush_inputs_to_zero(false, fpst
);
12972 float32 r
= float16_to_float32(a
, !ahp_mode
, fpst
);
12973 set_flush_inputs_to_zero(save
, fpst
);
12977 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, void *fpstp
, uint32_t ahp_mode
)
12979 /* Squash FZ16 to 0 for the duration of conversion. In this case,
12980 * it would affect flushing output denormals.
12982 float_status
*fpst
= fpstp
;
12983 flag save
= get_flush_to_zero(fpst
);
12984 set_flush_to_zero(false, fpst
);
12985 float16 r
= float32_to_float16(a
, !ahp_mode
, fpst
);
12986 set_flush_to_zero(save
, fpst
);
12990 float64
HELPER(vfp_fcvt_f16_to_f64
)(uint32_t a
, void *fpstp
, uint32_t ahp_mode
)
12992 /* Squash FZ16 to 0 for the duration of conversion. In this case,
12993 * it would affect flushing input denormals.
12995 float_status
*fpst
= fpstp
;
12996 flag save
= get_flush_inputs_to_zero(fpst
);
12997 set_flush_inputs_to_zero(false, fpst
);
12998 float64 r
= float16_to_float64(a
, !ahp_mode
, fpst
);
12999 set_flush_inputs_to_zero(save
, fpst
);
13003 uint32_t HELPER(vfp_fcvt_f64_to_f16
)(float64 a
, void *fpstp
, uint32_t ahp_mode
)
13005 /* Squash FZ16 to 0 for the duration of conversion. In this case,
13006 * it would affect flushing output denormals.
13008 float_status
*fpst
= fpstp
;
13009 flag save
= get_flush_to_zero(fpst
);
13010 set_flush_to_zero(false, fpst
);
13011 float16 r
= float64_to_float16(a
, !ahp_mode
, fpst
);
13012 set_flush_to_zero(save
, fpst
);
13016 #define float32_two make_float32(0x40000000)
13017 #define float32_three make_float32(0x40400000)
13018 #define float32_one_point_five make_float32(0x3fc00000)
13020 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
13022 float_status
*s
= &env
->vfp
.standard_fp_status
;
13023 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
13024 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
13025 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
13026 float_raise(float_flag_input_denormal
, s
);
13028 return float32_two
;
13030 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
13033 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
13035 float_status
*s
= &env
->vfp
.standard_fp_status
;
13037 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
13038 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
13039 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
13040 float_raise(float_flag_input_denormal
, s
);
13042 return float32_one_point_five
;
13044 product
= float32_mul(a
, b
, s
);
13045 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
13048 /* NEON helpers. */
13050 /* Constants 256 and 512 are used in some helpers; we avoid relying on
13051 * int->float conversions at run-time. */
13052 #define float64_256 make_float64(0x4070000000000000LL)
13053 #define float64_512 make_float64(0x4080000000000000LL)
13054 #define float16_maxnorm make_float16(0x7bff)
13055 #define float32_maxnorm make_float32(0x7f7fffff)
13056 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
13058 /* Reciprocal functions
13060 * The algorithm that must be used to calculate the estimate
13061 * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
13064 /* See RecipEstimate()
13066 * input is a 9 bit fixed point number
13067 * input range 256 .. 511 for a number from 0.5 <= x < 1.0.
13068 * result range 256 .. 511 for a number from 1.0 to 511/256.
13071 static int recip_estimate(int input
)
13074 assert(256 <= input
&& input
< 512);
13075 a
= (input
* 2) + 1;
13078 assert(256 <= r
&& r
< 512);
13083 * Common wrapper to call recip_estimate
13085 * The parameters are exponent and 64 bit fraction (without implicit
13086 * bit) where the binary point is nominally at bit 52. Returns a
13087 * float64 which can then be rounded to the appropriate size by the
13091 static uint64_t call_recip_estimate(int *exp
, int exp_off
, uint64_t frac
)
13093 uint32_t scaled
, estimate
;
13094 uint64_t result_frac
;
13097 /* Handle sub-normals */
13099 if (extract64(frac
, 51, 1) == 0) {
13107 /* scaled = UInt('1':fraction<51:44>) */
13108 scaled
= deposit32(1 << 8, 0, 8, extract64(frac
, 44, 8));
13109 estimate
= recip_estimate(scaled
);
13111 result_exp
= exp_off
- *exp
;
13112 result_frac
= deposit64(0, 44, 8, estimate
);
13113 if (result_exp
== 0) {
13114 result_frac
= deposit64(result_frac
>> 1, 51, 1, 1);
13115 } else if (result_exp
== -1) {
13116 result_frac
= deposit64(result_frac
>> 2, 50, 2, 1);
13122 return result_frac
;
13125 static bool round_to_inf(float_status
*fpst
, bool sign_bit
)
13127 switch (fpst
->float_rounding_mode
) {
13128 case float_round_nearest_even
: /* Round to Nearest */
13130 case float_round_up
: /* Round to +Inf */
13132 case float_round_down
: /* Round to -Inf */
13134 case float_round_to_zero
: /* Round to Zero */
13138 g_assert_not_reached();
13141 uint32_t HELPER(recpe_f16
)(uint32_t input
, void *fpstp
)
13143 float_status
*fpst
= fpstp
;
13144 float16 f16
= float16_squash_input_denormal(input
, fpst
);
13145 uint32_t f16_val
= float16_val(f16
);
13146 uint32_t f16_sign
= float16_is_neg(f16
);
13147 int f16_exp
= extract32(f16_val
, 10, 5);
13148 uint32_t f16_frac
= extract32(f16_val
, 0, 10);
13151 if (float16_is_any_nan(f16
)) {
13153 if (float16_is_signaling_nan(f16
, fpst
)) {
13154 float_raise(float_flag_invalid
, fpst
);
13155 nan
= float16_silence_nan(f16
, fpst
);
13157 if (fpst
->default_nan_mode
) {
13158 nan
= float16_default_nan(fpst
);
13161 } else if (float16_is_infinity(f16
)) {
13162 return float16_set_sign(float16_zero
, float16_is_neg(f16
));
13163 } else if (float16_is_zero(f16
)) {
13164 float_raise(float_flag_divbyzero
, fpst
);
13165 return float16_set_sign(float16_infinity
, float16_is_neg(f16
));
13166 } else if (float16_abs(f16
) < (1 << 8)) {
13167 /* Abs(value) < 2.0^-16 */
13168 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
13169 if (round_to_inf(fpst
, f16_sign
)) {
13170 return float16_set_sign(float16_infinity
, f16_sign
);
13172 return float16_set_sign(float16_maxnorm
, f16_sign
);
13174 } else if (f16_exp
>= 29 && fpst
->flush_to_zero
) {
13175 float_raise(float_flag_underflow
, fpst
);
13176 return float16_set_sign(float16_zero
, float16_is_neg(f16
));
13179 f64_frac
= call_recip_estimate(&f16_exp
, 29,
13180 ((uint64_t) f16_frac
) << (52 - 10));
13182 /* result = sign : result_exp<4:0> : fraction<51:42> */
13183 f16_val
= deposit32(0, 15, 1, f16_sign
);
13184 f16_val
= deposit32(f16_val
, 10, 5, f16_exp
);
13185 f16_val
= deposit32(f16_val
, 0, 10, extract64(f64_frac
, 52 - 10, 10));
13186 return make_float16(f16_val
);
13189 float32
HELPER(recpe_f32
)(float32 input
, void *fpstp
)
13191 float_status
*fpst
= fpstp
;
13192 float32 f32
= float32_squash_input_denormal(input
, fpst
);
13193 uint32_t f32_val
= float32_val(f32
);
13194 bool f32_sign
= float32_is_neg(f32
);
13195 int f32_exp
= extract32(f32_val
, 23, 8);
13196 uint32_t f32_frac
= extract32(f32_val
, 0, 23);
13199 if (float32_is_any_nan(f32
)) {
13201 if (float32_is_signaling_nan(f32
, fpst
)) {
13202 float_raise(float_flag_invalid
, fpst
);
13203 nan
= float32_silence_nan(f32
, fpst
);
13205 if (fpst
->default_nan_mode
) {
13206 nan
= float32_default_nan(fpst
);
13209 } else if (float32_is_infinity(f32
)) {
13210 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
13211 } else if (float32_is_zero(f32
)) {
13212 float_raise(float_flag_divbyzero
, fpst
);
13213 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
13214 } else if (float32_abs(f32
) < (1ULL << 21)) {
13215 /* Abs(value) < 2.0^-128 */
13216 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
13217 if (round_to_inf(fpst
, f32_sign
)) {
13218 return float32_set_sign(float32_infinity
, f32_sign
);
13220 return float32_set_sign(float32_maxnorm
, f32_sign
);
13222 } else if (f32_exp
>= 253 && fpst
->flush_to_zero
) {
13223 float_raise(float_flag_underflow
, fpst
);
13224 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
13227 f64_frac
= call_recip_estimate(&f32_exp
, 253,
13228 ((uint64_t) f32_frac
) << (52 - 23));
13230 /* result = sign : result_exp<7:0> : fraction<51:29> */
13231 f32_val
= deposit32(0, 31, 1, f32_sign
);
13232 f32_val
= deposit32(f32_val
, 23, 8, f32_exp
);
13233 f32_val
= deposit32(f32_val
, 0, 23, extract64(f64_frac
, 52 - 23, 23));
13234 return make_float32(f32_val
);
13237 float64
HELPER(recpe_f64
)(float64 input
, void *fpstp
)
13239 float_status
*fpst
= fpstp
;
13240 float64 f64
= float64_squash_input_denormal(input
, fpst
);
13241 uint64_t f64_val
= float64_val(f64
);
13242 bool f64_sign
= float64_is_neg(f64
);
13243 int f64_exp
= extract64(f64_val
, 52, 11);
13244 uint64_t f64_frac
= extract64(f64_val
, 0, 52);
13246 /* Deal with any special cases */
13247 if (float64_is_any_nan(f64
)) {
13249 if (float64_is_signaling_nan(f64
, fpst
)) {
13250 float_raise(float_flag_invalid
, fpst
);
13251 nan
= float64_silence_nan(f64
, fpst
);
13253 if (fpst
->default_nan_mode
) {
13254 nan
= float64_default_nan(fpst
);
13257 } else if (float64_is_infinity(f64
)) {
13258 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
13259 } else if (float64_is_zero(f64
)) {
13260 float_raise(float_flag_divbyzero
, fpst
);
13261 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
13262 } else if ((f64_val
& ~(1ULL << 63)) < (1ULL << 50)) {
13263 /* Abs(value) < 2.0^-1024 */
13264 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
13265 if (round_to_inf(fpst
, f64_sign
)) {
13266 return float64_set_sign(float64_infinity
, f64_sign
);
13268 return float64_set_sign(float64_maxnorm
, f64_sign
);
13270 } else if (f64_exp
>= 2045 && fpst
->flush_to_zero
) {
13271 float_raise(float_flag_underflow
, fpst
);
13272 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
13275 f64_frac
= call_recip_estimate(&f64_exp
, 2045, f64_frac
);
13277 /* result = sign : result_exp<10:0> : fraction<51:0>; */
13278 f64_val
= deposit64(0, 63, 1, f64_sign
);
13279 f64_val
= deposit64(f64_val
, 52, 11, f64_exp
);
13280 f64_val
= deposit64(f64_val
, 0, 52, f64_frac
);
13281 return make_float64(f64_val
);
13284 /* The algorithm that must be used to calculate the estimate
13285 * is specified by the ARM ARM.
13288 static int do_recip_sqrt_estimate(int a
)
13292 assert(128 <= a
&& a
< 512);
13300 while (a
* (b
+ 1) * (b
+ 1) < (1 << 28)) {
13303 estimate
= (b
+ 1) / 2;
13304 assert(256 <= estimate
&& estimate
< 512);
13310 static uint64_t recip_sqrt_estimate(int *exp
, int exp_off
, uint64_t frac
)
13316 while (extract64(frac
, 51, 1) == 0) {
13320 frac
= extract64(frac
, 0, 51) << 1;
13324 /* scaled = UInt('01':fraction<51:45>) */
13325 scaled
= deposit32(1 << 7, 0, 7, extract64(frac
, 45, 7));
13327 /* scaled = UInt('1':fraction<51:44>) */
13328 scaled
= deposit32(1 << 8, 0, 8, extract64(frac
, 44, 8));
13330 estimate
= do_recip_sqrt_estimate(scaled
);
13332 *exp
= (exp_off
- *exp
) / 2;
13333 return extract64(estimate
, 0, 8) << 44;
13336 uint32_t HELPER(rsqrte_f16
)(uint32_t input
, void *fpstp
)
13338 float_status
*s
= fpstp
;
13339 float16 f16
= float16_squash_input_denormal(input
, s
);
13340 uint16_t val
= float16_val(f16
);
13341 bool f16_sign
= float16_is_neg(f16
);
13342 int f16_exp
= extract32(val
, 10, 5);
13343 uint16_t f16_frac
= extract32(val
, 0, 10);
13346 if (float16_is_any_nan(f16
)) {
13348 if (float16_is_signaling_nan(f16
, s
)) {
13349 float_raise(float_flag_invalid
, s
);
13350 nan
= float16_silence_nan(f16
, s
);
13352 if (s
->default_nan_mode
) {
13353 nan
= float16_default_nan(s
);
13356 } else if (float16_is_zero(f16
)) {
13357 float_raise(float_flag_divbyzero
, s
);
13358 return float16_set_sign(float16_infinity
, f16_sign
);
13359 } else if (f16_sign
) {
13360 float_raise(float_flag_invalid
, s
);
13361 return float16_default_nan(s
);
13362 } else if (float16_is_infinity(f16
)) {
13363 return float16_zero
;
13366 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
13367 * preserving the parity of the exponent. */
13369 f64_frac
= ((uint64_t) f16_frac
) << (52 - 10);
13371 f64_frac
= recip_sqrt_estimate(&f16_exp
, 44, f64_frac
);
13373 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */
13374 val
= deposit32(0, 15, 1, f16_sign
);
13375 val
= deposit32(val
, 10, 5, f16_exp
);
13376 val
= deposit32(val
, 2, 8, extract64(f64_frac
, 52 - 8, 8));
13377 return make_float16(val
);
13380 float32
HELPER(rsqrte_f32
)(float32 input
, void *fpstp
)
13382 float_status
*s
= fpstp
;
13383 float32 f32
= float32_squash_input_denormal(input
, s
);
13384 uint32_t val
= float32_val(f32
);
13385 uint32_t f32_sign
= float32_is_neg(f32
);
13386 int f32_exp
= extract32(val
, 23, 8);
13387 uint32_t f32_frac
= extract32(val
, 0, 23);
13390 if (float32_is_any_nan(f32
)) {
13392 if (float32_is_signaling_nan(f32
, s
)) {
13393 float_raise(float_flag_invalid
, s
);
13394 nan
= float32_silence_nan(f32
, s
);
13396 if (s
->default_nan_mode
) {
13397 nan
= float32_default_nan(s
);
13400 } else if (float32_is_zero(f32
)) {
13401 float_raise(float_flag_divbyzero
, s
);
13402 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
13403 } else if (float32_is_neg(f32
)) {
13404 float_raise(float_flag_invalid
, s
);
13405 return float32_default_nan(s
);
13406 } else if (float32_is_infinity(f32
)) {
13407 return float32_zero
;
13410 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
13411 * preserving the parity of the exponent. */
13413 f64_frac
= ((uint64_t) f32_frac
) << 29;
13415 f64_frac
= recip_sqrt_estimate(&f32_exp
, 380, f64_frac
);
13417 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */
13418 val
= deposit32(0, 31, 1, f32_sign
);
13419 val
= deposit32(val
, 23, 8, f32_exp
);
13420 val
= deposit32(val
, 15, 8, extract64(f64_frac
, 52 - 8, 8));
13421 return make_float32(val
);
13424 float64
HELPER(rsqrte_f64
)(float64 input
, void *fpstp
)
13426 float_status
*s
= fpstp
;
13427 float64 f64
= float64_squash_input_denormal(input
, s
);
13428 uint64_t val
= float64_val(f64
);
13429 bool f64_sign
= float64_is_neg(f64
);
13430 int f64_exp
= extract64(val
, 52, 11);
13431 uint64_t f64_frac
= extract64(val
, 0, 52);
13433 if (float64_is_any_nan(f64
)) {
13435 if (float64_is_signaling_nan(f64
, s
)) {
13436 float_raise(float_flag_invalid
, s
);
13437 nan
= float64_silence_nan(f64
, s
);
13439 if (s
->default_nan_mode
) {
13440 nan
= float64_default_nan(s
);
13443 } else if (float64_is_zero(f64
)) {
13444 float_raise(float_flag_divbyzero
, s
);
13445 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
13446 } else if (float64_is_neg(f64
)) {
13447 float_raise(float_flag_invalid
, s
);
13448 return float64_default_nan(s
);
13449 } else if (float64_is_infinity(f64
)) {
13450 return float64_zero
;
13453 f64_frac
= recip_sqrt_estimate(&f64_exp
, 3068, f64_frac
);
13455 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */
13456 val
= deposit64(0, 61, 1, f64_sign
);
13457 val
= deposit64(val
, 52, 11, f64_exp
);
13458 val
= deposit64(val
, 44, 8, extract64(f64_frac
, 52 - 8, 8));
13459 return make_float64(val
);
13462 uint32_t HELPER(recpe_u32
)(uint32_t a
, void *fpstp
)
13464 /* float_status *s = fpstp; */
13465 int input
, estimate
;
13467 if ((a
& 0x80000000) == 0) {
13471 input
= extract32(a
, 23, 9);
13472 estimate
= recip_estimate(input
);
13474 return deposit32(0, (32 - 9), 9, estimate
);
13477 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, void *fpstp
)
13481 if ((a
& 0xc0000000) == 0) {
13485 estimate
= do_recip_sqrt_estimate(extract32(a
, 23, 9));
13487 return deposit32(0, 23, 9, estimate
);
13490 /* VFPv4 fused multiply-accumulate */
13491 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
13493 float_status
*fpst
= fpstp
;
13494 return float32_muladd(a
, b
, c
, 0, fpst
);
13497 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
13499 float_status
*fpst
= fpstp
;
13500 return float64_muladd(a
, b
, c
, 0, fpst
);
13503 /* ARMv8 round to integral */
13504 float32
HELPER(rints_exact
)(float32 x
, void *fp_status
)
13506 return float32_round_to_int(x
, fp_status
);
13509 float64
HELPER(rintd_exact
)(float64 x
, void *fp_status
)
13511 return float64_round_to_int(x
, fp_status
);
13514 float32
HELPER(rints
)(float32 x
, void *fp_status
)
13516 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
13519 ret
= float32_round_to_int(x
, fp_status
);
13521 /* Suppress any inexact exceptions the conversion produced */
13522 if (!(old_flags
& float_flag_inexact
)) {
13523 new_flags
= get_float_exception_flags(fp_status
);
13524 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
13530 float64
HELPER(rintd
)(float64 x
, void *fp_status
)
13532 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
13535 ret
= float64_round_to_int(x
, fp_status
);
13537 new_flags
= get_float_exception_flags(fp_status
);
13539 /* Suppress any inexact exceptions the conversion produced */
13540 if (!(old_flags
& float_flag_inexact
)) {
13541 new_flags
= get_float_exception_flags(fp_status
);
13542 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
13548 /* Convert ARM rounding mode to softfloat */
13549 int arm_rmode_to_sf(int rmode
)
13552 case FPROUNDING_TIEAWAY
:
13553 rmode
= float_round_ties_away
;
13555 case FPROUNDING_ODD
:
13556 /* FIXME: add support for TIEAWAY and ODD */
13557 qemu_log_mask(LOG_UNIMP
, "arm: unimplemented rounding mode: %d\n",
13559 /* fall through for now */
13560 case FPROUNDING_TIEEVEN
:
13562 rmode
= float_round_nearest_even
;
13564 case FPROUNDING_POSINF
:
13565 rmode
= float_round_up
;
13567 case FPROUNDING_NEGINF
:
13568 rmode
= float_round_down
;
13570 case FPROUNDING_ZERO
:
13571 rmode
= float_round_to_zero
;
13578 * The upper bytes of val (above the number specified by 'bytes') must have
13579 * been zeroed out by the caller.
13581 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
13585 stl_le_p(buf
, val
);
13587 /* zlib crc32 converts the accumulator and output to one's complement. */
13588 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
13591 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
13595 stl_le_p(buf
, val
);
13597 /* Linux crc32c converts the output to one's complement. */
13598 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
13601 /* Return the exception level to which FP-disabled exceptions should
13602 * be taken, or 0 if FP is enabled.
13604 int fp_exception_el(CPUARMState
*env
, int cur_el
)
13606 #ifndef CONFIG_USER_ONLY
13609 /* CPACR and the CPTR registers don't exist before v6, so FP is
13610 * always accessible
13612 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
13616 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
13617 * 0, 2 : trap EL0 and EL1/PL1 accesses
13618 * 1 : trap only EL0 accesses
13619 * 3 : trap no accesses
13621 fpen
= extract32(env
->cp15
.cpacr_el1
, 20, 2);
13625 if (cur_el
== 0 || cur_el
== 1) {
13626 /* Trap to PL1, which might be EL1 or EL3 */
13627 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
13632 if (cur_el
== 3 && !is_a64(env
)) {
13633 /* Secure PL1 running at EL3 */
13646 /* For the CPTR registers we don't need to guard with an ARM_FEATURE
13647 * check because zero bits in the registers mean "don't trap".
13650 /* CPTR_EL2 : present in v7VE or v8 */
13651 if (cur_el
<= 2 && extract32(env
->cp15
.cptr_el
[2], 10, 1)
13652 && !arm_is_secure_below_el3(env
)) {
13653 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
13657 /* CPTR_EL3 : present in v8 */
13658 if (extract32(env
->cp15
.cptr_el
[3], 10, 1)) {
13659 /* Trap all FP ops to EL3 */
13666 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState
*env
,
13667 bool secstate
, bool priv
)
13669 ARMMMUIdx mmu_idx
= ARM_MMU_IDX_M
;
13672 mmu_idx
|= ARM_MMU_IDX_M_PRIV
;
13675 if (armv7m_nvic_neg_prio_requested(env
->nvic
, secstate
)) {
13676 mmu_idx
|= ARM_MMU_IDX_M_NEGPRI
;
13680 mmu_idx
|= ARM_MMU_IDX_M_S
;
13686 /* Return the MMU index for a v7M CPU in the specified security state */
13687 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
13689 bool priv
= arm_current_el(env
) != 0;
13691 return arm_v7m_mmu_idx_for_secstate_and_priv(env
, secstate
, priv
);
13694 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
)
13698 if (arm_feature(env
, ARM_FEATURE_M
)) {
13699 return arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
13702 el
= arm_current_el(env
);
13703 if (el
< 2 && arm_is_secure_below_el3(env
)) {
13704 return ARMMMUIdx_S1SE0
+ el
;
13706 return ARMMMUIdx_S12NSE0
+ el
;
13710 int cpu_mmu_index(CPUARMState
*env
, bool ifetch
)
13712 return arm_to_core_mmu_idx(arm_mmu_idx(env
));
13715 #ifndef CONFIG_USER_ONLY
13716 ARMMMUIdx
arm_stage1_mmu_idx(CPUARMState
*env
)
13718 return stage_1_mmu_idx(arm_mmu_idx(env
));
13722 void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
13723 target_ulong
*cs_base
, uint32_t *pflags
)
13725 ARMMMUIdx mmu_idx
= arm_mmu_idx(env
);
13726 int current_el
= arm_current_el(env
);
13727 int fp_el
= fp_exception_el(env
, current_el
);
13728 uint32_t flags
= 0;
13731 ARMCPU
*cpu
= arm_env_get_cpu(env
);
13734 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, AARCH64_STATE
, 1);
13736 #ifndef CONFIG_USER_ONLY
13738 * Get control bits for tagged addresses. Note that the
13739 * translator only uses this for instruction addresses.
13742 ARMMMUIdx stage1
= stage_1_mmu_idx(mmu_idx
);
13743 ARMVAParameters p0
= aa64_va_parameters_both(env
, 0, stage1
);
13746 /* FIXME: ARMv8.1-VHE S2 translation regime. */
13747 if (regime_el(env
, stage1
) < 2) {
13748 ARMVAParameters p1
= aa64_va_parameters_both(env
, -1, stage1
);
13749 tbid
= (p1
.tbi
<< 1) | p0
.tbi
;
13750 tbii
= tbid
& ~((p1
.tbid
<< 1) | p0
.tbid
);
13753 tbii
= tbid
& !p0
.tbid
;
13756 flags
= FIELD_DP32(flags
, TBFLAG_A64
, TBII
, tbii
);
13760 if (cpu_isar_feature(aa64_sve
, cpu
)) {
13761 int sve_el
= sve_exception_el(env
, current_el
);
13764 /* If SVE is disabled, but FP is enabled,
13765 * then the effective len is 0.
13767 if (sve_el
!= 0 && fp_el
== 0) {
13770 zcr_len
= sve_zcr_len_for_el(env
, current_el
);
13772 flags
= FIELD_DP32(flags
, TBFLAG_A64
, SVEEXC_EL
, sve_el
);
13773 flags
= FIELD_DP32(flags
, TBFLAG_A64
, ZCR_LEN
, zcr_len
);
13776 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
13778 * In order to save space in flags, we record only whether
13779 * pauth is "inactive", meaning all insns are implemented as
13780 * a nop, or "active" when some action must be performed.
13781 * The decision of which action to take is left to a helper.
13784 if (current_el
== 0) {
13785 /* FIXME: ARMv8.1-VHE S2 translation regime. */
13786 sctlr
= env
->cp15
.sctlr_el
[1];
13788 sctlr
= env
->cp15
.sctlr_el
[current_el
];
13790 if (sctlr
& (SCTLR_EnIA
| SCTLR_EnIB
| SCTLR_EnDA
| SCTLR_EnDB
)) {
13791 flags
= FIELD_DP32(flags
, TBFLAG_A64
, PAUTH_ACTIVE
, 1);
13795 *pc
= env
->regs
[15];
13796 flags
= FIELD_DP32(flags
, TBFLAG_A32
, THUMB
, env
->thumb
);
13797 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VECLEN
, env
->vfp
.vec_len
);
13798 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VECSTRIDE
, env
->vfp
.vec_stride
);
13799 flags
= FIELD_DP32(flags
, TBFLAG_A32
, CONDEXEC
, env
->condexec_bits
);
13800 flags
= FIELD_DP32(flags
, TBFLAG_A32
, SCTLR_B
, arm_sctlr_b(env
));
13801 flags
= FIELD_DP32(flags
, TBFLAG_A32
, NS
, !access_secure_reg(env
));
13802 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)
13803 || arm_el_is_aa64(env
, 1)) {
13804 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VFPEN
, 1);
13806 flags
= FIELD_DP32(flags
, TBFLAG_A32
, XSCALE_CPAR
, env
->cp15
.c15_cpar
);
13809 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, MMUIDX
, arm_to_core_mmu_idx(mmu_idx
));
13811 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
13812 * states defined in the ARM ARM for software singlestep:
13813 * SS_ACTIVE PSTATE.SS State
13814 * 0 x Inactive (the TB flag for SS is always 0)
13815 * 1 0 Active-pending
13816 * 1 1 Active-not-pending
13818 if (arm_singlestep_active(env
)) {
13819 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, SS_ACTIVE
, 1);
13821 if (env
->pstate
& PSTATE_SS
) {
13822 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, PSTATE_SS
, 1);
13825 if (env
->uncached_cpsr
& PSTATE_SS
) {
13826 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, PSTATE_SS
, 1);
13830 if (arm_cpu_data_is_big_endian(env
)) {
13831 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, BE_DATA
, 1);
13833 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, FPEXC_EL
, fp_el
);
13835 if (arm_v7m_is_handler_mode(env
)) {
13836 flags
= FIELD_DP32(flags
, TBFLAG_A32
, HANDLER
, 1);
13839 /* v8M always applies stack limit checks unless CCR.STKOFHFNMIGN is
13840 * suppressing them because the requested execution priority is less than 0.
13842 if (arm_feature(env
, ARM_FEATURE_V8
) &&
13843 arm_feature(env
, ARM_FEATURE_M
) &&
13844 !((mmu_idx
& ARM_MMU_IDX_M_NEGPRI
) &&
13845 (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_STKOFHFNMIGN_MASK
))) {
13846 flags
= FIELD_DP32(flags
, TBFLAG_A32
, STACKCHECK
, 1);
13853 #ifdef TARGET_AARCH64
13855 * The manual says that when SVE is enabled and VQ is widened the
13856 * implementation is allowed to zero the previously inaccessible
13857 * portion of the registers. The corollary to that is that when
13858 * SVE is enabled and VQ is narrowed we are also allowed to zero
13859 * the now inaccessible portion of the registers.
13861 * The intent of this is that no predicate bit beyond VQ is ever set.
13862 * Which means that some operations on predicate registers themselves
13863 * may operate on full uint64_t or even unrolled across the maximum
13864 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
13865 * may well be cheaper than conditionals to restrict the operation
13866 * to the relevant portion of a uint16_t[16].
13868 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
13873 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
13874 assert(vq
<= arm_env_get_cpu(env
)->sve_max_vq
);
13876 /* Zap the high bits of the zregs. */
13877 for (i
= 0; i
< 32; i
++) {
13878 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
13881 /* Zap the high bits of the pregs and ffr. */
13884 pmask
= ~(-1ULL << (16 * (vq
& 3)));
13886 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
13887 for (i
= 0; i
< 17; ++i
) {
13888 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
13895 * Notice a change in SVE vector size when changing EL.
13897 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
,
13898 int new_el
, bool el0_a64
)
13900 ARMCPU
*cpu
= arm_env_get_cpu(env
);
13901 int old_len
, new_len
;
13902 bool old_a64
, new_a64
;
13904 /* Nothing to do if no SVE. */
13905 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
13909 /* Nothing to do if FP is disabled in either EL. */
13910 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
13915 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
13916 * at ELx, or not available because the EL is in AArch32 state, then
13917 * for all purposes other than a direct read, the ZCR_ELx.LEN field
13918 * has an effective value of 0".
13920 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
13921 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
13922 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
13923 * we already have the correct register contents when encountering the
13924 * vq0->vq0 transition between EL0->EL1.
13926 old_a64
= old_el
? arm_el_is_aa64(env
, old_el
) : el0_a64
;
13927 old_len
= (old_a64
&& !sve_exception_el(env
, old_el
)
13928 ? sve_zcr_len_for_el(env
, old_el
) : 0);
13929 new_a64
= new_el
? arm_el_is_aa64(env
, new_el
) : el0_a64
;
13930 new_len
= (new_a64
&& !sve_exception_el(env
, new_el
)
13931 ? sve_zcr_len_for_el(env
, new_el
) : 0);
13933 /* When changing vector length, clear inaccessible state. */
13934 if (new_len
< old_len
) {
13935 aarch64_sve_narrow_vq(env
, new_len
+ 1);