include/hw/display/dpcd.h

   1 /*
   2  * dpcd.h
   3  *
   4  *  Copyright (C)2015 : GreenSocs Ltd
   5  *      http://www.greensocs.com/ , email: info@greensocs.com
   6  *
   7  *  Developed by :
   8  *  Frederic Konrad   <fred.konrad@greensocs.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation, either version 2 of the License, or
  13  * (at your option)any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along
  21  * with this program; if not, see <http://www.gnu.org/licenses/>.
  22  *
  23  */
  24
  25 #ifndef DPCD_H
  26 #define DPCD_H
  27 #include "qom/object.h"
  28
  29
  30 #define TYPE_DPCD "dpcd"
  31 OBJECT_DECLARE_SIMPLE_TYPE(DPCDState, DPCD)
  32
  33 /* DCPD Revision. */
  34 #define DPCD_REVISION                           0x00
  35 #define DPCD_REV_1_0                            0x10
  36 #define DPCD_REV_1_1                            0x11
  37
  38 /* DCPD Max Link Rate. */
  39 #define DPCD_MAX_LINK_RATE                      0x01
  40 #define DPCD_1_62GBPS                           0x06
  41 #define DPCD_2_7GBPS                            0x0A
  42 #define DPCD_5_4GBPS                            0x14
  43
  44 #define DPCD_MAX_LANE_COUNT                     0x02
  45 #define DPCD_ONE_LANE                           0x01
  46 #define DPCD_TWO_LANES                          0x02
  47 #define DPCD_FOUR_LANES                         0x04
  48
  49 /* DCPD Max down spread. */
  50 #define DPCD_UP_TO_0_5                          0x01
  51 #define DPCD_NO_AUX_HANDSHAKE_LINK_TRAINING     0x40
  52
  53 /* DCPD Downstream port type. */
  54 #define DPCD_DISPLAY_PORT                       0x00
  55 #define DPCD_ANALOG                             0x02
  56 #define DPCD_DVI_HDMI                           0x04
  57 #define DPCD_OTHER                              0x06
  58
  59 /* DPCD Format conversion. */
  60 #define DPCD_FORMAT_CONVERSION                  0x08
  61
  62 /* Main link channel coding. */
  63 #define DPCD_ANSI_8B_10B                        0x01
  64
  65 /* Down stream port count. */
  66 #define DPCD_OUI_SUPPORTED                      0x80
  67
  68 /* Receiver port capability. */
  69 #define DPCD_RECEIVE_PORT0_CAP_0                0x08
  70 #define DPCD_RECEIVE_PORT0_CAP_1                0x09
  71 #define DPCD_EDID_PRESENT                       0x02
  72 #define DPCD_ASSOCIATED_TO_PRECEDING_PORT       0x04
  73
  74 /* Down stream port capability. */
  75 #define DPCD_CAP_DISPLAY_PORT                   0x000
  76 #define DPCD_CAP_ANALOG_VGA                     0x001
  77 #define DPCD_CAP_DVI                            0x002
  78 #define DPCD_CAP_HDMI                           0x003
  79 #define DPCD_CAP_OTHER                          0x100
  80
  81 #define DPCD_LANE0_1_STATUS                     0x202
  82 #define DPCD_LANE0_CR_DONE                      (1 << 0)
  83 #define DPCD_LANE0_CHANNEL_EQ_DONE              (1 << 1)
  84 #define DPCD_LANE0_SYMBOL_LOCKED                (1 << 2)
  85 #define DPCD_LANE1_CR_DONE                      (1 << 4)
  86 #define DPCD_LANE1_CHANNEL_EQ_DONE              (1 << 5)
  87 #define DPCD_LANE1_SYMBOL_LOCKED                (1 << 6)
  88
  89 #define DPCD_LANE2_3_STATUS                     0x203
  90 #define DPCD_LANE2_CR_DONE                      (1 << 0)
  91 #define DPCD_LANE2_CHANNEL_EQ_DONE              (1 << 1)
  92 #define DPCD_LANE2_SYMBOL_LOCKED                (1 << 2)
  93 #define DPCD_LANE3_CR_DONE                      (1 << 4)
  94 #define DPCD_LANE3_CHANNEL_EQ_DONE              (1 << 5)
  95 #define DPCD_LANE3_SYMBOL_LOCKED                (1 << 6)
  96
  97 #define DPCD_LANE_ALIGN_STATUS_UPDATED          0x204
  98 #define DPCD_INTERLANE_ALIGN_DONE               0x01
  99 #define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED     0x40
 100 #define DPCD_LINK_STATUS_UPDATED                0x80
 101
 102 #define DPCD_SINK_STATUS                        0x205
 103 #define DPCD_RECEIVE_PORT_0_STATUS              0x01
 104
 105 #endif /* DPCD_H */