target/sh4/cpu.c

   1 /*
   2  * QEMU SuperH CPU
   3  *
   4  * Copyright (c) 2005 Samuel Tardieu
   5  * Copyright (c) 2012 SUSE LINUX Products GmbH
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see
  19  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "qapi/error.h"
  24 #include "qemu/qemu-print.h"
  25 #include "cpu.h"
  26 #include "migration/vmstate.h"
  27 #include "exec/exec-all.h"
  28 #include "fpu/softfloat.h"
  29
  30
  31 static void superh_cpu_set_pc(CPUState *cs, vaddr value)
  32 {
  33     SuperHCPU *cpu = SUPERH_CPU(cs);
  34
  35     cpu->env.pc = value;
  36 }
  37
  38 static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
  39 {
  40     SuperHCPU *cpu = SUPERH_CPU(cs);
  41
  42     cpu->env.pc = tb->pc;
  43     cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK;
  44 }
  45
  46 static bool superh_cpu_has_work(CPUState *cs)
  47 {
  48     return cs->interrupt_request & CPU_INTERRUPT_HARD;
  49 }
  50
  51 /* CPUClass::reset() */
  52 static void superh_cpu_reset(CPUState *s)
  53 {
  54     SuperHCPU *cpu = SUPERH_CPU(s);
  55     SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
  56     CPUSH4State *env = &cpu->env;
  57
  58     scc->parent_reset(s);
  59
  60     memset(env, 0, offsetof(CPUSH4State, end_reset_fields));
  61
  62     env->pc = 0xA0000000;
  63 #if defined(CONFIG_USER_ONLY)
  64     env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
  65     set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
  66 #else
  67     env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) |
  68               (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0);
  69     env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
  70     set_float_rounding_mode(float_round_to_zero, &env->fp_status);
  71     set_flush_to_zero(1, &env->fp_status);
  72 #endif
  73     set_default_nan_mode(1, &env->fp_status);
  74 }
  75
  76 static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
  77 {
  78     info->mach = bfd_mach_sh4;
  79     info->print_insn = print_insn_sh;
  80 }
  81
  82 static void superh_cpu_list_entry(gpointer data, gpointer user_data)
  83 {
  84     const char *typename = object_class_get_name(OBJECT_CLASS(data));
  85     int len = strlen(typename) - strlen(SUPERH_CPU_TYPE_SUFFIX);
  86
  87     qemu_printf("%.*s\n", len, typename);
  88 }
  89
  90 void sh4_cpu_list(void)
  91 {
  92     GSList *list;
  93
  94     list = object_class_get_list_sorted(TYPE_SUPERH_CPU, false);
  95     g_slist_foreach(list, superh_cpu_list_entry, NULL);
  96     g_slist_free(list);
  97 }
  98
  99 static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
 100 {
 101     ObjectClass *oc;
 102     char *s, *typename = NULL;
 103
 104     s = g_ascii_strdown(cpu_model, -1);
 105     if (strcmp(s, "any") == 0) {
 106         oc = object_class_by_name(TYPE_SH7750R_CPU);
 107         goto out;
 108     }
 109
 110     typename = g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s);
 111     oc = object_class_by_name(typename);
 112     if (oc != NULL && object_class_is_abstract(oc)) {
 113         oc = NULL;
 114     }
 115
 116 out:
 117     g_free(s);
 118     g_free(typename);
 119     return oc;
 120 }
 121
 122 static void sh7750r_cpu_initfn(Object *obj)
 123 {
 124     SuperHCPU *cpu = SUPERH_CPU(obj);
 125     CPUSH4State *env = &cpu->env;
 126
 127     env->id = SH_CPU_SH7750R;
 128     env->features = SH_FEATURE_BCR3_AND_BCR4;
 129 }
 130
 131 static void sh7750r_class_init(ObjectClass *oc, void *data)
 132 {
 133     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 134
 135     scc->pvr = 0x00050000;
 136     scc->prr = 0x00000100;
 137     scc->cvr = 0x00110000;
 138 }
 139
 140 static void sh7751r_cpu_initfn(Object *obj)
 141 {
 142     SuperHCPU *cpu = SUPERH_CPU(obj);
 143     CPUSH4State *env = &cpu->env;
 144
 145     env->id = SH_CPU_SH7751R;
 146     env->features = SH_FEATURE_BCR3_AND_BCR4;
 147 }
 148
 149 static void sh7751r_class_init(ObjectClass *oc, void *data)
 150 {
 151     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 152
 153     scc->pvr = 0x04050005;
 154     scc->prr = 0x00000113;
 155     scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
 156 }
 157
 158 static void sh7785_cpu_initfn(Object *obj)
 159 {
 160     SuperHCPU *cpu = SUPERH_CPU(obj);
 161     CPUSH4State *env = &cpu->env;
 162
 163     env->id = SH_CPU_SH7785;
 164     env->features = SH_FEATURE_SH4A;
 165 }
 166
 167 static void sh7785_class_init(ObjectClass *oc, void *data)
 168 {
 169     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 170
 171     scc->pvr = 0x10300700;
 172     scc->prr = 0x00000200;
 173     scc->cvr = 0x71440211;
 174 }
 175
 176 static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
 177 {
 178     CPUState *cs = CPU(dev);
 179     SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
 180     Error *local_err = NULL;
 181
 182     cpu_exec_realizefn(cs, &local_err);
 183     if (local_err != NULL) {
 184         error_propagate(errp, local_err);
 185         return;
 186     }
 187
 188     cpu_reset(cs);
 189     qemu_init_vcpu(cs);
 190
 191     scc->parent_realize(dev, errp);
 192 }
 193
 194 static void superh_cpu_initfn(Object *obj)
 195 {
 196     SuperHCPU *cpu = SUPERH_CPU(obj);
 197     CPUSH4State *env = &cpu->env;
 198
 199     cpu_set_cpustate_pointers(cpu);
 200
 201     env->movcal_backup_tail = &(env->movcal_backup);
 202 }
 203
 204 static const VMStateDescription vmstate_sh_cpu = {
 205     .name = "cpu",
 206     .unmigratable = 1,
 207 };
 208
 209 static void superh_cpu_class_init(ObjectClass *oc, void *data)
 210 {
 211     DeviceClass *dc = DEVICE_CLASS(oc);
 212     CPUClass *cc = CPU_CLASS(oc);
 213     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 214
 215     device_class_set_parent_realize(dc, superh_cpu_realizefn,
 216                                     &scc->parent_realize);
 217
 218     scc->parent_reset = cc->reset;
 219     cc->reset = superh_cpu_reset;
 220
 221     cc->class_by_name = superh_cpu_class_by_name;
 222     cc->has_work = superh_cpu_has_work;
 223     cc->do_interrupt = superh_cpu_do_interrupt;
 224     cc->cpu_exec_interrupt = superh_cpu_exec_interrupt;
 225     cc->dump_state = superh_cpu_dump_state;
 226     cc->set_pc = superh_cpu_set_pc;
 227     cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
 228     cc->gdb_read_register = superh_cpu_gdb_read_register;
 229     cc->gdb_write_register = superh_cpu_gdb_write_register;
 230     cc->tlb_fill = superh_cpu_tlb_fill;
 231 #ifndef CONFIG_USER_ONLY
 232     cc->do_unaligned_access = superh_cpu_do_unaligned_access;
 233     cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
 234 #endif
 235     cc->disas_set_info = superh_cpu_disas_set_info;
 236     cc->tcg_initialize = sh4_translate_init;
 237
 238     cc->gdb_num_core_regs = 59;
 239
 240     dc->vmsd = &vmstate_sh_cpu;
 241 }
 242
 243 #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \
 244     {                                                    \
 245         .name = type_name,                               \
 246         .parent = TYPE_SUPERH_CPU,                       \
 247         .class_init = cinit,                             \
 248         .instance_init = initfn,                         \
 249     }
 250 static const TypeInfo superh_cpu_type_infos[] = {
 251     {
 252         .name = TYPE_SUPERH_CPU,
 253         .parent = TYPE_CPU,
 254         .instance_size = sizeof(SuperHCPU),
 255         .instance_init = superh_cpu_initfn,
 256         .abstract = true,
 257         .class_size = sizeof(SuperHCPUClass),
 258         .class_init = superh_cpu_class_init,
 259     },
 260     DEFINE_SUPERH_CPU_TYPE(TYPE_SH7750R_CPU, sh7750r_class_init,
 261                            sh7750r_cpu_initfn),
 262     DEFINE_SUPERH_CPU_TYPE(TYPE_SH7751R_CPU, sh7751r_class_init,
 263                            sh7751r_cpu_initfn),
 264     DEFINE_SUPERH_CPU_TYPE(TYPE_SH7785_CPU, sh7785_class_init,
 265                            sh7785_cpu_initfn),
 266
 267 };
 268
 269 DEFINE_TYPES(superh_cpu_type_infos)