?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
util/hbitmap: update orig_size on truncate
[qemu/ar7.git] / hw / audio / intel-hda.c
blobb78baac29542fcf9b3f1a5329dd5dc548499e86f
1 /*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Gerd Hoffmann <kraxel@redhat.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "hw/hw.h"
22 #include "hw/pci/pci.h"
23 #include "hw/pci/msi.h"
24 #include "qemu/timer.h"
25 #include "qemu/bitops.h"
26 #include "qemu/log.h"
27 #include "qemu/module.h"
28 #include "hw/audio/soundhw.h"
29 #include "intel-hda.h"
30 #include "intel-hda-defs.h"
31 #include "sysemu/dma.h"
32 #include "qapi/error.h"
33
34 /* --------------------------------------------------------------------- */
35 /* hda bus */
36
37 static Property hda_props[] = {
38 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1),
39 DEFINE_PROP_END_OF_LIST()
40 };
41
42 static const TypeInfo hda_codec_bus_info = {
43 .name = TYPE_HDA_BUS,
44 .parent = TYPE_BUS,
45 .instance_size = sizeof(HDACodecBus),
46 };
47
48 void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size,
49 hda_codec_response_func response,
50 hda_codec_xfer_func xfer)
51 {
52 qbus_create_inplace(bus, bus_size, TYPE_HDA_BUS, dev, NULL);
53 bus->response = response;
54 bus->xfer = xfer;
55 }
56
57 static void hda_codec_dev_realize(DeviceState *qdev, Error **errp)
58 {
59 HDACodecBus *bus = HDA_BUS(qdev->parent_bus);
60 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev);
61 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
62
63 if (dev->cad == -1) {
64 dev->cad = bus->next_cad;
65 }
66 if (dev->cad >= 15) {
67 error_setg(errp, "HDA audio codec address is full");
68 return;
69 }
70 bus->next_cad = dev->cad + 1;
71 if (cdc->init(dev) != 0) {
72 error_setg(errp, "HDA audio init failed");
73 }
74 }
75
76 static void hda_codec_dev_unrealize(DeviceState *qdev, Error **errp)
77 {
78 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev);
79 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
80
81 if (cdc->exit) {
82 cdc->exit(dev);
83 }
84 }
85
86 HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad)
87 {
88 BusChild *kid;
89 HDACodecDevice *cdev;
90
91 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
92 DeviceState *qdev = kid->child;
93 cdev = HDA_CODEC_DEVICE(qdev);
94 if (cdev->cad == cad) {
95 return cdev;
96 }
97 }
98 return NULL;
99 }
100
101 void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response)
102 {
103 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
104 bus->response(dev, solicited, response);
105 }
106
107 bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
108 uint8_t *buf, uint32_t len)
109 {
110 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
111 return bus->xfer(dev, stnr, output, buf, len);
112 }
113
114 /* --------------------------------------------------------------------- */
115 /* intel hda emulation */
116
117 typedef struct IntelHDAStream IntelHDAStream;
118 typedef struct IntelHDAState IntelHDAState;
119 typedef struct IntelHDAReg IntelHDAReg;
120
121 typedef struct bpl {
122 uint64_t addr;
123 uint32_t len;
124 uint32_t flags;
125 } bpl;
126
127 struct IntelHDAStream {
128 /* registers */
129 uint32_t ctl;
130 uint32_t lpib;
131 uint32_t cbl;
132 uint32_t lvi;
133 uint32_t fmt;
134 uint32_t bdlp_lbase;
135 uint32_t bdlp_ubase;
136
137 /* state */
138 bpl *bpl;
139 uint32_t bentries;
140 uint32_t bsize, be, bp;
141 };
142
143 struct IntelHDAState {
144 PCIDevice pci;
145 const char *name;
146 HDACodecBus codecs;
147
148 /* registers */
149 uint32_t g_ctl;
150 uint32_t wake_en;
151 uint32_t state_sts;
152 uint32_t int_ctl;
153 uint32_t int_sts;
154 uint32_t wall_clk;
155
156 uint32_t corb_lbase;
157 uint32_t corb_ubase;
158 uint32_t corb_rp;
159 uint32_t corb_wp;
160 uint32_t corb_ctl;
161 uint32_t corb_sts;
162 uint32_t corb_size;
163
164 uint32_t rirb_lbase;
165 uint32_t rirb_ubase;
166 uint32_t rirb_wp;
167 uint32_t rirb_cnt;
168 uint32_t rirb_ctl;
169 uint32_t rirb_sts;
170 uint32_t rirb_size;
171
172 uint32_t dp_lbase;
173 uint32_t dp_ubase;
174
175 uint32_t icw;
176 uint32_t irr;
177 uint32_t ics;
178
179 /* streams */
180 IntelHDAStream st[8];
181
182 /* state */
183 MemoryRegion mmio;
184 uint32_t rirb_count;
185 int64_t wall_base_ns;
186
187 /* debug logging */
188 const IntelHDAReg *last_reg;
189 uint32_t last_val;
190 uint32_t last_write;
191 uint32_t last_sec;
192 uint32_t repeat_count;
193
194 /* properties */
195 uint32_t debug;
196 OnOffAuto msi;
197 bool old_msi_addr;
198 };
199
200 #define TYPE_INTEL_HDA_GENERIC "intel-hda-generic"
201
202 #define INTEL_HDA(obj) \
203 OBJECT_CHECK(IntelHDAState, (obj), TYPE_INTEL_HDA_GENERIC)
204
205 struct IntelHDAReg {
206 const char *name; /* register name */
207 uint32_t size; /* size in bytes */
208 uint32_t reset; /* reset value */
209 uint32_t wmask; /* write mask */
210 uint32_t wclear; /* write 1 to clear bits */
211 uint32_t offset; /* location in IntelHDAState */
212 uint32_t shift; /* byte access entries for dwords */
213 uint32_t stream;
214 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old);
215 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg);
216 };
217
218 static void intel_hda_reset(DeviceState *dev);
219
220 /* --------------------------------------------------------------------- */
221
222 static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase)
223 {
224 return ((uint64_t)ubase << 32) | lbase;
225 }
226
227 static void intel_hda_update_int_sts(IntelHDAState *d)
228 {
229 uint32_t sts = 0;
230 uint32_t i;
231
232 /* update controller status */
233 if (d->rirb_sts & ICH6_RBSTS_IRQ) {
234 sts |= (1 << 30);
235 }
236 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) {
237 sts |= (1 << 30);
238 }
239 if (d->state_sts & d->wake_en) {
240 sts |= (1 << 30);
241 }
242
243 /* update stream status */
244 for (i = 0; i < 8; i++) {
245 /* buffer completion interrupt */
246 if (d->st[i].ctl & (1 << 26)) {
247 sts |= (1 << i);
248 }
249 }
250
251 /* update global status */
252 if (sts & d->int_ctl) {
253 sts |= (1U << 31);
254 }
255
256 d->int_sts = sts;
257 }
258
259 static void intel_hda_update_irq(IntelHDAState *d)
260 {
261 bool msi = msi_enabled(&d->pci);
262 int level;
263
264 intel_hda_update_int_sts(d);
265 if (d->int_sts & (1U << 31) && d->int_ctl & (1U << 31)) {
266 level = 1;
267 } else {
268 level = 0;
269 }
270 dprint(d, 2, "%s: level %d [%s]\n", __func__,
271 level, msi ? "msi" : "intx");
272 if (msi) {
273 if (level) {
274 msi_notify(&d->pci, 0);
275 }
276 } else {
277 pci_set_irq(&d->pci, level);
278 }
279 }
280
281 static int intel_hda_send_command(IntelHDAState *d, uint32_t verb)
282 {
283 uint32_t cad, nid, data;
284 HDACodecDevice *codec;
285 HDACodecDeviceClass *cdc;
286
287 cad = (verb >> 28) & 0x0f;
288 if (verb & (1 << 27)) {
289 /* indirect node addressing, not specified in HDA 1.0 */
290 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __func__);
291 return -1;
292 }
293 nid = (verb >> 20) & 0x7f;
294 data = verb & 0xfffff;
295
296 codec = hda_codec_find(&d->codecs, cad);
297 if (codec == NULL) {
298 dprint(d, 1, "%s: addressed non-existing codec\n", __func__);
299 return -1;
300 }
301 cdc = HDA_CODEC_DEVICE_GET_CLASS(codec);
302 cdc->command(codec, nid, data);
303 return 0;
304 }
305
306 static void intel_hda_corb_run(IntelHDAState *d)
307 {
308 hwaddr addr;
309 uint32_t rp, verb;
310
311 if (d->ics & ICH6_IRS_BUSY) {
312 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __func__, d->icw);
313 intel_hda_send_command(d, d->icw);
314 return;
315 }
316
317 for (;;) {
318 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) {
319 dprint(d, 2, "%s: !run\n", __func__);
320 return;
321 }
322 if ((d->corb_rp & 0xff) == d->corb_wp) {
323 dprint(d, 2, "%s: corb ring empty\n", __func__);
324 return;
325 }
326 if (d->rirb_count == d->rirb_cnt) {
327 dprint(d, 2, "%s: rirb count reached\n", __func__);
328 return;
329 }
330
331 rp = (d->corb_rp + 1) & 0xff;
332 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase);
333 verb = ldl_le_pci_dma(&d->pci, addr + 4*rp);
334 d->corb_rp = rp;
335
336 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __func__, rp, verb);
337 intel_hda_send_command(d, verb);
338 }
339 }
340
341 static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response)
342 {
343 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
344 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
345 hwaddr addr;
346 uint32_t wp, ex;
347
348 if (d->ics & ICH6_IRS_BUSY) {
349 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
350 __func__, response, dev->cad);
351 d->irr = response;
352 d->ics &= ~(ICH6_IRS_BUSY | 0xf0);
353 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4));
354 return;
355 }
356
357 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) {
358 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __func__);
359 return;
360 }
361
362 ex = (solicited ? 0 : (1 << 4)) | dev->cad;
363 wp = (d->rirb_wp + 1) & 0xff;
364 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase);
365 stl_le_pci_dma(&d->pci, addr + 8*wp, response);
366 stl_le_pci_dma(&d->pci, addr + 8*wp + 4, ex);
367 d->rirb_wp = wp;
368
369 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
370 __func__, wp, response, ex);
371
372 d->rirb_count++;
373 if (d->rirb_count == d->rirb_cnt) {
374 dprint(d, 2, "%s: rirb count reached (%d)\n", __func__, d->rirb_count);
375 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
376 d->rirb_sts |= ICH6_RBSTS_IRQ;
377 intel_hda_update_irq(d);
378 }
379 } else if ((d->corb_rp & 0xff) == d->corb_wp) {
380 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __func__,
381 d->rirb_count, d->rirb_cnt);
382 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
383 d->rirb_sts |= ICH6_RBSTS_IRQ;
384 intel_hda_update_irq(d);
385 }
386 }
387 }
388
389 static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
390 uint8_t *buf, uint32_t len)
391 {
392 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
393 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
394 hwaddr addr;
395 uint32_t s, copy, left;
396 IntelHDAStream *st;
397 bool irq = false;
398
399 st = output ? d->st + 4 : d->st;
400 for (s = 0; s < 4; s++) {
401 if (stnr == ((st[s].ctl >> 20) & 0x0f)) {
402 st = st + s;
403 break;
404 }
405 }
406 if (s == 4) {
407 return false;
408 }
409 if (st->bpl == NULL) {
410 return false;
411 }
412
413 left = len;
414 s = st->bentries;
415 while (left > 0 && s-- > 0) {
416 copy = left;
417 if (copy > st->bsize - st->lpib)
418 copy = st->bsize - st->lpib;
419 if (copy > st->bpl[st->be].len - st->bp)
420 copy = st->bpl[st->be].len - st->bp;
421
422 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n",
423 st->be, st->bp, st->bpl[st->be].len, copy);
424
425 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output);
426 st->lpib += copy;
427 st->bp += copy;
428 buf += copy;
429 left -= copy;
430
431 if (st->bpl[st->be].len == st->bp) {
432 /* bpl entry filled */
433 if (st->bpl[st->be].flags & 0x01) {
434 irq = true;
435 }
436 st->bp = 0;
437 st->be++;
438 if (st->be == st->bentries) {
439 /* bpl wrap around */
440 st->be = 0;
441 st->lpib = 0;
442 }
443 }
444 }
445 if (d->dp_lbase & 0x01) {
446 s = st - d->st;
447 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase);
448 stl_le_pci_dma(&d->pci, addr + 8*s, st->lpib);
449 }
450 dprint(d, 3, "dma: --\n");
451
452 if (irq) {
453 st->ctl |= (1 << 26); /* buffer completion interrupt */
454 intel_hda_update_irq(d);
455 }
456 return true;
457 }
458
459 static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st)
460 {
461 hwaddr addr;
462 uint8_t buf[16];
463 uint32_t i;
464
465 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase);
466 st->bentries = st->lvi +1;
467 g_free(st->bpl);
468 st->bpl = g_malloc(sizeof(bpl) * st->bentries);
469 for (i = 0; i < st->bentries; i++, addr += 16) {
470 pci_dma_read(&d->pci, addr, buf, 16);
471 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf);
472 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8));
473 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12));
474 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n",
475 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags);
476 }
477
478 st->bsize = st->cbl;
479 st->lpib = 0;
480 st->be = 0;
481 st->bp = 0;
482 }
483
484 static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output)
485 {
486 BusChild *kid;
487 HDACodecDevice *cdev;
488
489 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
490 DeviceState *qdev = kid->child;
491 HDACodecDeviceClass *cdc;
492
493 cdev = HDA_CODEC_DEVICE(qdev);
494 cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev);
495 if (cdc->stream) {
496 cdc->stream(cdev, stream, running, output);
497 }
498 }
499 }
500
501 /* --------------------------------------------------------------------- */
502
503 static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
504 {
505 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) {
506 intel_hda_reset(DEVICE(d));
507 }
508 }
509
510 static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
511 {
512 intel_hda_update_irq(d);
513 }
514
515 static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
516 {
517 intel_hda_update_irq(d);
518 }
519
520 static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
521 {
522 intel_hda_update_irq(d);
523 }
524
525 static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg)
526 {
527 int64_t ns;
528
529 ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - d->wall_base_ns;
530 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */
531 }
532
533 static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
534 {
535 intel_hda_corb_run(d);
536 }
537
538 static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
539 {
540 intel_hda_corb_run(d);
541 }
542
543 static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
544 {
545 if (d->rirb_wp & ICH6_RIRBWP_RST) {
546 d->rirb_wp = 0;
547 }
548 }
549
550 static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
551 {
552 intel_hda_update_irq(d);
553
554 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) {
555 /* cleared ICH6_RBSTS_IRQ */
556 d->rirb_count = 0;
557 intel_hda_corb_run(d);
558 }
559 }
560
561 static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
562 {
563 if (d->ics & ICH6_IRS_BUSY) {
564 intel_hda_corb_run(d);
565 }
566 }
567
568 static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
569 {
570 bool output = reg->stream >= 4;
571 IntelHDAStream *st = d->st + reg->stream;
572
573 if (st->ctl & 0x01) {
574 /* reset */
575 dprint(d, 1, "st #%d: reset\n", reg->stream);
576 st->ctl = SD_STS_FIFO_READY << 24;
577 }
578 if ((st->ctl & 0x02) != (old & 0x02)) {
579 uint32_t stnr = (st->ctl >> 20) & 0x0f;
580 /* run bit flipped */
581 if (st->ctl & 0x02) {
582 /* start */
583 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n",
584 reg->stream, stnr, st->cbl);
585 intel_hda_parse_bdl(d, st);
586 intel_hda_notify_codecs(d, stnr, true, output);
587 } else {
588 /* stop */
589 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr);
590 intel_hda_notify_codecs(d, stnr, false, output);
591 }
592 }
593 intel_hda_update_irq(d);
594 }
595
596 /* --------------------------------------------------------------------- */
597
598 #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o))
599
600 static const struct IntelHDAReg regtab[] = {
601 /* global */
602 [ ICH6_REG_GCAP ] = {
603 .name = "GCAP",
604 .size = 2,
605 .reset = 0x4401,
606 },
607 [ ICH6_REG_VMIN ] = {
608 .name = "VMIN",
609 .size = 1,
610 },
611 [ ICH6_REG_VMAJ ] = {
612 .name = "VMAJ",
613 .size = 1,
614 .reset = 1,
615 },
616 [ ICH6_REG_OUTPAY ] = {
617 .name = "OUTPAY",
618 .size = 2,
619 .reset = 0x3c,
620 },
621 [ ICH6_REG_INPAY ] = {
622 .name = "INPAY",
623 .size = 2,
624 .reset = 0x1d,
625 },
626 [ ICH6_REG_GCTL ] = {
627 .name = "GCTL",
628 .size = 4,
629 .wmask = 0x0103,
630 .offset = offsetof(IntelHDAState, g_ctl),
631 .whandler = intel_hda_set_g_ctl,
632 },
633 [ ICH6_REG_WAKEEN ] = {
634 .name = "WAKEEN",
635 .size = 2,
636 .wmask = 0x7fff,
637 .offset = offsetof(IntelHDAState, wake_en),
638 .whandler = intel_hda_set_wake_en,
639 },
640 [ ICH6_REG_STATESTS ] = {
641 .name = "STATESTS",
642 .size = 2,
643 .wmask = 0x7fff,
644 .wclear = 0x7fff,
645 .offset = offsetof(IntelHDAState, state_sts),
646 .whandler = intel_hda_set_state_sts,
647 },
648
649 /* interrupts */
650 [ ICH6_REG_INTCTL ] = {
651 .name = "INTCTL",
652 .size = 4,
653 .wmask = 0xc00000ff,
654 .offset = offsetof(IntelHDAState, int_ctl),
655 .whandler = intel_hda_set_int_ctl,
656 },
657 [ ICH6_REG_INTSTS ] = {
658 .name = "INTSTS",
659 .size = 4,
660 .wmask = 0xc00000ff,
661 .wclear = 0xc00000ff,
662 .offset = offsetof(IntelHDAState, int_sts),
663 },
664
665 /* misc */
666 [ ICH6_REG_WALLCLK ] = {
667 .name = "WALLCLK",
668 .size = 4,
669 .offset = offsetof(IntelHDAState, wall_clk),
670 .rhandler = intel_hda_get_wall_clk,
671 },
672 [ ICH6_REG_WALLCLK + 0x2000 ] = {
673 .name = "WALLCLK(alias)",
674 .size = 4,
675 .offset = offsetof(IntelHDAState, wall_clk),
676 .rhandler = intel_hda_get_wall_clk,
677 },
678
679 /* dma engine */
680 [ ICH6_REG_CORBLBASE ] = {
681 .name = "CORBLBASE",
682 .size = 4,
683 .wmask = 0xffffff80,
684 .offset = offsetof(IntelHDAState, corb_lbase),
685 },
686 [ ICH6_REG_CORBUBASE ] = {
687 .name = "CORBUBASE",
688 .size = 4,
689 .wmask = 0xffffffff,
690 .offset = offsetof(IntelHDAState, corb_ubase),
691 },
692 [ ICH6_REG_CORBWP ] = {
693 .name = "CORBWP",
694 .size = 2,
695 .wmask = 0xff,
696 .offset = offsetof(IntelHDAState, corb_wp),
697 .whandler = intel_hda_set_corb_wp,
698 },
699 [ ICH6_REG_CORBRP ] = {
700 .name = "CORBRP",
701 .size = 2,
702 .wmask = 0x80ff,
703 .offset = offsetof(IntelHDAState, corb_rp),
704 },
705 [ ICH6_REG_CORBCTL ] = {
706 .name = "CORBCTL",
707 .size = 1,
708 .wmask = 0x03,
709 .offset = offsetof(IntelHDAState, corb_ctl),
710 .whandler = intel_hda_set_corb_ctl,
711 },
712 [ ICH6_REG_CORBSTS ] = {
713 .name = "CORBSTS",
714 .size = 1,
715 .wmask = 0x01,
716 .wclear = 0x01,
717 .offset = offsetof(IntelHDAState, corb_sts),
718 },
719 [ ICH6_REG_CORBSIZE ] = {
720 .name = "CORBSIZE",
721 .size = 1,
722 .reset = 0x42,
723 .offset = offsetof(IntelHDAState, corb_size),
724 },
725 [ ICH6_REG_RIRBLBASE ] = {
726 .name = "RIRBLBASE",
727 .size = 4,
728 .wmask = 0xffffff80,
729 .offset = offsetof(IntelHDAState, rirb_lbase),
730 },
731 [ ICH6_REG_RIRBUBASE ] = {
732 .name = "RIRBUBASE",
733 .size = 4,
734 .wmask = 0xffffffff,
735 .offset = offsetof(IntelHDAState, rirb_ubase),
736 },
737 [ ICH6_REG_RIRBWP ] = {
738 .name = "RIRBWP",
739 .size = 2,
740 .wmask = 0x8000,
741 .offset = offsetof(IntelHDAState, rirb_wp),
742 .whandler = intel_hda_set_rirb_wp,
743 },
744 [ ICH6_REG_RINTCNT ] = {
745 .name = "RINTCNT",
746 .size = 2,
747 .wmask = 0xff,
748 .offset = offsetof(IntelHDAState, rirb_cnt),
749 },
750 [ ICH6_REG_RIRBCTL ] = {
751 .name = "RIRBCTL",
752 .size = 1,
753 .wmask = 0x07,
754 .offset = offsetof(IntelHDAState, rirb_ctl),
755 },
756 [ ICH6_REG_RIRBSTS ] = {
757 .name = "RIRBSTS",
758 .size = 1,
759 .wmask = 0x05,
760 .wclear = 0x05,
761 .offset = offsetof(IntelHDAState, rirb_sts),
762 .whandler = intel_hda_set_rirb_sts,
763 },
764 [ ICH6_REG_RIRBSIZE ] = {
765 .name = "RIRBSIZE",
766 .size = 1,
767 .reset = 0x42,
768 .offset = offsetof(IntelHDAState, rirb_size),
769 },
770
771 [ ICH6_REG_DPLBASE ] = {
772 .name = "DPLBASE",
773 .size = 4,
774 .wmask = 0xffffff81,
775 .offset = offsetof(IntelHDAState, dp_lbase),
776 },
777 [ ICH6_REG_DPUBASE ] = {
778 .name = "DPUBASE",
779 .size = 4,
780 .wmask = 0xffffffff,
781 .offset = offsetof(IntelHDAState, dp_ubase),
782 },
783
784 [ ICH6_REG_IC ] = {
785 .name = "ICW",
786 .size = 4,
787 .wmask = 0xffffffff,
788 .offset = offsetof(IntelHDAState, icw),
789 },
790 [ ICH6_REG_IR ] = {
791 .name = "IRR",
792 .size = 4,
793 .offset = offsetof(IntelHDAState, irr),
794 },
795 [ ICH6_REG_IRS ] = {
796 .name = "ICS",
797 .size = 2,
798 .wmask = 0x0003,
799 .wclear = 0x0002,
800 .offset = offsetof(IntelHDAState, ics),
801 .whandler = intel_hda_set_ics,
802 },
803
804 #define HDA_STREAM(_t, _i) \
805 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \
806 .stream = _i, \
807 .name = _t stringify(_i) " CTL", \
808 .size = 4, \
809 .wmask = 0x1cff001f, \
810 .offset = offsetof(IntelHDAState, st[_i].ctl), \
811 .whandler = intel_hda_set_st_ctl, \
812 }, \
813 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \
814 .stream = _i, \
815 .name = _t stringify(_i) " CTL(stnr)", \
816 .size = 1, \
817 .shift = 16, \
818 .wmask = 0x00ff0000, \
819 .offset = offsetof(IntelHDAState, st[_i].ctl), \
820 .whandler = intel_hda_set_st_ctl, \
821 }, \
822 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \
823 .stream = _i, \
824 .name = _t stringify(_i) " CTL(sts)", \
825 .size = 1, \
826 .shift = 24, \
827 .wmask = 0x1c000000, \
828 .wclear = 0x1c000000, \
829 .offset = offsetof(IntelHDAState, st[_i].ctl), \
830 .whandler = intel_hda_set_st_ctl, \
831 .reset = SD_STS_FIFO_READY << 24 \
832 }, \
833 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \
834 .stream = _i, \
835 .name = _t stringify(_i) " LPIB", \
836 .size = 4, \
837 .offset = offsetof(IntelHDAState, st[_i].lpib), \
838 }, \
839 [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \
840 .stream = _i, \
841 .name = _t stringify(_i) " LPIB(alias)", \
842 .size = 4, \
843 .offset = offsetof(IntelHDAState, st[_i].lpib), \
844 }, \
845 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \
846 .stream = _i, \
847 .name = _t stringify(_i) " CBL", \
848 .size = 4, \
849 .wmask = 0xffffffff, \
850 .offset = offsetof(IntelHDAState, st[_i].cbl), \
851 }, \
852 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \
853 .stream = _i, \
854 .name = _t stringify(_i) " LVI", \
855 .size = 2, \
856 .wmask = 0x00ff, \
857 .offset = offsetof(IntelHDAState, st[_i].lvi), \
858 }, \
859 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \
860 .stream = _i, \
861 .name = _t stringify(_i) " FIFOS", \
862 .size = 2, \
863 .reset = HDA_BUFFER_SIZE, \
864 }, \
865 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \
866 .stream = _i, \
867 .name = _t stringify(_i) " FMT", \
868 .size = 2, \
869 .wmask = 0x7f7f, \
870 .offset = offsetof(IntelHDAState, st[_i].fmt), \
871 }, \
872 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \
873 .stream = _i, \
874 .name = _t stringify(_i) " BDLPL", \
875 .size = 4, \
876 .wmask = 0xffffff80, \
877 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \
878 }, \
879 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \
880 .stream = _i, \
881 .name = _t stringify(_i) " BDLPU", \
882 .size = 4, \
883 .wmask = 0xffffffff, \
884 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \
885 }, \
886
887 HDA_STREAM("IN", 0)
888 HDA_STREAM("IN", 1)
889 HDA_STREAM("IN", 2)
890 HDA_STREAM("IN", 3)
891
892 HDA_STREAM("OUT", 4)
893 HDA_STREAM("OUT", 5)
894 HDA_STREAM("OUT", 6)
895 HDA_STREAM("OUT", 7)
896
897 };
898
899 static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr)
900 {
901 const IntelHDAReg *reg;
902
903 if (addr >= ARRAY_SIZE(regtab)) {
904 goto noreg;
905 }
906 reg = regtab+addr;
907 if (reg->name == NULL) {
908 goto noreg;
909 }
910 return reg;
911
912 noreg:
913 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr);
914 return NULL;
915 }
916
917 static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg)
918 {
919 uint8_t *addr = (void*)d;
920
921 addr += reg->offset;
922 return (uint32_t*)addr;
923 }
924
925 static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val,
926 uint32_t wmask)
927 {
928 uint32_t *addr;
929 uint32_t old;
930
931 if (!reg) {
932 return;
933 }
934 if (!reg->wmask) {
935 qemu_log_mask(LOG_GUEST_ERROR, "intel-hda: write to r/o reg %s\n",
936 reg->name);
937 return;
938 }
939
940 if (d->debug) {
941 time_t now = time(NULL);
942 if (d->last_write && d->last_reg == reg && d->last_val == val) {
943 d->repeat_count++;
944 if (d->last_sec != now) {
945 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
946 d->last_sec = now;
947 d->repeat_count = 0;
948 }
949 } else {
950 if (d->repeat_count) {
951 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
952 }
953 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask);
954 d->last_write = 1;
955 d->last_reg = reg;
956 d->last_val = val;
957 d->last_sec = now;
958 d->repeat_count = 0;
959 }
960 }
961 assert(reg->offset != 0);
962
963 addr = intel_hda_reg_addr(d, reg);
964 old = *addr;
965
966 if (reg->shift) {
967 val <<= reg->shift;
968 wmask <<= reg->shift;
969 }
970 wmask &= reg->wmask;
971 *addr &= ~wmask;
972 *addr |= wmask & val;
973 *addr &= ~(val & reg->wclear);
974
975 if (reg->whandler) {
976 reg->whandler(d, reg, old);
977 }
978 }
979
980 static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg,
981 uint32_t rmask)
982 {
983 uint32_t *addr, ret;
984
985 if (!reg) {
986 return 0;
987 }
988
989 if (reg->rhandler) {
990 reg->rhandler(d, reg);
991 }
992
993 if (reg->offset == 0) {
994 /* constant read-only register */
995 ret = reg->reset;
996 } else {
997 addr = intel_hda_reg_addr(d, reg);
998 ret = *addr;
999 if (reg->shift) {
1000 ret >>= reg->shift;
1001 }
1002 ret &= rmask;
1003 }
1004 if (d->debug) {
1005 time_t now = time(NULL);
1006 if (!d->last_write && d->last_reg == reg && d->last_val == ret) {
1007 d->repeat_count++;
1008 if (d->last_sec != now) {
1009 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1010 d->last_sec = now;
1011 d->repeat_count = 0;
1012 }
1013 } else {
1014 if (d->repeat_count) {
1015 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1016 }
1017 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask);
1018 d->last_write = 0;
1019 d->last_reg = reg;
1020 d->last_val = ret;
1021 d->last_sec = now;
1022 d->repeat_count = 0;
1023 }
1024 }
1025 return ret;
1026 }
1027
1028 static void intel_hda_regs_reset(IntelHDAState *d)
1029 {
1030 uint32_t *addr;
1031 int i;
1032
1033 for (i = 0; i < ARRAY_SIZE(regtab); i++) {
1034 if (regtab[i].name == NULL) {
1035 continue;
1036 }
1037 if (regtab[i].offset == 0) {
1038 continue;
1039 }
1040 addr = intel_hda_reg_addr(d, regtab + i);
1041 *addr = regtab[i].reset;
1042 }
1043 }
1044
1045 /* --------------------------------------------------------------------- */
1046
1047 static void intel_hda_mmio_write(void *opaque, hwaddr addr, uint64_t val,
1048 unsigned size)
1049 {
1050 IntelHDAState *d = opaque;
1051 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1052
1053 intel_hda_reg_write(d, reg, val, MAKE_64BIT_MASK(0, size * 8));
1054 }
1055
1056 static uint64_t intel_hda_mmio_read(void *opaque, hwaddr addr, unsigned size)
1057 {
1058 IntelHDAState *d = opaque;
1059 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1060
1061 return intel_hda_reg_read(d, reg, MAKE_64BIT_MASK(0, size * 8));
1062 }
1063
1064 static const MemoryRegionOps intel_hda_mmio_ops = {
1065 .read = intel_hda_mmio_read,
1066 .write = intel_hda_mmio_write,
1067 .impl = {
1068 .min_access_size = 1,
1069 .max_access_size = 4,
1070 },
1071 .endianness = DEVICE_NATIVE_ENDIAN,
1072 };
1073
1074 /* --------------------------------------------------------------------- */
1075
1076 static void intel_hda_reset(DeviceState *dev)
1077 {
1078 BusChild *kid;
1079 IntelHDAState *d = INTEL_HDA(dev);
1080 HDACodecDevice *cdev;
1081
1082 intel_hda_regs_reset(d);
1083 d->wall_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1084
1085 /* reset codecs */
1086 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
1087 DeviceState *qdev = kid->child;
1088 cdev = HDA_CODEC_DEVICE(qdev);
1089 device_reset(DEVICE(cdev));
1090 d->state_sts |= (1 << cdev->cad);
1091 }
1092 intel_hda_update_irq(d);
1093 }
1094
1095 static void intel_hda_realize(PCIDevice *pci, Error **errp)
1096 {
1097 IntelHDAState *d = INTEL_HDA(pci);
1098 uint8_t *conf = d->pci.config;
1099 Error *err = NULL;
1100 int ret;
1101
1102 d->name = object_get_typename(OBJECT(d));
1103
1104 pci_config_set_interrupt_pin(conf, 1);
1105
1106 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1107 conf[0x40] = 0x01;
1108
1109 if (d->msi != ON_OFF_AUTO_OFF) {
1110 ret = msi_init(&d->pci, d->old_msi_addr ? 0x50 : 0x60,
1111 1, true, false, &err);
1112 /* Any error other than -ENOTSUP(board's MSI support is broken)
1113 * is a programming error */
1114 assert(!ret || ret == -ENOTSUP);
1115 if (ret && d->msi == ON_OFF_AUTO_ON) {
1116 /* Can't satisfy user's explicit msi=on request, fail */
1117 error_append_hint(&err, "You have to use msi=auto (default) or "
1118 "msi=off with this machine type.\n");
1119 error_propagate(errp, err);
1120 return;
1121 }
1122 assert(!err || d->msi == ON_OFF_AUTO_AUTO);
1123 /* With msi=auto, we fall back to MSI off silently */
1124 error_free(err);
1125 }
1126
1127 memory_region_init_io(&d->mmio, OBJECT(d), &intel_hda_mmio_ops, d,
1128 "intel-hda", 0x4000);
1129 pci_register_bar(&d->pci, 0, 0, &d->mmio);
1130
1131 hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs),
1132 intel_hda_response, intel_hda_xfer);
1133 }
1134
1135 static void intel_hda_exit(PCIDevice *pci)
1136 {
1137 IntelHDAState *d = INTEL_HDA(pci);
1138
1139 msi_uninit(&d->pci);
1140 }
1141
1142 static int intel_hda_post_load(void *opaque, int version)
1143 {
1144 IntelHDAState* d = opaque;
1145 int i;
1146
1147 dprint(d, 1, "%s\n", __func__);
1148 for (i = 0; i < ARRAY_SIZE(d->st); i++) {
1149 if (d->st[i].ctl & 0x02) {
1150 intel_hda_parse_bdl(d, &d->st[i]);
1151 }
1152 }
1153 intel_hda_update_irq(d);
1154 return 0;
1155 }
1156
1157 static const VMStateDescription vmstate_intel_hda_stream = {
1158 .name = "intel-hda-stream",
1159 .version_id = 1,
1160 .fields = (VMStateField[]) {
1161 VMSTATE_UINT32(ctl, IntelHDAStream),
1162 VMSTATE_UINT32(lpib, IntelHDAStream),
1163 VMSTATE_UINT32(cbl, IntelHDAStream),
1164 VMSTATE_UINT32(lvi, IntelHDAStream),
1165 VMSTATE_UINT32(fmt, IntelHDAStream),
1166 VMSTATE_UINT32(bdlp_lbase, IntelHDAStream),
1167 VMSTATE_UINT32(bdlp_ubase, IntelHDAStream),
1168 VMSTATE_END_OF_LIST()
1169 }
1170 };
1171
1172 static const VMStateDescription vmstate_intel_hda = {
1173 .name = "intel-hda",
1174 .version_id = 1,
1175 .post_load = intel_hda_post_load,
1176 .fields = (VMStateField[]) {
1177 VMSTATE_PCI_DEVICE(pci, IntelHDAState),
1178
1179 /* registers */
1180 VMSTATE_UINT32(g_ctl, IntelHDAState),
1181 VMSTATE_UINT32(wake_en, IntelHDAState),
1182 VMSTATE_UINT32(state_sts, IntelHDAState),
1183 VMSTATE_UINT32(int_ctl, IntelHDAState),
1184 VMSTATE_UINT32(int_sts, IntelHDAState),
1185 VMSTATE_UINT32(wall_clk, IntelHDAState),
1186 VMSTATE_UINT32(corb_lbase, IntelHDAState),
1187 VMSTATE_UINT32(corb_ubase, IntelHDAState),
1188 VMSTATE_UINT32(corb_rp, IntelHDAState),
1189 VMSTATE_UINT32(corb_wp, IntelHDAState),
1190 VMSTATE_UINT32(corb_ctl, IntelHDAState),
1191 VMSTATE_UINT32(corb_sts, IntelHDAState),
1192 VMSTATE_UINT32(corb_size, IntelHDAState),
1193 VMSTATE_UINT32(rirb_lbase, IntelHDAState),
1194 VMSTATE_UINT32(rirb_ubase, IntelHDAState),
1195 VMSTATE_UINT32(rirb_wp, IntelHDAState),
1196 VMSTATE_UINT32(rirb_cnt, IntelHDAState),
1197 VMSTATE_UINT32(rirb_ctl, IntelHDAState),
1198 VMSTATE_UINT32(rirb_sts, IntelHDAState),
1199 VMSTATE_UINT32(rirb_size, IntelHDAState),
1200 VMSTATE_UINT32(dp_lbase, IntelHDAState),
1201 VMSTATE_UINT32(dp_ubase, IntelHDAState),
1202 VMSTATE_UINT32(icw, IntelHDAState),
1203 VMSTATE_UINT32(irr, IntelHDAState),
1204 VMSTATE_UINT32(ics, IntelHDAState),
1205 VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0,
1206 vmstate_intel_hda_stream,
1207 IntelHDAStream),
1208
1209 /* additional state info */
1210 VMSTATE_UINT32(rirb_count, IntelHDAState),
1211 VMSTATE_INT64(wall_base_ns, IntelHDAState),
1212
1213 VMSTATE_END_OF_LIST()
1214 }
1215 };
1216
1217 static Property intel_hda_properties[] = {
1218 DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0),
1219 DEFINE_PROP_ON_OFF_AUTO("msi", IntelHDAState, msi, ON_OFF_AUTO_AUTO),
1220 DEFINE_PROP_BOOL("old_msi_addr", IntelHDAState, old_msi_addr, false),
1221 DEFINE_PROP_END_OF_LIST(),
1222 };
1223
1224 static void intel_hda_class_init(ObjectClass *klass, void *data)
1225 {
1226 DeviceClass *dc = DEVICE_CLASS(klass);
1227 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1228
1229 k->realize = intel_hda_realize;
1230 k->exit = intel_hda_exit;
1231 k->vendor_id = PCI_VENDOR_ID_INTEL;
1232 k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO;
1233 dc->reset = intel_hda_reset;
1234 dc->vmsd = &vmstate_intel_hda;
1235 dc->props = intel_hda_properties;
1236 }
1237
1238 static void intel_hda_class_init_ich6(ObjectClass *klass, void *data)
1239 {
1240 DeviceClass *dc = DEVICE_CLASS(klass);
1241 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1242
1243 k->device_id = 0x2668;
1244 k->revision = 1;
1245 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
1246 dc->desc = "Intel HD Audio Controller (ich6)";
1247 }
1248
1249 static void intel_hda_class_init_ich9(ObjectClass *klass, void *data)
1250 {
1251 DeviceClass *dc = DEVICE_CLASS(klass);
1252 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1253
1254 k->device_id = 0x293e;
1255 k->revision = 3;
1256 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
1257 dc->desc = "Intel HD Audio Controller (ich9)";
1258 }
1259
1260 static const TypeInfo intel_hda_info = {
1261 .name = TYPE_INTEL_HDA_GENERIC,
1262 .parent = TYPE_PCI_DEVICE,
1263 .instance_size = sizeof(IntelHDAState),
1264 .class_init = intel_hda_class_init,
1265 .abstract = true,
1266 .interfaces = (InterfaceInfo[]) {
1267 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1268 { },
1269 },
1270 };
1271
1272 static const TypeInfo intel_hda_info_ich6 = {
1273 .name = "intel-hda",
1274 .parent = TYPE_INTEL_HDA_GENERIC,
1275 .class_init = intel_hda_class_init_ich6,
1276 };
1277
1278 static const TypeInfo intel_hda_info_ich9 = {
1279 .name = "ich9-intel-hda",
1280 .parent = TYPE_INTEL_HDA_GENERIC,
1281 .class_init = intel_hda_class_init_ich9,
1282 };
1283
1284 static void hda_codec_device_class_init(ObjectClass *klass, void *data)
1285 {
1286 DeviceClass *k = DEVICE_CLASS(klass);
1287 k->realize = hda_codec_dev_realize;
1288 k->unrealize = hda_codec_dev_unrealize;
1289 set_bit(DEVICE_CATEGORY_SOUND, k->categories);
1290 k->bus_type = TYPE_HDA_BUS;
1291 k->props = hda_props;
1292 }
1293
1294 static const TypeInfo hda_codec_device_type_info = {
1295 .name = TYPE_HDA_CODEC_DEVICE,
1296 .parent = TYPE_DEVICE,
1297 .instance_size = sizeof(HDACodecDevice),
1298 .abstract = true,
1299 .class_size = sizeof(HDACodecDeviceClass),
1300 .class_init = hda_codec_device_class_init,
1301 };
1302
1303 /*
1304 * create intel hda controller with codec attached to it,
1305 * so '-soundhw hda' works.
1306 */
1307 static int intel_hda_and_codec_init(PCIBus *bus)
1308 {
1309 DeviceState *controller;
1310 BusState *hdabus;
1311 DeviceState *codec;
1312
1313 controller = DEVICE(pci_create_simple(bus, -1, "intel-hda"));
1314 hdabus = QLIST_FIRST(&controller->child_bus);
1315 codec = qdev_create(hdabus, "hda-duplex");
1316 qdev_init_nofail(codec);
1317 return 0;
1318 }
1319
1320 static void intel_hda_register_types(void)
1321 {
1322 type_register_static(&hda_codec_bus_info);
1323 type_register_static(&intel_hda_info);
1324 type_register_static(&intel_hda_info_ich6);
1325 type_register_static(&intel_hda_info_ich9);
1326 type_register_static(&hda_codec_device_type_info);
1327 pci_register_soundhw("hda", "Intel HD Audio", intel_hda_and_codec_init);
1328 }
1329
1330 type_init(intel_hda_register_types)
AR7 emulation for QEMU