2 * internal execution defines for qemu
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu-common.h"
24 #include "exec/tb-context.h"
26 /* allow to see translation results - the slowdown should be negligible, so we leave it */
29 /* Page tracking code uses ram addresses in system mode, and virtual
30 addresses in userspace mode. Define tb_page_addr_t to be an appropriate
32 #if defined(CONFIG_USER_ONLY)
33 typedef abi_ulong tb_page_addr_t
;
34 #define TB_PAGE_ADDR_FMT TARGET_ABI_FMT_lx
36 typedef ram_addr_t tb_page_addr_t
;
37 #define TB_PAGE_ADDR_FMT RAM_ADDR_FMT
42 void gen_intermediate_code(CPUState
*cpu
, struct TranslationBlock
*tb
);
43 void restore_state_to_opc(CPUArchState
*env
, struct TranslationBlock
*tb
,
46 void cpu_gen_init(void);
47 bool cpu_restore_state(CPUState
*cpu
, uintptr_t searched_pc
);
49 void QEMU_NORETURN
cpu_loop_exit_noexc(CPUState
*cpu
);
50 void QEMU_NORETURN
cpu_io_recompile(CPUState
*cpu
, uintptr_t retaddr
);
51 TranslationBlock
*tb_gen_code(CPUState
*cpu
,
52 target_ulong pc
, target_ulong cs_base
,
56 void QEMU_NORETURN
cpu_loop_exit(CPUState
*cpu
);
57 void QEMU_NORETURN
cpu_loop_exit_restore(CPUState
*cpu
, uintptr_t pc
);
58 void QEMU_NORETURN
cpu_loop_exit_atomic(CPUState
*cpu
, uintptr_t pc
);
60 #if !defined(CONFIG_USER_ONLY)
61 void cpu_reloading_memory_map(void);
63 * cpu_address_space_init:
64 * @cpu: CPU to add this address space to
65 * @as: address space to add
66 * @asidx: integer index of this address space
68 * Add the specified address space to the CPU's cpu_ases list.
69 * The address space added with @asidx 0 is the one used for the
70 * convenience pointer cpu->as.
71 * The target-specific code which registers ASes is responsible
72 * for defining what semantics address space 0, 1, 2, etc have.
74 * Before the first call to this function, the caller must set
75 * cpu->num_ases to the total number of address spaces it needs
78 * Note that with KVM only one address space is supported.
80 void cpu_address_space_init(CPUState
*cpu
, AddressSpace
*as
, int asidx
);
83 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
87 * @cpu: CPU whose TLB should be flushed
88 * @addr: virtual address of page to be flushed
90 * Flush one page from the TLB of the specified CPU, for all
93 void tlb_flush_page(CPUState
*cpu
, target_ulong addr
);
95 * tlb_flush_page_all_cpus:
96 * @cpu: src CPU of the flush
97 * @addr: virtual address of page to be flushed
99 * Flush one page from the TLB of the specified CPU, for all
102 void tlb_flush_page_all_cpus(CPUState
*src
, target_ulong addr
);
104 * tlb_flush_page_all_cpus_synced:
105 * @cpu: src CPU of the flush
106 * @addr: virtual address of page to be flushed
108 * Flush one page from the TLB of the specified CPU, for all MMU
109 * indexes like tlb_flush_page_all_cpus except the source vCPUs work
110 * is scheduled as safe work meaning all flushes will be complete once
111 * the source vCPUs safe work is complete. This will depend on when
112 * the guests translation ends the TB.
114 void tlb_flush_page_all_cpus_synced(CPUState
*src
, target_ulong addr
);
117 * @cpu: CPU whose TLB should be flushed
119 * Flush the entire TLB for the specified CPU. Most CPU architectures
120 * allow the implementation to drop entries from the TLB at any time
121 * so this is generally safe. If more selective flushing is required
122 * use one of the other functions for efficiency.
124 void tlb_flush(CPUState
*cpu
);
126 * tlb_flush_all_cpus:
127 * @cpu: src CPU of the flush
129 void tlb_flush_all_cpus(CPUState
*src_cpu
);
131 * tlb_flush_all_cpus_synced:
132 * @cpu: src CPU of the flush
134 * Like tlb_flush_all_cpus except this except the source vCPUs work is
135 * scheduled as safe work meaning all flushes will be complete once
136 * the source vCPUs safe work is complete. This will depend on when
137 * the guests translation ends the TB.
139 void tlb_flush_all_cpus_synced(CPUState
*src_cpu
);
141 * tlb_flush_page_by_mmuidx:
142 * @cpu: CPU whose TLB should be flushed
143 * @addr: virtual address of page to be flushed
144 * @idxmap: bitmap of MMU indexes to flush
146 * Flush one page from the TLB of the specified CPU, for the specified
149 void tlb_flush_page_by_mmuidx(CPUState
*cpu
, target_ulong addr
,
152 * tlb_flush_page_by_mmuidx_all_cpus:
153 * @cpu: Originating CPU of the flush
154 * @addr: virtual address of page to be flushed
155 * @idxmap: bitmap of MMU indexes to flush
157 * Flush one page from the TLB of all CPUs, for the specified
160 void tlb_flush_page_by_mmuidx_all_cpus(CPUState
*cpu
, target_ulong addr
,
163 * tlb_flush_page_by_mmuidx_all_cpus_synced:
164 * @cpu: Originating CPU of the flush
165 * @addr: virtual address of page to be flushed
166 * @idxmap: bitmap of MMU indexes to flush
168 * Flush one page from the TLB of all CPUs, for the specified MMU
169 * indexes like tlb_flush_page_by_mmuidx_all_cpus except the source
170 * vCPUs work is scheduled as safe work meaning all flushes will be
171 * complete once the source vCPUs safe work is complete. This will
172 * depend on when the guests translation ends the TB.
174 void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState
*cpu
, target_ulong addr
,
177 * tlb_flush_by_mmuidx:
178 * @cpu: CPU whose TLB should be flushed
179 * @wait: If true ensure synchronisation by exiting the cpu_loop
180 * @idxmap: bitmap of MMU indexes to flush
182 * Flush all entries from the TLB of the specified CPU, for the specified
185 void tlb_flush_by_mmuidx(CPUState
*cpu
, uint16_t idxmap
);
187 * tlb_flush_by_mmuidx_all_cpus:
188 * @cpu: Originating CPU of the flush
189 * @idxmap: bitmap of MMU indexes to flush
191 * Flush all entries from all TLBs of all CPUs, for the specified
194 void tlb_flush_by_mmuidx_all_cpus(CPUState
*cpu
, uint16_t idxmap
);
196 * tlb_flush_by_mmuidx_all_cpus_synced:
197 * @cpu: Originating CPU of the flush
198 * @idxmap: bitmap of MMU indexes to flush
200 * Flush all entries from all TLBs of all CPUs, for the specified
201 * MMU indexes like tlb_flush_by_mmuidx_all_cpus except except the source
202 * vCPUs work is scheduled as safe work meaning all flushes will be
203 * complete once the source vCPUs safe work is complete. This will
204 * depend on when the guests translation ends the TB.
206 void tlb_flush_by_mmuidx_all_cpus_synced(CPUState
*cpu
, uint16_t idxmap
);
208 * tlb_set_page_with_attrs:
209 * @cpu: CPU to add this TLB entry for
210 * @vaddr: virtual address of page to add entry for
211 * @paddr: physical address of the page
212 * @attrs: memory transaction attributes
213 * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)
214 * @mmu_idx: MMU index to insert TLB entry for
215 * @size: size of the page in bytes
217 * Add an entry to this CPU's TLB (a mapping from virtual address
218 * @vaddr to physical address @paddr) with the specified memory
219 * transaction attributes. This is generally called by the target CPU
220 * specific code after it has been called through the tlb_fill()
221 * entry point and performed a successful page table walk to find
222 * the physical address and attributes for the virtual address
223 * which provoked the TLB miss.
225 * At most one entry for a given virtual address is permitted. Only a
226 * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only
227 * used by tlb_flush_page.
229 void tlb_set_page_with_attrs(CPUState
*cpu
, target_ulong vaddr
,
230 hwaddr paddr
, MemTxAttrs attrs
,
231 int prot
, int mmu_idx
, target_ulong size
);
234 * This function is equivalent to calling tlb_set_page_with_attrs()
235 * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided
236 * as a convenience for CPUs which don't use memory transaction attributes.
238 void tlb_set_page(CPUState
*cpu
, target_ulong vaddr
,
239 hwaddr paddr
, int prot
,
240 int mmu_idx
, target_ulong size
);
241 void tb_invalidate_phys_addr(AddressSpace
*as
, hwaddr addr
);
242 void probe_write(CPUArchState
*env
, target_ulong addr
, int mmu_idx
,
245 static inline void tlb_flush_page(CPUState
*cpu
, target_ulong addr
)
248 static inline void tlb_flush_page_all_cpus(CPUState
*src
, target_ulong addr
)
251 static inline void tlb_flush_page_all_cpus_synced(CPUState
*src
,
255 static inline void tlb_flush(CPUState
*cpu
)
258 static inline void tlb_flush_all_cpus(CPUState
*src_cpu
)
261 static inline void tlb_flush_all_cpus_synced(CPUState
*src_cpu
)
264 static inline void tlb_flush_page_by_mmuidx(CPUState
*cpu
,
265 target_ulong addr
, uint16_t idxmap
)
269 static inline void tlb_flush_by_mmuidx(CPUState
*cpu
, uint16_t idxmap
)
272 static inline void tlb_flush_page_by_mmuidx_all_cpus(CPUState
*cpu
,
277 static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState
*cpu
,
282 static inline void tlb_flush_by_mmuidx_all_cpus(CPUState
*cpu
, uint16_t idxmap
)
285 static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState
*cpu
,
289 static inline void tb_invalidate_phys_addr(AddressSpace
*as
, hwaddr addr
)
294 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
296 /* Estimated block size for TB allocation. */
297 /* ??? The following is based on a 2015 survey of x86_64 host output.
298 Better would seem to be some sort of dynamically sized TB array,
299 adapting to the block sizes actually being produced. */
300 #if defined(CONFIG_SOFTMMU)
301 #define CODE_GEN_AVG_BLOCK_SIZE 400
303 #define CODE_GEN_AVG_BLOCK_SIZE 150
307 * Translation Cache-related fields of a TB.
310 void *ptr
; /* pointer to the translated code */
311 uint8_t *search
; /* pointer to search data */
314 struct TranslationBlock
{
315 target_ulong pc
; /* simulated PC corresponding to this block (EIP + CS base) */
316 target_ulong cs_base
; /* CS base for this block */
317 uint32_t flags
; /* flags defining in which context the code was generated */
318 uint16_t size
; /* size of target code for this block (1 <=
319 size <= TARGET_PAGE_SIZE) */
321 uint32_t cflags
; /* compile flags */
322 #define CF_COUNT_MASK 0x7fff
323 #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
324 #define CF_NOCACHE 0x10000 /* To be freed after execution */
325 #define CF_USE_ICOUNT 0x20000
326 #define CF_IGNORE_ICOUNT 0x40000 /* Do not generate icount code */
327 #define CF_INVALID 0x80000 /* TB is stale. Setters must acquire tb_lock */
328 #define CF_PARALLEL 0x100000 /* Generate code for a parallel context */
329 /* cflags' mask for hashing/comparison */
330 #define CF_HASH_MASK (CF_PARALLEL)
332 /* Per-vCPU dynamic tracing state used to generate this TB */
333 uint32_t trace_vcpu_dstate
;
337 /* original tb when cflags has CF_NOCACHE */
338 struct TranslationBlock
*orig_tb
;
339 /* first and second physical page containing code. The lower bit
340 of the pointer tells the index in page_next[] */
341 struct TranslationBlock
*page_next
[2];
342 tb_page_addr_t page_addr
[2];
344 /* The following data are used to directly call another TB from
345 * the code of this one. This can be done either by emitting direct or
346 * indirect native jump instructions. These jumps are reset so that the TB
347 * just continues its execution. The TB can be linked to another one by
348 * setting one of the jump targets (or patching the jump instruction). Only
349 * two of such jumps are supported.
351 uint16_t jmp_reset_offset
[2]; /* offset of original jump target */
352 #define TB_JMP_RESET_OFFSET_INVALID 0xffff /* indicates no jump generated */
353 uintptr_t jmp_target_arg
[2]; /* target address or offset */
355 /* Each TB has an associated circular list of TBs jumping to this one.
356 * jmp_list_first points to the first TB jumping to this one.
357 * jmp_list_next is used to point to the next TB in a list.
358 * Since each TB can have two jumps, it can participate in two lists.
359 * jmp_list_first and jmp_list_next are 4-byte aligned pointers to a
360 * TranslationBlock structure, but the two least significant bits of
361 * them are used to encode which data field of the pointed TB should
362 * be used to traverse the list further from that TB:
363 * 0 => jmp_list_next[0], 1 => jmp_list_next[1], 2 => jmp_list_first.
364 * In other words, 0/1 tells which jump is used in the pointed TB,
365 * and 2 means that this is a pointer back to the target TB of this list.
367 uintptr_t jmp_list_next
[2];
368 uintptr_t jmp_list_first
;
371 extern bool parallel_cpus
;
373 /* Hide the atomic_read to make code a little easier on the eyes */
374 static inline uint32_t tb_cflags(const TranslationBlock
*tb
)
376 return atomic_read(&tb
->cflags
);
379 /* current cflags for hashing/comparison */
380 static inline uint32_t curr_cflags(void)
382 return parallel_cpus
? CF_PARALLEL
: 0;
385 void tb_free(TranslationBlock
*tb
);
386 void tb_flush(CPUState
*cpu
);
387 void tb_phys_invalidate(TranslationBlock
*tb
, tb_page_addr_t page_addr
);
388 TranslationBlock
*tb_htable_lookup(CPUState
*cpu
, target_ulong pc
,
389 target_ulong cs_base
, uint32_t flags
,
391 void tb_set_jmp_target(TranslationBlock
*tb
, int n
, uintptr_t addr
);
393 /* GETPC is the true target of the return instruction that we'll execute. */
394 #if defined(CONFIG_TCG_INTERPRETER)
395 extern uintptr_t tci_tb_ptr
;
396 # define GETPC() tci_tb_ptr
399 ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
402 /* The true return address will often point to a host insn that is part of
403 the next translated guest insn. Adjust the address backward to point to
404 the middle of the call insn. Subtracting one would do the job except for
405 several compressed mode architectures (arm, mips) which set the low bit
406 to indicate the compressed mode; subtracting two works around that. It
407 is also the case that there are no host isas that contain a call insn
408 smaller than 4 bytes, so we don't worry about special-casing this. */
412 void tb_unlock(void);
413 void tb_lock_reset(void);
415 #if !defined(CONFIG_USER_ONLY)
417 struct MemoryRegion
*iotlb_to_region(CPUState
*cpu
,
418 hwaddr index
, MemTxAttrs attrs
);
420 void tlb_fill(CPUState
*cpu
, target_ulong addr
, MMUAccessType access_type
,
421 int mmu_idx
, uintptr_t retaddr
);
425 #if defined(CONFIG_USER_ONLY)
426 void mmap_lock(void);
427 void mmap_unlock(void);
428 bool have_mmap_lock(void);
430 static inline tb_page_addr_t
get_page_addr_code(CPUArchState
*env1
, target_ulong addr
)
435 static inline void mmap_lock(void) {}
436 static inline void mmap_unlock(void) {}
439 tb_page_addr_t
get_page_addr_code(CPUArchState
*env1
, target_ulong addr
);
441 void tlb_reset_dirty(CPUState
*cpu
, ram_addr_t start1
, ram_addr_t length
);
442 void tlb_set_dirty(CPUState
*cpu
, target_ulong vaddr
);
445 void tb_flush_jmp_cache(CPUState
*cpu
, target_ulong addr
);
447 MemoryRegionSection
*
448 address_space_translate_for_iotlb(CPUState
*cpu
, int asidx
, hwaddr addr
,
449 hwaddr
*xlat
, hwaddr
*plen
);
450 hwaddr
memory_region_section_get_iotlb(CPUState
*cpu
,
451 MemoryRegionSection
*section
,
453 hwaddr paddr
, hwaddr xlat
,
455 target_ulong
*address
);
456 bool memory_region_is_unassigned(MemoryRegion
*mr
);
461 extern int singlestep
;