2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 /* define it to use liveness analysis (better code) */
26 #define USE_LIVENESS_ANALYSIS
27 #define USE_TCG_OPTIMIZATIONS
31 /* Define to jump the ELF file used to communicate with GDB. */
34 #if !defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG)
35 /* define it to suppress various consistency checks (faster) */
39 #include "qemu-common.h"
40 #include "qemu/cache-utils.h"
41 #include "qemu/host-utils.h"
42 #include "qemu/timer.h"
44 /* Note: the long term plan is to reduce the dependencies on the QEMU
45 CPU definitions. Currently they are used for qemu_ld/st
47 #define NO_CPU_IO_DEFS
52 #if UINTPTR_MAX == UINT32_MAX
53 # define ELF_CLASS ELFCLASS32
55 # define ELF_CLASS ELFCLASS64
57 #ifdef HOST_WORDS_BIGENDIAN
58 # define ELF_DATA ELFDATA2MSB
60 # define ELF_DATA ELFDATA2LSB
65 /* Forward declarations for functions declared in tcg-target.c and used here. */
66 static void tcg_target_init(TCGContext
*s
);
67 static void tcg_target_qemu_prologue(TCGContext
*s
);
68 static void patch_reloc(tcg_insn_unit
*code_ptr
, int type
,
69 intptr_t value
, intptr_t addend
);
71 /* The CIE and FDE header definitions will be common to all hosts. */
73 uint32_t len
__attribute__((aligned((sizeof(void *)))));
79 uint8_t return_column
;
82 typedef struct QEMU_PACKED
{
83 uint32_t len
__attribute__((aligned((sizeof(void *)))));
87 } DebugFrameFDEHeader
;
89 typedef struct QEMU_PACKED
{
91 DebugFrameFDEHeader fde
;
94 static void tcg_register_jit_int(void *buf
, size_t size
,
95 const void *debug_frame
,
96 size_t debug_frame_size
)
97 __attribute__((unused
));
99 /* Forward declarations for functions declared and used in tcg-target.c. */
100 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
);
101 static void tcg_out_ld(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg1
,
103 static void tcg_out_mov(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg
);
104 static void tcg_out_movi(TCGContext
*s
, TCGType type
,
105 TCGReg ret
, tcg_target_long arg
);
106 static void tcg_out_op(TCGContext
*s
, TCGOpcode opc
, const TCGArg
*args
,
107 const int *const_args
);
108 static void tcg_out_st(TCGContext
*s
, TCGType type
, TCGReg arg
, TCGReg arg1
,
110 static void tcg_out_call(TCGContext
*s
, tcg_insn_unit
*target
);
111 static int tcg_target_const_match(tcg_target_long val
, TCGType type
,
112 const TCGArgConstraint
*arg_ct
);
113 static void tcg_out_tb_init(TCGContext
*s
);
114 static void tcg_out_tb_finalize(TCGContext
*s
);
117 TCGOpDef tcg_op_defs
[] = {
118 #define DEF(s, oargs, iargs, cargs, flags) { #s, oargs, iargs, cargs, iargs + oargs + cargs, flags },
122 const size_t tcg_op_defs_max
= ARRAY_SIZE(tcg_op_defs
);
124 static TCGRegSet tcg_target_available_regs
[2];
125 static TCGRegSet tcg_target_call_clobber_regs
;
127 #if TCG_TARGET_INSN_UNIT_SIZE == 1
128 static inline void tcg_out8(TCGContext
*s
, uint8_t v
)
133 static inline void tcg_patch8(tcg_insn_unit
*p
, uint8_t v
)
139 #if TCG_TARGET_INSN_UNIT_SIZE <= 2
140 static inline void tcg_out16(TCGContext
*s
, uint16_t v
)
142 if (TCG_TARGET_INSN_UNIT_SIZE
== 2) {
145 tcg_insn_unit
*p
= s
->code_ptr
;
146 memcpy(p
, &v
, sizeof(v
));
147 s
->code_ptr
= p
+ (2 / TCG_TARGET_INSN_UNIT_SIZE
);
151 static inline void tcg_patch16(tcg_insn_unit
*p
, uint16_t v
)
153 if (TCG_TARGET_INSN_UNIT_SIZE
== 2) {
156 memcpy(p
, &v
, sizeof(v
));
161 #if TCG_TARGET_INSN_UNIT_SIZE <= 4
162 static inline void tcg_out32(TCGContext
*s
, uint32_t v
)
164 if (TCG_TARGET_INSN_UNIT_SIZE
== 4) {
167 tcg_insn_unit
*p
= s
->code_ptr
;
168 memcpy(p
, &v
, sizeof(v
));
169 s
->code_ptr
= p
+ (4 / TCG_TARGET_INSN_UNIT_SIZE
);
173 static inline void tcg_patch32(tcg_insn_unit
*p
, uint32_t v
)
175 if (TCG_TARGET_INSN_UNIT_SIZE
== 4) {
178 memcpy(p
, &v
, sizeof(v
));
183 #if TCG_TARGET_INSN_UNIT_SIZE <= 8
184 static inline void tcg_out64(TCGContext
*s
, uint64_t v
)
186 if (TCG_TARGET_INSN_UNIT_SIZE
== 8) {
189 tcg_insn_unit
*p
= s
->code_ptr
;
190 memcpy(p
, &v
, sizeof(v
));
191 s
->code_ptr
= p
+ (8 / TCG_TARGET_INSN_UNIT_SIZE
);
195 static inline void tcg_patch64(tcg_insn_unit
*p
, uint64_t v
)
197 if (TCG_TARGET_INSN_UNIT_SIZE
== 8) {
200 memcpy(p
, &v
, sizeof(v
));
205 /* label relocation processing */
207 static void tcg_out_reloc(TCGContext
*s
, tcg_insn_unit
*code_ptr
, int type
,
208 int label_index
, intptr_t addend
)
213 l
= &s
->labels
[label_index
];
215 /* FIXME: This may break relocations on RISC targets that
216 modify instruction fields in place. The caller may not have
217 written the initial value. */
218 patch_reloc(code_ptr
, type
, l
->u
.value
, addend
);
220 /* add a new relocation entry */
221 r
= tcg_malloc(sizeof(TCGRelocation
));
225 r
->next
= l
->u
.first_reloc
;
226 l
->u
.first_reloc
= r
;
230 static void tcg_out_label(TCGContext
*s
, int label_index
, tcg_insn_unit
*ptr
)
232 TCGLabel
*l
= &s
->labels
[label_index
];
233 intptr_t value
= (intptr_t)ptr
;
236 assert(!l
->has_value
);
238 for (r
= l
->u
.first_reloc
; r
!= NULL
; r
= r
->next
) {
239 patch_reloc(r
->ptr
, r
->type
, value
, r
->addend
);
243 l
->u
.value_ptr
= ptr
;
246 int gen_new_label(void)
248 TCGContext
*s
= &tcg_ctx
;
252 if (s
->nb_labels
>= TCG_MAX_LABELS
)
254 idx
= s
->nb_labels
++;
257 l
->u
.first_reloc
= NULL
;
261 #include "tcg-target.c"
263 /* pool based memory allocation */
264 void *tcg_malloc_internal(TCGContext
*s
, int size
)
269 if (size
> TCG_POOL_CHUNK_SIZE
) {
270 /* big malloc: insert a new pool (XXX: could optimize) */
271 p
= g_malloc(sizeof(TCGPool
) + size
);
273 p
->next
= s
->pool_first_large
;
274 s
->pool_first_large
= p
;
285 pool_size
= TCG_POOL_CHUNK_SIZE
;
286 p
= g_malloc(sizeof(TCGPool
) + pool_size
);
290 s
->pool_current
->next
= p
;
299 s
->pool_cur
= p
->data
+ size
;
300 s
->pool_end
= p
->data
+ p
->size
;
304 void tcg_pool_reset(TCGContext
*s
)
307 for (p
= s
->pool_first_large
; p
; p
= t
) {
311 s
->pool_first_large
= NULL
;
312 s
->pool_cur
= s
->pool_end
= NULL
;
313 s
->pool_current
= NULL
;
316 typedef struct TCGHelperInfo
{
323 #include "exec/helper-proto.h"
325 static const TCGHelperInfo all_helpers
[] = {
326 #include "exec/helper-tcg.h"
329 void tcg_context_init(TCGContext
*s
)
331 int op
, total_args
, n
, i
;
333 TCGArgConstraint
*args_ct
;
335 GHashTable
*helper_table
;
337 memset(s
, 0, sizeof(*s
));
340 /* Count total number of arguments and allocate the corresponding
343 for(op
= 0; op
< NB_OPS
; op
++) {
344 def
= &tcg_op_defs
[op
];
345 n
= def
->nb_iargs
+ def
->nb_oargs
;
349 args_ct
= g_malloc(sizeof(TCGArgConstraint
) * total_args
);
350 sorted_args
= g_malloc(sizeof(int) * total_args
);
352 for(op
= 0; op
< NB_OPS
; op
++) {
353 def
= &tcg_op_defs
[op
];
354 def
->args_ct
= args_ct
;
355 def
->sorted_args
= sorted_args
;
356 n
= def
->nb_iargs
+ def
->nb_oargs
;
361 /* Register helpers. */
362 /* Use g_direct_hash/equal for direct pointer comparisons on func. */
363 s
->helpers
= helper_table
= g_hash_table_new(NULL
, NULL
);
365 for (i
= 0; i
< ARRAY_SIZE(all_helpers
); ++i
) {
366 g_hash_table_insert(helper_table
, (gpointer
)all_helpers
[i
].func
,
367 (gpointer
)&all_helpers
[i
]);
373 void tcg_prologue_init(TCGContext
*s
)
375 /* init global prologue and epilogue */
376 s
->code_buf
= s
->code_gen_prologue
;
377 s
->code_ptr
= s
->code_buf
;
378 tcg_target_qemu_prologue(s
);
379 flush_icache_range((uintptr_t)s
->code_buf
, (uintptr_t)s
->code_ptr
);
382 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM
)) {
383 size_t size
= tcg_current_code_size(s
);
384 qemu_log("PROLOGUE: [size=%zu]\n", size
);
385 log_disas(s
->code_buf
, size
);
392 void tcg_set_frame(TCGContext
*s
, int reg
, intptr_t start
, intptr_t size
)
394 s
->frame_start
= start
;
395 s
->frame_end
= start
+ size
;
399 void tcg_func_start(TCGContext
*s
)
402 s
->nb_temps
= s
->nb_globals
;
404 /* No temps have been previously allocated for size or locality. */
405 memset(s
->free_temps
, 0, sizeof(s
->free_temps
));
407 s
->labels
= tcg_malloc(sizeof(TCGLabel
) * TCG_MAX_LABELS
);
409 s
->current_frame_offset
= s
->frame_start
;
411 #ifdef CONFIG_DEBUG_TCG
412 s
->goto_tb_issue_mask
= 0;
415 s
->gen_opc_ptr
= s
->gen_opc_buf
;
416 s
->gen_opparam_ptr
= s
->gen_opparam_buf
;
418 s
->be
= tcg_malloc(sizeof(TCGBackendData
));
421 static inline void tcg_temp_alloc(TCGContext
*s
, int n
)
423 if (n
> TCG_MAX_TEMPS
)
427 static inline int tcg_global_reg_new_internal(TCGType type
, int reg
,
430 TCGContext
*s
= &tcg_ctx
;
434 #if TCG_TARGET_REG_BITS == 32
435 if (type
!= TCG_TYPE_I32
)
438 if (tcg_regset_test_reg(s
->reserved_regs
, reg
))
441 tcg_temp_alloc(s
, s
->nb_globals
+ 1);
442 ts
= &s
->temps
[s
->nb_globals
];
443 ts
->base_type
= type
;
449 tcg_regset_set_reg(s
->reserved_regs
, reg
);
453 TCGv_i32
tcg_global_reg_new_i32(int reg
, const char *name
)
457 idx
= tcg_global_reg_new_internal(TCG_TYPE_I32
, reg
, name
);
458 return MAKE_TCGV_I32(idx
);
461 TCGv_i64
tcg_global_reg_new_i64(int reg
, const char *name
)
465 idx
= tcg_global_reg_new_internal(TCG_TYPE_I64
, reg
, name
);
466 return MAKE_TCGV_I64(idx
);
469 static inline int tcg_global_mem_new_internal(TCGType type
, int reg
,
473 TCGContext
*s
= &tcg_ctx
;
478 #if TCG_TARGET_REG_BITS == 32
479 if (type
== TCG_TYPE_I64
) {
481 tcg_temp_alloc(s
, s
->nb_globals
+ 2);
482 ts
= &s
->temps
[s
->nb_globals
];
483 ts
->base_type
= type
;
484 ts
->type
= TCG_TYPE_I32
;
486 ts
->mem_allocated
= 1;
488 #ifdef HOST_WORDS_BIGENDIAN
489 ts
->mem_offset
= offset
+ 4;
491 ts
->mem_offset
= offset
;
493 pstrcpy(buf
, sizeof(buf
), name
);
494 pstrcat(buf
, sizeof(buf
), "_0");
495 ts
->name
= strdup(buf
);
498 ts
->base_type
= type
;
499 ts
->type
= TCG_TYPE_I32
;
501 ts
->mem_allocated
= 1;
503 #ifdef HOST_WORDS_BIGENDIAN
504 ts
->mem_offset
= offset
;
506 ts
->mem_offset
= offset
+ 4;
508 pstrcpy(buf
, sizeof(buf
), name
);
509 pstrcat(buf
, sizeof(buf
), "_1");
510 ts
->name
= strdup(buf
);
516 tcg_temp_alloc(s
, s
->nb_globals
+ 1);
517 ts
= &s
->temps
[s
->nb_globals
];
518 ts
->base_type
= type
;
521 ts
->mem_allocated
= 1;
523 ts
->mem_offset
= offset
;
530 TCGv_i32
tcg_global_mem_new_i32(int reg
, intptr_t offset
, const char *name
)
532 int idx
= tcg_global_mem_new_internal(TCG_TYPE_I32
, reg
, offset
, name
);
533 return MAKE_TCGV_I32(idx
);
536 TCGv_i64
tcg_global_mem_new_i64(int reg
, intptr_t offset
, const char *name
)
538 int idx
= tcg_global_mem_new_internal(TCG_TYPE_I64
, reg
, offset
, name
);
539 return MAKE_TCGV_I64(idx
);
542 static inline int tcg_temp_new_internal(TCGType type
, int temp_local
)
544 TCGContext
*s
= &tcg_ctx
;
548 k
= type
+ (temp_local
? TCG_TYPE_COUNT
: 0);
549 idx
= find_first_bit(s
->free_temps
[k
].l
, TCG_MAX_TEMPS
);
550 if (idx
< TCG_MAX_TEMPS
) {
551 /* There is already an available temp with the right type. */
552 clear_bit(idx
, s
->free_temps
[k
].l
);
555 ts
->temp_allocated
= 1;
556 assert(ts
->base_type
== type
);
557 assert(ts
->temp_local
== temp_local
);
560 #if TCG_TARGET_REG_BITS == 32
561 if (type
== TCG_TYPE_I64
) {
562 tcg_temp_alloc(s
, s
->nb_temps
+ 2);
563 ts
= &s
->temps
[s
->nb_temps
];
564 ts
->base_type
= type
;
565 ts
->type
= TCG_TYPE_I32
;
566 ts
->temp_allocated
= 1;
567 ts
->temp_local
= temp_local
;
570 ts
->base_type
= type
;
571 ts
->type
= TCG_TYPE_I32
;
572 ts
->temp_allocated
= 1;
573 ts
->temp_local
= temp_local
;
579 tcg_temp_alloc(s
, s
->nb_temps
+ 1);
580 ts
= &s
->temps
[s
->nb_temps
];
581 ts
->base_type
= type
;
583 ts
->temp_allocated
= 1;
584 ts
->temp_local
= temp_local
;
590 #if defined(CONFIG_DEBUG_TCG)
596 TCGv_i32
tcg_temp_new_internal_i32(int temp_local
)
600 idx
= tcg_temp_new_internal(TCG_TYPE_I32
, temp_local
);
601 return MAKE_TCGV_I32(idx
);
604 TCGv_i64
tcg_temp_new_internal_i64(int temp_local
)
608 idx
= tcg_temp_new_internal(TCG_TYPE_I64
, temp_local
);
609 return MAKE_TCGV_I64(idx
);
612 static void tcg_temp_free_internal(int idx
)
614 TCGContext
*s
= &tcg_ctx
;
618 #if defined(CONFIG_DEBUG_TCG)
620 if (s
->temps_in_use
< 0) {
621 fprintf(stderr
, "More temporaries freed than allocated!\n");
625 assert(idx
>= s
->nb_globals
&& idx
< s
->nb_temps
);
627 assert(ts
->temp_allocated
!= 0);
628 ts
->temp_allocated
= 0;
630 k
= ts
->base_type
+ (ts
->temp_local
? TCG_TYPE_COUNT
: 0);
631 set_bit(idx
, s
->free_temps
[k
].l
);
634 void tcg_temp_free_i32(TCGv_i32 arg
)
636 tcg_temp_free_internal(GET_TCGV_I32(arg
));
639 void tcg_temp_free_i64(TCGv_i64 arg
)
641 tcg_temp_free_internal(GET_TCGV_I64(arg
));
644 TCGv_i32
tcg_const_i32(int32_t val
)
647 t0
= tcg_temp_new_i32();
648 tcg_gen_movi_i32(t0
, val
);
652 TCGv_i64
tcg_const_i64(int64_t val
)
655 t0
= tcg_temp_new_i64();
656 tcg_gen_movi_i64(t0
, val
);
660 TCGv_i32
tcg_const_local_i32(int32_t val
)
663 t0
= tcg_temp_local_new_i32();
664 tcg_gen_movi_i32(t0
, val
);
668 TCGv_i64
tcg_const_local_i64(int64_t val
)
671 t0
= tcg_temp_local_new_i64();
672 tcg_gen_movi_i64(t0
, val
);
676 #if defined(CONFIG_DEBUG_TCG)
677 void tcg_clear_temp_count(void)
679 TCGContext
*s
= &tcg_ctx
;
683 int tcg_check_temp_count(void)
685 TCGContext
*s
= &tcg_ctx
;
686 if (s
->temps_in_use
) {
687 /* Clear the count so that we don't give another
688 * warning immediately next time around.
697 /* Note: we convert the 64 bit args to 32 bit and do some alignment
698 and endian swap. Maybe it would be better to do the alignment
699 and endian swap in tcg_reg_alloc_call(). */
700 void tcg_gen_callN(TCGContext
*s
, void *func
, TCGArg ret
,
701 int nargs
, TCGArg
*args
)
703 int i
, real_args
, nb_rets
;
704 unsigned sizemask
, flags
;
708 info
= g_hash_table_lookup(s
->helpers
, (gpointer
)func
);
710 sizemask
= info
->sizemask
;
712 #if defined(__sparc__) && !defined(__arch64__) \
713 && !defined(CONFIG_TCG_INTERPRETER)
714 /* We have 64-bit values in one register, but need to pass as two
715 separate parameters. Split them. */
716 int orig_sizemask
= sizemask
;
717 int orig_nargs
= nargs
;
720 TCGV_UNUSED_I64(retl
);
721 TCGV_UNUSED_I64(reth
);
723 TCGArg
*split_args
= __builtin_alloca(sizeof(TCGArg
) * nargs
* 2);
724 for (i
= real_args
= 0; i
< nargs
; ++i
) {
725 int is_64bit
= sizemask
& (1 << (i
+1)*2);
727 TCGv_i64 orig
= MAKE_TCGV_I64(args
[i
]);
728 TCGv_i32 h
= tcg_temp_new_i32();
729 TCGv_i32 l
= tcg_temp_new_i32();
730 tcg_gen_extr_i64_i32(l
, h
, orig
);
731 split_args
[real_args
++] = GET_TCGV_I32(h
);
732 split_args
[real_args
++] = GET_TCGV_I32(l
);
734 split_args
[real_args
++] = args
[i
];
741 #elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
742 for (i
= 0; i
< nargs
; ++i
) {
743 int is_64bit
= sizemask
& (1 << (i
+1)*2);
744 int is_signed
= sizemask
& (2 << (i
+1)*2);
746 TCGv_i64 temp
= tcg_temp_new_i64();
747 TCGv_i64 orig
= MAKE_TCGV_I64(args
[i
]);
749 tcg_gen_ext32s_i64(temp
, orig
);
751 tcg_gen_ext32u_i64(temp
, orig
);
753 args
[i
] = GET_TCGV_I64(temp
);
756 #endif /* TCG_TARGET_EXTEND_ARGS */
758 *s
->gen_opc_ptr
++ = INDEX_op_call
;
759 nparam
= s
->gen_opparam_ptr
++;
760 if (ret
!= TCG_CALL_DUMMY_ARG
) {
761 #if defined(__sparc__) && !defined(__arch64__) \
762 && !defined(CONFIG_TCG_INTERPRETER)
763 if (orig_sizemask
& 1) {
764 /* The 32-bit ABI is going to return the 64-bit value in
765 the %o0/%o1 register pair. Prepare for this by using
766 two return temporaries, and reassemble below. */
767 retl
= tcg_temp_new_i64();
768 reth
= tcg_temp_new_i64();
769 *s
->gen_opparam_ptr
++ = GET_TCGV_I64(reth
);
770 *s
->gen_opparam_ptr
++ = GET_TCGV_I64(retl
);
773 *s
->gen_opparam_ptr
++ = ret
;
777 if (TCG_TARGET_REG_BITS
< 64 && (sizemask
& 1)) {
778 #ifdef HOST_WORDS_BIGENDIAN
779 *s
->gen_opparam_ptr
++ = ret
+ 1;
780 *s
->gen_opparam_ptr
++ = ret
;
782 *s
->gen_opparam_ptr
++ = ret
;
783 *s
->gen_opparam_ptr
++ = ret
+ 1;
787 *s
->gen_opparam_ptr
++ = ret
;
795 for (i
= 0; i
< nargs
; i
++) {
796 int is_64bit
= sizemask
& (1 << (i
+1)*2);
797 if (TCG_TARGET_REG_BITS
< 64 && is_64bit
) {
798 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
799 /* some targets want aligned 64 bit args */
801 *s
->gen_opparam_ptr
++ = TCG_CALL_DUMMY_ARG
;
805 /* If stack grows up, then we will be placing successive
806 arguments at lower addresses, which means we need to
807 reverse the order compared to how we would normally
808 treat either big or little-endian. For those arguments
809 that will wind up in registers, this still works for
810 HPPA (the only current STACK_GROWSUP target) since the
811 argument registers are *also* allocated in decreasing
812 order. If another such target is added, this logic may
813 have to get more complicated to differentiate between
814 stack arguments and register arguments. */
815 #if defined(HOST_WORDS_BIGENDIAN) != defined(TCG_TARGET_STACK_GROWSUP)
816 *s
->gen_opparam_ptr
++ = args
[i
] + 1;
817 *s
->gen_opparam_ptr
++ = args
[i
];
819 *s
->gen_opparam_ptr
++ = args
[i
];
820 *s
->gen_opparam_ptr
++ = args
[i
] + 1;
826 *s
->gen_opparam_ptr
++ = args
[i
];
829 *s
->gen_opparam_ptr
++ = (uintptr_t)func
;
830 *s
->gen_opparam_ptr
++ = flags
;
832 *nparam
= (nb_rets
<< 16) | real_args
;
834 /* total parameters, needed to go backward in the instruction stream */
835 *s
->gen_opparam_ptr
++ = 1 + nb_rets
+ real_args
+ 3;
837 #if defined(__sparc__) && !defined(__arch64__) \
838 && !defined(CONFIG_TCG_INTERPRETER)
839 /* Free all of the parts we allocated above. */
840 for (i
= real_args
= 0; i
< orig_nargs
; ++i
) {
841 int is_64bit
= orig_sizemask
& (1 << (i
+1)*2);
843 TCGv_i32 h
= MAKE_TCGV_I32(args
[real_args
++]);
844 TCGv_i32 l
= MAKE_TCGV_I32(args
[real_args
++]);
845 tcg_temp_free_i32(h
);
846 tcg_temp_free_i32(l
);
851 if (orig_sizemask
& 1) {
852 /* The 32-bit ABI returned two 32-bit pieces. Re-assemble them.
853 Note that describing these as TCGv_i64 eliminates an unnecessary
854 zero-extension that tcg_gen_concat_i32_i64 would create. */
855 tcg_gen_concat32_i64(MAKE_TCGV_I64(ret
), retl
, reth
);
856 tcg_temp_free_i64(retl
);
857 tcg_temp_free_i64(reth
);
859 #elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
860 for (i
= 0; i
< nargs
; ++i
) {
861 int is_64bit
= sizemask
& (1 << (i
+1)*2);
863 TCGv_i64 temp
= MAKE_TCGV_I64(args
[i
]);
864 tcg_temp_free_i64(temp
);
867 #endif /* TCG_TARGET_EXTEND_ARGS */
870 #if TCG_TARGET_REG_BITS == 32
871 void tcg_gen_shifti_i64(TCGv_i64 ret
, TCGv_i64 arg1
,
872 int c
, int right
, int arith
)
875 tcg_gen_mov_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
));
876 tcg_gen_mov_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
));
877 } else if (c
>= 32) {
881 tcg_gen_sari_i32(TCGV_LOW(ret
), TCGV_HIGH(arg1
), c
);
882 tcg_gen_sari_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
), 31);
884 tcg_gen_shri_i32(TCGV_LOW(ret
), TCGV_HIGH(arg1
), c
);
885 tcg_gen_movi_i32(TCGV_HIGH(ret
), 0);
888 tcg_gen_shli_i32(TCGV_HIGH(ret
), TCGV_LOW(arg1
), c
);
889 tcg_gen_movi_i32(TCGV_LOW(ret
), 0);
894 t0
= tcg_temp_new_i32();
895 t1
= tcg_temp_new_i32();
897 tcg_gen_shli_i32(t0
, TCGV_HIGH(arg1
), 32 - c
);
899 tcg_gen_sari_i32(t1
, TCGV_HIGH(arg1
), c
);
901 tcg_gen_shri_i32(t1
, TCGV_HIGH(arg1
), c
);
902 tcg_gen_shri_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
), c
);
903 tcg_gen_or_i32(TCGV_LOW(ret
), TCGV_LOW(ret
), t0
);
904 tcg_gen_mov_i32(TCGV_HIGH(ret
), t1
);
906 tcg_gen_shri_i32(t0
, TCGV_LOW(arg1
), 32 - c
);
907 /* Note: ret can be the same as arg1, so we use t1 */
908 tcg_gen_shli_i32(t1
, TCGV_LOW(arg1
), c
);
909 tcg_gen_shli_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
), c
);
910 tcg_gen_or_i32(TCGV_HIGH(ret
), TCGV_HIGH(ret
), t0
);
911 tcg_gen_mov_i32(TCGV_LOW(ret
), t1
);
913 tcg_temp_free_i32(t0
);
914 tcg_temp_free_i32(t1
);
919 static inline TCGMemOp
tcg_canonicalize_memop(TCGMemOp op
, bool is64
, bool st
)
921 switch (op
& MO_SIZE
) {
944 void tcg_gen_qemu_ld_i32(TCGv_i32 val
, TCGv addr
, TCGArg idx
, TCGMemOp memop
)
946 memop
= tcg_canonicalize_memop(memop
, 0, 0);
948 *tcg_ctx
.gen_opc_ptr
++ = INDEX_op_qemu_ld_i32
;
949 tcg_add_param_i32(val
);
950 tcg_add_param_tl(addr
);
951 *tcg_ctx
.gen_opparam_ptr
++ = memop
;
952 *tcg_ctx
.gen_opparam_ptr
++ = idx
;
955 void tcg_gen_qemu_st_i32(TCGv_i32 val
, TCGv addr
, TCGArg idx
, TCGMemOp memop
)
957 memop
= tcg_canonicalize_memop(memop
, 0, 1);
959 *tcg_ctx
.gen_opc_ptr
++ = INDEX_op_qemu_st_i32
;
960 tcg_add_param_i32(val
);
961 tcg_add_param_tl(addr
);
962 *tcg_ctx
.gen_opparam_ptr
++ = memop
;
963 *tcg_ctx
.gen_opparam_ptr
++ = idx
;
966 void tcg_gen_qemu_ld_i64(TCGv_i64 val
, TCGv addr
, TCGArg idx
, TCGMemOp memop
)
968 memop
= tcg_canonicalize_memop(memop
, 1, 0);
970 #if TCG_TARGET_REG_BITS == 32
971 if ((memop
& MO_SIZE
) < MO_64
) {
972 tcg_gen_qemu_ld_i32(TCGV_LOW(val
), addr
, idx
, memop
);
973 if (memop
& MO_SIGN
) {
974 tcg_gen_sari_i32(TCGV_HIGH(val
), TCGV_LOW(val
), 31);
976 tcg_gen_movi_i32(TCGV_HIGH(val
), 0);
982 *tcg_ctx
.gen_opc_ptr
++ = INDEX_op_qemu_ld_i64
;
983 tcg_add_param_i64(val
);
984 tcg_add_param_tl(addr
);
985 *tcg_ctx
.gen_opparam_ptr
++ = memop
;
986 *tcg_ctx
.gen_opparam_ptr
++ = idx
;
989 void tcg_gen_qemu_st_i64(TCGv_i64 val
, TCGv addr
, TCGArg idx
, TCGMemOp memop
)
991 memop
= tcg_canonicalize_memop(memop
, 1, 1);
993 #if TCG_TARGET_REG_BITS == 32
994 if ((memop
& MO_SIZE
) < MO_64
) {
995 tcg_gen_qemu_st_i32(TCGV_LOW(val
), addr
, idx
, memop
);
1000 *tcg_ctx
.gen_opc_ptr
++ = INDEX_op_qemu_st_i64
;
1001 tcg_add_param_i64(val
);
1002 tcg_add_param_tl(addr
);
1003 *tcg_ctx
.gen_opparam_ptr
++ = memop
;
1004 *tcg_ctx
.gen_opparam_ptr
++ = idx
;
1007 static void tcg_reg_alloc_start(TCGContext
*s
)
1011 for(i
= 0; i
< s
->nb_globals
; i
++) {
1013 if (ts
->fixed_reg
) {
1014 ts
->val_type
= TEMP_VAL_REG
;
1016 ts
->val_type
= TEMP_VAL_MEM
;
1019 for(i
= s
->nb_globals
; i
< s
->nb_temps
; i
++) {
1021 if (ts
->temp_local
) {
1022 ts
->val_type
= TEMP_VAL_MEM
;
1024 ts
->val_type
= TEMP_VAL_DEAD
;
1026 ts
->mem_allocated
= 0;
1029 for(i
= 0; i
< TCG_TARGET_NB_REGS
; i
++) {
1030 s
->reg_to_temp
[i
] = -1;
1034 static char *tcg_get_arg_str_idx(TCGContext
*s
, char *buf
, int buf_size
,
1039 assert(idx
>= 0 && idx
< s
->nb_temps
);
1040 ts
= &s
->temps
[idx
];
1041 if (idx
< s
->nb_globals
) {
1042 pstrcpy(buf
, buf_size
, ts
->name
);
1045 snprintf(buf
, buf_size
, "loc%d", idx
- s
->nb_globals
);
1047 snprintf(buf
, buf_size
, "tmp%d", idx
- s
->nb_globals
);
1052 char *tcg_get_arg_str_i32(TCGContext
*s
, char *buf
, int buf_size
, TCGv_i32 arg
)
1054 return tcg_get_arg_str_idx(s
, buf
, buf_size
, GET_TCGV_I32(arg
));
1057 char *tcg_get_arg_str_i64(TCGContext
*s
, char *buf
, int buf_size
, TCGv_i64 arg
)
1059 return tcg_get_arg_str_idx(s
, buf
, buf_size
, GET_TCGV_I64(arg
));
1062 /* Find helper name. */
1063 static inline const char *tcg_find_helper(TCGContext
*s
, uintptr_t val
)
1065 const char *ret
= NULL
;
1067 TCGHelperInfo
*info
= g_hash_table_lookup(s
->helpers
, (gpointer
)val
);
1075 static const char * const cond_name
[] =
1077 [TCG_COND_NEVER
] = "never",
1078 [TCG_COND_ALWAYS
] = "always",
1079 [TCG_COND_EQ
] = "eq",
1080 [TCG_COND_NE
] = "ne",
1081 [TCG_COND_LT
] = "lt",
1082 [TCG_COND_GE
] = "ge",
1083 [TCG_COND_LE
] = "le",
1084 [TCG_COND_GT
] = "gt",
1085 [TCG_COND_LTU
] = "ltu",
1086 [TCG_COND_GEU
] = "geu",
1087 [TCG_COND_LEU
] = "leu",
1088 [TCG_COND_GTU
] = "gtu"
1091 static const char * const ldst_name
[] =
1107 void tcg_dump_ops(TCGContext
*s
)
1109 const uint16_t *opc_ptr
;
1113 int i
, k
, nb_oargs
, nb_iargs
, nb_cargs
, first_insn
;
1114 const TCGOpDef
*def
;
1118 opc_ptr
= s
->gen_opc_buf
;
1119 args
= s
->gen_opparam_buf
;
1120 while (opc_ptr
< s
->gen_opc_ptr
) {
1122 def
= &tcg_op_defs
[c
];
1123 if (c
== INDEX_op_debug_insn_start
) {
1125 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
1126 pc
= ((uint64_t)args
[1] << 32) | args
[0];
1133 qemu_log(" ---- 0x%" PRIx64
, pc
);
1135 nb_oargs
= def
->nb_oargs
;
1136 nb_iargs
= def
->nb_iargs
;
1137 nb_cargs
= def
->nb_cargs
;
1138 } else if (c
== INDEX_op_call
) {
1141 /* variable number of arguments */
1143 nb_oargs
= arg
>> 16;
1144 nb_iargs
= arg
& 0xffff;
1145 nb_cargs
= def
->nb_cargs
;
1147 /* function name, flags, out args */
1148 qemu_log(" %s %s,$0x%" TCG_PRIlx
",$%d", def
->name
,
1149 tcg_find_helper(s
, args
[nb_oargs
+ nb_iargs
]),
1150 args
[nb_oargs
+ nb_iargs
+ 1], nb_oargs
);
1151 for (i
= 0; i
< nb_oargs
; i
++) {
1152 qemu_log(",%s", tcg_get_arg_str_idx(s
, buf
, sizeof(buf
),
1155 for (i
= 0; i
< nb_iargs
; i
++) {
1156 TCGArg arg
= args
[nb_oargs
+ i
];
1157 const char *t
= "<dummy>";
1158 if (arg
!= TCG_CALL_DUMMY_ARG
) {
1159 t
= tcg_get_arg_str_idx(s
, buf
, sizeof(buf
), arg
);
1164 qemu_log(" %s ", def
->name
);
1165 if (c
== INDEX_op_nopn
) {
1166 /* variable number of arguments */
1171 nb_oargs
= def
->nb_oargs
;
1172 nb_iargs
= def
->nb_iargs
;
1173 nb_cargs
= def
->nb_cargs
;
1177 for(i
= 0; i
< nb_oargs
; i
++) {
1181 qemu_log("%s", tcg_get_arg_str_idx(s
, buf
, sizeof(buf
),
1184 for(i
= 0; i
< nb_iargs
; i
++) {
1188 qemu_log("%s", tcg_get_arg_str_idx(s
, buf
, sizeof(buf
),
1192 case INDEX_op_brcond_i32
:
1193 case INDEX_op_setcond_i32
:
1194 case INDEX_op_movcond_i32
:
1195 case INDEX_op_brcond2_i32
:
1196 case INDEX_op_setcond2_i32
:
1197 case INDEX_op_brcond_i64
:
1198 case INDEX_op_setcond_i64
:
1199 case INDEX_op_movcond_i64
:
1200 if (args
[k
] < ARRAY_SIZE(cond_name
) && cond_name
[args
[k
]]) {
1201 qemu_log(",%s", cond_name
[args
[k
++]]);
1203 qemu_log(",$0x%" TCG_PRIlx
, args
[k
++]);
1207 case INDEX_op_qemu_ld_i32
:
1208 case INDEX_op_qemu_st_i32
:
1209 case INDEX_op_qemu_ld_i64
:
1210 case INDEX_op_qemu_st_i64
:
1211 if (args
[k
] < ARRAY_SIZE(ldst_name
) && ldst_name
[args
[k
]]) {
1212 qemu_log(",%s", ldst_name
[args
[k
++]]);
1214 qemu_log(",$0x%" TCG_PRIlx
, args
[k
++]);
1222 for(; i
< nb_cargs
; i
++) {
1227 qemu_log("$0x%" TCG_PRIlx
, arg
);
1231 args
+= nb_iargs
+ nb_oargs
+ nb_cargs
;
1235 /* we give more priority to constraints with less registers */
1236 static int get_constraint_priority(const TCGOpDef
*def
, int k
)
1238 const TCGArgConstraint
*arg_ct
;
1241 arg_ct
= &def
->args_ct
[k
];
1242 if (arg_ct
->ct
& TCG_CT_ALIAS
) {
1243 /* an alias is equivalent to a single register */
1246 if (!(arg_ct
->ct
& TCG_CT_REG
))
1249 for(i
= 0; i
< TCG_TARGET_NB_REGS
; i
++) {
1250 if (tcg_regset_test_reg(arg_ct
->u
.regs
, i
))
1254 return TCG_TARGET_NB_REGS
- n
+ 1;
1257 /* sort from highest priority to lowest */
1258 static void sort_constraints(TCGOpDef
*def
, int start
, int n
)
1260 int i
, j
, p1
, p2
, tmp
;
1262 for(i
= 0; i
< n
; i
++)
1263 def
->sorted_args
[start
+ i
] = start
+ i
;
1266 for(i
= 0; i
< n
- 1; i
++) {
1267 for(j
= i
+ 1; j
< n
; j
++) {
1268 p1
= get_constraint_priority(def
, def
->sorted_args
[start
+ i
]);
1269 p2
= get_constraint_priority(def
, def
->sorted_args
[start
+ j
]);
1271 tmp
= def
->sorted_args
[start
+ i
];
1272 def
->sorted_args
[start
+ i
] = def
->sorted_args
[start
+ j
];
1273 def
->sorted_args
[start
+ j
] = tmp
;
1279 void tcg_add_target_add_op_defs(const TCGTargetOpDef
*tdefs
)
1287 if (tdefs
->op
== (TCGOpcode
)-1)
1290 assert((unsigned)op
< NB_OPS
);
1291 def
= &tcg_op_defs
[op
];
1292 #if defined(CONFIG_DEBUG_TCG)
1293 /* Duplicate entry in op definitions? */
1297 nb_args
= def
->nb_iargs
+ def
->nb_oargs
;
1298 for(i
= 0; i
< nb_args
; i
++) {
1299 ct_str
= tdefs
->args_ct_str
[i
];
1300 /* Incomplete TCGTargetOpDef entry? */
1301 assert(ct_str
!= NULL
);
1302 tcg_regset_clear(def
->args_ct
[i
].u
.regs
);
1303 def
->args_ct
[i
].ct
= 0;
1304 if (ct_str
[0] >= '0' && ct_str
[0] <= '9') {
1306 oarg
= ct_str
[0] - '0';
1307 assert(oarg
< def
->nb_oargs
);
1308 assert(def
->args_ct
[oarg
].ct
& TCG_CT_REG
);
1309 /* TCG_CT_ALIAS is for the output arguments. The input
1310 argument is tagged with TCG_CT_IALIAS. */
1311 def
->args_ct
[i
] = def
->args_ct
[oarg
];
1312 def
->args_ct
[oarg
].ct
= TCG_CT_ALIAS
;
1313 def
->args_ct
[oarg
].alias_index
= i
;
1314 def
->args_ct
[i
].ct
|= TCG_CT_IALIAS
;
1315 def
->args_ct
[i
].alias_index
= oarg
;
1318 if (*ct_str
== '\0')
1322 def
->args_ct
[i
].ct
|= TCG_CT_CONST
;
1326 if (target_parse_constraint(&def
->args_ct
[i
], &ct_str
) < 0) {
1327 fprintf(stderr
, "Invalid constraint '%s' for arg %d of operation '%s'\n",
1328 ct_str
, i
, def
->name
);
1336 /* TCGTargetOpDef entry with too much information? */
1337 assert(i
== TCG_MAX_OP_ARGS
|| tdefs
->args_ct_str
[i
] == NULL
);
1339 /* sort the constraints (XXX: this is just an heuristic) */
1340 sort_constraints(def
, 0, def
->nb_oargs
);
1341 sort_constraints(def
, def
->nb_oargs
, def
->nb_iargs
);
1347 printf("%s: sorted=", def
->name
);
1348 for(i
= 0; i
< def
->nb_oargs
+ def
->nb_iargs
; i
++)
1349 printf(" %d", def
->sorted_args
[i
]);
1356 #if defined(CONFIG_DEBUG_TCG)
1358 for (op
= 0; op
< ARRAY_SIZE(tcg_op_defs
); op
++) {
1359 const TCGOpDef
*def
= &tcg_op_defs
[op
];
1360 if (def
->flags
& TCG_OPF_NOT_PRESENT
) {
1361 /* Wrong entry in op definitions? */
1363 fprintf(stderr
, "Invalid op definition for %s\n", def
->name
);
1367 /* Missing entry in op definitions? */
1369 fprintf(stderr
, "Missing op definition for %s\n", def
->name
);
1380 #ifdef USE_LIVENESS_ANALYSIS
1382 /* set a nop for an operation using 'nb_args' */
1383 static inline void tcg_set_nop(TCGContext
*s
, uint16_t *opc_ptr
,
1384 TCGArg
*args
, int nb_args
)
1387 *opc_ptr
= INDEX_op_nop
;
1389 *opc_ptr
= INDEX_op_nopn
;
1391 args
[nb_args
- 1] = nb_args
;
1395 /* liveness analysis: end of function: all temps are dead, and globals
1396 should be in memory. */
1397 static inline void tcg_la_func_end(TCGContext
*s
, uint8_t *dead_temps
,
1400 memset(dead_temps
, 1, s
->nb_temps
);
1401 memset(mem_temps
, 1, s
->nb_globals
);
1402 memset(mem_temps
+ s
->nb_globals
, 0, s
->nb_temps
- s
->nb_globals
);
1405 /* liveness analysis: end of basic block: all temps are dead, globals
1406 and local temps should be in memory. */
1407 static inline void tcg_la_bb_end(TCGContext
*s
, uint8_t *dead_temps
,
1412 memset(dead_temps
, 1, s
->nb_temps
);
1413 memset(mem_temps
, 1, s
->nb_globals
);
1414 for(i
= s
->nb_globals
; i
< s
->nb_temps
; i
++) {
1415 mem_temps
[i
] = s
->temps
[i
].temp_local
;
1419 /* Liveness analysis : update the opc_dead_args array to tell if a
1420 given input arguments is dead. Instructions updating dead
1421 temporaries are removed. */
1422 static void tcg_liveness_analysis(TCGContext
*s
)
1424 int i
, op_index
, nb_args
, nb_iargs
, nb_oargs
, nb_ops
;
1425 TCGOpcode op
, op_new
, op_new2
;
1427 const TCGOpDef
*def
;
1428 uint8_t *dead_temps
, *mem_temps
;
1433 s
->gen_opc_ptr
++; /* skip end */
1435 nb_ops
= s
->gen_opc_ptr
- s
->gen_opc_buf
;
1437 s
->op_dead_args
= tcg_malloc(nb_ops
* sizeof(uint16_t));
1438 s
->op_sync_args
= tcg_malloc(nb_ops
* sizeof(uint8_t));
1440 dead_temps
= tcg_malloc(s
->nb_temps
);
1441 mem_temps
= tcg_malloc(s
->nb_temps
);
1442 tcg_la_func_end(s
, dead_temps
, mem_temps
);
1444 args
= s
->gen_opparam_ptr
;
1445 op_index
= nb_ops
- 1;
1446 while (op_index
>= 0) {
1447 op
= s
->gen_opc_buf
[op_index
];
1448 def
= &tcg_op_defs
[op
];
1457 nb_iargs
= arg
& 0xffff;
1458 nb_oargs
= arg
>> 16;
1459 call_flags
= args
[nb_oargs
+ nb_iargs
+ 1];
1461 /* pure functions can be removed if their result is not
1463 if (call_flags
& TCG_CALL_NO_SIDE_EFFECTS
) {
1464 for (i
= 0; i
< nb_oargs
; i
++) {
1466 if (!dead_temps
[arg
] || mem_temps
[arg
]) {
1467 goto do_not_remove_call
;
1470 tcg_set_nop(s
, s
->gen_opc_buf
+ op_index
,
1475 /* output args are dead */
1478 for (i
= 0; i
< nb_oargs
; i
++) {
1480 if (dead_temps
[arg
]) {
1481 dead_args
|= (1 << i
);
1483 if (mem_temps
[arg
]) {
1484 sync_args
|= (1 << i
);
1486 dead_temps
[arg
] = 1;
1490 if (!(call_flags
& TCG_CALL_NO_READ_GLOBALS
)) {
1491 /* globals should be synced to memory */
1492 memset(mem_temps
, 1, s
->nb_globals
);
1494 if (!(call_flags
& (TCG_CALL_NO_WRITE_GLOBALS
|
1495 TCG_CALL_NO_READ_GLOBALS
))) {
1496 /* globals should go back to memory */
1497 memset(dead_temps
, 1, s
->nb_globals
);
1500 /* input args are live */
1501 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
1503 if (arg
!= TCG_CALL_DUMMY_ARG
) {
1504 if (dead_temps
[arg
]) {
1505 dead_args
|= (1 << i
);
1507 dead_temps
[arg
] = 0;
1510 s
->op_dead_args
[op_index
] = dead_args
;
1511 s
->op_sync_args
[op_index
] = sync_args
;
1516 case INDEX_op_debug_insn_start
:
1517 args
-= def
->nb_args
;
1523 case INDEX_op_discard
:
1525 /* mark the temporary as dead */
1526 dead_temps
[args
[0]] = 1;
1527 mem_temps
[args
[0]] = 0;
1532 case INDEX_op_add2_i32
:
1533 op_new
= INDEX_op_add_i32
;
1535 case INDEX_op_sub2_i32
:
1536 op_new
= INDEX_op_sub_i32
;
1538 case INDEX_op_add2_i64
:
1539 op_new
= INDEX_op_add_i64
;
1541 case INDEX_op_sub2_i64
:
1542 op_new
= INDEX_op_sub_i64
;
1547 /* Test if the high part of the operation is dead, but not
1548 the low part. The result can be optimized to a simple
1549 add or sub. This happens often for x86_64 guest when the
1550 cpu mode is set to 32 bit. */
1551 if (dead_temps
[args
[1]] && !mem_temps
[args
[1]]) {
1552 if (dead_temps
[args
[0]] && !mem_temps
[args
[0]]) {
1555 /* Create the single operation plus nop. */
1556 s
->gen_opc_buf
[op_index
] = op
= op_new
;
1559 assert(s
->gen_opc_buf
[op_index
+ 1] == INDEX_op_nop
);
1560 tcg_set_nop(s
, s
->gen_opc_buf
+ op_index
+ 1, args
+ 3, 3);
1561 /* Fall through and mark the single-word operation live. */
1567 case INDEX_op_mulu2_i32
:
1568 op_new
= INDEX_op_mul_i32
;
1569 op_new2
= INDEX_op_muluh_i32
;
1570 have_op_new2
= TCG_TARGET_HAS_muluh_i32
;
1572 case INDEX_op_muls2_i32
:
1573 op_new
= INDEX_op_mul_i32
;
1574 op_new2
= INDEX_op_mulsh_i32
;
1575 have_op_new2
= TCG_TARGET_HAS_mulsh_i32
;
1577 case INDEX_op_mulu2_i64
:
1578 op_new
= INDEX_op_mul_i64
;
1579 op_new2
= INDEX_op_muluh_i64
;
1580 have_op_new2
= TCG_TARGET_HAS_muluh_i64
;
1582 case INDEX_op_muls2_i64
:
1583 op_new
= INDEX_op_mul_i64
;
1584 op_new2
= INDEX_op_mulsh_i64
;
1585 have_op_new2
= TCG_TARGET_HAS_mulsh_i64
;
1591 if (dead_temps
[args
[1]] && !mem_temps
[args
[1]]) {
1592 if (dead_temps
[args
[0]] && !mem_temps
[args
[0]]) {
1593 /* Both parts of the operation are dead. */
1596 /* The high part of the operation is dead; generate the low. */
1597 s
->gen_opc_buf
[op_index
] = op
= op_new
;
1600 } else if (have_op_new2
&& dead_temps
[args
[0]]
1601 && !mem_temps
[args
[0]]) {
1602 /* The low part of the operation is dead; generate the high. */
1603 s
->gen_opc_buf
[op_index
] = op
= op_new2
;
1610 assert(s
->gen_opc_buf
[op_index
+ 1] == INDEX_op_nop
);
1611 tcg_set_nop(s
, s
->gen_opc_buf
+ op_index
+ 1, args
+ 3, 1);
1612 /* Mark the single-word operation live. */
1617 /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */
1618 args
-= def
->nb_args
;
1619 nb_iargs
= def
->nb_iargs
;
1620 nb_oargs
= def
->nb_oargs
;
1622 /* Test if the operation can be removed because all
1623 its outputs are dead. We assume that nb_oargs == 0
1624 implies side effects */
1625 if (!(def
->flags
& TCG_OPF_SIDE_EFFECTS
) && nb_oargs
!= 0) {
1626 for(i
= 0; i
< nb_oargs
; i
++) {
1628 if (!dead_temps
[arg
] || mem_temps
[arg
]) {
1633 tcg_set_nop(s
, s
->gen_opc_buf
+ op_index
, args
, def
->nb_args
);
1634 #ifdef CONFIG_PROFILER
1640 /* output args are dead */
1643 for(i
= 0; i
< nb_oargs
; i
++) {
1645 if (dead_temps
[arg
]) {
1646 dead_args
|= (1 << i
);
1648 if (mem_temps
[arg
]) {
1649 sync_args
|= (1 << i
);
1651 dead_temps
[arg
] = 1;
1655 /* if end of basic block, update */
1656 if (def
->flags
& TCG_OPF_BB_END
) {
1657 tcg_la_bb_end(s
, dead_temps
, mem_temps
);
1658 } else if (def
->flags
& TCG_OPF_SIDE_EFFECTS
) {
1659 /* globals should be synced to memory */
1660 memset(mem_temps
, 1, s
->nb_globals
);
1663 /* input args are live */
1664 for(i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
1666 if (dead_temps
[arg
]) {
1667 dead_args
|= (1 << i
);
1669 dead_temps
[arg
] = 0;
1671 s
->op_dead_args
[op_index
] = dead_args
;
1672 s
->op_sync_args
[op_index
] = sync_args
;
1679 if (args
!= s
->gen_opparam_buf
) {
1684 /* dummy liveness analysis */
1685 static void tcg_liveness_analysis(TCGContext
*s
)
1688 nb_ops
= s
->gen_opc_ptr
- s
->gen_opc_buf
;
1690 s
->op_dead_args
= tcg_malloc(nb_ops
* sizeof(uint16_t));
1691 memset(s
->op_dead_args
, 0, nb_ops
* sizeof(uint16_t));
1692 s
->op_sync_args
= tcg_malloc(nb_ops
* sizeof(uint8_t));
1693 memset(s
->op_sync_args
, 0, nb_ops
* sizeof(uint8_t));
1698 static void dump_regs(TCGContext
*s
)
1704 for(i
= 0; i
< s
->nb_temps
; i
++) {
1706 printf(" %10s: ", tcg_get_arg_str_idx(s
, buf
, sizeof(buf
), i
));
1707 switch(ts
->val_type
) {
1709 printf("%s", tcg_target_reg_names
[ts
->reg
]);
1712 printf("%d(%s)", (int)ts
->mem_offset
, tcg_target_reg_names
[ts
->mem_reg
]);
1714 case TEMP_VAL_CONST
:
1715 printf("$0x%" TCG_PRIlx
, ts
->val
);
1727 for(i
= 0; i
< TCG_TARGET_NB_REGS
; i
++) {
1728 if (s
->reg_to_temp
[i
] >= 0) {
1730 tcg_target_reg_names
[i
],
1731 tcg_get_arg_str_idx(s
, buf
, sizeof(buf
), s
->reg_to_temp
[i
]));
1736 static void check_regs(TCGContext
*s
)
1742 for(reg
= 0; reg
< TCG_TARGET_NB_REGS
; reg
++) {
1743 k
= s
->reg_to_temp
[reg
];
1746 if (ts
->val_type
!= TEMP_VAL_REG
||
1748 printf("Inconsistency for register %s:\n",
1749 tcg_target_reg_names
[reg
]);
1754 for(k
= 0; k
< s
->nb_temps
; k
++) {
1756 if (ts
->val_type
== TEMP_VAL_REG
&&
1758 s
->reg_to_temp
[ts
->reg
] != k
) {
1759 printf("Inconsistency for temp %s:\n",
1760 tcg_get_arg_str_idx(s
, buf
, sizeof(buf
), k
));
1762 printf("reg state:\n");
1770 static void temp_allocate_frame(TCGContext
*s
, int temp
)
1773 ts
= &s
->temps
[temp
];
1774 #if !(defined(__sparc__) && TCG_TARGET_REG_BITS == 64)
1775 /* Sparc64 stack is accessed with offset of 2047 */
1776 s
->current_frame_offset
= (s
->current_frame_offset
+
1777 (tcg_target_long
)sizeof(tcg_target_long
) - 1) &
1778 ~(sizeof(tcg_target_long
) - 1);
1780 if (s
->current_frame_offset
+ (tcg_target_long
)sizeof(tcg_target_long
) >
1784 ts
->mem_offset
= s
->current_frame_offset
;
1785 ts
->mem_reg
= s
->frame_reg
;
1786 ts
->mem_allocated
= 1;
1787 s
->current_frame_offset
+= sizeof(tcg_target_long
);
1790 /* sync register 'reg' by saving it to the corresponding temporary */
1791 static inline void tcg_reg_sync(TCGContext
*s
, int reg
)
1796 temp
= s
->reg_to_temp
[reg
];
1797 ts
= &s
->temps
[temp
];
1798 assert(ts
->val_type
== TEMP_VAL_REG
);
1799 if (!ts
->mem_coherent
&& !ts
->fixed_reg
) {
1800 if (!ts
->mem_allocated
) {
1801 temp_allocate_frame(s
, temp
);
1803 tcg_out_st(s
, ts
->type
, reg
, ts
->mem_reg
, ts
->mem_offset
);
1805 ts
->mem_coherent
= 1;
1808 /* free register 'reg' by spilling the corresponding temporary if necessary */
1809 static void tcg_reg_free(TCGContext
*s
, int reg
)
1813 temp
= s
->reg_to_temp
[reg
];
1815 tcg_reg_sync(s
, reg
);
1816 s
->temps
[temp
].val_type
= TEMP_VAL_MEM
;
1817 s
->reg_to_temp
[reg
] = -1;
1821 /* Allocate a register belonging to reg1 & ~reg2 */
1822 static int tcg_reg_alloc(TCGContext
*s
, TCGRegSet reg1
, TCGRegSet reg2
)
1827 tcg_regset_andnot(reg_ct
, reg1
, reg2
);
1829 /* first try free registers */
1830 for(i
= 0; i
< ARRAY_SIZE(tcg_target_reg_alloc_order
); i
++) {
1831 reg
= tcg_target_reg_alloc_order
[i
];
1832 if (tcg_regset_test_reg(reg_ct
, reg
) && s
->reg_to_temp
[reg
] == -1)
1836 /* XXX: do better spill choice */
1837 for(i
= 0; i
< ARRAY_SIZE(tcg_target_reg_alloc_order
); i
++) {
1838 reg
= tcg_target_reg_alloc_order
[i
];
1839 if (tcg_regset_test_reg(reg_ct
, reg
)) {
1840 tcg_reg_free(s
, reg
);
1848 /* mark a temporary as dead. */
1849 static inline void temp_dead(TCGContext
*s
, int temp
)
1853 ts
= &s
->temps
[temp
];
1854 if (!ts
->fixed_reg
) {
1855 if (ts
->val_type
== TEMP_VAL_REG
) {
1856 s
->reg_to_temp
[ts
->reg
] = -1;
1858 if (temp
< s
->nb_globals
|| ts
->temp_local
) {
1859 ts
->val_type
= TEMP_VAL_MEM
;
1861 ts
->val_type
= TEMP_VAL_DEAD
;
1866 /* sync a temporary to memory. 'allocated_regs' is used in case a
1867 temporary registers needs to be allocated to store a constant. */
1868 static inline void temp_sync(TCGContext
*s
, int temp
, TCGRegSet allocated_regs
)
1872 ts
= &s
->temps
[temp
];
1873 if (!ts
->fixed_reg
) {
1874 switch(ts
->val_type
) {
1875 case TEMP_VAL_CONST
:
1876 ts
->reg
= tcg_reg_alloc(s
, tcg_target_available_regs
[ts
->type
],
1878 ts
->val_type
= TEMP_VAL_REG
;
1879 s
->reg_to_temp
[ts
->reg
] = temp
;
1880 ts
->mem_coherent
= 0;
1881 tcg_out_movi(s
, ts
->type
, ts
->reg
, ts
->val
);
1884 tcg_reg_sync(s
, ts
->reg
);
1895 /* save a temporary to memory. 'allocated_regs' is used in case a
1896 temporary registers needs to be allocated to store a constant. */
1897 static inline void temp_save(TCGContext
*s
, int temp
, TCGRegSet allocated_regs
)
1899 #ifdef USE_LIVENESS_ANALYSIS
1900 /* The liveness analysis already ensures that globals are back
1901 in memory. Keep an assert for safety. */
1902 assert(s
->temps
[temp
].val_type
== TEMP_VAL_MEM
|| s
->temps
[temp
].fixed_reg
);
1904 temp_sync(s
, temp
, allocated_regs
);
1909 /* save globals to their canonical location and assume they can be
1910 modified be the following code. 'allocated_regs' is used in case a
1911 temporary registers needs to be allocated to store a constant. */
1912 static void save_globals(TCGContext
*s
, TCGRegSet allocated_regs
)
1916 for(i
= 0; i
< s
->nb_globals
; i
++) {
1917 temp_save(s
, i
, allocated_regs
);
1921 /* sync globals to their canonical location and assume they can be
1922 read by the following code. 'allocated_regs' is used in case a
1923 temporary registers needs to be allocated to store a constant. */
1924 static void sync_globals(TCGContext
*s
, TCGRegSet allocated_regs
)
1928 for (i
= 0; i
< s
->nb_globals
; i
++) {
1929 #ifdef USE_LIVENESS_ANALYSIS
1930 assert(s
->temps
[i
].val_type
!= TEMP_VAL_REG
|| s
->temps
[i
].fixed_reg
||
1931 s
->temps
[i
].mem_coherent
);
1933 temp_sync(s
, i
, allocated_regs
);
1938 /* at the end of a basic block, we assume all temporaries are dead and
1939 all globals are stored at their canonical location. */
1940 static void tcg_reg_alloc_bb_end(TCGContext
*s
, TCGRegSet allocated_regs
)
1945 for(i
= s
->nb_globals
; i
< s
->nb_temps
; i
++) {
1947 if (ts
->temp_local
) {
1948 temp_save(s
, i
, allocated_regs
);
1950 #ifdef USE_LIVENESS_ANALYSIS
1951 /* The liveness analysis already ensures that temps are dead.
1952 Keep an assert for safety. */
1953 assert(ts
->val_type
== TEMP_VAL_DEAD
);
1960 save_globals(s
, allocated_regs
);
1963 #define IS_DEAD_ARG(n) ((dead_args >> (n)) & 1)
1964 #define NEED_SYNC_ARG(n) ((sync_args >> (n)) & 1)
1966 static void tcg_reg_alloc_movi(TCGContext
*s
, const TCGArg
*args
,
1967 uint16_t dead_args
, uint8_t sync_args
)
1970 tcg_target_ulong val
;
1972 ots
= &s
->temps
[args
[0]];
1975 if (ots
->fixed_reg
) {
1976 /* for fixed registers, we do not do any constant
1978 tcg_out_movi(s
, ots
->type
, ots
->reg
, val
);
1980 /* The movi is not explicitly generated here */
1981 if (ots
->val_type
== TEMP_VAL_REG
)
1982 s
->reg_to_temp
[ots
->reg
] = -1;
1983 ots
->val_type
= TEMP_VAL_CONST
;
1986 if (NEED_SYNC_ARG(0)) {
1987 temp_sync(s
, args
[0], s
->reserved_regs
);
1989 if (IS_DEAD_ARG(0)) {
1990 temp_dead(s
, args
[0]);
1994 static void tcg_reg_alloc_mov(TCGContext
*s
, const TCGOpDef
*def
,
1995 const TCGArg
*args
, uint16_t dead_args
,
1998 TCGRegSet allocated_regs
;
2000 TCGType otype
, itype
;
2002 tcg_regset_set(allocated_regs
, s
->reserved_regs
);
2003 ots
= &s
->temps
[args
[0]];
2004 ts
= &s
->temps
[args
[1]];
2006 /* Note that otype != itype for no-op truncation. */
2010 /* If the source value is not in a register, and we're going to be
2011 forced to have it in a register in order to perform the copy,
2012 then copy the SOURCE value into its own register first. That way
2013 we don't have to reload SOURCE the next time it is used. */
2014 if (((NEED_SYNC_ARG(0) || ots
->fixed_reg
) && ts
->val_type
!= TEMP_VAL_REG
)
2015 || ts
->val_type
== TEMP_VAL_MEM
) {
2016 ts
->reg
= tcg_reg_alloc(s
, tcg_target_available_regs
[itype
],
2018 if (ts
->val_type
== TEMP_VAL_MEM
) {
2019 tcg_out_ld(s
, itype
, ts
->reg
, ts
->mem_reg
, ts
->mem_offset
);
2020 ts
->mem_coherent
= 1;
2021 } else if (ts
->val_type
== TEMP_VAL_CONST
) {
2022 tcg_out_movi(s
, itype
, ts
->reg
, ts
->val
);
2024 s
->reg_to_temp
[ts
->reg
] = args
[1];
2025 ts
->val_type
= TEMP_VAL_REG
;
2028 if (IS_DEAD_ARG(0) && !ots
->fixed_reg
) {
2029 /* mov to a non-saved dead register makes no sense (even with
2030 liveness analysis disabled). */
2031 assert(NEED_SYNC_ARG(0));
2032 /* The code above should have moved the temp to a register. */
2033 assert(ts
->val_type
== TEMP_VAL_REG
);
2034 if (!ots
->mem_allocated
) {
2035 temp_allocate_frame(s
, args
[0]);
2037 tcg_out_st(s
, otype
, ts
->reg
, ots
->mem_reg
, ots
->mem_offset
);
2038 if (IS_DEAD_ARG(1)) {
2039 temp_dead(s
, args
[1]);
2041 temp_dead(s
, args
[0]);
2042 } else if (ts
->val_type
== TEMP_VAL_CONST
) {
2043 /* propagate constant */
2044 if (ots
->val_type
== TEMP_VAL_REG
) {
2045 s
->reg_to_temp
[ots
->reg
] = -1;
2047 ots
->val_type
= TEMP_VAL_CONST
;
2050 /* The code in the first if block should have moved the
2051 temp to a register. */
2052 assert(ts
->val_type
== TEMP_VAL_REG
);
2053 if (IS_DEAD_ARG(1) && !ts
->fixed_reg
&& !ots
->fixed_reg
) {
2054 /* the mov can be suppressed */
2055 if (ots
->val_type
== TEMP_VAL_REG
) {
2056 s
->reg_to_temp
[ots
->reg
] = -1;
2059 temp_dead(s
, args
[1]);
2061 if (ots
->val_type
!= TEMP_VAL_REG
) {
2062 /* When allocating a new register, make sure to not spill the
2064 tcg_regset_set_reg(allocated_regs
, ts
->reg
);
2065 ots
->reg
= tcg_reg_alloc(s
, tcg_target_available_regs
[otype
],
2068 tcg_out_mov(s
, otype
, ots
->reg
, ts
->reg
);
2070 ots
->val_type
= TEMP_VAL_REG
;
2071 ots
->mem_coherent
= 0;
2072 s
->reg_to_temp
[ots
->reg
] = args
[0];
2073 if (NEED_SYNC_ARG(0)) {
2074 tcg_reg_sync(s
, ots
->reg
);
2079 static void tcg_reg_alloc_op(TCGContext
*s
,
2080 const TCGOpDef
*def
, TCGOpcode opc
,
2081 const TCGArg
*args
, uint16_t dead_args
,
2084 TCGRegSet allocated_regs
;
2085 int i
, k
, nb_iargs
, nb_oargs
, reg
;
2087 const TCGArgConstraint
*arg_ct
;
2089 TCGArg new_args
[TCG_MAX_OP_ARGS
];
2090 int const_args
[TCG_MAX_OP_ARGS
];
2092 nb_oargs
= def
->nb_oargs
;
2093 nb_iargs
= def
->nb_iargs
;
2095 /* copy constants */
2096 memcpy(new_args
+ nb_oargs
+ nb_iargs
,
2097 args
+ nb_oargs
+ nb_iargs
,
2098 sizeof(TCGArg
) * def
->nb_cargs
);
2100 /* satisfy input constraints */
2101 tcg_regset_set(allocated_regs
, s
->reserved_regs
);
2102 for(k
= 0; k
< nb_iargs
; k
++) {
2103 i
= def
->sorted_args
[nb_oargs
+ k
];
2105 arg_ct
= &def
->args_ct
[i
];
2106 ts
= &s
->temps
[arg
];
2107 if (ts
->val_type
== TEMP_VAL_MEM
) {
2108 reg
= tcg_reg_alloc(s
, arg_ct
->u
.regs
, allocated_regs
);
2109 tcg_out_ld(s
, ts
->type
, reg
, ts
->mem_reg
, ts
->mem_offset
);
2110 ts
->val_type
= TEMP_VAL_REG
;
2112 ts
->mem_coherent
= 1;
2113 s
->reg_to_temp
[reg
] = arg
;
2114 } else if (ts
->val_type
== TEMP_VAL_CONST
) {
2115 if (tcg_target_const_match(ts
->val
, ts
->type
, arg_ct
)) {
2116 /* constant is OK for instruction */
2118 new_args
[i
] = ts
->val
;
2121 /* need to move to a register */
2122 reg
= tcg_reg_alloc(s
, arg_ct
->u
.regs
, allocated_regs
);
2123 tcg_out_movi(s
, ts
->type
, reg
, ts
->val
);
2124 ts
->val_type
= TEMP_VAL_REG
;
2126 ts
->mem_coherent
= 0;
2127 s
->reg_to_temp
[reg
] = arg
;
2130 assert(ts
->val_type
== TEMP_VAL_REG
);
2131 if (arg_ct
->ct
& TCG_CT_IALIAS
) {
2132 if (ts
->fixed_reg
) {
2133 /* if fixed register, we must allocate a new register
2134 if the alias is not the same register */
2135 if (arg
!= args
[arg_ct
->alias_index
])
2136 goto allocate_in_reg
;
2138 /* if the input is aliased to an output and if it is
2139 not dead after the instruction, we must allocate
2140 a new register and move it */
2141 if (!IS_DEAD_ARG(i
)) {
2142 goto allocate_in_reg
;
2147 if (tcg_regset_test_reg(arg_ct
->u
.regs
, reg
)) {
2148 /* nothing to do : the constraint is satisfied */
2151 /* allocate a new register matching the constraint
2152 and move the temporary register into it */
2153 reg
= tcg_reg_alloc(s
, arg_ct
->u
.regs
, allocated_regs
);
2154 tcg_out_mov(s
, ts
->type
, reg
, ts
->reg
);
2158 tcg_regset_set_reg(allocated_regs
, reg
);
2162 /* mark dead temporaries and free the associated registers */
2163 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
2164 if (IS_DEAD_ARG(i
)) {
2165 temp_dead(s
, args
[i
]);
2169 if (def
->flags
& TCG_OPF_BB_END
) {
2170 tcg_reg_alloc_bb_end(s
, allocated_regs
);
2172 if (def
->flags
& TCG_OPF_CALL_CLOBBER
) {
2173 /* XXX: permit generic clobber register list ? */
2174 for(reg
= 0; reg
< TCG_TARGET_NB_REGS
; reg
++) {
2175 if (tcg_regset_test_reg(tcg_target_call_clobber_regs
, reg
)) {
2176 tcg_reg_free(s
, reg
);
2180 if (def
->flags
& TCG_OPF_SIDE_EFFECTS
) {
2181 /* sync globals if the op has side effects and might trigger
2183 sync_globals(s
, allocated_regs
);
2186 /* satisfy the output constraints */
2187 tcg_regset_set(allocated_regs
, s
->reserved_regs
);
2188 for(k
= 0; k
< nb_oargs
; k
++) {
2189 i
= def
->sorted_args
[k
];
2191 arg_ct
= &def
->args_ct
[i
];
2192 ts
= &s
->temps
[arg
];
2193 if (arg_ct
->ct
& TCG_CT_ALIAS
) {
2194 reg
= new_args
[arg_ct
->alias_index
];
2196 /* if fixed register, we try to use it */
2198 if (ts
->fixed_reg
&&
2199 tcg_regset_test_reg(arg_ct
->u
.regs
, reg
)) {
2202 reg
= tcg_reg_alloc(s
, arg_ct
->u
.regs
, allocated_regs
);
2204 tcg_regset_set_reg(allocated_regs
, reg
);
2205 /* if a fixed register is used, then a move will be done afterwards */
2206 if (!ts
->fixed_reg
) {
2207 if (ts
->val_type
== TEMP_VAL_REG
) {
2208 s
->reg_to_temp
[ts
->reg
] = -1;
2210 ts
->val_type
= TEMP_VAL_REG
;
2212 /* temp value is modified, so the value kept in memory is
2213 potentially not the same */
2214 ts
->mem_coherent
= 0;
2215 s
->reg_to_temp
[reg
] = arg
;
2222 /* emit instruction */
2223 tcg_out_op(s
, opc
, new_args
, const_args
);
2225 /* move the outputs in the correct register if needed */
2226 for(i
= 0; i
< nb_oargs
; i
++) {
2227 ts
= &s
->temps
[args
[i
]];
2229 if (ts
->fixed_reg
&& ts
->reg
!= reg
) {
2230 tcg_out_mov(s
, ts
->type
, ts
->reg
, reg
);
2232 if (NEED_SYNC_ARG(i
)) {
2233 tcg_reg_sync(s
, reg
);
2235 if (IS_DEAD_ARG(i
)) {
2236 temp_dead(s
, args
[i
]);
2241 #ifdef TCG_TARGET_STACK_GROWSUP
2242 #define STACK_DIR(x) (-(x))
2244 #define STACK_DIR(x) (x)
2247 static int tcg_reg_alloc_call(TCGContext
*s
, const TCGOpDef
*def
,
2248 TCGOpcode opc
, const TCGArg
*args
,
2249 uint16_t dead_args
, uint8_t sync_args
)
2251 int nb_iargs
, nb_oargs
, flags
, nb_regs
, i
, reg
, nb_params
;
2254 intptr_t stack_offset
;
2255 size_t call_stack_size
;
2256 tcg_insn_unit
*func_addr
;
2258 TCGRegSet allocated_regs
;
2262 nb_oargs
= arg
>> 16;
2263 nb_iargs
= arg
& 0xffff;
2264 nb_params
= nb_iargs
;
2266 func_addr
= (tcg_insn_unit
*)(intptr_t)args
[nb_oargs
+ nb_iargs
];
2267 flags
= args
[nb_oargs
+ nb_iargs
+ 1];
2269 nb_regs
= ARRAY_SIZE(tcg_target_call_iarg_regs
);
2270 if (nb_regs
> nb_params
) {
2271 nb_regs
= nb_params
;
2274 /* assign stack slots first */
2275 call_stack_size
= (nb_params
- nb_regs
) * sizeof(tcg_target_long
);
2276 call_stack_size
= (call_stack_size
+ TCG_TARGET_STACK_ALIGN
- 1) &
2277 ~(TCG_TARGET_STACK_ALIGN
- 1);
2278 allocate_args
= (call_stack_size
> TCG_STATIC_CALL_ARGS_SIZE
);
2279 if (allocate_args
) {
2280 /* XXX: if more than TCG_STATIC_CALL_ARGS_SIZE is needed,
2281 preallocate call stack */
2285 stack_offset
= TCG_TARGET_CALL_STACK_OFFSET
;
2286 for(i
= nb_regs
; i
< nb_params
; i
++) {
2287 arg
= args
[nb_oargs
+ i
];
2288 #ifdef TCG_TARGET_STACK_GROWSUP
2289 stack_offset
-= sizeof(tcg_target_long
);
2291 if (arg
!= TCG_CALL_DUMMY_ARG
) {
2292 ts
= &s
->temps
[arg
];
2293 if (ts
->val_type
== TEMP_VAL_REG
) {
2294 tcg_out_st(s
, ts
->type
, ts
->reg
, TCG_REG_CALL_STACK
, stack_offset
);
2295 } else if (ts
->val_type
== TEMP_VAL_MEM
) {
2296 reg
= tcg_reg_alloc(s
, tcg_target_available_regs
[ts
->type
],
2298 /* XXX: not correct if reading values from the stack */
2299 tcg_out_ld(s
, ts
->type
, reg
, ts
->mem_reg
, ts
->mem_offset
);
2300 tcg_out_st(s
, ts
->type
, reg
, TCG_REG_CALL_STACK
, stack_offset
);
2301 } else if (ts
->val_type
== TEMP_VAL_CONST
) {
2302 reg
= tcg_reg_alloc(s
, tcg_target_available_regs
[ts
->type
],
2304 /* XXX: sign extend may be needed on some targets */
2305 tcg_out_movi(s
, ts
->type
, reg
, ts
->val
);
2306 tcg_out_st(s
, ts
->type
, reg
, TCG_REG_CALL_STACK
, stack_offset
);
2311 #ifndef TCG_TARGET_STACK_GROWSUP
2312 stack_offset
+= sizeof(tcg_target_long
);
2316 /* assign input registers */
2317 tcg_regset_set(allocated_regs
, s
->reserved_regs
);
2318 for(i
= 0; i
< nb_regs
; i
++) {
2319 arg
= args
[nb_oargs
+ i
];
2320 if (arg
!= TCG_CALL_DUMMY_ARG
) {
2321 ts
= &s
->temps
[arg
];
2322 reg
= tcg_target_call_iarg_regs
[i
];
2323 tcg_reg_free(s
, reg
);
2324 if (ts
->val_type
== TEMP_VAL_REG
) {
2325 if (ts
->reg
!= reg
) {
2326 tcg_out_mov(s
, ts
->type
, reg
, ts
->reg
);
2328 } else if (ts
->val_type
== TEMP_VAL_MEM
) {
2329 tcg_out_ld(s
, ts
->type
, reg
, ts
->mem_reg
, ts
->mem_offset
);
2330 } else if (ts
->val_type
== TEMP_VAL_CONST
) {
2331 /* XXX: sign extend ? */
2332 tcg_out_movi(s
, ts
->type
, reg
, ts
->val
);
2336 tcg_regset_set_reg(allocated_regs
, reg
);
2340 /* mark dead temporaries and free the associated registers */
2341 for(i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
2342 if (IS_DEAD_ARG(i
)) {
2343 temp_dead(s
, args
[i
]);
2347 /* clobber call registers */
2348 for(reg
= 0; reg
< TCG_TARGET_NB_REGS
; reg
++) {
2349 if (tcg_regset_test_reg(tcg_target_call_clobber_regs
, reg
)) {
2350 tcg_reg_free(s
, reg
);
2354 /* Save globals if they might be written by the helper, sync them if
2355 they might be read. */
2356 if (flags
& TCG_CALL_NO_READ_GLOBALS
) {
2358 } else if (flags
& TCG_CALL_NO_WRITE_GLOBALS
) {
2359 sync_globals(s
, allocated_regs
);
2361 save_globals(s
, allocated_regs
);
2364 tcg_out_call(s
, func_addr
);
2366 /* assign output registers and emit moves if needed */
2367 for(i
= 0; i
< nb_oargs
; i
++) {
2369 ts
= &s
->temps
[arg
];
2370 reg
= tcg_target_call_oarg_regs
[i
];
2371 assert(s
->reg_to_temp
[reg
] == -1);
2373 if (ts
->fixed_reg
) {
2374 if (ts
->reg
!= reg
) {
2375 tcg_out_mov(s
, ts
->type
, ts
->reg
, reg
);
2378 if (ts
->val_type
== TEMP_VAL_REG
) {
2379 s
->reg_to_temp
[ts
->reg
] = -1;
2381 ts
->val_type
= TEMP_VAL_REG
;
2383 ts
->mem_coherent
= 0;
2384 s
->reg_to_temp
[reg
] = arg
;
2385 if (NEED_SYNC_ARG(i
)) {
2386 tcg_reg_sync(s
, reg
);
2388 if (IS_DEAD_ARG(i
)) {
2389 temp_dead(s
, args
[i
]);
2394 return nb_iargs
+ nb_oargs
+ def
->nb_cargs
+ 1;
2397 #ifdef CONFIG_PROFILER
2399 static int64_t tcg_table_op_count
[NB_OPS
];
2401 static void dump_op_count(void)
2405 f
= fopen("/tmp/op.log", "w");
2406 for(i
= INDEX_op_end
; i
< NB_OPS
; i
++) {
2407 fprintf(f
, "%s %" PRId64
"\n", tcg_op_defs
[i
].name
, tcg_table_op_count
[i
]);
2414 static inline int tcg_gen_code_common(TCGContext
*s
,
2415 tcg_insn_unit
*gen_code_buf
,
2420 const TCGOpDef
*def
;
2424 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
))) {
2431 #ifdef CONFIG_PROFILER
2432 s
->opt_time
-= profile_getclock();
2435 #ifdef USE_TCG_OPTIMIZATIONS
2436 s
->gen_opparam_ptr
=
2437 tcg_optimize(s
, s
->gen_opc_ptr
, s
->gen_opparam_buf
, tcg_op_defs
);
2440 #ifdef CONFIG_PROFILER
2441 s
->opt_time
+= profile_getclock();
2442 s
->la_time
-= profile_getclock();
2445 tcg_liveness_analysis(s
);
2447 #ifdef CONFIG_PROFILER
2448 s
->la_time
+= profile_getclock();
2452 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT
))) {
2453 qemu_log("OP after optimization and liveness analysis:\n");
2459 tcg_reg_alloc_start(s
);
2461 s
->code_buf
= gen_code_buf
;
2462 s
->code_ptr
= gen_code_buf
;
2466 args
= s
->gen_opparam_buf
;
2470 opc
= s
->gen_opc_buf
[op_index
];
2471 #ifdef CONFIG_PROFILER
2472 tcg_table_op_count
[opc
]++;
2474 def
= &tcg_op_defs
[opc
];
2476 printf("%s: %d %d %d\n", def
->name
,
2477 def
->nb_oargs
, def
->nb_iargs
, def
->nb_cargs
);
2481 case INDEX_op_mov_i32
:
2482 case INDEX_op_mov_i64
:
2483 tcg_reg_alloc_mov(s
, def
, args
, s
->op_dead_args
[op_index
],
2484 s
->op_sync_args
[op_index
]);
2486 case INDEX_op_movi_i32
:
2487 case INDEX_op_movi_i64
:
2488 tcg_reg_alloc_movi(s
, args
, s
->op_dead_args
[op_index
],
2489 s
->op_sync_args
[op_index
]);
2491 case INDEX_op_debug_insn_start
:
2492 /* debug instruction */
2502 case INDEX_op_discard
:
2503 temp_dead(s
, args
[0]);
2505 case INDEX_op_set_label
:
2506 tcg_reg_alloc_bb_end(s
, s
->reserved_regs
);
2507 tcg_out_label(s
, args
[0], s
->code_ptr
);
2510 args
+= tcg_reg_alloc_call(s
, def
, opc
, args
,
2511 s
->op_dead_args
[op_index
],
2512 s
->op_sync_args
[op_index
]);
2517 /* Sanity check that we've not introduced any unhandled opcodes. */
2518 if (def
->flags
& TCG_OPF_NOT_PRESENT
) {
2521 /* Note: in order to speed up the code, it would be much
2522 faster to have specialized register allocator functions for
2523 some common argument patterns */
2524 tcg_reg_alloc_op(s
, def
, opc
, args
, s
->op_dead_args
[op_index
],
2525 s
->op_sync_args
[op_index
]);
2528 args
+= def
->nb_args
;
2530 if (search_pc
>= 0 && search_pc
< tcg_current_code_size(s
)) {
2539 /* Generate TB finalization at the end of block */
2540 tcg_out_tb_finalize(s
);
2544 int tcg_gen_code(TCGContext
*s
, tcg_insn_unit
*gen_code_buf
)
2546 #ifdef CONFIG_PROFILER
2549 n
= (s
->gen_opc_ptr
- s
->gen_opc_buf
);
2551 if (n
> s
->op_count_max
)
2552 s
->op_count_max
= n
;
2554 s
->temp_count
+= s
->nb_temps
;
2555 if (s
->nb_temps
> s
->temp_count_max
)
2556 s
->temp_count_max
= s
->nb_temps
;
2560 tcg_gen_code_common(s
, gen_code_buf
, -1);
2562 /* flush instruction cache */
2563 flush_icache_range((uintptr_t)s
->code_buf
, (uintptr_t)s
->code_ptr
);
2565 return tcg_current_code_size(s
);
2568 /* Return the index of the micro operation such as the pc after is <
2569 offset bytes from the start of the TB. The contents of gen_code_buf must
2570 not be changed, though writing the same values is ok.
2571 Return -1 if not found. */
2572 int tcg_gen_code_search_pc(TCGContext
*s
, tcg_insn_unit
*gen_code_buf
,
2575 return tcg_gen_code_common(s
, gen_code_buf
, offset
);
2578 #ifdef CONFIG_PROFILER
2579 void tcg_dump_info(FILE *f
, fprintf_function cpu_fprintf
)
2581 TCGContext
*s
= &tcg_ctx
;
2584 tot
= s
->interm_time
+ s
->code_time
;
2585 cpu_fprintf(f
, "JIT cycles %" PRId64
" (%0.3f s at 2.4 GHz)\n",
2587 cpu_fprintf(f
, "translated TBs %" PRId64
" (aborted=%" PRId64
" %0.1f%%)\n",
2589 s
->tb_count1
- s
->tb_count
,
2590 s
->tb_count1
? (double)(s
->tb_count1
- s
->tb_count
) / s
->tb_count1
* 100.0 : 0);
2591 cpu_fprintf(f
, "avg ops/TB %0.1f max=%d\n",
2592 s
->tb_count
? (double)s
->op_count
/ s
->tb_count
: 0, s
->op_count_max
);
2593 cpu_fprintf(f
, "deleted ops/TB %0.2f\n",
2595 (double)s
->del_op_count
/ s
->tb_count
: 0);
2596 cpu_fprintf(f
, "avg temps/TB %0.2f max=%d\n",
2598 (double)s
->temp_count
/ s
->tb_count
: 0,
2601 cpu_fprintf(f
, "cycles/op %0.1f\n",
2602 s
->op_count
? (double)tot
/ s
->op_count
: 0);
2603 cpu_fprintf(f
, "cycles/in byte %0.1f\n",
2604 s
->code_in_len
? (double)tot
/ s
->code_in_len
: 0);
2605 cpu_fprintf(f
, "cycles/out byte %0.1f\n",
2606 s
->code_out_len
? (double)tot
/ s
->code_out_len
: 0);
2609 cpu_fprintf(f
, " gen_interm time %0.1f%%\n",
2610 (double)s
->interm_time
/ tot
* 100.0);
2611 cpu_fprintf(f
, " gen_code time %0.1f%%\n",
2612 (double)s
->code_time
/ tot
* 100.0);
2613 cpu_fprintf(f
, "optim./code time %0.1f%%\n",
2614 (double)s
->opt_time
/ (s
->code_time
? s
->code_time
: 1)
2616 cpu_fprintf(f
, "liveness/code time %0.1f%%\n",
2617 (double)s
->la_time
/ (s
->code_time
? s
->code_time
: 1) * 100.0);
2618 cpu_fprintf(f
, "cpu_restore count %" PRId64
"\n",
2620 cpu_fprintf(f
, " avg cycles %0.1f\n",
2621 s
->restore_count
? (double)s
->restore_time
/ s
->restore_count
: 0);
2626 void tcg_dump_info(FILE *f
, fprintf_function cpu_fprintf
)
2628 cpu_fprintf(f
, "[TCG profiler not compiled]\n");
2632 #ifdef ELF_HOST_MACHINE
2633 /* In order to use this feature, the backend needs to do three things:
2635 (1) Define ELF_HOST_MACHINE to indicate both what value to
2636 put into the ELF image and to indicate support for the feature.
2638 (2) Define tcg_register_jit. This should create a buffer containing
2639 the contents of a .debug_frame section that describes the post-
2640 prologue unwind info for the tcg machine.
2642 (3) Call tcg_register_jit_int, with the constructed .debug_frame.
2645 /* Begin GDB interface. THE FOLLOWING MUST MATCH GDB DOCS. */
2652 struct jit_code_entry
{
2653 struct jit_code_entry
*next_entry
;
2654 struct jit_code_entry
*prev_entry
;
2655 const void *symfile_addr
;
2656 uint64_t symfile_size
;
2659 struct jit_descriptor
{
2661 uint32_t action_flag
;
2662 struct jit_code_entry
*relevant_entry
;
2663 struct jit_code_entry
*first_entry
;
2666 void __jit_debug_register_code(void) __attribute__((noinline
));
2667 void __jit_debug_register_code(void)
2672 /* Must statically initialize the version, because GDB may check
2673 the version before we can set it. */
2674 struct jit_descriptor __jit_debug_descriptor
= { 1, 0, 0, 0 };
2676 /* End GDB interface. */
2678 static int find_string(const char *strtab
, const char *str
)
2680 const char *p
= strtab
+ 1;
2683 if (strcmp(p
, str
) == 0) {
2690 static void tcg_register_jit_int(void *buf_ptr
, size_t buf_size
,
2691 const void *debug_frame
,
2692 size_t debug_frame_size
)
2694 struct __attribute__((packed
)) DebugInfo
{
2701 uintptr_t cu_low_pc
;
2702 uintptr_t cu_high_pc
;
2705 uintptr_t fn_low_pc
;
2706 uintptr_t fn_high_pc
;
2715 struct DebugInfo di
;
2720 struct ElfImage
*img
;
2722 static const struct ElfImage img_template
= {
2724 .e_ident
[EI_MAG0
] = ELFMAG0
,
2725 .e_ident
[EI_MAG1
] = ELFMAG1
,
2726 .e_ident
[EI_MAG2
] = ELFMAG2
,
2727 .e_ident
[EI_MAG3
] = ELFMAG3
,
2728 .e_ident
[EI_CLASS
] = ELF_CLASS
,
2729 .e_ident
[EI_DATA
] = ELF_DATA
,
2730 .e_ident
[EI_VERSION
] = EV_CURRENT
,
2732 .e_machine
= ELF_HOST_MACHINE
,
2733 .e_version
= EV_CURRENT
,
2734 .e_phoff
= offsetof(struct ElfImage
, phdr
),
2735 .e_shoff
= offsetof(struct ElfImage
, shdr
),
2736 .e_ehsize
= sizeof(ElfW(Shdr
)),
2737 .e_phentsize
= sizeof(ElfW(Phdr
)),
2739 .e_shentsize
= sizeof(ElfW(Shdr
)),
2740 .e_shnum
= ARRAY_SIZE(img
->shdr
),
2741 .e_shstrndx
= ARRAY_SIZE(img
->shdr
) - 1,
2742 #ifdef ELF_HOST_FLAGS
2743 .e_flags
= ELF_HOST_FLAGS
,
2746 .e_ident
[EI_OSABI
] = ELF_OSABI
,
2754 [0] = { .sh_type
= SHT_NULL
},
2755 /* Trick: The contents of code_gen_buffer are not present in
2756 this fake ELF file; that got allocated elsewhere. Therefore
2757 we mark .text as SHT_NOBITS (similar to .bss) so that readers
2758 will not look for contents. We can record any address. */
2760 .sh_type
= SHT_NOBITS
,
2761 .sh_flags
= SHF_EXECINSTR
| SHF_ALLOC
,
2763 [2] = { /* .debug_info */
2764 .sh_type
= SHT_PROGBITS
,
2765 .sh_offset
= offsetof(struct ElfImage
, di
),
2766 .sh_size
= sizeof(struct DebugInfo
),
2768 [3] = { /* .debug_abbrev */
2769 .sh_type
= SHT_PROGBITS
,
2770 .sh_offset
= offsetof(struct ElfImage
, da
),
2771 .sh_size
= sizeof(img
->da
),
2773 [4] = { /* .debug_frame */
2774 .sh_type
= SHT_PROGBITS
,
2775 .sh_offset
= sizeof(struct ElfImage
),
2777 [5] = { /* .symtab */
2778 .sh_type
= SHT_SYMTAB
,
2779 .sh_offset
= offsetof(struct ElfImage
, sym
),
2780 .sh_size
= sizeof(img
->sym
),
2782 .sh_link
= ARRAY_SIZE(img
->shdr
) - 1,
2783 .sh_entsize
= sizeof(ElfW(Sym
)),
2785 [6] = { /* .strtab */
2786 .sh_type
= SHT_STRTAB
,
2787 .sh_offset
= offsetof(struct ElfImage
, str
),
2788 .sh_size
= sizeof(img
->str
),
2792 [1] = { /* code_gen_buffer */
2793 .st_info
= ELF_ST_INFO(STB_GLOBAL
, STT_FUNC
),
2798 .len
= sizeof(struct DebugInfo
) - 4,
2800 .ptr_size
= sizeof(void *),
2802 .cu_lang
= 0x8001, /* DW_LANG_Mips_Assembler */
2804 .fn_name
= "code_gen_buffer"
2807 1, /* abbrev number (the cu) */
2808 0x11, 1, /* DW_TAG_compile_unit, has children */
2809 0x13, 0x5, /* DW_AT_language, DW_FORM_data2 */
2810 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
2811 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
2812 0, 0, /* end of abbrev */
2813 2, /* abbrev number (the fn) */
2814 0x2e, 0, /* DW_TAG_subprogram, no children */
2815 0x3, 0x8, /* DW_AT_name, DW_FORM_string */
2816 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
2817 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
2818 0, 0, /* end of abbrev */
2819 0 /* no more abbrev */
2821 .str
= "\0" ".text\0" ".debug_info\0" ".debug_abbrev\0"
2822 ".debug_frame\0" ".symtab\0" ".strtab\0" "code_gen_buffer",
2825 /* We only need a single jit entry; statically allocate it. */
2826 static struct jit_code_entry one_entry
;
2828 uintptr_t buf
= (uintptr_t)buf_ptr
;
2829 size_t img_size
= sizeof(struct ElfImage
) + debug_frame_size
;
2830 DebugFrameHeader
*dfh
;
2832 img
= g_malloc(img_size
);
2833 *img
= img_template
;
2835 img
->phdr
.p_vaddr
= buf
;
2836 img
->phdr
.p_paddr
= buf
;
2837 img
->phdr
.p_memsz
= buf_size
;
2839 img
->shdr
[1].sh_name
= find_string(img
->str
, ".text");
2840 img
->shdr
[1].sh_addr
= buf
;
2841 img
->shdr
[1].sh_size
= buf_size
;
2843 img
->shdr
[2].sh_name
= find_string(img
->str
, ".debug_info");
2844 img
->shdr
[3].sh_name
= find_string(img
->str
, ".debug_abbrev");
2846 img
->shdr
[4].sh_name
= find_string(img
->str
, ".debug_frame");
2847 img
->shdr
[4].sh_size
= debug_frame_size
;
2849 img
->shdr
[5].sh_name
= find_string(img
->str
, ".symtab");
2850 img
->shdr
[6].sh_name
= find_string(img
->str
, ".strtab");
2852 img
->sym
[1].st_name
= find_string(img
->str
, "code_gen_buffer");
2853 img
->sym
[1].st_value
= buf
;
2854 img
->sym
[1].st_size
= buf_size
;
2856 img
->di
.cu_low_pc
= buf
;
2857 img
->di
.cu_high_pc
= buf
+ buf_size
;
2858 img
->di
.fn_low_pc
= buf
;
2859 img
->di
.fn_high_pc
= buf
+ buf_size
;
2861 dfh
= (DebugFrameHeader
*)(img
+ 1);
2862 memcpy(dfh
, debug_frame
, debug_frame_size
);
2863 dfh
->fde
.func_start
= buf
;
2864 dfh
->fde
.func_len
= buf_size
;
2867 /* Enable this block to be able to debug the ELF image file creation.
2868 One can use readelf, objdump, or other inspection utilities. */
2870 FILE *f
= fopen("/tmp/qemu.jit", "w+b");
2872 if (fwrite(img
, img_size
, 1, f
) != img_size
) {
2873 /* Avoid stupid unused return value warning for fwrite. */
2880 one_entry
.symfile_addr
= img
;
2881 one_entry
.symfile_size
= img_size
;
2883 __jit_debug_descriptor
.action_flag
= JIT_REGISTER_FN
;
2884 __jit_debug_descriptor
.relevant_entry
= &one_entry
;
2885 __jit_debug_descriptor
.first_entry
= &one_entry
;
2886 __jit_debug_register_code();
2889 /* No support for the feature. Provide the entry point expected by exec.c,
2890 and implement the internal function we declared earlier. */
2892 static void tcg_register_jit_int(void *buf
, size_t size
,
2893 const void *debug_frame
,
2894 size_t debug_frame_size
)
2898 void tcg_register_jit(void *buf
, size_t buf_size
)
2901 #endif /* ELF_HOST_MACHINE */