hw/char/etraxfs_ser.c

   1 /*
   2  * QEMU ETRAX System Emulator
   3  *
   4  * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/irq.h"
  27 #include "hw/qdev-properties.h"
  28 #include "hw/sysbus.h"
  29 #include "chardev/char-fe.h"
  30 #include "qemu/log.h"
  31 #include "qemu/module.h"
  32 #include "qom/object.h"
  33
  34 #define D(x)
  35
  36 #define RW_TR_CTRL     (0x00 / 4)
  37 #define RW_TR_DMA_EN   (0x04 / 4)
  38 #define RW_REC_CTRL    (0x08 / 4)
  39 #define RW_DOUT        (0x1c / 4)
  40 #define RS_STAT_DIN    (0x20 / 4)
  41 #define R_STAT_DIN     (0x24 / 4)
  42 #define RW_INTR_MASK   (0x2c / 4)
  43 #define RW_ACK_INTR    (0x30 / 4)
  44 #define R_INTR         (0x34 / 4)
  45 #define R_MASKED_INTR  (0x38 / 4)
  46 #define R_MAX          (0x3c / 4)
  47
  48 #define STAT_DAV     16
  49 #define STAT_TR_IDLE 22
  50 #define STAT_TR_RDY  24
  51
  52 #define TYPE_ETRAX_FS_SERIAL "etraxfs,serial"
  53 typedef struct ETRAXSerial ETRAXSerial;
  54 DECLARE_INSTANCE_CHECKER(ETRAXSerial, ETRAX_SERIAL,
  55                          TYPE_ETRAX_FS_SERIAL)
  56
  57 struct ETRAXSerial {
  58     SysBusDevice parent_obj;
  59
  60     MemoryRegion mmio;
  61     CharBackend chr;
  62     qemu_irq irq;
  63
  64     int pending_tx;
  65
  66     uint8_t rx_fifo[16];
  67     unsigned int rx_fifo_pos;
  68     unsigned int rx_fifo_len;
  69
  70     /* Control registers.  */
  71     uint32_t regs[R_MAX];
  72 };
  73
  74 static void ser_update_irq(ETRAXSerial *s)
  75 {
  76
  77     if (s->rx_fifo_len) {
  78         s->regs[R_INTR] |= 8;
  79     } else {
  80         s->regs[R_INTR] &= ~8;
  81     }
  82
  83     s->regs[R_MASKED_INTR] = s->regs[R_INTR] & s->regs[RW_INTR_MASK];
  84     qemu_set_irq(s->irq, !!s->regs[R_MASKED_INTR]);
  85 }
  86
  87 static uint64_t
  88 ser_read(void *opaque, hwaddr addr, unsigned int size)
  89 {
  90     ETRAXSerial *s = opaque;
  91     uint32_t r = 0;
  92
  93     addr >>= 2;
  94     switch (addr)
  95     {
  96         case R_STAT_DIN:
  97             r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
  98             if (s->rx_fifo_len) {
  99                 r |= 1 << STAT_DAV;
 100             }
 101             r |= 1 << STAT_TR_RDY;
 102             r |= 1 << STAT_TR_IDLE;
 103             break;
 104         case RS_STAT_DIN:
 105             r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
 106             if (s->rx_fifo_len) {
 107                 r |= 1 << STAT_DAV;
 108                 s->rx_fifo_len--;
 109             }
 110             r |= 1 << STAT_TR_RDY;
 111             r |= 1 << STAT_TR_IDLE;
 112             break;
 113         default:
 114             r = s->regs[addr];
 115             D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, r));
 116             break;
 117     }
 118     return r;
 119 }
 120
 121 static void
 122 ser_write(void *opaque, hwaddr addr,
 123           uint64_t val64, unsigned int size)
 124 {
 125     ETRAXSerial *s = opaque;
 126     uint32_t value = val64;
 127     unsigned char ch = val64;
 128
 129     D(qemu_log("%s " TARGET_FMT_plx "=%x\n",  __func__, addr, value));
 130     addr >>= 2;
 131     switch (addr)
 132     {
 133         case RW_DOUT:
 134             /* XXX this blocks entire thread. Rewrite to use
 135              * qemu_chr_fe_write and background I/O callbacks */
 136             qemu_chr_fe_write_all(&s->chr, &ch, 1);
 137             s->regs[R_INTR] |= 3;
 138             s->pending_tx = 1;
 139             s->regs[addr] = value;
 140             break;
 141         case RW_ACK_INTR:
 142             if (s->pending_tx) {
 143                 value &= ~1;
 144                 s->pending_tx = 0;
 145                 D(qemu_log("fixedup value=%x r_intr=%x\n",
 146                            value, s->regs[R_INTR]));
 147             }
 148             s->regs[addr] = value;
 149             s->regs[R_INTR] &= ~value;
 150             D(printf("r_intr=%x\n", s->regs[R_INTR]));
 151             break;
 152         default:
 153             s->regs[addr] = value;
 154             break;
 155     }
 156     ser_update_irq(s);
 157 }
 158
 159 static const MemoryRegionOps ser_ops = {
 160     .read = ser_read,
 161     .write = ser_write,
 162     .endianness = DEVICE_NATIVE_ENDIAN,
 163     .valid = {
 164         .min_access_size = 4,
 165         .max_access_size = 4
 166     }
 167 };
 168
 169 static Property etraxfs_ser_properties[] = {
 170     DEFINE_PROP_CHR("chardev", ETRAXSerial, chr),
 171     DEFINE_PROP_END_OF_LIST(),
 172 };
 173
 174 static void serial_receive(void *opaque, const uint8_t *buf, int size)
 175 {
 176     ETRAXSerial *s = opaque;
 177     int i;
 178
 179     /* Got a byte.  */
 180     if (s->rx_fifo_len >= 16) {
 181         D(qemu_log("WARNING: UART dropped char.\n"));
 182         return;
 183     }
 184
 185     for (i = 0; i < size; i++) {
 186         s->rx_fifo[s->rx_fifo_pos] = buf[i];
 187         s->rx_fifo_pos++;
 188         s->rx_fifo_pos &= 15;
 189         s->rx_fifo_len++;
 190     }
 191
 192     ser_update_irq(s);
 193 }
 194
 195 static int serial_can_receive(void *opaque)
 196 {
 197     ETRAXSerial *s = opaque;
 198
 199     /* Is the receiver enabled?  */
 200     if (!(s->regs[RW_REC_CTRL] & (1 << 3))) {
 201         return 0;
 202     }
 203
 204     return sizeof(s->rx_fifo) - s->rx_fifo_len;
 205 }
 206
 207 static void serial_event(void *opaque, QEMUChrEvent event)
 208 {
 209
 210 }
 211
 212 static void etraxfs_ser_reset(DeviceState *d)
 213 {
 214     ETRAXSerial *s = ETRAX_SERIAL(d);
 215
 216     /* transmitter begins ready and idle.  */
 217     s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY);
 218     s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE);
 219
 220     s->regs[RW_REC_CTRL] = 0x10000;
 221
 222 }
 223
 224 static void etraxfs_ser_init(Object *obj)
 225 {
 226     ETRAXSerial *s = ETRAX_SERIAL(obj);
 227     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 228
 229     sysbus_init_irq(dev, &s->irq);
 230     memory_region_init_io(&s->mmio, obj, &ser_ops, s,
 231                           "etraxfs-serial", R_MAX * 4);
 232     sysbus_init_mmio(dev, &s->mmio);
 233 }
 234
 235 static void etraxfs_ser_realize(DeviceState *dev, Error **errp)
 236 {
 237     ETRAXSerial *s = ETRAX_SERIAL(dev);
 238
 239     qemu_chr_fe_set_handlers(&s->chr,
 240                              serial_can_receive, serial_receive,
 241                              serial_event, NULL, s, NULL, true);
 242 }
 243
 244 static void etraxfs_ser_class_init(ObjectClass *klass, void *data)
 245 {
 246     DeviceClass *dc = DEVICE_CLASS(klass);
 247
 248     dc->reset = etraxfs_ser_reset;
 249     device_class_set_props(dc, etraxfs_ser_properties);
 250     dc->realize = etraxfs_ser_realize;
 251 }
 252
 253 static const TypeInfo etraxfs_ser_info = {
 254     .name          = TYPE_ETRAX_FS_SERIAL,
 255     .parent        = TYPE_SYS_BUS_DEVICE,
 256     .instance_size = sizeof(ETRAXSerial),
 257     .instance_init = etraxfs_ser_init,
 258     .class_init    = etraxfs_ser_class_init,
 259 };
 260
 261 static void etraxfs_serial_register_types(void)
 262 {
 263     type_register_static(&etraxfs_ser_info);
 264 }
 265
 266 type_init(etraxfs_serial_register_types)