1 #include "qemu/osdep.h"
2 #include "qemu/units.h"
3 #include "target/arm/idau.h"
7 #include "exec/gdbstub.h"
8 #include "exec/helper-proto.h"
9 #include "qemu/host-utils.h"
10 #include "sysemu/arch_init.h"
11 #include "sysemu/sysemu.h"
12 #include "qemu/bitops.h"
13 #include "qemu/crc32c.h"
14 #include "qemu/qemu-print.h"
15 #include "exec/exec-all.h"
16 #include "exec/cpu_ldst.h"
18 #include <zlib.h> /* For crc32 */
19 #include "exec/semihost.h"
20 #include "sysemu/cpus.h"
21 #include "sysemu/kvm.h"
22 #include "fpu/softfloat.h"
23 #include "qemu/range.h"
24 #include "qapi/qapi-commands-target.h"
26 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
28 #ifndef CONFIG_USER_ONLY
29 /* Cacheability and shareability attributes for a memory access */
30 typedef struct ARMCacheAttrs
{
31 unsigned int attrs
:8; /* as in the MAIR register encoding */
32 unsigned int shareability
:2; /* as in the SH field of the VMSAv8-64 PTEs */
35 static bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
36 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
37 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
38 target_ulong
*page_size
,
39 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
);
41 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
42 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
43 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
44 target_ulong
*page_size_ptr
,
45 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
);
47 /* Security attributes for an address, as returned by v8m_security_lookup. */
48 typedef struct V8M_SAttributes
{
49 bool subpage
; /* true if these attrs don't cover the whole TARGET_PAGE */
58 static void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
59 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
60 V8M_SAttributes
*sattrs
);
63 static void switch_mode(CPUARMState
*env
, int mode
);
65 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
69 /* VFP data registers are always little-endian. */
70 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
72 stq_le_p(buf
, *aa32_vfp_dreg(env
, reg
));
75 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
76 /* Aliases for Q regs. */
79 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
81 stq_le_p(buf
+ 8, q
[1]);
85 switch (reg
- nregs
) {
86 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
87 case 1: stl_p(buf
, vfp_get_fpscr(env
)); return 4;
88 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
93 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
97 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
99 *aa32_vfp_dreg(env
, reg
) = ldq_le_p(buf
);
102 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
105 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
106 q
[0] = ldq_le_p(buf
);
107 q
[1] = ldq_le_p(buf
+ 8);
111 switch (reg
- nregs
) {
112 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
113 case 1: vfp_set_fpscr(env
, ldl_p(buf
)); return 4;
114 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
119 static int aarch64_fpu_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
123 /* 128 bit FP register */
125 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
127 stq_le_p(buf
+ 8, q
[1]);
132 stl_p(buf
, vfp_get_fpsr(env
));
136 stl_p(buf
, vfp_get_fpcr(env
));
143 static int aarch64_fpu_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
147 /* 128 bit FP register */
149 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
150 q
[0] = ldq_le_p(buf
);
151 q
[1] = ldq_le_p(buf
+ 8);
156 vfp_set_fpsr(env
, ldl_p(buf
));
160 vfp_set_fpcr(env
, ldl_p(buf
));
167 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
169 assert(ri
->fieldoffset
);
170 if (cpreg_field_is_64bit(ri
)) {
171 return CPREG_FIELD64(env
, ri
);
173 return CPREG_FIELD32(env
, ri
);
177 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
180 assert(ri
->fieldoffset
);
181 if (cpreg_field_is_64bit(ri
)) {
182 CPREG_FIELD64(env
, ri
) = value
;
184 CPREG_FIELD32(env
, ri
) = value
;
188 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
190 return (char *)env
+ ri
->fieldoffset
;
193 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
195 /* Raw read of a coprocessor register (as needed for migration, etc). */
196 if (ri
->type
& ARM_CP_CONST
) {
197 return ri
->resetvalue
;
198 } else if (ri
->raw_readfn
) {
199 return ri
->raw_readfn(env
, ri
);
200 } else if (ri
->readfn
) {
201 return ri
->readfn(env
, ri
);
203 return raw_read(env
, ri
);
207 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
210 /* Raw write of a coprocessor register (as needed for migration, etc).
211 * Note that constant registers are treated as write-ignored; the
212 * caller should check for success by whether a readback gives the
215 if (ri
->type
& ARM_CP_CONST
) {
217 } else if (ri
->raw_writefn
) {
218 ri
->raw_writefn(env
, ri
, v
);
219 } else if (ri
->writefn
) {
220 ri
->writefn(env
, ri
, v
);
222 raw_write(env
, ri
, v
);
226 static int arm_gdb_get_sysreg(CPUARMState
*env
, uint8_t *buf
, int reg
)
228 ARMCPU
*cpu
= arm_env_get_cpu(env
);
229 const ARMCPRegInfo
*ri
;
232 key
= cpu
->dyn_xml
.cpregs_keys
[reg
];
233 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
235 if (cpreg_field_is_64bit(ri
)) {
236 return gdb_get_reg64(buf
, (uint64_t)read_raw_cp_reg(env
, ri
));
238 return gdb_get_reg32(buf
, (uint32_t)read_raw_cp_reg(env
, ri
));
244 static int arm_gdb_set_sysreg(CPUARMState
*env
, uint8_t *buf
, int reg
)
249 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
251 /* Return true if the regdef would cause an assertion if you called
252 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
253 * program bug for it not to have the NO_RAW flag).
254 * NB that returning false here doesn't necessarily mean that calling
255 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
256 * read/write access functions which are safe for raw use" from "has
257 * read/write access functions which have side effects but has forgotten
258 * to provide raw access functions".
259 * The tests here line up with the conditions in read/write_raw_cp_reg()
260 * and assertions in raw_read()/raw_write().
262 if ((ri
->type
& ARM_CP_CONST
) ||
264 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
270 bool write_cpustate_to_list(ARMCPU
*cpu
, bool kvm_sync
)
272 /* Write the coprocessor state from cpu->env to the (index,value) list. */
276 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
277 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
278 const ARMCPRegInfo
*ri
;
281 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
286 if (ri
->type
& ARM_CP_NO_RAW
) {
290 newval
= read_raw_cp_reg(&cpu
->env
, ri
);
293 * Only sync if the previous list->cpustate sync succeeded.
294 * Rather than tracking the success/failure state for every
295 * item in the list, we just recheck "does the raw write we must
296 * have made in write_list_to_cpustate() read back OK" here.
298 uint64_t oldval
= cpu
->cpreg_values
[i
];
300 if (oldval
== newval
) {
304 write_raw_cp_reg(&cpu
->env
, ri
, oldval
);
305 if (read_raw_cp_reg(&cpu
->env
, ri
) != oldval
) {
309 write_raw_cp_reg(&cpu
->env
, ri
, newval
);
311 cpu
->cpreg_values
[i
] = newval
;
316 bool write_list_to_cpustate(ARMCPU
*cpu
)
321 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
322 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
323 uint64_t v
= cpu
->cpreg_values
[i
];
324 const ARMCPRegInfo
*ri
;
326 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
331 if (ri
->type
& ARM_CP_NO_RAW
) {
334 /* Write value and confirm it reads back as written
335 * (to catch read-only registers and partially read-only
336 * registers where the incoming migration value doesn't match)
338 write_raw_cp_reg(&cpu
->env
, ri
, v
);
339 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
346 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
348 ARMCPU
*cpu
= opaque
;
350 const ARMCPRegInfo
*ri
;
352 regidx
= *(uint32_t *)key
;
353 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
355 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
356 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
357 /* The value array need not be initialized at this point */
358 cpu
->cpreg_array_len
++;
362 static void count_cpreg(gpointer key
, gpointer opaque
)
364 ARMCPU
*cpu
= opaque
;
366 const ARMCPRegInfo
*ri
;
368 regidx
= *(uint32_t *)key
;
369 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
371 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
372 cpu
->cpreg_array_len
++;
376 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
378 uint64_t aidx
= cpreg_to_kvm_id(*(uint32_t *)a
);
379 uint64_t bidx
= cpreg_to_kvm_id(*(uint32_t *)b
);
390 void init_cpreg_list(ARMCPU
*cpu
)
392 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
393 * Note that we require cpreg_tuples[] to be sorted by key ID.
398 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
399 keys
= g_list_sort(keys
, cpreg_key_compare
);
401 cpu
->cpreg_array_len
= 0;
403 g_list_foreach(keys
, count_cpreg
, cpu
);
405 arraylen
= cpu
->cpreg_array_len
;
406 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
407 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
408 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
409 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
410 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
411 cpu
->cpreg_array_len
= 0;
413 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
415 assert(cpu
->cpreg_array_len
== arraylen
);
421 * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
422 * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
424 * access_el3_aa32ns: Used to check AArch32 register views.
425 * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
427 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
428 const ARMCPRegInfo
*ri
,
431 bool secure
= arm_is_secure_below_el3(env
);
433 assert(!arm_el_is_aa64(env
, 3));
435 return CP_ACCESS_TRAP_UNCATEGORIZED
;
440 static CPAccessResult
access_el3_aa32ns_aa64any(CPUARMState
*env
,
441 const ARMCPRegInfo
*ri
,
444 if (!arm_el_is_aa64(env
, 3)) {
445 return access_el3_aa32ns(env
, ri
, isread
);
450 /* Some secure-only AArch32 registers trap to EL3 if used from
451 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
452 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
453 * We assume that the .access field is set to PL1_RW.
455 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
456 const ARMCPRegInfo
*ri
,
459 if (arm_current_el(env
) == 3) {
462 if (arm_is_secure_below_el3(env
)) {
463 return CP_ACCESS_TRAP_EL3
;
465 /* This will be EL1 NS and EL2 NS, which just UNDEF */
466 return CP_ACCESS_TRAP_UNCATEGORIZED
;
469 /* Check for traps to "powerdown debug" registers, which are controlled
472 static CPAccessResult
access_tdosa(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
475 int el
= arm_current_el(env
);
476 bool mdcr_el2_tdosa
= (env
->cp15
.mdcr_el2
& MDCR_TDOSA
) ||
477 (env
->cp15
.mdcr_el2
& MDCR_TDE
) ||
478 (arm_hcr_el2_eff(env
) & HCR_TGE
);
480 if (el
< 2 && mdcr_el2_tdosa
&& !arm_is_secure_below_el3(env
)) {
481 return CP_ACCESS_TRAP_EL2
;
483 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDOSA
)) {
484 return CP_ACCESS_TRAP_EL3
;
489 /* Check for traps to "debug ROM" registers, which are controlled
490 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
492 static CPAccessResult
access_tdra(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
495 int el
= arm_current_el(env
);
496 bool mdcr_el2_tdra
= (env
->cp15
.mdcr_el2
& MDCR_TDRA
) ||
497 (env
->cp15
.mdcr_el2
& MDCR_TDE
) ||
498 (arm_hcr_el2_eff(env
) & HCR_TGE
);
500 if (el
< 2 && mdcr_el2_tdra
&& !arm_is_secure_below_el3(env
)) {
501 return CP_ACCESS_TRAP_EL2
;
503 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
504 return CP_ACCESS_TRAP_EL3
;
509 /* Check for traps to general debug registers, which are controlled
510 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
512 static CPAccessResult
access_tda(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
515 int el
= arm_current_el(env
);
516 bool mdcr_el2_tda
= (env
->cp15
.mdcr_el2
& MDCR_TDA
) ||
517 (env
->cp15
.mdcr_el2
& MDCR_TDE
) ||
518 (arm_hcr_el2_eff(env
) & HCR_TGE
);
520 if (el
< 2 && mdcr_el2_tda
&& !arm_is_secure_below_el3(env
)) {
521 return CP_ACCESS_TRAP_EL2
;
523 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
524 return CP_ACCESS_TRAP_EL3
;
529 /* Check for traps to performance monitor registers, which are controlled
530 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
532 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
535 int el
= arm_current_el(env
);
537 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
538 && !arm_is_secure_below_el3(env
)) {
539 return CP_ACCESS_TRAP_EL2
;
541 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
542 return CP_ACCESS_TRAP_EL3
;
547 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
549 ARMCPU
*cpu
= arm_env_get_cpu(env
);
551 raw_write(env
, ri
, value
);
552 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
555 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
557 ARMCPU
*cpu
= arm_env_get_cpu(env
);
559 if (raw_read(env
, ri
) != value
) {
560 /* Unlike real hardware the qemu TLB uses virtual addresses,
561 * not modified virtual addresses, so this causes a TLB flush.
564 raw_write(env
, ri
, value
);
568 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
571 ARMCPU
*cpu
= arm_env_get_cpu(env
);
573 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
574 && !extended_addresses_enabled(env
)) {
575 /* For VMSA (when not using the LPAE long descriptor page table
576 * format) this register includes the ASID, so do a TLB flush.
577 * For PMSA it is purely a process ID and no action is needed.
581 raw_write(env
, ri
, value
);
584 /* IS variants of TLB operations must affect all cores */
585 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
588 CPUState
*cs
= ENV_GET_CPU(env
);
590 tlb_flush_all_cpus_synced(cs
);
593 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
596 CPUState
*cs
= ENV_GET_CPU(env
);
598 tlb_flush_all_cpus_synced(cs
);
601 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
604 CPUState
*cs
= ENV_GET_CPU(env
);
606 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
609 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
612 CPUState
*cs
= ENV_GET_CPU(env
);
614 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
618 * Non-IS variants of TLB operations are upgraded to
619 * IS versions if we are at NS EL1 and HCR_EL2.FB is set to
620 * force broadcast of these operations.
622 static bool tlb_force_broadcast(CPUARMState
*env
)
624 return (env
->cp15
.hcr_el2
& HCR_FB
) &&
625 arm_current_el(env
) == 1 && arm_is_secure_below_el3(env
);
628 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
631 /* Invalidate all (TLBIALL) */
632 ARMCPU
*cpu
= arm_env_get_cpu(env
);
634 if (tlb_force_broadcast(env
)) {
635 tlbiall_is_write(env
, NULL
, value
);
642 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
645 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
646 ARMCPU
*cpu
= arm_env_get_cpu(env
);
648 if (tlb_force_broadcast(env
)) {
649 tlbimva_is_write(env
, NULL
, value
);
653 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
656 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
659 /* Invalidate by ASID (TLBIASID) */
660 ARMCPU
*cpu
= arm_env_get_cpu(env
);
662 if (tlb_force_broadcast(env
)) {
663 tlbiasid_is_write(env
, NULL
, value
);
670 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
673 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
674 ARMCPU
*cpu
= arm_env_get_cpu(env
);
676 if (tlb_force_broadcast(env
)) {
677 tlbimvaa_is_write(env
, NULL
, value
);
681 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
684 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
687 CPUState
*cs
= ENV_GET_CPU(env
);
689 tlb_flush_by_mmuidx(cs
,
690 ARMMMUIdxBit_S12NSE1
|
691 ARMMMUIdxBit_S12NSE0
|
695 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
698 CPUState
*cs
= ENV_GET_CPU(env
);
700 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
701 ARMMMUIdxBit_S12NSE1
|
702 ARMMMUIdxBit_S12NSE0
|
706 static void tlbiipas2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
709 /* Invalidate by IPA. This has to invalidate any structures that
710 * contain only stage 2 translation information, but does not need
711 * to apply to structures that contain combined stage 1 and stage 2
712 * translation information.
713 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
715 CPUState
*cs
= ENV_GET_CPU(env
);
718 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
722 pageaddr
= sextract64(value
<< 12, 0, 40);
724 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S2NS
);
727 static void tlbiipas2_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
730 CPUState
*cs
= ENV_GET_CPU(env
);
733 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
737 pageaddr
= sextract64(value
<< 12, 0, 40);
739 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
743 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
746 CPUState
*cs
= ENV_GET_CPU(env
);
748 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E2
);
751 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
754 CPUState
*cs
= ENV_GET_CPU(env
);
756 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E2
);
759 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
762 CPUState
*cs
= ENV_GET_CPU(env
);
763 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
765 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E2
);
768 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
771 CPUState
*cs
= ENV_GET_CPU(env
);
772 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
774 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
778 static const ARMCPRegInfo cp_reginfo
[] = {
779 /* Define the secure and non-secure FCSE identifier CP registers
780 * separately because there is no secure bank in V8 (no _EL3). This allows
781 * the secure register to be properly reset and migrated. There is also no
782 * v8 EL1 version of the register so the non-secure instance stands alone.
785 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
786 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
787 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
788 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
789 { .name
= "FCSEIDR_S",
790 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
791 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
792 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
793 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
794 /* Define the secure and non-secure context identifier CP registers
795 * separately because there is no secure bank in V8 (no _EL3). This allows
796 * the secure register to be properly reset and migrated. In the
797 * non-secure case, the 32-bit register will have reset and migration
798 * disabled during registration as it is handled by the 64-bit instance.
800 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
801 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
802 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
803 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
804 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
805 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
806 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
807 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
808 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
809 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
813 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
814 /* NB: Some of these registers exist in v8 but with more precise
815 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
817 /* MMU Domain access control / MPU write buffer control */
819 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
820 .access
= PL1_RW
, .resetvalue
= 0,
821 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
822 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
823 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
824 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
825 * For v6 and v5, these mappings are overly broad.
827 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
828 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
829 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
830 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
831 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
832 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
833 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
834 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
835 /* Cache maintenance ops; some of this space may be overridden later. */
836 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
837 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
838 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
842 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
843 /* Not all pre-v6 cores implemented this WFI, so this is slightly
846 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
847 .access
= PL1_W
, .type
= ARM_CP_WFI
},
851 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
852 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
853 * is UNPREDICTABLE; we choose to NOP as most implementations do).
855 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
856 .access
= PL1_W
, .type
= ARM_CP_WFI
},
857 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
858 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
859 * OMAPCP will override this space.
861 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
862 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
864 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
865 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
867 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
868 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
869 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
871 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
872 * implementing it as RAZ means the "debug architecture version" bits
873 * will read as a reserved value, which should cause Linux to not try
874 * to use the debug hardware.
876 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
877 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
878 /* MMU TLB control. Note that the wildcarding means we cover not just
879 * the unified TLB ops but also the dside/iside/inner-shareable variants.
881 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
882 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
883 .type
= ARM_CP_NO_RAW
},
884 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
885 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
886 .type
= ARM_CP_NO_RAW
},
887 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
888 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
889 .type
= ARM_CP_NO_RAW
},
890 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
891 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
892 .type
= ARM_CP_NO_RAW
},
893 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
894 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
895 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
896 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
900 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
905 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
906 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
907 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
908 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
909 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
911 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
912 /* VFP coprocessor: cp10 & cp11 [23:20] */
913 mask
|= (1 << 31) | (1 << 30) | (0xf << 20);
915 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
916 /* ASEDIS [31] bit is RAO/WI */
920 /* VFPv3 and upwards with NEON implement 32 double precision
921 * registers (D0-D31).
923 if (!arm_feature(env
, ARM_FEATURE_NEON
) ||
924 !arm_feature(env
, ARM_FEATURE_VFP3
)) {
925 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
931 env
->cp15
.cpacr_el1
= value
;
934 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
936 /* Call cpacr_write() so that we reset with the correct RAO bits set
937 * for our CPU features.
939 cpacr_write(env
, ri
, 0);
942 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
945 if (arm_feature(env
, ARM_FEATURE_V8
)) {
946 /* Check if CPACR accesses are to be trapped to EL2 */
947 if (arm_current_el(env
) == 1 &&
948 (env
->cp15
.cptr_el
[2] & CPTR_TCPAC
) && !arm_is_secure(env
)) {
949 return CP_ACCESS_TRAP_EL2
;
950 /* Check if CPACR accesses are to be trapped to EL3 */
951 } else if (arm_current_el(env
) < 3 &&
952 (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
953 return CP_ACCESS_TRAP_EL3
;
960 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
963 /* Check if CPTR accesses are set to trap to EL3 */
964 if (arm_current_el(env
) == 2 && (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
965 return CP_ACCESS_TRAP_EL3
;
971 static const ARMCPRegInfo v6_cp_reginfo
[] = {
972 /* prefetch by MVA in v6, NOP in v7 */
973 { .name
= "MVA_prefetch",
974 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
975 .access
= PL1_W
, .type
= ARM_CP_NOP
},
976 /* We need to break the TB after ISB to execute self-modifying code
977 * correctly and also to take any pending interrupts immediately.
978 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
980 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
981 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
982 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
983 .access
= PL0_W
, .type
= ARM_CP_NOP
},
984 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
985 .access
= PL0_W
, .type
= ARM_CP_NOP
},
986 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
988 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
989 offsetof(CPUARMState
, cp15
.ifar_ns
) },
991 /* Watchpoint Fault Address Register : should actually only be present
992 * for 1136, 1176, 11MPCore.
994 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
995 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
996 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
997 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
998 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
999 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
},
1003 /* Definitions for the PMU registers */
1004 #define PMCRN_MASK 0xf800
1005 #define PMCRN_SHIFT 11
1013 #define PMXEVTYPER_P 0x80000000
1014 #define PMXEVTYPER_U 0x40000000
1015 #define PMXEVTYPER_NSK 0x20000000
1016 #define PMXEVTYPER_NSU 0x10000000
1017 #define PMXEVTYPER_NSH 0x08000000
1018 #define PMXEVTYPER_M 0x04000000
1019 #define PMXEVTYPER_MT 0x02000000
1020 #define PMXEVTYPER_EVTCOUNT 0x0000ffff
1021 #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \
1022 PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
1023 PMXEVTYPER_M | PMXEVTYPER_MT | \
1024 PMXEVTYPER_EVTCOUNT)
1026 #define PMCCFILTR 0xf8000000
1027 #define PMCCFILTR_M PMXEVTYPER_M
1028 #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)
1030 static inline uint32_t pmu_num_counters(CPUARMState
*env
)
1032 return (env
->cp15
.c9_pmcr
& PMCRN_MASK
) >> PMCRN_SHIFT
;
1035 /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
1036 static inline uint64_t pmu_counter_mask(CPUARMState
*env
)
1038 return (1 << 31) | ((1 << pmu_num_counters(env
)) - 1);
1041 typedef struct pm_event
{
1042 uint16_t number
; /* PMEVTYPER.evtCount is 16 bits wide */
1043 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
1044 bool (*supported
)(CPUARMState
*);
1046 * Retrieve the current count of the underlying event. The programmed
1047 * counters hold a difference from the return value from this function
1049 uint64_t (*get_count
)(CPUARMState
*);
1051 * Return how many nanoseconds it will take (at a minimum) for count events
1052 * to occur. A negative value indicates the counter will never overflow, or
1053 * that the counter has otherwise arranged for the overflow bit to be set
1054 * and the PMU interrupt to be raised on overflow.
1056 int64_t (*ns_per_count
)(uint64_t);
1059 static bool event_always_supported(CPUARMState
*env
)
1064 static uint64_t swinc_get_count(CPUARMState
*env
)
1067 * SW_INCR events are written directly to the pmevcntr's by writes to
1068 * PMSWINC, so there is no underlying count maintained by the PMU itself
1073 static int64_t swinc_ns_per(uint64_t ignored
)
1079 * Return the underlying cycle count for the PMU cycle counters. If we're in
1080 * usermode, simply return 0.
1082 static uint64_t cycles_get_count(CPUARMState
*env
)
1084 #ifndef CONFIG_USER_ONLY
1085 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1086 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1088 return cpu_get_host_ticks();
1092 #ifndef CONFIG_USER_ONLY
1093 static int64_t cycles_ns_per(uint64_t cycles
)
1095 return (ARM_CPU_FREQ
/ NANOSECONDS_PER_SECOND
) * cycles
;
1098 static bool instructions_supported(CPUARMState
*env
)
1100 return use_icount
== 1 /* Precise instruction counting */;
1103 static uint64_t instructions_get_count(CPUARMState
*env
)
1105 return (uint64_t)cpu_get_icount_raw();
1108 static int64_t instructions_ns_per(uint64_t icount
)
1110 return cpu_icount_to_ns((int64_t)icount
);
1114 static const pm_event pm_events
[] = {
1115 { .number
= 0x000, /* SW_INCR */
1116 .supported
= event_always_supported
,
1117 .get_count
= swinc_get_count
,
1118 .ns_per_count
= swinc_ns_per
,
1120 #ifndef CONFIG_USER_ONLY
1121 { .number
= 0x008, /* INST_RETIRED, Instruction architecturally executed */
1122 .supported
= instructions_supported
,
1123 .get_count
= instructions_get_count
,
1124 .ns_per_count
= instructions_ns_per
,
1126 { .number
= 0x011, /* CPU_CYCLES, Cycle */
1127 .supported
= event_always_supported
,
1128 .get_count
= cycles_get_count
,
1129 .ns_per_count
= cycles_ns_per
,
1135 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1136 * events (i.e. the statistical profiling extension), this implementation
1137 * should first be updated to something sparse instead of the current
1138 * supported_event_map[] array.
1140 #define MAX_EVENT_ID 0x11
1141 #define UNSUPPORTED_EVENT UINT16_MAX
1142 static uint16_t supported_event_map
[MAX_EVENT_ID
+ 1];
1145 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1146 * of ARM event numbers to indices in our pm_events array.
1148 * Note: Events in the 0x40XX range are not currently supported.
1150 void pmu_init(ARMCPU
*cpu
)
1155 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1158 for (i
= 0; i
< ARRAY_SIZE(supported_event_map
); i
++) {
1159 supported_event_map
[i
] = UNSUPPORTED_EVENT
;
1164 for (i
= 0; i
< ARRAY_SIZE(pm_events
); i
++) {
1165 const pm_event
*cnt
= &pm_events
[i
];
1166 assert(cnt
->number
<= MAX_EVENT_ID
);
1167 /* We do not currently support events in the 0x40xx range */
1168 assert(cnt
->number
<= 0x3f);
1170 if (cnt
->supported(&cpu
->env
)) {
1171 supported_event_map
[cnt
->number
] = i
;
1172 uint64_t event_mask
= 1ULL << (cnt
->number
& 0x1f);
1173 if (cnt
->number
& 0x20) {
1174 cpu
->pmceid1
|= event_mask
;
1176 cpu
->pmceid0
|= event_mask
;
1183 * Check at runtime whether a PMU event is supported for the current machine
1185 static bool event_supported(uint16_t number
)
1187 if (number
> MAX_EVENT_ID
) {
1190 return supported_event_map
[number
] != UNSUPPORTED_EVENT
;
1193 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1196 /* Performance monitor registers user accessibility is controlled
1197 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1198 * trapping to EL2 or EL3 for other accesses.
1200 int el
= arm_current_el(env
);
1202 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
1203 return CP_ACCESS_TRAP
;
1205 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
1206 && !arm_is_secure_below_el3(env
)) {
1207 return CP_ACCESS_TRAP_EL2
;
1209 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
1210 return CP_ACCESS_TRAP_EL3
;
1213 return CP_ACCESS_OK
;
1216 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
1217 const ARMCPRegInfo
*ri
,
1220 /* ER: event counter read trap control */
1221 if (arm_feature(env
, ARM_FEATURE_V8
)
1222 && arm_current_el(env
) == 0
1223 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
1225 return CP_ACCESS_OK
;
1228 return pmreg_access(env
, ri
, isread
);
1231 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1232 const ARMCPRegInfo
*ri
,
1235 /* SW: software increment write trap control */
1236 if (arm_feature(env
, ARM_FEATURE_V8
)
1237 && arm_current_el(env
) == 0
1238 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1240 return CP_ACCESS_OK
;
1243 return pmreg_access(env
, ri
, isread
);
1246 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1247 const ARMCPRegInfo
*ri
,
1250 /* ER: event counter read trap control */
1251 if (arm_feature(env
, ARM_FEATURE_V8
)
1252 && arm_current_el(env
) == 0
1253 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1254 return CP_ACCESS_OK
;
1257 return pmreg_access(env
, ri
, isread
);
1260 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1261 const ARMCPRegInfo
*ri
,
1264 /* CR: cycle counter read trap control */
1265 if (arm_feature(env
, ARM_FEATURE_V8
)
1266 && arm_current_el(env
) == 0
1267 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1269 return CP_ACCESS_OK
;
1272 return pmreg_access(env
, ri
, isread
);
1275 /* Returns true if the counter (pass 31 for PMCCNTR) should count events using
1276 * the current EL, security state, and register configuration.
1278 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
1281 bool e
, p
, u
, nsk
, nsu
, nsh
, m
;
1282 bool enabled
, prohibited
, filtered
;
1283 bool secure
= arm_is_secure(env
);
1284 int el
= arm_current_el(env
);
1285 uint8_t hpmn
= env
->cp15
.mdcr_el2
& MDCR_HPMN
;
1287 if (!arm_feature(env
, ARM_FEATURE_PMU
)) {
1291 if (!arm_feature(env
, ARM_FEATURE_EL2
) ||
1292 (counter
< hpmn
|| counter
== 31)) {
1293 e
= env
->cp15
.c9_pmcr
& PMCRE
;
1295 e
= env
->cp15
.mdcr_el2
& MDCR_HPME
;
1297 enabled
= e
&& (env
->cp15
.c9_pmcnten
& (1 << counter
));
1300 if (el
== 2 && (counter
< hpmn
|| counter
== 31)) {
1301 prohibited
= env
->cp15
.mdcr_el2
& MDCR_HPMD
;
1306 prohibited
= arm_feature(env
, ARM_FEATURE_EL3
) &&
1307 (env
->cp15
.mdcr_el3
& MDCR_SPME
);
1310 if (prohibited
&& counter
== 31) {
1311 prohibited
= env
->cp15
.c9_pmcr
& PMCRDP
;
1314 if (counter
== 31) {
1315 filter
= env
->cp15
.pmccfiltr_el0
;
1317 filter
= env
->cp15
.c14_pmevtyper
[counter
];
1320 p
= filter
& PMXEVTYPER_P
;
1321 u
= filter
& PMXEVTYPER_U
;
1322 nsk
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSK
);
1323 nsu
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSU
);
1324 nsh
= arm_feature(env
, ARM_FEATURE_EL2
) && (filter
& PMXEVTYPER_NSH
);
1325 m
= arm_el_is_aa64(env
, 1) &&
1326 arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_M
);
1329 filtered
= secure
? u
: u
!= nsu
;
1330 } else if (el
== 1) {
1331 filtered
= secure
? p
: p
!= nsk
;
1332 } else if (el
== 2) {
1338 if (counter
!= 31) {
1340 * If not checking PMCCNTR, ensure the counter is setup to an event we
1343 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
1344 if (!event_supported(event
)) {
1349 return enabled
&& !prohibited
&& !filtered
;
1352 static void pmu_update_irq(CPUARMState
*env
)
1354 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1355 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
1356 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
1360 * Ensure c15_ccnt is the guest-visible count so that operations such as
1361 * enabling/disabling the counter or filtering, modifying the count itself,
1362 * etc. can be done logically. This is essentially a no-op if the counter is
1363 * not enabled at the time of the call.
1365 static void pmccntr_op_start(CPUARMState
*env
)
1367 uint64_t cycles
= cycles_get_count(env
);
1369 if (pmu_counter_enabled(env
, 31)) {
1370 uint64_t eff_cycles
= cycles
;
1371 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1372 /* Increment once every 64 processor clock cycles */
1376 uint64_t new_pmccntr
= eff_cycles
- env
->cp15
.c15_ccnt_delta
;
1378 uint64_t overflow_mask
= env
->cp15
.c9_pmcr
& PMCRLC
? \
1379 1ull << 63 : 1ull << 31;
1380 if (env
->cp15
.c15_ccnt
& ~new_pmccntr
& overflow_mask
) {
1381 env
->cp15
.c9_pmovsr
|= (1 << 31);
1382 pmu_update_irq(env
);
1385 env
->cp15
.c15_ccnt
= new_pmccntr
;
1387 env
->cp15
.c15_ccnt_delta
= cycles
;
1391 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1392 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1395 static void pmccntr_op_finish(CPUARMState
*env
)
1397 if (pmu_counter_enabled(env
, 31)) {
1398 #ifndef CONFIG_USER_ONLY
1399 /* Calculate when the counter will next overflow */
1400 uint64_t remaining_cycles
= -env
->cp15
.c15_ccnt
;
1401 if (!(env
->cp15
.c9_pmcr
& PMCRLC
)) {
1402 remaining_cycles
= (uint32_t)remaining_cycles
;
1404 int64_t overflow_in
= cycles_ns_per(remaining_cycles
);
1406 if (overflow_in
> 0) {
1407 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1409 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1410 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1414 uint64_t prev_cycles
= env
->cp15
.c15_ccnt_delta
;
1415 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1416 /* Increment once every 64 processor clock cycles */
1419 env
->cp15
.c15_ccnt_delta
= prev_cycles
- env
->cp15
.c15_ccnt
;
1423 static void pmevcntr_op_start(CPUARMState
*env
, uint8_t counter
)
1426 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1428 if (event_supported(event
)) {
1429 uint16_t event_idx
= supported_event_map
[event
];
1430 count
= pm_events
[event_idx
].get_count(env
);
1433 if (pmu_counter_enabled(env
, counter
)) {
1434 uint32_t new_pmevcntr
= count
- env
->cp15
.c14_pmevcntr_delta
[counter
];
1436 if (env
->cp15
.c14_pmevcntr
[counter
] & ~new_pmevcntr
& INT32_MIN
) {
1437 env
->cp15
.c9_pmovsr
|= (1 << counter
);
1438 pmu_update_irq(env
);
1440 env
->cp15
.c14_pmevcntr
[counter
] = new_pmevcntr
;
1442 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1445 static void pmevcntr_op_finish(CPUARMState
*env
, uint8_t counter
)
1447 if (pmu_counter_enabled(env
, counter
)) {
1448 #ifndef CONFIG_USER_ONLY
1449 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1450 uint16_t event_idx
= supported_event_map
[event
];
1451 uint64_t delta
= UINT32_MAX
-
1452 (uint32_t)env
->cp15
.c14_pmevcntr
[counter
] + 1;
1453 int64_t overflow_in
= pm_events
[event_idx
].ns_per_count(delta
);
1455 if (overflow_in
> 0) {
1456 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1458 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1459 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1463 env
->cp15
.c14_pmevcntr_delta
[counter
] -=
1464 env
->cp15
.c14_pmevcntr
[counter
];
1468 void pmu_op_start(CPUARMState
*env
)
1471 pmccntr_op_start(env
);
1472 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1473 pmevcntr_op_start(env
, i
);
1477 void pmu_op_finish(CPUARMState
*env
)
1480 pmccntr_op_finish(env
);
1481 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1482 pmevcntr_op_finish(env
, i
);
1486 void pmu_pre_el_change(ARMCPU
*cpu
, void *ignored
)
1488 pmu_op_start(&cpu
->env
);
1491 void pmu_post_el_change(ARMCPU
*cpu
, void *ignored
)
1493 pmu_op_finish(&cpu
->env
);
1496 void arm_pmu_timer_cb(void *opaque
)
1498 ARMCPU
*cpu
= opaque
;
1501 * Update all the counter values based on the current underlying counts,
1502 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1503 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1504 * counter may expire.
1506 pmu_op_start(&cpu
->env
);
1507 pmu_op_finish(&cpu
->env
);
1510 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1515 if (value
& PMCRC
) {
1516 /* The counter has been reset */
1517 env
->cp15
.c15_ccnt
= 0;
1520 if (value
& PMCRP
) {
1522 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1523 env
->cp15
.c14_pmevcntr
[i
] = 0;
1527 /* only the DP, X, D and E bits are writable */
1528 env
->cp15
.c9_pmcr
&= ~0x39;
1529 env
->cp15
.c9_pmcr
|= (value
& 0x39);
1534 static void pmswinc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1538 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1539 /* Increment a counter's count iff: */
1540 if ((value
& (1 << i
)) && /* counter's bit is set */
1541 /* counter is enabled and not filtered */
1542 pmu_counter_enabled(env
, i
) &&
1543 /* counter is SW_INCR */
1544 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
1545 pmevcntr_op_start(env
, i
);
1548 * Detect if this write causes an overflow since we can't predict
1549 * PMSWINC overflows like we can for other events
1551 uint32_t new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
1553 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& INT32_MIN
) {
1554 env
->cp15
.c9_pmovsr
|= (1 << i
);
1555 pmu_update_irq(env
);
1558 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
1560 pmevcntr_op_finish(env
, i
);
1565 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1568 pmccntr_op_start(env
);
1569 ret
= env
->cp15
.c15_ccnt
;
1570 pmccntr_op_finish(env
);
1574 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1577 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1578 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1579 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1582 env
->cp15
.c9_pmselr
= value
& 0x1f;
1585 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1588 pmccntr_op_start(env
);
1589 env
->cp15
.c15_ccnt
= value
;
1590 pmccntr_op_finish(env
);
1593 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1596 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1598 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1601 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1604 pmccntr_op_start(env
);
1605 env
->cp15
.pmccfiltr_el0
= value
& PMCCFILTR_EL0
;
1606 pmccntr_op_finish(env
);
1609 static void pmccfiltr_write_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1612 pmccntr_op_start(env
);
1613 /* M is not accessible from AArch32 */
1614 env
->cp15
.pmccfiltr_el0
= (env
->cp15
.pmccfiltr_el0
& PMCCFILTR_M
) |
1615 (value
& PMCCFILTR
);
1616 pmccntr_op_finish(env
);
1619 static uint64_t pmccfiltr_read_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1621 /* M is not visible in AArch32 */
1622 return env
->cp15
.pmccfiltr_el0
& PMCCFILTR
;
1625 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1628 value
&= pmu_counter_mask(env
);
1629 env
->cp15
.c9_pmcnten
|= value
;
1632 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1635 value
&= pmu_counter_mask(env
);
1636 env
->cp15
.c9_pmcnten
&= ~value
;
1639 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1642 value
&= pmu_counter_mask(env
);
1643 env
->cp15
.c9_pmovsr
&= ~value
;
1644 pmu_update_irq(env
);
1647 static void pmovsset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1650 value
&= pmu_counter_mask(env
);
1651 env
->cp15
.c9_pmovsr
|= value
;
1652 pmu_update_irq(env
);
1655 static void pmevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1656 uint64_t value
, const uint8_t counter
)
1658 if (counter
== 31) {
1659 pmccfiltr_write(env
, ri
, value
);
1660 } else if (counter
< pmu_num_counters(env
)) {
1661 pmevcntr_op_start(env
, counter
);
1664 * If this counter's event type is changing, store the current
1665 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1666 * pmevcntr_op_finish has the correct baseline when it converts back to
1669 uint16_t old_event
= env
->cp15
.c14_pmevtyper
[counter
] &
1670 PMXEVTYPER_EVTCOUNT
;
1671 uint16_t new_event
= value
& PMXEVTYPER_EVTCOUNT
;
1672 if (old_event
!= new_event
) {
1674 if (event_supported(new_event
)) {
1675 uint16_t event_idx
= supported_event_map
[new_event
];
1676 count
= pm_events
[event_idx
].get_count(env
);
1678 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1681 env
->cp15
.c14_pmevtyper
[counter
] = value
& PMXEVTYPER_MASK
;
1682 pmevcntr_op_finish(env
, counter
);
1684 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1685 * PMSELR value is equal to or greater than the number of implemented
1686 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1690 static uint64_t pmevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1691 const uint8_t counter
)
1693 if (counter
== 31) {
1694 return env
->cp15
.pmccfiltr_el0
;
1695 } else if (counter
< pmu_num_counters(env
)) {
1696 return env
->cp15
.c14_pmevtyper
[counter
];
1699 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1700 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1706 static void pmevtyper_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1709 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1710 pmevtyper_write(env
, ri
, value
, counter
);
1713 static void pmevtyper_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1716 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1717 env
->cp15
.c14_pmevtyper
[counter
] = value
;
1720 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1721 * pmu_op_finish calls when loading saved state for a migration. Because
1722 * we're potentially updating the type of event here, the value written to
1723 * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
1724 * different counter type. Therefore, we need to set this value to the
1725 * current count for the counter type we're writing so that pmu_op_finish
1726 * has the correct count for its calculation.
1728 uint16_t event
= value
& PMXEVTYPER_EVTCOUNT
;
1729 if (event_supported(event
)) {
1730 uint16_t event_idx
= supported_event_map
[event
];
1731 env
->cp15
.c14_pmevcntr_delta
[counter
] =
1732 pm_events
[event_idx
].get_count(env
);
1736 static uint64_t pmevtyper_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1738 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1739 return pmevtyper_read(env
, ri
, counter
);
1742 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1745 pmevtyper_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1748 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1750 return pmevtyper_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1753 static void pmevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1754 uint64_t value
, uint8_t counter
)
1756 if (counter
< pmu_num_counters(env
)) {
1757 pmevcntr_op_start(env
, counter
);
1758 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1759 pmevcntr_op_finish(env
, counter
);
1762 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1763 * are CONSTRAINED UNPREDICTABLE.
1767 static uint64_t pmevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1770 if (counter
< pmu_num_counters(env
)) {
1772 pmevcntr_op_start(env
, counter
);
1773 ret
= env
->cp15
.c14_pmevcntr
[counter
];
1774 pmevcntr_op_finish(env
, counter
);
1777 /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1778 * are CONSTRAINED UNPREDICTABLE. */
1783 static void pmevcntr_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1786 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1787 pmevcntr_write(env
, ri
, value
, counter
);
1790 static uint64_t pmevcntr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1792 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1793 return pmevcntr_read(env
, ri
, counter
);
1796 static void pmevcntr_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1799 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1800 assert(counter
< pmu_num_counters(env
));
1801 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1802 pmevcntr_write(env
, ri
, value
, counter
);
1805 static uint64_t pmevcntr_rawread(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1807 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1808 assert(counter
< pmu_num_counters(env
));
1809 return env
->cp15
.c14_pmevcntr
[counter
];
1812 static void pmxevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1815 pmevcntr_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1818 static uint64_t pmxevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1820 return pmevcntr_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1823 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1826 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1827 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1829 env
->cp15
.c9_pmuserenr
= value
& 1;
1833 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1836 /* We have no event counters so only the C bit can be changed */
1837 value
&= pmu_counter_mask(env
);
1838 env
->cp15
.c9_pminten
|= value
;
1839 pmu_update_irq(env
);
1842 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1845 value
&= pmu_counter_mask(env
);
1846 env
->cp15
.c9_pminten
&= ~value
;
1847 pmu_update_irq(env
);
1850 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1853 /* Note that even though the AArch64 view of this register has bits
1854 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1855 * architectural requirements for bits which are RES0 only in some
1856 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1857 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1859 raw_write(env
, ri
, value
& ~0x1FULL
);
1862 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1864 /* Begin with base v8.0 state. */
1865 uint32_t valid_mask
= 0x3fff;
1866 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1868 if (arm_el_is_aa64(env
, 3)) {
1869 value
|= SCR_FW
| SCR_AW
; /* these two bits are RES1. */
1870 valid_mask
&= ~SCR_NET
;
1872 valid_mask
&= ~(SCR_RW
| SCR_ST
);
1875 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1876 valid_mask
&= ~SCR_HCE
;
1878 /* On ARMv7, SMD (or SCD as it is called in v7) is only
1879 * supported if EL2 exists. The bit is UNK/SBZP when
1880 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1881 * when EL2 is unavailable.
1882 * On ARMv8, this bit is always available.
1884 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1885 !arm_feature(env
, ARM_FEATURE_V8
)) {
1886 valid_mask
&= ~SCR_SMD
;
1889 if (cpu_isar_feature(aa64_lor
, cpu
)) {
1890 valid_mask
|= SCR_TLOR
;
1892 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
1893 valid_mask
|= SCR_API
| SCR_APK
;
1896 /* Clear all-context RES0 bits. */
1897 value
&= valid_mask
;
1898 raw_write(env
, ri
, value
);
1901 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1903 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1905 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1908 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1909 ri
->secure
& ARM_CP_SECSTATE_S
);
1911 return cpu
->ccsidr
[index
];
1914 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1917 raw_write(env
, ri
, value
& 0xf);
1920 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1922 CPUState
*cs
= ENV_GET_CPU(env
);
1923 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
1926 if (hcr_el2
& HCR_IMO
) {
1927 if (cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) {
1931 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
1936 if (hcr_el2
& HCR_FMO
) {
1937 if (cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) {
1941 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
1946 /* External aborts are not possible in QEMU so A bit is always clear */
1950 static const ARMCPRegInfo v7_cp_reginfo
[] = {
1951 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
1952 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
1953 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1954 /* Performance monitors are implementation defined in v7,
1955 * but with an ARM recommended set of registers, which we
1958 * Performance registers fall into three categories:
1959 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
1960 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
1961 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
1962 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
1963 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
1965 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
1966 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1967 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1968 .writefn
= pmcntenset_write
,
1969 .accessfn
= pmreg_access
,
1970 .raw_writefn
= raw_write
},
1971 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
,
1972 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
1973 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1974 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
1975 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
1976 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
1978 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1979 .accessfn
= pmreg_access
,
1980 .writefn
= pmcntenclr_write
,
1981 .type
= ARM_CP_ALIAS
},
1982 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1983 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
1984 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1985 .type
= ARM_CP_ALIAS
,
1986 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
1987 .writefn
= pmcntenclr_write
},
1988 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
1989 .access
= PL0_RW
, .type
= ARM_CP_IO
,
1990 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
1991 .accessfn
= pmreg_access
,
1992 .writefn
= pmovsr_write
,
1993 .raw_writefn
= raw_write
},
1994 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1995 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
1996 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1997 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
1998 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
1999 .writefn
= pmovsr_write
,
2000 .raw_writefn
= raw_write
},
2001 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
2002 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2003 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2004 .writefn
= pmswinc_write
},
2005 { .name
= "PMSWINC_EL0", .state
= ARM_CP_STATE_AA64
,
2006 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 4,
2007 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2008 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2009 .writefn
= pmswinc_write
},
2010 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
2011 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
2012 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
2013 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
2014 .raw_writefn
= raw_write
},
2015 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
2016 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
2017 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
2018 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
2019 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
2020 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
2021 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2022 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
2023 .accessfn
= pmreg_access_ccntr
},
2024 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2025 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
2026 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
2028 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ccnt
),
2029 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
2030 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
, },
2031 { .name
= "PMCCFILTR", .cp
= 15, .opc1
= 0, .crn
= 14, .crm
= 15, .opc2
= 7,
2032 .writefn
= pmccfiltr_write_a32
, .readfn
= pmccfiltr_read_a32
,
2033 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2034 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2036 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
2037 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
2038 .writefn
= pmccfiltr_write
, .raw_writefn
= raw_write
,
2039 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2041 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
2043 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
2044 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2045 .accessfn
= pmreg_access
,
2046 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2047 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
2048 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
2049 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2050 .accessfn
= pmreg_access
,
2051 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2052 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
2053 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2054 .accessfn
= pmreg_access_xevcntr
,
2055 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2056 { .name
= "PMXEVCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2057 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 2,
2058 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2059 .accessfn
= pmreg_access_xevcntr
,
2060 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2061 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
2062 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
2063 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
2065 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2066 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
2067 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
2068 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
2069 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
2071 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2072 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
2073 .access
= PL1_RW
, .accessfn
= access_tpm
,
2074 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2075 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
2077 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
2078 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
2079 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
2080 .access
= PL1_RW
, .accessfn
= access_tpm
,
2082 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2083 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
2084 .resetvalue
= 0x0 },
2085 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
2086 .access
= PL1_RW
, .accessfn
= access_tpm
,
2087 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2088 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2089 .writefn
= pmintenclr_write
, },
2090 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
2091 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
2092 .access
= PL1_RW
, .accessfn
= access_tpm
,
2093 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2094 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2095 .writefn
= pmintenclr_write
},
2096 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
2097 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
2098 .access
= PL1_R
, .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
2099 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
2100 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
2101 .access
= PL1_RW
, .writefn
= csselr_write
, .resetvalue
= 0,
2102 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
2103 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
2104 /* Auxiliary ID register: this actually has an IMPDEF value but for now
2105 * just RAZ for all cores:
2107 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
2108 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
2109 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2110 /* Auxiliary fault status registers: these also are IMPDEF, and we
2111 * choose to RAZ/WI for all cores.
2113 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2114 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
2115 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2116 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2117 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
2118 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2119 /* MAIR can just read-as-written because we don't implement caches
2120 * and so don't need to care about memory attributes.
2122 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
2123 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2124 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
2126 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
2127 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
2128 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
2130 /* For non-long-descriptor page tables these are PRRR and NMRR;
2131 * regardless they still act as reads-as-written for QEMU.
2133 /* MAIR0/1 are defined separately from their 64-bit counterpart which
2134 * allows them to assign the correct fieldoffset based on the endianness
2135 * handled in the field definitions.
2137 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
2138 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0, .access
= PL1_RW
,
2139 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
2140 offsetof(CPUARMState
, cp15
.mair0_ns
) },
2141 .resetfn
= arm_cp_reset_ignore
},
2142 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
2143 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1, .access
= PL1_RW
,
2144 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
2145 offsetof(CPUARMState
, cp15
.mair1_ns
) },
2146 .resetfn
= arm_cp_reset_ignore
},
2147 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
2148 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
2149 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
2150 /* 32 bit ITLB invalidates */
2151 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2152 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
2153 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2154 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2155 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2156 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
2157 /* 32 bit DTLB invalidates */
2158 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2159 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
2160 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2161 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2162 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2163 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
2164 /* 32 bit TLB invalidates */
2165 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2166 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
2167 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2168 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2169 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2170 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
2171 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2172 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
2176 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
2177 /* 32 bit TLB invalidates, Inner Shareable */
2178 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2179 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_is_write
},
2180 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2181 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
2182 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2183 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
2184 .writefn
= tlbiasid_is_write
},
2185 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2186 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
2187 .writefn
= tlbimvaa_is_write
},
2191 static const ARMCPRegInfo pmovsset_cp_reginfo
[] = {
2192 /* PMOVSSET is not implemented in v7 before v7ve */
2193 { .name
= "PMOVSSET", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 3,
2194 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2195 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2196 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2197 .writefn
= pmovsset_write
,
2198 .raw_writefn
= raw_write
},
2199 { .name
= "PMOVSSET_EL0", .state
= ARM_CP_STATE_AA64
,
2200 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 3,
2201 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2202 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2203 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2204 .writefn
= pmovsset_write
,
2205 .raw_writefn
= raw_write
},
2209 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2216 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2219 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
2220 return CP_ACCESS_TRAP
;
2222 return CP_ACCESS_OK
;
2225 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
2226 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
2227 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
2229 .writefn
= teecr_write
},
2230 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
2231 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
2232 .accessfn
= teehbr_access
, .resetvalue
= 0 },
2236 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
2237 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
2238 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
2240 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
2241 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
2243 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
2244 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
2245 .resetfn
= arm_cp_reset_ignore
},
2246 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
2247 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
2248 .access
= PL0_R
|PL1_W
,
2249 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
2251 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
2252 .access
= PL0_R
|PL1_W
,
2253 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
2254 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
2255 .resetfn
= arm_cp_reset_ignore
},
2256 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2257 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
2259 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
2260 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
2262 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
2263 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
2268 #ifndef CONFIG_USER_ONLY
2270 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2273 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2274 * Writable only at the highest implemented exception level.
2276 int el
= arm_current_el(env
);
2280 if (!extract32(env
->cp15
.c14_cntkctl
, 0, 2)) {
2281 return CP_ACCESS_TRAP
;
2285 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
2286 arm_is_secure_below_el3(env
)) {
2287 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2288 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2296 if (!isread
&& el
< arm_highest_el(env
)) {
2297 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2300 return CP_ACCESS_OK
;
2303 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
2306 unsigned int cur_el
= arm_current_el(env
);
2307 bool secure
= arm_is_secure(env
);
2309 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
2311 !extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
2312 return CP_ACCESS_TRAP
;
2315 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
2316 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
2317 !extract32(env
->cp15
.cnthctl_el2
, 0, 1)) {
2318 return CP_ACCESS_TRAP_EL2
;
2320 return CP_ACCESS_OK
;
2323 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
2326 unsigned int cur_el
= arm_current_el(env
);
2327 bool secure
= arm_is_secure(env
);
2329 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
2330 * EL0[PV]TEN is zero.
2333 !extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
2334 return CP_ACCESS_TRAP
;
2337 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
2338 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
2339 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2340 return CP_ACCESS_TRAP_EL2
;
2342 return CP_ACCESS_OK
;
2345 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
2346 const ARMCPRegInfo
*ri
,
2349 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
2352 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
2353 const ARMCPRegInfo
*ri
,
2356 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
2359 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2362 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
2365 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2368 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
2371 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
2372 const ARMCPRegInfo
*ri
,
2375 /* The AArch64 register view of the secure physical timer is
2376 * always accessible from EL3, and configurably accessible from
2379 switch (arm_current_el(env
)) {
2381 if (!arm_is_secure(env
)) {
2382 return CP_ACCESS_TRAP
;
2384 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
2385 return CP_ACCESS_TRAP_EL3
;
2387 return CP_ACCESS_OK
;
2390 return CP_ACCESS_TRAP
;
2392 return CP_ACCESS_OK
;
2394 g_assert_not_reached();
2398 static uint64_t gt_get_countervalue(CPUARMState
*env
)
2400 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / GTIMER_SCALE
;
2403 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
2405 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
2408 /* Timer enabled: calculate and set current ISTATUS, irq, and
2409 * reset timer to when ISTATUS next has to change
2411 uint64_t offset
= timeridx
== GTIMER_VIRT
?
2412 cpu
->env
.cp15
.cntvoff_el2
: 0;
2413 uint64_t count
= gt_get_countervalue(&cpu
->env
);
2414 /* Note that this must be unsigned 64 bit arithmetic: */
2415 int istatus
= count
- offset
>= gt
->cval
;
2419 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
2421 irqstate
= (istatus
&& !(gt
->ctl
& 2));
2422 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2425 /* Next transition is when count rolls back over to zero */
2426 nexttick
= UINT64_MAX
;
2428 /* Next transition is when we hit cval */
2429 nexttick
= gt
->cval
+ offset
;
2431 /* Note that the desired next expiry time might be beyond the
2432 * signed-64-bit range of a QEMUTimer -- in this case we just
2433 * set the timer for as far in the future as possible. When the
2434 * timer expires we will reset the timer for any remaining period.
2436 if (nexttick
> INT64_MAX
/ GTIMER_SCALE
) {
2437 nexttick
= INT64_MAX
/ GTIMER_SCALE
;
2439 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
2440 trace_arm_gt_recalc(timeridx
, irqstate
, nexttick
);
2442 /* Timer disabled: ISTATUS and timer output always clear */
2444 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
2445 timer_del(cpu
->gt_timer
[timeridx
]);
2446 trace_arm_gt_recalc_disabled(timeridx
);
2450 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2453 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2455 timer_del(cpu
->gt_timer
[timeridx
]);
2458 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2460 return gt_get_countervalue(env
);
2463 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2465 return gt_get_countervalue(env
) - env
->cp15
.cntvoff_el2
;
2468 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2472 trace_arm_gt_cval_write(timeridx
, value
);
2473 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
2474 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
2477 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2480 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
2482 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
2483 (gt_get_countervalue(env
) - offset
));
2486 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2490 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
2492 trace_arm_gt_tval_write(timeridx
, value
);
2493 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
2494 sextract64(value
, 0, 32);
2495 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
2498 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2502 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2503 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
2505 trace_arm_gt_ctl_write(timeridx
, value
);
2506 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
2507 if ((oldval
^ value
) & 1) {
2508 /* Enable toggled */
2509 gt_recalc_timer(cpu
, timeridx
);
2510 } else if ((oldval
^ value
) & 2) {
2511 /* IMASK toggled: don't need to recalculate,
2512 * just set the interrupt line based on ISTATUS
2514 int irqstate
= (oldval
& 4) && !(value
& 2);
2516 trace_arm_gt_imask_toggle(timeridx
, irqstate
);
2517 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2521 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2523 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
2526 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2529 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
2532 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2534 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
2537 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2540 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
2543 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2546 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
2549 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2551 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
2554 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2557 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
2560 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2562 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
2565 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2568 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
2571 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2574 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
2577 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2580 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2582 trace_arm_gt_cntvoff_write(value
);
2583 raw_write(env
, ri
, value
);
2584 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2587 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2589 gt_timer_reset(env
, ri
, GTIMER_HYP
);
2592 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2595 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
2598 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2600 return gt_tval_read(env
, ri
, GTIMER_HYP
);
2603 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2606 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
2609 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2612 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
2615 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2617 gt_timer_reset(env
, ri
, GTIMER_SEC
);
2620 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2623 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
2626 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2628 return gt_tval_read(env
, ri
, GTIMER_SEC
);
2631 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2634 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
2637 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2640 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
2643 void arm_gt_ptimer_cb(void *opaque
)
2645 ARMCPU
*cpu
= opaque
;
2647 gt_recalc_timer(cpu
, GTIMER_PHYS
);
2650 void arm_gt_vtimer_cb(void *opaque
)
2652 ARMCPU
*cpu
= opaque
;
2654 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2657 void arm_gt_htimer_cb(void *opaque
)
2659 ARMCPU
*cpu
= opaque
;
2661 gt_recalc_timer(cpu
, GTIMER_HYP
);
2664 void arm_gt_stimer_cb(void *opaque
)
2666 ARMCPU
*cpu
= opaque
;
2668 gt_recalc_timer(cpu
, GTIMER_SEC
);
2671 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
2672 /* Note that CNTFRQ is purely reads-as-written for the benefit
2673 * of software; writing it doesn't actually change the timer frequency.
2674 * Our reset value matches the fixed frequency we implement the timer at.
2676 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
2677 .type
= ARM_CP_ALIAS
,
2678 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
2679 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
2681 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
2682 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
2683 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
2684 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
2685 .resetvalue
= (1000 * 1000 * 1000) / GTIMER_SCALE
,
2687 /* overall control: mostly access permissions */
2688 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
2689 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
2691 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
2694 /* per-timer control */
2695 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
2696 .secure
= ARM_CP_SECSTATE_NS
,
2697 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
2698 .accessfn
= gt_ptimer_access
,
2699 .fieldoffset
= offsetoflow32(CPUARMState
,
2700 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
2701 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
2703 { .name
= "CNTP_CTL_S",
2704 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
2705 .secure
= ARM_CP_SECSTATE_S
,
2706 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
2707 .accessfn
= gt_ptimer_access
,
2708 .fieldoffset
= offsetoflow32(CPUARMState
,
2709 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
2710 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
2712 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
2713 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
2714 .type
= ARM_CP_IO
, .access
= PL0_RW
,
2715 .accessfn
= gt_ptimer_access
,
2716 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
2718 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
2720 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
2721 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
2722 .accessfn
= gt_vtimer_access
,
2723 .fieldoffset
= offsetoflow32(CPUARMState
,
2724 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
2725 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
2727 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
2728 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
2729 .type
= ARM_CP_IO
, .access
= PL0_RW
,
2730 .accessfn
= gt_vtimer_access
,
2731 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
2733 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
2735 /* TimerValue views: a 32 bit downcounting view of the underlying state */
2736 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2737 .secure
= ARM_CP_SECSTATE_NS
,
2738 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2739 .accessfn
= gt_ptimer_access
,
2740 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
2742 { .name
= "CNTP_TVAL_S",
2743 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2744 .secure
= ARM_CP_SECSTATE_S
,
2745 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2746 .accessfn
= gt_ptimer_access
,
2747 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
2749 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2750 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
2751 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2752 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
2753 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
2755 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
2756 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2757 .accessfn
= gt_vtimer_access
,
2758 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
2760 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2761 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
2762 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2763 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
2764 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
2766 /* The counter itself */
2767 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
2768 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
2769 .accessfn
= gt_pct_access
,
2770 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
2772 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
2773 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
2774 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2775 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
2777 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
2778 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
2779 .accessfn
= gt_vct_access
,
2780 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
2782 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
2783 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
2784 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2785 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
2787 /* Comparison value, indicating when the timer goes off */
2788 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
2789 .secure
= ARM_CP_SECSTATE_NS
,
2791 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2792 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
2793 .accessfn
= gt_ptimer_access
,
2794 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
2796 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
2797 .secure
= ARM_CP_SECSTATE_S
,
2799 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2800 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
2801 .accessfn
= gt_ptimer_access
,
2802 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
2804 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2805 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
2808 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
2809 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
2810 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
2812 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
2814 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2815 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
2816 .accessfn
= gt_vtimer_access
,
2817 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
2819 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2820 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
2823 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
2824 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
2825 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
2827 /* Secure timer -- this is actually restricted to only EL3
2828 * and configurably Secure-EL1 via the accessfn.
2830 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
2831 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
2832 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
2833 .accessfn
= gt_stimer_access
,
2834 .readfn
= gt_sec_tval_read
,
2835 .writefn
= gt_sec_tval_write
,
2836 .resetfn
= gt_sec_timer_reset
,
2838 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
2839 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
2840 .type
= ARM_CP_IO
, .access
= PL1_RW
,
2841 .accessfn
= gt_stimer_access
,
2842 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
2844 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
2846 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
2847 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
2848 .type
= ARM_CP_IO
, .access
= PL1_RW
,
2849 .accessfn
= gt_stimer_access
,
2850 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
2851 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
2858 /* In user-mode most of the generic timer registers are inaccessible
2859 * however modern kernels (4.12+) allow access to cntvct_el0
2862 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2864 /* Currently we have no support for QEMUTimer in linux-user so we
2865 * can't call gt_get_countervalue(env), instead we directly
2866 * call the lower level functions.
2868 return cpu_get_clock() / GTIMER_SCALE
;
2871 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
2872 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
2873 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
2874 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
2875 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
2876 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
2878 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
2879 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
2880 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2881 .readfn
= gt_virt_cnt_read
,
2888 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
2890 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2891 raw_write(env
, ri
, value
);
2892 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
2893 raw_write(env
, ri
, value
& 0xfffff6ff);
2895 raw_write(env
, ri
, value
& 0xfffff1ff);
2899 #ifndef CONFIG_USER_ONLY
2900 /* get_phys_addr() isn't present for user-mode-only targets */
2902 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2906 /* The ATS12NSO* operations must trap to EL3 if executed in
2907 * Secure EL1 (which can only happen if EL3 is AArch64).
2908 * They are simply UNDEF if executed from NS EL1.
2909 * They function normally from EL2 or EL3.
2911 if (arm_current_el(env
) == 1) {
2912 if (arm_is_secure_below_el3(env
)) {
2913 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3
;
2915 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2918 return CP_ACCESS_OK
;
2921 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
2922 MMUAccessType access_type
, ARMMMUIdx mmu_idx
)
2925 target_ulong page_size
;
2929 bool format64
= false;
2930 MemTxAttrs attrs
= {};
2931 ARMMMUFaultInfo fi
= {};
2932 ARMCacheAttrs cacheattrs
= {};
2934 ret
= get_phys_addr(env
, value
, access_type
, mmu_idx
, &phys_addr
, &attrs
,
2935 &prot
, &page_size
, &fi
, &cacheattrs
);
2939 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2942 * * TTBCR.EAE determines whether the result is returned using the
2943 * 32-bit or the 64-bit PAR format
2944 * * Instructions executed in Hyp mode always use the 64bit format
2946 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
2947 * * The Non-secure TTBCR.EAE bit is set to 1
2948 * * The implementation includes EL2, and the value of HCR.VM is 1
2950 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
2952 * ATS1Hx always uses the 64bit format.
2954 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
2956 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
2957 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
2958 format64
|= env
->cp15
.hcr_el2
& (HCR_VM
| HCR_DC
);
2960 format64
|= arm_current_el(env
) == 2;
2966 /* Create a 64-bit PAR */
2967 par64
= (1 << 11); /* LPAE bit always set */
2969 par64
|= phys_addr
& ~0xfffULL
;
2970 if (!attrs
.secure
) {
2971 par64
|= (1 << 9); /* NS */
2973 par64
|= (uint64_t)cacheattrs
.attrs
<< 56; /* ATTR */
2974 par64
|= cacheattrs
.shareability
<< 7; /* SH */
2976 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
2979 par64
|= (fsr
& 0x3f) << 1; /* FS */
2981 par64
|= (1 << 9); /* S */
2984 par64
|= (1 << 8); /* PTW */
2988 /* fsr is a DFSR/IFSR value for the short descriptor
2989 * translation table format (with WnR always clear).
2990 * Convert it to a 32-bit PAR.
2993 /* We do not set any attribute bits in the PAR */
2994 if (page_size
== (1 << 24)
2995 && arm_feature(env
, ARM_FEATURE_V7
)) {
2996 par64
= (phys_addr
& 0xff000000) | (1 << 1);
2998 par64
= phys_addr
& 0xfffff000;
3000 if (!attrs
.secure
) {
3001 par64
|= (1 << 9); /* NS */
3004 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
3006 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
3007 ((fsr
& 0xf) << 1) | 1;
3013 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3015 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3018 int el
= arm_current_el(env
);
3019 bool secure
= arm_is_secure_below_el3(env
);
3021 switch (ri
->opc2
& 6) {
3023 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
3026 mmu_idx
= ARMMMUIdx_S1E3
;
3029 mmu_idx
= ARMMMUIdx_S1NSE1
;
3032 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
3035 g_assert_not_reached();
3039 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3042 mmu_idx
= ARMMMUIdx_S1SE0
;
3045 mmu_idx
= ARMMMUIdx_S1NSE0
;
3048 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
3051 g_assert_not_reached();
3055 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3056 mmu_idx
= ARMMMUIdx_S12NSE1
;
3059 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3060 mmu_idx
= ARMMMUIdx_S12NSE0
;
3063 g_assert_not_reached();
3066 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
);
3068 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3071 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3074 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3077 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_S1E2
);
3079 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3082 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3085 if (arm_current_el(env
) == 3 && !(env
->cp15
.scr_el3
& SCR_NS
)) {
3086 return CP_ACCESS_TRAP
;
3088 return CP_ACCESS_OK
;
3091 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3094 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3096 int secure
= arm_is_secure_below_el3(env
);
3098 switch (ri
->opc2
& 6) {
3101 case 0: /* AT S1E1R, AT S1E1W */
3102 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
3104 case 4: /* AT S1E2R, AT S1E2W */
3105 mmu_idx
= ARMMMUIdx_S1E2
;
3107 case 6: /* AT S1E3R, AT S1E3W */
3108 mmu_idx
= ARMMMUIdx_S1E3
;
3111 g_assert_not_reached();
3114 case 2: /* AT S1E0R, AT S1E0W */
3115 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
3117 case 4: /* AT S12E1R, AT S12E1W */
3118 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S12NSE1
;
3120 case 6: /* AT S12E0R, AT S12E0W */
3121 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S12NSE0
;
3124 g_assert_not_reached();
3127 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
, mmu_idx
);
3131 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
3132 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
3133 .access
= PL1_RW
, .resetvalue
= 0,
3134 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
3135 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
3136 .writefn
= par_write
},
3137 #ifndef CONFIG_USER_ONLY
3138 /* This underdecoding is safe because the reginfo is NO_RAW. */
3139 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
3140 .access
= PL1_W
, .accessfn
= ats_access
,
3141 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
},
3146 /* Return basic MPU access permission bits. */
3147 static uint32_t simple_mpu_ap_bits(uint32_t val
)
3154 for (i
= 0; i
< 16; i
+= 2) {
3155 ret
|= (val
>> i
) & mask
;
3161 /* Pad basic MPU access permission bits to extended format. */
3162 static uint32_t extended_mpu_ap_bits(uint32_t val
)
3169 for (i
= 0; i
< 16; i
+= 2) {
3170 ret
|= (val
& mask
) << i
;
3176 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3179 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
3182 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3184 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
3187 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3190 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
3193 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3195 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
3198 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3200 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3206 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3210 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3213 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3214 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3220 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3221 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3225 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3228 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3229 uint32_t nrgs
= cpu
->pmsav7_dregion
;
3231 if (value
>= nrgs
) {
3232 qemu_log_mask(LOG_GUEST_ERROR
,
3233 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3234 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
3238 raw_write(env
, ri
, value
);
3241 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
3242 /* Reset for all these registers is handled in arm_cpu_reset(),
3243 * because the PMSAv7 is also used by M-profile CPUs, which do
3244 * not register cpregs but still need the state to be reset.
3246 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
3247 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3248 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
3249 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3250 .resetfn
= arm_cp_reset_ignore
},
3251 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
3252 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3253 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
3254 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3255 .resetfn
= arm_cp_reset_ignore
},
3256 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
3257 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3258 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
3259 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3260 .resetfn
= arm_cp_reset_ignore
},
3261 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
3263 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
3264 .writefn
= pmsav7_rgnr_write
,
3265 .resetfn
= arm_cp_reset_ignore
},
3269 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
3270 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3271 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3272 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3273 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
3274 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3275 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3276 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3277 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
3278 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
3280 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3282 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
3284 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3286 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
3288 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
3289 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
3291 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
3292 /* Protection region base and size registers */
3293 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
3294 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3295 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
3296 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
3297 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3298 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
3299 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
3300 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3301 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
3302 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
3303 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3304 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
3305 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
3306 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3307 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
3308 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
3309 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3310 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
3311 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
3312 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3313 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
3314 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
3315 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3316 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
3320 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3323 TCR
*tcr
= raw_ptr(env
, ri
);
3324 int maskshift
= extract32(value
, 0, 3);
3326 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
3327 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
3328 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
3329 * using Long-desciptor translation table format */
3330 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
3331 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3332 /* In an implementation that includes the Security Extensions
3333 * TTBCR has additional fields PD0 [4] and PD1 [5] for
3334 * Short-descriptor translation table format.
3336 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
3342 /* Update the masks corresponding to the TCR bank being written
3343 * Note that we always calculate mask and base_mask, but
3344 * they are only used for short-descriptor tables (ie if EAE is 0);
3345 * for long-descriptor tables the TCR fields are used differently
3346 * and the mask and base_mask values are meaningless.
3348 tcr
->raw_tcr
= value
;
3349 tcr
->mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
3350 tcr
->base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
3353 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3356 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3357 TCR
*tcr
= raw_ptr(env
, ri
);
3359 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3360 /* With LPAE the TTBCR could result in a change of ASID
3361 * via the TTBCR.A1 bit, so do a TLB flush.
3363 tlb_flush(CPU(cpu
));
3365 /* Preserve the high half of TCR_EL1, set via TTBCR2. */
3366 value
= deposit64(tcr
->raw_tcr
, 0, 32, value
);
3367 vmsa_ttbcr_raw_write(env
, ri
, value
);
3370 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3372 TCR
*tcr
= raw_ptr(env
, ri
);
3374 /* Reset both the TCR as well as the masks corresponding to the bank of
3375 * the TCR being reset.
3379 tcr
->base_mask
= 0xffffc000u
;
3382 static void vmsa_tcr_el1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3385 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3386 TCR
*tcr
= raw_ptr(env
, ri
);
3388 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
3389 tlb_flush(CPU(cpu
));
3390 tcr
->raw_tcr
= value
;
3393 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3396 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
3397 if (cpreg_field_is_64bit(ri
) &&
3398 extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
3399 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3400 tlb_flush(CPU(cpu
));
3402 raw_write(env
, ri
, value
);
3405 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3408 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3409 CPUState
*cs
= CPU(cpu
);
3411 /* Accesses to VTTBR may change the VMID so we must flush the TLB. */
3412 if (raw_read(env
, ri
) != value
) {
3413 tlb_flush_by_mmuidx(cs
,
3414 ARMMMUIdxBit_S12NSE1
|
3415 ARMMMUIdxBit_S12NSE0
|
3417 raw_write(env
, ri
, value
);
3421 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
3422 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3423 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3424 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
3425 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
3426 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3427 .access
= PL1_RW
, .resetvalue
= 0,
3428 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
3429 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
3430 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
3431 .access
= PL1_RW
, .resetvalue
= 0,
3432 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
3433 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
3434 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
3435 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
3436 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
3441 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
3442 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
3443 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
3445 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
3446 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
3447 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
3448 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
3449 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
3450 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
3451 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
3452 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
3453 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
3454 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
3455 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
3456 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
3457 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
3458 .access
= PL1_RW
, .writefn
= vmsa_tcr_el1_write
,
3459 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
3460 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
3461 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
3462 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
3463 .raw_writefn
= vmsa_ttbcr_raw_write
,
3464 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
3465 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
3469 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
3470 * qemu tlbs nor adjusting cached masks.
3472 static const ARMCPRegInfo ttbcr2_reginfo
= {
3473 .name
= "TTBCR2", .cp
= 15, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 3,
3474 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3475 .bank_fieldoffsets
= { offsetofhigh32(CPUARMState
, cp15
.tcr_el
[3]),
3476 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[1]) },
3479 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3482 env
->cp15
.c15_ticonfig
= value
& 0xe7;
3483 /* The OS_TYPE bit in this register changes the reported CPUID! */
3484 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
3485 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
3488 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3491 env
->cp15
.c15_threadid
= value
& 0xffff;
3494 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3497 /* Wait-for-interrupt (deprecated) */
3498 cpu_interrupt(CPU(arm_env_get_cpu(env
)), CPU_INTERRUPT_HALT
);
3501 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3504 /* On OMAP there are registers indicating the max/min index of dcache lines
3505 * containing a dirty line; cache flush operations have to reset these.
3507 env
->cp15
.c15_i_max
= 0x000;
3508 env
->cp15
.c15_i_min
= 0xff0;
3511 static const ARMCPRegInfo omap_cp_reginfo
[] = {
3512 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
3513 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
3514 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
3516 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
3517 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
3518 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
3520 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
3521 .writefn
= omap_ticonfig_write
},
3522 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
3524 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
3525 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
3526 .access
= PL1_RW
, .resetvalue
= 0xff0,
3527 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
3528 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
3530 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
3531 .writefn
= omap_threadid_write
},
3532 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
3533 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
3534 .type
= ARM_CP_NO_RAW
,
3535 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
3536 /* TODO: Peripheral port remap register:
3537 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
3538 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
3541 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
3542 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
3543 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
3544 .writefn
= omap_cachemaint_write
},
3545 { .name
= "C9", .cp
= 15, .crn
= 9,
3546 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
3547 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
3551 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3554 env
->cp15
.c15_cpar
= value
& 0x3fff;
3557 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
3558 { .name
= "XSCALE_CPAR",
3559 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
3560 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
3561 .writefn
= xscale_cpar_write
, },
3562 { .name
= "XSCALE_AUXCR",
3563 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
3564 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
3566 /* XScale specific cache-lockdown: since we have no cache we NOP these
3567 * and hope the guest does not really rely on cache behaviour.
3569 { .name
= "XSCALE_LOCK_ICACHE_LINE",
3570 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
3571 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3572 { .name
= "XSCALE_UNLOCK_ICACHE",
3573 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
3574 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3575 { .name
= "XSCALE_DCACHE_LOCK",
3576 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
3577 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
3578 { .name
= "XSCALE_UNLOCK_DCACHE",
3579 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
3580 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3584 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
3585 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
3586 * implementation of this implementation-defined space.
3587 * Ideally this should eventually disappear in favour of actually
3588 * implementing the correct behaviour for all cores.
3590 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
3591 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
3593 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
3598 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
3599 /* Cache status: RAZ because we have no cache so it's always clean */
3600 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
3601 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3606 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
3607 /* We never have a a block transfer operation in progress */
3608 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
3609 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3611 /* The cache ops themselves: these all NOP for QEMU */
3612 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
3613 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3614 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
3615 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3616 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
3617 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3618 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
3619 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3620 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
3621 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3622 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
3623 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3627 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
3628 /* The cache test-and-clean instructions always return (1 << 30)
3629 * to indicate that there are no dirty cache lines.
3631 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
3632 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3633 .resetvalue
= (1 << 30) },
3634 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
3635 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3636 .resetvalue
= (1 << 30) },
3640 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
3641 /* Ignore ReadBuffer accesses */
3642 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
3643 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
3644 .access
= PL1_RW
, .resetvalue
= 0,
3645 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
3649 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3651 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3652 unsigned int cur_el
= arm_current_el(env
);
3653 bool secure
= arm_is_secure(env
);
3655 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
3656 return env
->cp15
.vpidr_el2
;
3658 return raw_read(env
, ri
);
3661 static uint64_t mpidr_read_val(CPUARMState
*env
)
3663 ARMCPU
*cpu
= ARM_CPU(arm_env_get_cpu(env
));
3664 uint64_t mpidr
= cpu
->mp_affinity
;
3666 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
3667 mpidr
|= (1U << 31);
3668 /* Cores which are uniprocessor (non-coherent)
3669 * but still implement the MP extensions set
3670 * bit 30. (For instance, Cortex-R5).
3672 if (cpu
->mp_is_up
) {
3673 mpidr
|= (1u << 30);
3679 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3681 unsigned int cur_el
= arm_current_el(env
);
3682 bool secure
= arm_is_secure(env
);
3684 if (arm_feature(env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
3685 return env
->cp15
.vmpidr_el2
;
3687 return mpidr_read_val(env
);
3690 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
3692 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
3693 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
3694 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
3696 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
3697 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
3698 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
3700 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
3701 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
3702 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
3703 offsetof(CPUARMState
, cp15
.par_ns
)} },
3704 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
3705 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3706 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
3707 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
3708 .writefn
= vmsa_ttbr_write
, },
3709 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
3710 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3711 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
3712 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
3713 .writefn
= vmsa_ttbr_write
, },
3717 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3719 return vfp_get_fpcr(env
);
3722 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3725 vfp_set_fpcr(env
, value
);
3728 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3730 return vfp_get_fpsr(env
);
3733 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3736 vfp_set_fpsr(env
, value
);
3739 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3742 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UMA
)) {
3743 return CP_ACCESS_TRAP
;
3745 return CP_ACCESS_OK
;
3748 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3751 env
->daif
= value
& PSTATE_DAIF
;
3754 static CPAccessResult
aa64_cacheop_access(CPUARMState
*env
,
3755 const ARMCPRegInfo
*ri
,
3758 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
3759 * SCTLR_EL1.UCI is set.
3761 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCI
)) {
3762 return CP_ACCESS_TRAP
;
3764 return CP_ACCESS_OK
;
3767 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
3768 * Page D4-1736 (DDI0487A.b)
3771 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3774 CPUState
*cs
= ENV_GET_CPU(env
);
3775 bool sec
= arm_is_secure_below_el3(env
);
3778 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3779 ARMMMUIdxBit_S1SE1
|
3780 ARMMMUIdxBit_S1SE0
);
3782 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3783 ARMMMUIdxBit_S12NSE1
|
3784 ARMMMUIdxBit_S12NSE0
);
3788 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3791 CPUState
*cs
= ENV_GET_CPU(env
);
3793 if (tlb_force_broadcast(env
)) {
3794 tlbi_aa64_vmalle1is_write(env
, NULL
, value
);
3798 if (arm_is_secure_below_el3(env
)) {
3799 tlb_flush_by_mmuidx(cs
,
3800 ARMMMUIdxBit_S1SE1
|
3801 ARMMMUIdxBit_S1SE0
);
3803 tlb_flush_by_mmuidx(cs
,
3804 ARMMMUIdxBit_S12NSE1
|
3805 ARMMMUIdxBit_S12NSE0
);
3809 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3812 /* Note that the 'ALL' scope must invalidate both stage 1 and
3813 * stage 2 translations, whereas most other scopes only invalidate
3814 * stage 1 translations.
3816 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3817 CPUState
*cs
= CPU(cpu
);
3819 if (arm_is_secure_below_el3(env
)) {
3820 tlb_flush_by_mmuidx(cs
,
3821 ARMMMUIdxBit_S1SE1
|
3822 ARMMMUIdxBit_S1SE0
);
3824 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3825 tlb_flush_by_mmuidx(cs
,
3826 ARMMMUIdxBit_S12NSE1
|
3827 ARMMMUIdxBit_S12NSE0
|
3830 tlb_flush_by_mmuidx(cs
,
3831 ARMMMUIdxBit_S12NSE1
|
3832 ARMMMUIdxBit_S12NSE0
);
3837 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3840 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3841 CPUState
*cs
= CPU(cpu
);
3843 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E2
);
3846 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3849 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3850 CPUState
*cs
= CPU(cpu
);
3852 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E3
);
3855 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3858 /* Note that the 'ALL' scope must invalidate both stage 1 and
3859 * stage 2 translations, whereas most other scopes only invalidate
3860 * stage 1 translations.
3862 CPUState
*cs
= ENV_GET_CPU(env
);
3863 bool sec
= arm_is_secure_below_el3(env
);
3864 bool has_el2
= arm_feature(env
, ARM_FEATURE_EL2
);
3867 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3868 ARMMMUIdxBit_S1SE1
|
3869 ARMMMUIdxBit_S1SE0
);
3870 } else if (has_el2
) {
3871 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3872 ARMMMUIdxBit_S12NSE1
|
3873 ARMMMUIdxBit_S12NSE0
|
3876 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3877 ARMMMUIdxBit_S12NSE1
|
3878 ARMMMUIdxBit_S12NSE0
);
3882 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3885 CPUState
*cs
= ENV_GET_CPU(env
);
3887 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E2
);
3890 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3893 CPUState
*cs
= ENV_GET_CPU(env
);
3895 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E3
);
3898 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3901 /* Invalidate by VA, EL2
3902 * Currently handles both VAE2 and VALE2, since we don't support
3903 * flush-last-level-only.
3905 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3906 CPUState
*cs
= CPU(cpu
);
3907 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3909 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E2
);
3912 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3915 /* Invalidate by VA, EL3
3916 * Currently handles both VAE3 and VALE3, since we don't support
3917 * flush-last-level-only.
3919 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3920 CPUState
*cs
= CPU(cpu
);
3921 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3923 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E3
);
3926 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3929 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3930 CPUState
*cs
= CPU(cpu
);
3931 bool sec
= arm_is_secure_below_el3(env
);
3932 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3935 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3936 ARMMMUIdxBit_S1SE1
|
3937 ARMMMUIdxBit_S1SE0
);
3939 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3940 ARMMMUIdxBit_S12NSE1
|
3941 ARMMMUIdxBit_S12NSE0
);
3945 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3948 /* Invalidate by VA, EL1&0 (AArch64 version).
3949 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
3950 * since we don't support flush-for-specific-ASID-only or
3951 * flush-last-level-only.
3953 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3954 CPUState
*cs
= CPU(cpu
);
3955 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3957 if (tlb_force_broadcast(env
)) {
3958 tlbi_aa64_vae1is_write(env
, NULL
, value
);
3962 if (arm_is_secure_below_el3(env
)) {
3963 tlb_flush_page_by_mmuidx(cs
, pageaddr
,
3964 ARMMMUIdxBit_S1SE1
|
3965 ARMMMUIdxBit_S1SE0
);
3967 tlb_flush_page_by_mmuidx(cs
, pageaddr
,
3968 ARMMMUIdxBit_S12NSE1
|
3969 ARMMMUIdxBit_S12NSE0
);
3973 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3976 CPUState
*cs
= ENV_GET_CPU(env
);
3977 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3979 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3983 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3986 CPUState
*cs
= ENV_GET_CPU(env
);
3987 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3989 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3993 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3996 /* Invalidate by IPA. This has to invalidate any structures that
3997 * contain only stage 2 translation information, but does not need
3998 * to apply to structures that contain combined stage 1 and stage 2
3999 * translation information.
4000 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
4002 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4003 CPUState
*cs
= CPU(cpu
);
4006 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
4010 pageaddr
= sextract64(value
<< 12, 0, 48);
4012 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S2NS
);
4015 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4018 CPUState
*cs
= ENV_GET_CPU(env
);
4021 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
4025 pageaddr
= sextract64(value
<< 12, 0, 48);
4027 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4031 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4034 /* We don't implement EL2, so the only control on DC ZVA is the
4035 * bit in the SCTLR which can prohibit access for EL0.
4037 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
4038 return CP_ACCESS_TRAP
;
4040 return CP_ACCESS_OK
;
4043 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4045 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4046 int dzp_bit
= 1 << 4;
4048 /* DZP indicates whether DC ZVA access is allowed */
4049 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
4052 return cpu
->dcz_blocksize
| dzp_bit
;
4055 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4058 if (!(env
->pstate
& PSTATE_SP
)) {
4059 /* Access to SP_EL0 is undefined if it's being used as
4060 * the stack pointer.
4062 return CP_ACCESS_TRAP_UNCATEGORIZED
;
4064 return CP_ACCESS_OK
;
4067 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4069 return env
->pstate
& PSTATE_SP
;
4072 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
4074 update_spsel(env
, val
);
4077 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4080 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4082 if (raw_read(env
, ri
) == value
) {
4083 /* Skip the TLB flush if nothing actually changed; Linux likes
4084 * to do a lot of pointless SCTLR writes.
4089 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
4090 /* M bit is RAZ/WI for PMSA with no MPU implemented */
4094 raw_write(env
, ri
, value
);
4095 /* ??? Lots of these bits are not implemented. */
4096 /* This may enable/disable the MMU, so do a TLB flush. */
4097 tlb_flush(CPU(cpu
));
4100 static CPAccessResult
fpexc32_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4103 if ((env
->cp15
.cptr_el
[2] & CPTR_TFP
) && arm_current_el(env
) == 2) {
4104 return CP_ACCESS_TRAP_FP_EL2
;
4106 if (env
->cp15
.cptr_el
[3] & CPTR_TFP
) {
4107 return CP_ACCESS_TRAP_FP_EL3
;
4109 return CP_ACCESS_OK
;
4112 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4115 env
->cp15
.mdcr_el3
= value
& SDCR_VALID_MASK
;
4118 static const ARMCPRegInfo v8_cp_reginfo
[] = {
4119 /* Minimal set of EL0-visible registers. This will need to be expanded
4120 * significantly for system emulation of AArch64 CPUs.
4122 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
4123 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
4124 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
4125 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
4126 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
4127 .type
= ARM_CP_NO_RAW
,
4128 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
4129 .fieldoffset
= offsetof(CPUARMState
, daif
),
4130 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
4131 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
4132 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
4133 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4134 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
4135 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
4136 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
4137 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4138 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
4139 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
4140 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
4141 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
4142 .readfn
= aa64_dczid_read
},
4143 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
4144 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
4145 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
4146 #ifndef CONFIG_USER_ONLY
4147 /* Avoid overhead of an access check that always passes in user-mode */
4148 .accessfn
= aa64_zva_access
,
4151 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
4152 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
4153 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
4154 /* Cache ops: all NOPs since we don't emulate caches */
4155 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
4156 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
4157 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4158 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
4159 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
4160 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4161 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
4162 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
4163 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4164 .accessfn
= aa64_cacheop_access
},
4165 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
4166 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
4167 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4168 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
4169 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
4170 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4171 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
4172 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
4173 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4174 .accessfn
= aa64_cacheop_access
},
4175 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
4176 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
4177 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4178 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
4179 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
4180 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4181 .accessfn
= aa64_cacheop_access
},
4182 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
4183 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
4184 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4185 .accessfn
= aa64_cacheop_access
},
4186 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
4187 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
4188 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4189 /* TLBI operations */
4190 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
4191 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
4192 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4193 .writefn
= tlbi_aa64_vmalle1is_write
},
4194 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
4195 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
4196 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4197 .writefn
= tlbi_aa64_vae1is_write
},
4198 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
4199 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
4200 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4201 .writefn
= tlbi_aa64_vmalle1is_write
},
4202 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
4203 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
4204 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4205 .writefn
= tlbi_aa64_vae1is_write
},
4206 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
4207 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
4208 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4209 .writefn
= tlbi_aa64_vae1is_write
},
4210 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
4211 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
4212 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4213 .writefn
= tlbi_aa64_vae1is_write
},
4214 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
4215 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
4216 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4217 .writefn
= tlbi_aa64_vmalle1_write
},
4218 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
4219 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
4220 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4221 .writefn
= tlbi_aa64_vae1_write
},
4222 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
4223 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
4224 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4225 .writefn
= tlbi_aa64_vmalle1_write
},
4226 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
4227 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
4228 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4229 .writefn
= tlbi_aa64_vae1_write
},
4230 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
4231 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
4232 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4233 .writefn
= tlbi_aa64_vae1_write
},
4234 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
4235 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
4236 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4237 .writefn
= tlbi_aa64_vae1_write
},
4238 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
4239 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
4240 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4241 .writefn
= tlbi_aa64_ipas2e1is_write
},
4242 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
4243 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
4244 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4245 .writefn
= tlbi_aa64_ipas2e1is_write
},
4246 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
4247 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
4248 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4249 .writefn
= tlbi_aa64_alle1is_write
},
4250 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
4251 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
4252 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4253 .writefn
= tlbi_aa64_alle1is_write
},
4254 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
4255 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
4256 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4257 .writefn
= tlbi_aa64_ipas2e1_write
},
4258 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
4259 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
4260 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4261 .writefn
= tlbi_aa64_ipas2e1_write
},
4262 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
4263 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
4264 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4265 .writefn
= tlbi_aa64_alle1_write
},
4266 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
4267 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
4268 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4269 .writefn
= tlbi_aa64_alle1is_write
},
4270 #ifndef CONFIG_USER_ONLY
4271 /* 64 bit address translation operations */
4272 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
4273 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
4274 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4275 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
4276 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
4277 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4278 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
4279 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
4280 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4281 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
4282 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
4283 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4284 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
4285 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
4286 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4287 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
4288 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
4289 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4290 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
4291 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
4292 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4293 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
4294 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
4295 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4296 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
4297 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
4298 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
4299 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4300 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
4301 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
4302 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4303 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
4304 .type
= ARM_CP_ALIAS
,
4305 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
4306 .access
= PL1_RW
, .resetvalue
= 0,
4307 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
4308 .writefn
= par_write
},
4310 /* TLB invalidate last level of translation table walk */
4311 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
4312 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
4313 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
4314 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
4315 .writefn
= tlbimvaa_is_write
},
4316 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
4317 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
4318 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
4319 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
4320 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
4321 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4322 .writefn
= tlbimva_hyp_write
},
4323 { .name
= "TLBIMVALHIS",
4324 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
4325 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4326 .writefn
= tlbimva_hyp_is_write
},
4327 { .name
= "TLBIIPAS2",
4328 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
4329 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4330 .writefn
= tlbiipas2_write
},
4331 { .name
= "TLBIIPAS2IS",
4332 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
4333 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4334 .writefn
= tlbiipas2_is_write
},
4335 { .name
= "TLBIIPAS2L",
4336 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
4337 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4338 .writefn
= tlbiipas2_write
},
4339 { .name
= "TLBIIPAS2LIS",
4340 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
4341 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4342 .writefn
= tlbiipas2_is_write
},
4343 /* 32 bit cache operations */
4344 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
4345 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4346 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
4347 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4348 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
4349 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4350 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
4351 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4352 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
4353 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4354 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
4355 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4356 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
4357 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4358 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
4359 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4360 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
4361 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4362 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
4363 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4364 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
4365 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4366 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
4367 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4368 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
4369 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4370 /* MMU Domain access control / MPU write buffer control */
4371 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
4372 .access
= PL1_RW
, .resetvalue
= 0,
4373 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
4374 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
4375 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
4376 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
4377 .type
= ARM_CP_ALIAS
,
4378 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
4380 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
4381 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
4382 .type
= ARM_CP_ALIAS
,
4383 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
4385 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
4386 /* We rely on the access checks not allowing the guest to write to the
4387 * state field when SPSel indicates that it's being used as the stack
4390 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
4391 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
4392 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
4393 .type
= ARM_CP_ALIAS
,
4394 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
4395 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
4396 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
4397 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
4398 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
4399 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
4400 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
4401 .type
= ARM_CP_NO_RAW
,
4402 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
4403 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
4404 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
4405 .type
= ARM_CP_ALIAS
,
4406 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]),
4407 .access
= PL2_RW
, .accessfn
= fpexc32_access
},
4408 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
4409 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
4410 .access
= PL2_RW
, .resetvalue
= 0,
4411 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
4412 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
4413 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
4414 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
4415 .access
= PL2_RW
, .resetvalue
= 0,
4416 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
4417 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
4418 .type
= ARM_CP_ALIAS
,
4419 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
4421 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
4422 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
4423 .type
= ARM_CP_ALIAS
,
4424 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
4426 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
4427 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
4428 .type
= ARM_CP_ALIAS
,
4429 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
4431 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
4432 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
4433 .type
= ARM_CP_ALIAS
,
4434 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
4436 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
4437 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
4438 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
4440 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
4441 { .name
= "SDCR", .type
= ARM_CP_ALIAS
,
4442 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
4443 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
4444 .writefn
= sdcr_write
,
4445 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
4449 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
4450 static const ARMCPRegInfo el3_no_el2_cp_reginfo
[] = {
4451 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
4452 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
4454 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
4455 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4456 .type
= ARM_CP_NO_RAW
,
4457 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
4459 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4460 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
4461 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
4462 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4463 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
4464 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
4466 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4467 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
4468 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
4469 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4470 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
4471 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
4472 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4474 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
4475 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
4476 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4477 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
4478 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
4479 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4481 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
4482 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
4483 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4485 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
4486 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
4487 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4489 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
4490 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
4491 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4493 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4494 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
4495 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4496 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4497 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
4498 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
4499 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4500 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
4501 .cp
= 15, .opc1
= 6, .crm
= 2,
4502 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4503 .type
= ARM_CP_CONST
| ARM_CP_64BIT
, .resetvalue
= 0 },
4504 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
4505 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
4506 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4507 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
4508 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
4509 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4510 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
4511 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
4512 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4513 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
4514 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
4515 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4516 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
4517 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
4519 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
4520 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
4521 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4522 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
4523 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
4524 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4525 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
4526 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
4528 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
4529 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
4530 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4531 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
4532 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
4534 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
4535 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
4536 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4537 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
4538 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
4539 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4540 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4541 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
4542 .access
= PL2_RW
, .accessfn
= access_tda
,
4543 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4544 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_BOTH
,
4545 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
4546 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
4547 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4548 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
4549 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
4550 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4551 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
4552 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
4553 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4554 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
4555 .type
= ARM_CP_CONST
,
4556 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
4557 .access
= PL2_RW
, .resetvalue
= 0 },
4561 /* Ditto, but for registers which exist in ARMv8 but not v7 */
4562 static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo
[] = {
4563 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
4564 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
4566 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4570 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
4572 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4573 uint64_t valid_mask
= HCR_MASK
;
4575 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4576 valid_mask
&= ~HCR_HCD
;
4577 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
4578 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
4579 * However, if we're using the SMC PSCI conduit then QEMU is
4580 * effectively acting like EL3 firmware and so the guest at
4581 * EL2 should retain the ability to prevent EL1 from being
4582 * able to make SMC calls into the ersatz firmware, so in
4583 * that case HCR.TSC should be read/write.
4585 valid_mask
&= ~HCR_TSC
;
4587 if (cpu_isar_feature(aa64_lor
, cpu
)) {
4588 valid_mask
|= HCR_TLOR
;
4590 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
4591 valid_mask
|= HCR_API
| HCR_APK
;
4594 /* Clear RES0 bits. */
4595 value
&= valid_mask
;
4597 /* These bits change the MMU setup:
4598 * HCR_VM enables stage 2 translation
4599 * HCR_PTW forbids certain page-table setups
4600 * HCR_DC Disables stage1 and enables stage2 translation
4602 if ((env
->cp15
.hcr_el2
^ value
) & (HCR_VM
| HCR_PTW
| HCR_DC
)) {
4603 tlb_flush(CPU(cpu
));
4605 env
->cp15
.hcr_el2
= value
;
4608 * Updates to VI and VF require us to update the status of
4609 * virtual interrupts, which are the logical OR of these bits
4610 * and the state of the input lines from the GIC. (This requires
4611 * that we have the iothread lock, which is done by marking the
4612 * reginfo structs as ARM_CP_IO.)
4613 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
4614 * possible for it to be taken immediately, because VIRQ and
4615 * VFIQ are masked unless running at EL0 or EL1, and HCR
4616 * can only be written at EL2.
4618 g_assert(qemu_mutex_iothread_locked());
4619 arm_cpu_update_virq(cpu
);
4620 arm_cpu_update_vfiq(cpu
);
4623 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4626 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
4627 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
4628 hcr_write(env
, NULL
, value
);
4631 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4634 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
4635 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
4636 hcr_write(env
, NULL
, value
);
4640 * Return the effective value of HCR_EL2.
4641 * Bits that are not included here:
4642 * RW (read from SCR_EL3.RW as needed)
4644 uint64_t arm_hcr_el2_eff(CPUARMState
*env
)
4646 uint64_t ret
= env
->cp15
.hcr_el2
;
4648 if (arm_is_secure_below_el3(env
)) {
4650 * "This register has no effect if EL2 is not enabled in the
4651 * current Security state". This is ARMv8.4-SecEL2 speak for
4652 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
4654 * Prior to that, the language was "In an implementation that
4655 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
4656 * as if this field is 0 for all purposes other than a direct
4657 * read or write access of HCR_EL2". With lots of enumeration
4658 * on a per-field basis. In current QEMU, this is condition
4659 * is arm_is_secure_below_el3.
4661 * Since the v8.4 language applies to the entire register, and
4662 * appears to be backward compatible, use that.
4665 } else if (ret
& HCR_TGE
) {
4666 /* These bits are up-to-date as of ARMv8.4. */
4667 if (ret
& HCR_E2H
) {
4668 ret
&= ~(HCR_VM
| HCR_FMO
| HCR_IMO
| HCR_AMO
|
4669 HCR_BSU_MASK
| HCR_DC
| HCR_TWI
| HCR_TWE
|
4670 HCR_TID0
| HCR_TID2
| HCR_TPCP
| HCR_TPU
|
4671 HCR_TDZ
| HCR_CD
| HCR_ID
| HCR_MIOCNCE
);
4673 ret
|= HCR_FMO
| HCR_IMO
| HCR_AMO
;
4675 ret
&= ~(HCR_SWIO
| HCR_PTW
| HCR_VF
| HCR_VI
| HCR_VSE
|
4676 HCR_FB
| HCR_TID1
| HCR_TID3
| HCR_TSC
| HCR_TACR
|
4677 HCR_TSW
| HCR_TTLB
| HCR_TVM
| HCR_HCD
| HCR_TRVM
|
4684 static const ARMCPRegInfo el2_cp_reginfo
[] = {
4685 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
4687 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
4688 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
4689 .writefn
= hcr_write
},
4690 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
4691 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
4692 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
4693 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
4694 .writefn
= hcr_writelow
},
4695 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
4696 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
4697 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4698 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
4699 .type
= ARM_CP_ALIAS
,
4700 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
4702 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
4703 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
4704 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
4705 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
4706 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
4707 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
4708 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
4709 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
4710 .type
= ARM_CP_ALIAS
,
4711 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
4713 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
4714 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
4715 .type
= ARM_CP_ALIAS
,
4716 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
4718 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
4719 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
4720 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
4721 .access
= PL2_RW
, .writefn
= vbar_write
,
4722 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
4724 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
4725 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
4726 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
4727 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
4728 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
4729 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
4730 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
4731 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]) },
4732 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
4733 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
4734 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
4736 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
4737 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
4738 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
4739 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
4740 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
4741 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
4742 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4744 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
4745 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
4746 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
4747 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4749 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
4750 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
4751 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4753 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
4754 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
4755 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4757 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4758 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
4760 /* no .writefn needed as this can't cause an ASID change;
4761 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
4763 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
4764 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
4765 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
4766 .type
= ARM_CP_ALIAS
,
4767 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4768 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
4769 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
4770 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
4772 /* no .writefn needed as this can't cause an ASID change;
4773 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
4775 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
4776 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
4777 .cp
= 15, .opc1
= 6, .crm
= 2,
4778 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4779 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4780 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
4781 .writefn
= vttbr_write
},
4782 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
4783 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
4784 .access
= PL2_RW
, .writefn
= vttbr_write
,
4785 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
4786 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
4787 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
4788 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
4789 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
4790 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
4791 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
4792 .access
= PL2_RW
, .resetvalue
= 0,
4793 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
4794 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
4795 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
4796 .access
= PL2_RW
, .resetvalue
= 0,
4797 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
4798 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
4799 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4800 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
4801 { .name
= "TLBIALLNSNH",
4802 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
4803 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4804 .writefn
= tlbiall_nsnh_write
},
4805 { .name
= "TLBIALLNSNHIS",
4806 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
4807 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4808 .writefn
= tlbiall_nsnh_is_write
},
4809 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
4810 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4811 .writefn
= tlbiall_hyp_write
},
4812 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
4813 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4814 .writefn
= tlbiall_hyp_is_write
},
4815 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
4816 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4817 .writefn
= tlbimva_hyp_write
},
4818 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
4819 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4820 .writefn
= tlbimva_hyp_is_write
},
4821 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
4822 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
4823 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4824 .writefn
= tlbi_aa64_alle2_write
},
4825 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
4826 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
4827 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4828 .writefn
= tlbi_aa64_vae2_write
},
4829 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
4830 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
4831 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4832 .writefn
= tlbi_aa64_vae2_write
},
4833 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
4834 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
4835 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4836 .writefn
= tlbi_aa64_alle2is_write
},
4837 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
4838 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
4839 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4840 .writefn
= tlbi_aa64_vae2is_write
},
4841 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
4842 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
4843 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4844 .writefn
= tlbi_aa64_vae2is_write
},
4845 #ifndef CONFIG_USER_ONLY
4846 /* Unlike the other EL2-related AT operations, these must
4847 * UNDEF from EL3 if EL2 is not implemented, which is why we
4848 * define them here rather than with the rest of the AT ops.
4850 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
4851 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
4852 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
4853 .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4854 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
4855 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
4856 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
4857 .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4858 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
4859 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
4860 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
4861 * to behave as if SCR.NS was 1.
4863 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
4865 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
},
4866 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
4868 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
},
4869 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
4870 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
4871 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
4872 * reset values as IMPDEF. We choose to reset to 3 to comply with
4873 * both ARMv7 and ARMv8.
4875 .access
= PL2_RW
, .resetvalue
= 3,
4876 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
4877 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
4878 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
4879 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
4880 .writefn
= gt_cntvoff_write
,
4881 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
4882 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
4883 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
4884 .writefn
= gt_cntvoff_write
,
4885 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
4886 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
4887 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
4888 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
4889 .type
= ARM_CP_IO
, .access
= PL2_RW
,
4890 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
4891 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
4892 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
4893 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
4894 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
4895 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
4896 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
4897 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
4898 .resetfn
= gt_hyp_timer_reset
,
4899 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
4900 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
4902 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
4904 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
4906 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
4908 /* The only field of MDCR_EL2 that has a defined architectural reset value
4909 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
4910 * don't implement any PMU event counters, so using zero as a reset
4911 * value for MDCR_EL2 is okay
4913 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4914 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
4915 .access
= PL2_RW
, .resetvalue
= 0,
4916 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
), },
4917 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
4918 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
4919 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4920 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
4921 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
4922 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
4924 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
4925 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
4926 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
4928 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
4932 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
4933 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
4934 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
4935 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
4937 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
4938 .writefn
= hcr_writehigh
},
4942 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4945 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
4946 * At Secure EL1 it traps to EL3.
4948 if (arm_current_el(env
) == 3) {
4949 return CP_ACCESS_OK
;
4951 if (arm_is_secure_below_el3(env
)) {
4952 return CP_ACCESS_TRAP_EL3
;
4954 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
4956 return CP_ACCESS_OK
;
4958 return CP_ACCESS_TRAP_UNCATEGORIZED
;
4961 static const ARMCPRegInfo el3_cp_reginfo
[] = {
4962 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
4963 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
4964 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
4965 .resetvalue
= 0, .writefn
= scr_write
},
4966 { .name
= "SCR", .type
= ARM_CP_ALIAS
,
4967 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
4968 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
4969 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
4970 .writefn
= scr_write
},
4971 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
4972 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
4973 .access
= PL3_RW
, .resetvalue
= 0,
4974 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
4976 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
4977 .access
= PL3_RW
, .resetvalue
= 0,
4978 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
4979 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
4980 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
4981 .writefn
= vbar_write
, .resetvalue
= 0,
4982 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
4983 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
4984 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
4985 .access
= PL3_RW
, .resetvalue
= 0,
4986 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
4987 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
4988 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
4990 /* no .writefn needed as this can't cause an ASID change;
4991 * we must provide a .raw_writefn and .resetfn because we handle
4992 * reset and migration for the AArch32 TTBCR(S), which might be
4993 * using mask and base_mask.
4995 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= vmsa_ttbcr_raw_write
,
4996 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
4997 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
4998 .type
= ARM_CP_ALIAS
,
4999 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
5001 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
5002 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
5003 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
5004 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
5005 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
5006 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
5007 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
5008 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
5009 .type
= ARM_CP_ALIAS
,
5010 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
5012 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
5013 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
5014 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
5015 .access
= PL3_RW
, .writefn
= vbar_write
,
5016 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
5018 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
5019 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
5020 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
5021 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
5022 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
5023 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
5024 .access
= PL3_RW
, .resetvalue
= 0,
5025 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
5026 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
5027 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
5028 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5030 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
5031 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
5032 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5034 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
5035 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
5036 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5038 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
5039 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
5040 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5041 .writefn
= tlbi_aa64_alle3is_write
},
5042 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
5043 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
5044 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5045 .writefn
= tlbi_aa64_vae3is_write
},
5046 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
5047 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
5048 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5049 .writefn
= tlbi_aa64_vae3is_write
},
5050 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
5051 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
5052 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5053 .writefn
= tlbi_aa64_alle3_write
},
5054 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
5055 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
5056 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5057 .writefn
= tlbi_aa64_vae3_write
},
5058 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
5059 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
5060 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5061 .writefn
= tlbi_aa64_vae3_write
},
5065 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5068 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
5069 * but the AArch32 CTR has its own reginfo struct)
5071 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
5072 return CP_ACCESS_TRAP
;
5074 return CP_ACCESS_OK
;
5077 static void oslar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5080 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
5081 * read via a bit in OSLSR_EL1.
5085 if (ri
->state
== ARM_CP_STATE_AA32
) {
5086 oslock
= (value
== 0xC5ACCE55);
5091 env
->cp15
.oslsr_el1
= deposit32(env
->cp15
.oslsr_el1
, 1, 1, oslock
);
5094 static const ARMCPRegInfo debug_cp_reginfo
[] = {
5095 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
5096 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
5097 * unlike DBGDRAR it is never accessible from EL0.
5098 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
5101 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
5102 .access
= PL0_R
, .accessfn
= access_tdra
,
5103 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5104 { .name
= "MDRAR_EL1", .state
= ARM_CP_STATE_AA64
,
5105 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
5106 .access
= PL1_R
, .accessfn
= access_tdra
,
5107 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5108 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
5109 .access
= PL0_R
, .accessfn
= access_tdra
,
5110 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5111 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
5112 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_BOTH
,
5113 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
5114 .access
= PL1_RW
, .accessfn
= access_tda
,
5115 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
),
5117 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
5118 * We don't implement the configurable EL0 access.
5120 { .name
= "MDCCSR_EL0", .state
= ARM_CP_STATE_BOTH
,
5121 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
5122 .type
= ARM_CP_ALIAS
,
5123 .access
= PL1_R
, .accessfn
= access_tda
,
5124 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
), },
5125 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_BOTH
,
5126 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
5127 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
5128 .accessfn
= access_tdosa
,
5129 .writefn
= oslar_write
},
5130 { .name
= "OSLSR_EL1", .state
= ARM_CP_STATE_BOTH
,
5131 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 4,
5132 .access
= PL1_R
, .resetvalue
= 10,
5133 .accessfn
= access_tdosa
,
5134 .fieldoffset
= offsetof(CPUARMState
, cp15
.oslsr_el1
) },
5135 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
5136 { .name
= "OSDLR_EL1", .state
= ARM_CP_STATE_BOTH
,
5137 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 4,
5138 .access
= PL1_RW
, .accessfn
= access_tdosa
,
5139 .type
= ARM_CP_NOP
},
5140 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
5141 * implement vector catch debug events yet.
5144 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
5145 .access
= PL1_RW
, .accessfn
= access_tda
,
5146 .type
= ARM_CP_NOP
},
5147 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
5148 * to save and restore a 32-bit guest's DBGVCR)
5150 { .name
= "DBGVCR32_EL2", .state
= ARM_CP_STATE_AA64
,
5151 .opc0
= 2, .opc1
= 4, .crn
= 0, .crm
= 7, .opc2
= 0,
5152 .access
= PL2_RW
, .accessfn
= access_tda
,
5153 .type
= ARM_CP_NOP
},
5154 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
5155 * Channel but Linux may try to access this register. The 32-bit
5156 * alias is DBGDCCINT.
5158 { .name
= "MDCCINT_EL1", .state
= ARM_CP_STATE_BOTH
,
5159 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
5160 .access
= PL1_RW
, .accessfn
= access_tda
,
5161 .type
= ARM_CP_NOP
},
5165 static const ARMCPRegInfo debug_lpae_cp_reginfo
[] = {
5166 /* 64 bit access versions of the (dummy) debug registers */
5167 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
5168 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
5169 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
5170 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
5174 /* Return the exception level to which exceptions should be taken
5175 * via SVEAccessTrap. If an exception should be routed through
5176 * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
5177 * take care of raising that exception.
5178 * C.f. the ARM pseudocode function CheckSVEEnabled.
5180 int sve_exception_el(CPUARMState
*env
, int el
)
5182 #ifndef CONFIG_USER_ONLY
5184 bool disabled
= false;
5186 /* The CPACR.ZEN controls traps to EL1:
5187 * 0, 2 : trap EL0 and EL1 accesses
5188 * 1 : trap only EL0 accesses
5189 * 3 : trap no accesses
5191 if (!extract32(env
->cp15
.cpacr_el1
, 16, 1)) {
5193 } else if (!extract32(env
->cp15
.cpacr_el1
, 17, 1)) {
5198 return (arm_feature(env
, ARM_FEATURE_EL2
)
5199 && (arm_hcr_el2_eff(env
) & HCR_TGE
) ? 2 : 1);
5202 /* Check CPACR.FPEN. */
5203 if (!extract32(env
->cp15
.cpacr_el1
, 20, 1)) {
5205 } else if (!extract32(env
->cp15
.cpacr_el1
, 21, 1)) {
5213 /* CPTR_EL2. Since TZ and TFP are positive,
5214 * they will be zero when EL2 is not present.
5216 if (el
<= 2 && !arm_is_secure_below_el3(env
)) {
5217 if (env
->cp15
.cptr_el
[2] & CPTR_TZ
) {
5220 if (env
->cp15
.cptr_el
[2] & CPTR_TFP
) {
5225 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
5226 if (arm_feature(env
, ARM_FEATURE_EL3
)
5227 && !(env
->cp15
.cptr_el
[3] & CPTR_EZ
)) {
5235 * Given that SVE is enabled, return the vector length for EL.
5237 uint32_t sve_zcr_len_for_el(CPUARMState
*env
, int el
)
5239 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5240 uint32_t zcr_len
= cpu
->sve_max_vq
- 1;
5243 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[1]);
5245 if (el
< 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
5246 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[2]);
5248 if (el
< 3 && arm_feature(env
, ARM_FEATURE_EL3
)) {
5249 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[3]);
5254 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5257 int cur_el
= arm_current_el(env
);
5258 int old_len
= sve_zcr_len_for_el(env
, cur_el
);
5261 /* Bits other than [3:0] are RAZ/WI. */
5262 raw_write(env
, ri
, value
& 0xf);
5265 * Because we arrived here, we know both FP and SVE are enabled;
5266 * otherwise we would have trapped access to the ZCR_ELn register.
5268 new_len
= sve_zcr_len_for_el(env
, cur_el
);
5269 if (new_len
< old_len
) {
5270 aarch64_sve_narrow_vq(env
, new_len
+ 1);
5274 static const ARMCPRegInfo zcr_el1_reginfo
= {
5275 .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
5276 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
5277 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
5278 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
5279 .writefn
= zcr_write
, .raw_writefn
= raw_write
5282 static const ARMCPRegInfo zcr_el2_reginfo
= {
5283 .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
5284 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
5285 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
5286 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
5287 .writefn
= zcr_write
, .raw_writefn
= raw_write
5290 static const ARMCPRegInfo zcr_no_el2_reginfo
= {
5291 .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
5292 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
5293 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
5294 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
5297 static const ARMCPRegInfo zcr_el3_reginfo
= {
5298 .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
5299 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
5300 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
5301 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
5302 .writefn
= zcr_write
, .raw_writefn
= raw_write
5305 void hw_watchpoint_update(ARMCPU
*cpu
, int n
)
5307 CPUARMState
*env
= &cpu
->env
;
5309 vaddr wvr
= env
->cp15
.dbgwvr
[n
];
5310 uint64_t wcr
= env
->cp15
.dbgwcr
[n
];
5312 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
5314 if (env
->cpu_watchpoint
[n
]) {
5315 cpu_watchpoint_remove_by_ref(CPU(cpu
), env
->cpu_watchpoint
[n
]);
5316 env
->cpu_watchpoint
[n
] = NULL
;
5319 if (!extract64(wcr
, 0, 1)) {
5320 /* E bit clear : watchpoint disabled */
5324 switch (extract64(wcr
, 3, 2)) {
5326 /* LSC 00 is reserved and must behave as if the wp is disabled */
5329 flags
|= BP_MEM_READ
;
5332 flags
|= BP_MEM_WRITE
;
5335 flags
|= BP_MEM_ACCESS
;
5339 /* Attempts to use both MASK and BAS fields simultaneously are
5340 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
5341 * thus generating a watchpoint for every byte in the masked region.
5343 mask
= extract64(wcr
, 24, 4);
5344 if (mask
== 1 || mask
== 2) {
5345 /* Reserved values of MASK; we must act as if the mask value was
5346 * some non-reserved value, or as if the watchpoint were disabled.
5347 * We choose the latter.
5351 /* Watchpoint covers an aligned area up to 2GB in size */
5353 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
5354 * whether the watchpoint fires when the unmasked bits match; we opt
5355 * to generate the exceptions.
5359 /* Watchpoint covers bytes defined by the byte address select bits */
5360 int bas
= extract64(wcr
, 5, 8);
5364 /* This must act as if the watchpoint is disabled */
5368 if (extract64(wvr
, 2, 1)) {
5369 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
5370 * ignored, and BAS[3:0] define which bytes to watch.
5374 /* The BAS bits are supposed to be programmed to indicate a contiguous
5375 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
5376 * we fire for each byte in the word/doubleword addressed by the WVR.
5377 * We choose to ignore any non-zero bits after the first range of 1s.
5379 basstart
= ctz32(bas
);
5380 len
= cto32(bas
>> basstart
);
5384 cpu_watchpoint_insert(CPU(cpu
), wvr
, len
, flags
,
5385 &env
->cpu_watchpoint
[n
]);
5388 void hw_watchpoint_update_all(ARMCPU
*cpu
)
5391 CPUARMState
*env
= &cpu
->env
;
5393 /* Completely clear out existing QEMU watchpoints and our array, to
5394 * avoid possible stale entries following migration load.
5396 cpu_watchpoint_remove_all(CPU(cpu
), BP_CPU
);
5397 memset(env
->cpu_watchpoint
, 0, sizeof(env
->cpu_watchpoint
));
5399 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_watchpoint
); i
++) {
5400 hw_watchpoint_update(cpu
, i
);
5404 static void dbgwvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5407 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5410 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
5411 * register reads and behaves as if values written are sign extended.
5412 * Bits [1:0] are RES0.
5414 value
= sextract64(value
, 0, 49) & ~3ULL;
5416 raw_write(env
, ri
, value
);
5417 hw_watchpoint_update(cpu
, i
);
5420 static void dbgwcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5423 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5426 raw_write(env
, ri
, value
);
5427 hw_watchpoint_update(cpu
, i
);
5430 void hw_breakpoint_update(ARMCPU
*cpu
, int n
)
5432 CPUARMState
*env
= &cpu
->env
;
5433 uint64_t bvr
= env
->cp15
.dbgbvr
[n
];
5434 uint64_t bcr
= env
->cp15
.dbgbcr
[n
];
5439 if (env
->cpu_breakpoint
[n
]) {
5440 cpu_breakpoint_remove_by_ref(CPU(cpu
), env
->cpu_breakpoint
[n
]);
5441 env
->cpu_breakpoint
[n
] = NULL
;
5444 if (!extract64(bcr
, 0, 1)) {
5445 /* E bit clear : watchpoint disabled */
5449 bt
= extract64(bcr
, 20, 4);
5452 case 4: /* unlinked address mismatch (reserved if AArch64) */
5453 case 5: /* linked address mismatch (reserved if AArch64) */
5454 qemu_log_mask(LOG_UNIMP
,
5455 "arm: address mismatch breakpoint types not implemented\n");
5457 case 0: /* unlinked address match */
5458 case 1: /* linked address match */
5460 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
5461 * we behave as if the register was sign extended. Bits [1:0] are
5462 * RES0. The BAS field is used to allow setting breakpoints on 16
5463 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
5464 * a bp will fire if the addresses covered by the bp and the addresses
5465 * covered by the insn overlap but the insn doesn't start at the
5466 * start of the bp address range. We choose to require the insn and
5467 * the bp to have the same address. The constraints on writing to
5468 * BAS enforced in dbgbcr_write mean we have only four cases:
5469 * 0b0000 => no breakpoint
5470 * 0b0011 => breakpoint on addr
5471 * 0b1100 => breakpoint on addr + 2
5472 * 0b1111 => breakpoint on addr
5473 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
5475 int bas
= extract64(bcr
, 5, 4);
5476 addr
= sextract64(bvr
, 0, 49) & ~3ULL;
5485 case 2: /* unlinked context ID match */
5486 case 8: /* unlinked VMID match (reserved if no EL2) */
5487 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
5488 qemu_log_mask(LOG_UNIMP
,
5489 "arm: unlinked context breakpoint types not implemented\n");
5491 case 9: /* linked VMID match (reserved if no EL2) */
5492 case 11: /* linked context ID and VMID match (reserved if no EL2) */
5493 case 3: /* linked context ID match */
5495 /* We must generate no events for Linked context matches (unless
5496 * they are linked to by some other bp/wp, which is handled in
5497 * updates for the linking bp/wp). We choose to also generate no events
5498 * for reserved values.
5503 cpu_breakpoint_insert(CPU(cpu
), addr
, flags
, &env
->cpu_breakpoint
[n
]);
5506 void hw_breakpoint_update_all(ARMCPU
*cpu
)
5509 CPUARMState
*env
= &cpu
->env
;
5511 /* Completely clear out existing QEMU breakpoints and our array, to
5512 * avoid possible stale entries following migration load.
5514 cpu_breakpoint_remove_all(CPU(cpu
), BP_CPU
);
5515 memset(env
->cpu_breakpoint
, 0, sizeof(env
->cpu_breakpoint
));
5517 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_breakpoint
); i
++) {
5518 hw_breakpoint_update(cpu
, i
);
5522 static void dbgbvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5525 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5528 raw_write(env
, ri
, value
);
5529 hw_breakpoint_update(cpu
, i
);
5532 static void dbgbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5535 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5538 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
5541 value
= deposit64(value
, 6, 1, extract64(value
, 5, 1));
5542 value
= deposit64(value
, 8, 1, extract64(value
, 7, 1));
5544 raw_write(env
, ri
, value
);
5545 hw_breakpoint_update(cpu
, i
);
5548 static void define_debug_regs(ARMCPU
*cpu
)
5550 /* Define v7 and v8 architectural debug registers.
5551 * These are just dummy implementations for now.
5554 int wrps
, brps
, ctx_cmps
;
5555 ARMCPRegInfo dbgdidr
= {
5556 .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
5557 .access
= PL0_R
, .accessfn
= access_tda
,
5558 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->dbgdidr
,
5561 /* Note that all these register fields hold "number of Xs minus 1". */
5562 brps
= extract32(cpu
->dbgdidr
, 24, 4);
5563 wrps
= extract32(cpu
->dbgdidr
, 28, 4);
5564 ctx_cmps
= extract32(cpu
->dbgdidr
, 20, 4);
5566 assert(ctx_cmps
<= brps
);
5568 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
5569 * of the debug registers such as number of breakpoints;
5570 * check that if they both exist then they agree.
5572 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
5573 assert(extract32(cpu
->id_aa64dfr0
, 12, 4) == brps
);
5574 assert(extract32(cpu
->id_aa64dfr0
, 20, 4) == wrps
);
5575 assert(extract32(cpu
->id_aa64dfr0
, 28, 4) == ctx_cmps
);
5578 define_one_arm_cp_reg(cpu
, &dbgdidr
);
5579 define_arm_cp_regs(cpu
, debug_cp_reginfo
);
5581 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
)) {
5582 define_arm_cp_regs(cpu
, debug_lpae_cp_reginfo
);
5585 for (i
= 0; i
< brps
+ 1; i
++) {
5586 ARMCPRegInfo dbgregs
[] = {
5587 { .name
= "DBGBVR", .state
= ARM_CP_STATE_BOTH
,
5588 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
5589 .access
= PL1_RW
, .accessfn
= access_tda
,
5590 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]),
5591 .writefn
= dbgbvr_write
, .raw_writefn
= raw_write
5593 { .name
= "DBGBCR", .state
= ARM_CP_STATE_BOTH
,
5594 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
5595 .access
= PL1_RW
, .accessfn
= access_tda
,
5596 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]),
5597 .writefn
= dbgbcr_write
, .raw_writefn
= raw_write
5601 define_arm_cp_regs(cpu
, dbgregs
);
5604 for (i
= 0; i
< wrps
+ 1; i
++) {
5605 ARMCPRegInfo dbgregs
[] = {
5606 { .name
= "DBGWVR", .state
= ARM_CP_STATE_BOTH
,
5607 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
5608 .access
= PL1_RW
, .accessfn
= access_tda
,
5609 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]),
5610 .writefn
= dbgwvr_write
, .raw_writefn
= raw_write
5612 { .name
= "DBGWCR", .state
= ARM_CP_STATE_BOTH
,
5613 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
5614 .access
= PL1_RW
, .accessfn
= access_tda
,
5615 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]),
5616 .writefn
= dbgwcr_write
, .raw_writefn
= raw_write
5620 define_arm_cp_regs(cpu
, dbgregs
);
5624 /* We don't know until after realize whether there's a GICv3
5625 * attached, and that is what registers the gicv3 sysregs.
5626 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
5629 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5631 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5632 uint64_t pfr1
= cpu
->id_pfr1
;
5634 if (env
->gicv3state
) {
5640 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5642 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5643 uint64_t pfr0
= cpu
->isar
.id_aa64pfr0
;
5645 if (env
->gicv3state
) {
5651 /* Shared logic between LORID and the rest of the LOR* registers.
5652 * Secure state has already been delt with.
5654 static CPAccessResult
access_lor_ns(CPUARMState
*env
)
5656 int el
= arm_current_el(env
);
5658 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TLOR
)) {
5659 return CP_ACCESS_TRAP_EL2
;
5661 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TLOR
)) {
5662 return CP_ACCESS_TRAP_EL3
;
5664 return CP_ACCESS_OK
;
5667 static CPAccessResult
access_lorid(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5670 if (arm_is_secure_below_el3(env
)) {
5671 /* Access ok in secure mode. */
5672 return CP_ACCESS_OK
;
5674 return access_lor_ns(env
);
5677 static CPAccessResult
access_lor_other(CPUARMState
*env
,
5678 const ARMCPRegInfo
*ri
, bool isread
)
5680 if (arm_is_secure_below_el3(env
)) {
5681 /* Access denied in secure mode. */
5682 return CP_ACCESS_TRAP
;
5684 return access_lor_ns(env
);
5687 #ifdef TARGET_AARCH64
5688 static CPAccessResult
access_pauth(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5691 int el
= arm_current_el(env
);
5694 arm_feature(env
, ARM_FEATURE_EL2
) &&
5695 !(arm_hcr_el2_eff(env
) & HCR_APK
)) {
5696 return CP_ACCESS_TRAP_EL2
;
5699 arm_feature(env
, ARM_FEATURE_EL3
) &&
5700 !(env
->cp15
.scr_el3
& SCR_APK
)) {
5701 return CP_ACCESS_TRAP_EL3
;
5703 return CP_ACCESS_OK
;
5706 static const ARMCPRegInfo pauth_reginfo
[] = {
5707 { .name
= "APDAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
5708 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 0,
5709 .access
= PL1_RW
, .accessfn
= access_pauth
,
5710 .fieldoffset
= offsetof(CPUARMState
, apda_key
.lo
) },
5711 { .name
= "APDAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
5712 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 1,
5713 .access
= PL1_RW
, .accessfn
= access_pauth
,
5714 .fieldoffset
= offsetof(CPUARMState
, apda_key
.hi
) },
5715 { .name
= "APDBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
5716 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 2,
5717 .access
= PL1_RW
, .accessfn
= access_pauth
,
5718 .fieldoffset
= offsetof(CPUARMState
, apdb_key
.lo
) },
5719 { .name
= "APDBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
5720 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 3,
5721 .access
= PL1_RW
, .accessfn
= access_pauth
,
5722 .fieldoffset
= offsetof(CPUARMState
, apdb_key
.hi
) },
5723 { .name
= "APGAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
5724 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 0,
5725 .access
= PL1_RW
, .accessfn
= access_pauth
,
5726 .fieldoffset
= offsetof(CPUARMState
, apga_key
.lo
) },
5727 { .name
= "APGAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
5728 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 1,
5729 .access
= PL1_RW
, .accessfn
= access_pauth
,
5730 .fieldoffset
= offsetof(CPUARMState
, apga_key
.hi
) },
5731 { .name
= "APIAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
5732 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 0,
5733 .access
= PL1_RW
, .accessfn
= access_pauth
,
5734 .fieldoffset
= offsetof(CPUARMState
, apia_key
.lo
) },
5735 { .name
= "APIAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
5736 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 1,
5737 .access
= PL1_RW
, .accessfn
= access_pauth
,
5738 .fieldoffset
= offsetof(CPUARMState
, apia_key
.hi
) },
5739 { .name
= "APIBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
5740 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 2,
5741 .access
= PL1_RW
, .accessfn
= access_pauth
,
5742 .fieldoffset
= offsetof(CPUARMState
, apib_key
.lo
) },
5743 { .name
= "APIBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
5744 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 3,
5745 .access
= PL1_RW
, .accessfn
= access_pauth
,
5746 .fieldoffset
= offsetof(CPUARMState
, apib_key
.hi
) },
5751 static CPAccessResult
access_predinv(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5754 int el
= arm_current_el(env
);
5757 uint64_t sctlr
= arm_sctlr(env
, el
);
5758 if (!(sctlr
& SCTLR_EnRCTX
)) {
5759 return CP_ACCESS_TRAP
;
5761 } else if (el
== 1) {
5762 uint64_t hcr
= arm_hcr_el2_eff(env
);
5764 return CP_ACCESS_TRAP_EL2
;
5767 return CP_ACCESS_OK
;
5770 static const ARMCPRegInfo predinv_reginfo
[] = {
5771 { .name
= "CFP_RCTX", .state
= ARM_CP_STATE_AA64
,
5772 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 4,
5773 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
5774 { .name
= "DVP_RCTX", .state
= ARM_CP_STATE_AA64
,
5775 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 5,
5776 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
5777 { .name
= "CPP_RCTX", .state
= ARM_CP_STATE_AA64
,
5778 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 7,
5779 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
5781 * Note the AArch32 opcodes have a different OPC1.
5783 { .name
= "CFPRCTX", .state
= ARM_CP_STATE_AA32
,
5784 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 4,
5785 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
5786 { .name
= "DVPRCTX", .state
= ARM_CP_STATE_AA32
,
5787 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 5,
5788 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
5789 { .name
= "CPPRCTX", .state
= ARM_CP_STATE_AA32
,
5790 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 7,
5791 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
5795 void register_cp_regs_for_features(ARMCPU
*cpu
)
5797 /* Register all the coprocessor registers based on feature bits */
5798 CPUARMState
*env
= &cpu
->env
;
5799 if (arm_feature(env
, ARM_FEATURE_M
)) {
5800 /* M profile has no coprocessor registers */
5804 define_arm_cp_regs(cpu
, cp_reginfo
);
5805 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
5806 /* Must go early as it is full of wildcards that may be
5807 * overridden by later definitions.
5809 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
5812 if (arm_feature(env
, ARM_FEATURE_V6
)) {
5813 /* The ID registers all have impdef reset values */
5814 ARMCPRegInfo v6_idregs
[] = {
5815 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
5816 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
5817 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5818 .resetvalue
= cpu
->id_pfr0
},
5819 /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
5820 * the value of the GIC field until after we define these regs.
5822 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
5823 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
5824 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
5825 .readfn
= id_pfr1_read
,
5826 .writefn
= arm_cp_write_ignore
},
5827 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
5828 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
5829 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5830 .resetvalue
= cpu
->id_dfr0
},
5831 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
5832 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
5833 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5834 .resetvalue
= cpu
->id_afr0
},
5835 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
5836 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
5837 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5838 .resetvalue
= cpu
->id_mmfr0
},
5839 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
5840 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
5841 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5842 .resetvalue
= cpu
->id_mmfr1
},
5843 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
5844 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
5845 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5846 .resetvalue
= cpu
->id_mmfr2
},
5847 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
5848 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
5849 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5850 .resetvalue
= cpu
->id_mmfr3
},
5851 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
5852 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
5853 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5854 .resetvalue
= cpu
->isar
.id_isar0
},
5855 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
5856 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
5857 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5858 .resetvalue
= cpu
->isar
.id_isar1
},
5859 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
5860 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
5861 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5862 .resetvalue
= cpu
->isar
.id_isar2
},
5863 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
5864 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
5865 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5866 .resetvalue
= cpu
->isar
.id_isar3
},
5867 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
5868 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
5869 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5870 .resetvalue
= cpu
->isar
.id_isar4
},
5871 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
5872 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
5873 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5874 .resetvalue
= cpu
->isar
.id_isar5
},
5875 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
5876 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
5877 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5878 .resetvalue
= cpu
->id_mmfr4
},
5879 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
5880 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
5881 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5882 .resetvalue
= cpu
->isar
.id_isar6
},
5885 define_arm_cp_regs(cpu
, v6_idregs
);
5886 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
5888 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
5890 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
5891 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
5893 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
5894 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
5895 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
5897 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
5898 define_arm_cp_regs(cpu
, pmovsset_cp_reginfo
);
5900 if (arm_feature(env
, ARM_FEATURE_V7
)) {
5901 /* v7 performance monitor control register: same implementor
5902 * field as main ID register, and we implement four counters in
5903 * addition to the cycle count register.
5905 unsigned int i
, pmcrn
= 4;
5906 ARMCPRegInfo pmcr
= {
5907 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
5909 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
5910 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
5911 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
5912 .raw_writefn
= raw_write
,
5914 ARMCPRegInfo pmcr64
= {
5915 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
5916 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
5917 .access
= PL0_RW
, .accessfn
= pmreg_access
,
5919 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
5920 .resetvalue
= (cpu
->midr
& 0xff000000) | (pmcrn
<< PMCRN_SHIFT
),
5921 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
5923 define_one_arm_cp_reg(cpu
, &pmcr
);
5924 define_one_arm_cp_reg(cpu
, &pmcr64
);
5925 for (i
= 0; i
< pmcrn
; i
++) {
5926 char *pmevcntr_name
= g_strdup_printf("PMEVCNTR%d", i
);
5927 char *pmevcntr_el0_name
= g_strdup_printf("PMEVCNTR%d_EL0", i
);
5928 char *pmevtyper_name
= g_strdup_printf("PMEVTYPER%d", i
);
5929 char *pmevtyper_el0_name
= g_strdup_printf("PMEVTYPER%d_EL0", i
);
5930 ARMCPRegInfo pmev_regs
[] = {
5931 { .name
= pmevcntr_name
, .cp
= 15, .crn
= 14,
5932 .crm
= 8 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
5933 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
5934 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
5935 .accessfn
= pmreg_access
},
5936 { .name
= pmevcntr_el0_name
, .state
= ARM_CP_STATE_AA64
,
5937 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 8 | (3 & (i
>> 3)),
5938 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
5940 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
5941 .raw_readfn
= pmevcntr_rawread
,
5942 .raw_writefn
= pmevcntr_rawwrite
},
5943 { .name
= pmevtyper_name
, .cp
= 15, .crn
= 14,
5944 .crm
= 12 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
5945 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
5946 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
5947 .accessfn
= pmreg_access
},
5948 { .name
= pmevtyper_el0_name
, .state
= ARM_CP_STATE_AA64
,
5949 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 12 | (3 & (i
>> 3)),
5950 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
5952 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
5953 .raw_writefn
= pmevtyper_rawwrite
},
5956 define_arm_cp_regs(cpu
, pmev_regs
);
5957 g_free(pmevcntr_name
);
5958 g_free(pmevcntr_el0_name
);
5959 g_free(pmevtyper_name
);
5960 g_free(pmevtyper_el0_name
);
5962 ARMCPRegInfo clidr
= {
5963 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
5964 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
5965 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->clidr
5967 define_one_arm_cp_reg(cpu
, &clidr
);
5968 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
5969 define_debug_regs(cpu
);
5971 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
5973 if (FIELD_EX32(cpu
->id_dfr0
, ID_DFR0
, PERFMON
) >= 4 &&
5974 FIELD_EX32(cpu
->id_dfr0
, ID_DFR0
, PERFMON
) != 0xf) {
5975 ARMCPRegInfo v81_pmu_regs
[] = {
5976 { .name
= "PMCEID2", .state
= ARM_CP_STATE_AA32
,
5977 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 4,
5978 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
5979 .resetvalue
= extract64(cpu
->pmceid0
, 32, 32) },
5980 { .name
= "PMCEID3", .state
= ARM_CP_STATE_AA32
,
5981 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 5,
5982 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
5983 .resetvalue
= extract64(cpu
->pmceid1
, 32, 32) },
5986 define_arm_cp_regs(cpu
, v81_pmu_regs
);
5988 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5989 /* AArch64 ID registers, which all have impdef reset values.
5990 * Note that within the ID register ranges the unused slots
5991 * must all RAZ, not UNDEF; future architecture versions may
5992 * define new registers here.
5994 ARMCPRegInfo v8_idregs
[] = {
5995 /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't
5996 * know the right value for the GIC field until after we
5997 * define these regs.
5999 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
6000 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
6001 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
6002 .readfn
= id_aa64pfr0_read
,
6003 .writefn
= arm_cp_write_ignore
},
6004 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
6005 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
6006 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6007 .resetvalue
= cpu
->isar
.id_aa64pfr1
},
6008 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6009 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
6010 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6012 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6013 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
6014 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6016 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
6017 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
6018 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6019 /* At present, only SVEver == 0 is defined anyway. */
6021 { .name
= "ID_AA64PFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6022 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
6023 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6025 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6026 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
6027 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6029 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6030 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
6031 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6033 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
6034 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
6035 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6036 .resetvalue
= cpu
->id_aa64dfr0
},
6037 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
6038 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
6039 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6040 .resetvalue
= cpu
->id_aa64dfr1
},
6041 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6042 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
6043 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6045 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6046 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
6047 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6049 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
6050 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
6051 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6052 .resetvalue
= cpu
->id_aa64afr0
},
6053 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
6054 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
6055 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6056 .resetvalue
= cpu
->id_aa64afr1
},
6057 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6058 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
6059 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6061 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6062 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
6063 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6065 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
6066 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
6067 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6068 .resetvalue
= cpu
->isar
.id_aa64isar0
},
6069 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
6070 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
6071 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6072 .resetvalue
= cpu
->isar
.id_aa64isar1
},
6073 { .name
= "ID_AA64ISAR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6074 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
6075 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6077 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6078 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
6079 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6081 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6082 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
6083 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6085 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6086 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
6087 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6089 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6090 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
6091 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6093 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6094 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
6095 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6097 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
6098 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
6099 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6100 .resetvalue
= cpu
->isar
.id_aa64mmfr0
},
6101 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
6102 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
6103 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6104 .resetvalue
= cpu
->isar
.id_aa64mmfr1
},
6105 { .name
= "ID_AA64MMFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6106 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
6107 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6109 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6110 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
6111 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6113 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6114 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
6115 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6117 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6118 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
6119 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6121 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6122 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
6123 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6125 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6126 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
6127 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6129 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
6130 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
6131 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6132 .resetvalue
= cpu
->isar
.mvfr0
},
6133 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
6134 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
6135 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6136 .resetvalue
= cpu
->isar
.mvfr1
},
6137 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
6138 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
6139 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6140 .resetvalue
= cpu
->isar
.mvfr2
},
6141 { .name
= "MVFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6142 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
6143 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6145 { .name
= "MVFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6146 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
6147 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6149 { .name
= "MVFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6150 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
6151 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6153 { .name
= "MVFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6154 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
6155 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6157 { .name
= "MVFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6158 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
6159 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6161 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
6162 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
6163 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6164 .resetvalue
= extract64(cpu
->pmceid0
, 0, 32) },
6165 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
6166 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
6167 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6168 .resetvalue
= cpu
->pmceid0
},
6169 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
6170 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
6171 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6172 .resetvalue
= extract64(cpu
->pmceid1
, 0, 32) },
6173 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
6174 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
6175 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6176 .resetvalue
= cpu
->pmceid1
},
6179 #ifdef CONFIG_USER_ONLY
6180 ARMCPRegUserSpaceInfo v8_user_idregs
[] = {
6181 { .name
= "ID_AA64PFR0_EL1",
6182 .exported_bits
= 0x000f000f00ff0000,
6183 .fixed_bits
= 0x0000000000000011 },
6184 { .name
= "ID_AA64PFR1_EL1",
6185 .exported_bits
= 0x00000000000000f0 },
6186 { .name
= "ID_AA64PFR*_EL1_RESERVED",
6188 { .name
= "ID_AA64ZFR0_EL1" },
6189 { .name
= "ID_AA64MMFR0_EL1",
6190 .fixed_bits
= 0x00000000ff000000 },
6191 { .name
= "ID_AA64MMFR1_EL1" },
6192 { .name
= "ID_AA64MMFR*_EL1_RESERVED",
6194 { .name
= "ID_AA64DFR0_EL1",
6195 .fixed_bits
= 0x0000000000000006 },
6196 { .name
= "ID_AA64DFR1_EL1" },
6197 { .name
= "ID_AA64DFR*_EL1_RESERVED",
6199 { .name
= "ID_AA64AFR*",
6201 { .name
= "ID_AA64ISAR0_EL1",
6202 .exported_bits
= 0x00fffffff0fffff0 },
6203 { .name
= "ID_AA64ISAR1_EL1",
6204 .exported_bits
= 0x000000f0ffffffff },
6205 { .name
= "ID_AA64ISAR*_EL1_RESERVED",
6207 REGUSERINFO_SENTINEL
6209 modify_arm_cp_regs(v8_idregs
, v8_user_idregs
);
6211 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
6212 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
6213 !arm_feature(env
, ARM_FEATURE_EL2
)) {
6214 ARMCPRegInfo rvbar
= {
6215 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
6216 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
6217 .type
= ARM_CP_CONST
, .access
= PL1_R
, .resetvalue
= cpu
->rvbar
6219 define_one_arm_cp_reg(cpu
, &rvbar
);
6221 define_arm_cp_regs(cpu
, v8_idregs
);
6222 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
6224 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
6225 uint64_t vmpidr_def
= mpidr_read_val(env
);
6226 ARMCPRegInfo vpidr_regs
[] = {
6227 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
6228 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
6229 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6230 .resetvalue
= cpu
->midr
, .type
= ARM_CP_ALIAS
,
6231 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
6232 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
6233 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
6234 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
6235 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
6236 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
6237 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
6238 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6239 .resetvalue
= vmpidr_def
, .type
= ARM_CP_ALIAS
,
6240 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
6241 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
6242 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
6244 .resetvalue
= vmpidr_def
,
6245 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
6248 define_arm_cp_regs(cpu
, vpidr_regs
);
6249 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
6250 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6251 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
6253 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
6254 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
6255 ARMCPRegInfo rvbar
= {
6256 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
6257 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
6258 .type
= ARM_CP_CONST
, .access
= PL2_R
, .resetvalue
= cpu
->rvbar
6260 define_one_arm_cp_reg(cpu
, &rvbar
);
6263 /* If EL2 is missing but higher ELs are enabled, we need to
6264 * register the no_el2 reginfos.
6266 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6267 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
6268 * of MIDR_EL1 and MPIDR_EL1.
6270 ARMCPRegInfo vpidr_regs
[] = {
6271 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
6272 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
6273 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
6274 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->midr
,
6275 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
6276 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
6277 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
6278 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
6279 .type
= ARM_CP_NO_RAW
,
6280 .writefn
= arm_cp_write_ignore
, .readfn
= mpidr_read
},
6283 define_arm_cp_regs(cpu
, vpidr_regs
);
6284 define_arm_cp_regs(cpu
, el3_no_el2_cp_reginfo
);
6285 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6286 define_arm_cp_regs(cpu
, el3_no_el2_v8_cp_reginfo
);
6290 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6291 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
6292 ARMCPRegInfo el3_regs
[] = {
6293 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
6294 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
6295 .type
= ARM_CP_CONST
, .access
= PL3_R
, .resetvalue
= cpu
->rvbar
},
6296 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
6297 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
6299 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
6300 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
6301 .resetvalue
= cpu
->reset_sctlr
},
6305 define_arm_cp_regs(cpu
, el3_regs
);
6307 /* The behaviour of NSACR is sufficiently various that we don't
6308 * try to describe it in a single reginfo:
6309 * if EL3 is 64 bit, then trap to EL3 from S EL1,
6310 * reads as constant 0xc00 from NS EL1 and NS EL2
6311 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
6312 * if v7 without EL3, register doesn't exist
6313 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
6315 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6316 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
6317 ARMCPRegInfo nsacr
= {
6318 .name
= "NSACR", .type
= ARM_CP_CONST
,
6319 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
6320 .access
= PL1_RW
, .accessfn
= nsacr_access
,
6323 define_one_arm_cp_reg(cpu
, &nsacr
);
6325 ARMCPRegInfo nsacr
= {
6327 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
6328 .access
= PL3_RW
| PL1_R
,
6330 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
6332 define_one_arm_cp_reg(cpu
, &nsacr
);
6335 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6336 ARMCPRegInfo nsacr
= {
6337 .name
= "NSACR", .type
= ARM_CP_CONST
,
6338 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
6342 define_one_arm_cp_reg(cpu
, &nsacr
);
6346 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
6347 if (arm_feature(env
, ARM_FEATURE_V6
)) {
6348 /* PMSAv6 not implemented */
6349 assert(arm_feature(env
, ARM_FEATURE_V7
));
6350 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
6351 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
6353 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
6356 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
6357 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
6358 /* TTCBR2 is introduced with ARMv8.2-A32HPD. */
6359 if (FIELD_EX32(cpu
->id_mmfr4
, ID_MMFR4
, HPDS
) != 0) {
6360 define_one_arm_cp_reg(cpu
, &ttbcr2_reginfo
);
6363 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
6364 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
6366 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
6367 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
6369 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
6370 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
6372 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
6373 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
6375 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
6376 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
6378 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
6379 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
6381 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
6382 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
6384 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
6385 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
6387 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
6388 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
6390 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
6391 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
6393 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
6394 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
6396 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
6397 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
6398 * be read-only (ie write causes UNDEF exception).
6401 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
6402 /* Pre-v8 MIDR space.
6403 * Note that the MIDR isn't a simple constant register because
6404 * of the TI925 behaviour where writes to another register can
6405 * cause the MIDR value to change.
6407 * Unimplemented registers in the c15 0 0 0 space default to
6408 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
6409 * and friends override accordingly.
6412 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
6413 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
6414 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
6415 .readfn
= midr_read
,
6416 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
6417 .type
= ARM_CP_OVERRIDE
},
6418 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
6420 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
6421 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6423 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
6424 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6426 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
6427 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6429 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
6430 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6432 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
6433 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6436 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
6437 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6438 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
6439 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
6440 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
6441 .readfn
= midr_read
},
6442 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
6443 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
6444 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
6445 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
6446 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
6447 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
6448 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
6449 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6450 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
6451 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
6454 ARMCPRegInfo id_cp_reginfo
[] = {
6455 /* These are common to v8 and pre-v8 */
6457 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
6458 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
6459 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
6460 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
6461 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
6462 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
6463 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
6465 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
6466 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6469 /* TLBTR is specific to VMSA */
6470 ARMCPRegInfo id_tlbtr_reginfo
= {
6472 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
6473 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
6475 /* MPUIR is specific to PMSA V6+ */
6476 ARMCPRegInfo id_mpuir_reginfo
= {
6478 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
6479 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6480 .resetvalue
= cpu
->pmsav7_dregion
<< 8
6482 ARMCPRegInfo crn0_wi_reginfo
= {
6483 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
6484 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
6485 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
6487 #ifdef CONFIG_USER_ONLY
6488 ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo
[] = {
6489 { .name
= "MIDR_EL1",
6490 .exported_bits
= 0x00000000ffffffff },
6491 { .name
= "REVIDR_EL1" },
6492 REGUSERINFO_SENTINEL
6494 modify_arm_cp_regs(id_v8_midr_cp_reginfo
, id_v8_user_midr_cp_reginfo
);
6496 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
6497 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
6499 /* Register the blanket "writes ignored" value first to cover the
6500 * whole space. Then update the specific ID registers to allow write
6501 * access, so that they ignore writes rather than causing them to
6504 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
6505 for (r
= id_pre_v8_midr_cp_reginfo
;
6506 r
->type
!= ARM_CP_SENTINEL
; r
++) {
6509 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
6512 id_mpuir_reginfo
.access
= PL1_RW
;
6513 id_tlbtr_reginfo
.access
= PL1_RW
;
6515 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6516 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
6518 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
6520 define_arm_cp_regs(cpu
, id_cp_reginfo
);
6521 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
6522 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
6523 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
6524 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
6528 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
6529 ARMCPRegInfo mpidr_cp_reginfo
[] = {
6530 { .name
= "MPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6531 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
6532 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
6535 #ifdef CONFIG_USER_ONLY
6536 ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo
[] = {
6537 { .name
= "MPIDR_EL1",
6538 .fixed_bits
= 0x0000000080000000 },
6539 REGUSERINFO_SENTINEL
6541 modify_arm_cp_regs(mpidr_cp_reginfo
, mpidr_user_cp_reginfo
);
6543 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
6546 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
6547 ARMCPRegInfo auxcr_reginfo
[] = {
6548 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
6549 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
6550 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
6551 .resetvalue
= cpu
->reset_auxcr
},
6552 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
6553 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
6554 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6556 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
6557 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
6558 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6562 define_arm_cp_regs(cpu
, auxcr_reginfo
);
6563 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6564 /* HACTLR2 maps to ACTLR_EL2[63:32] and is not in ARMv7 */
6565 ARMCPRegInfo hactlr2_reginfo
= {
6566 .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
6567 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
6568 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6571 define_one_arm_cp_reg(cpu
, &hactlr2_reginfo
);
6575 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
6576 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
6577 /* 32 bit view is [31:18] 0...0 [43:32]. */
6578 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
6579 | extract64(cpu
->reset_cbar
, 32, 12);
6580 ARMCPRegInfo cbar_reginfo
[] = {
6582 .type
= ARM_CP_CONST
,
6583 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
6584 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
6585 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
6586 .type
= ARM_CP_CONST
,
6587 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
6588 .access
= PL1_R
, .resetvalue
= cbar32
},
6591 /* We don't implement a r/w 64 bit CBAR currently */
6592 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
6593 define_arm_cp_regs(cpu
, cbar_reginfo
);
6595 ARMCPRegInfo cbar
= {
6597 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
6598 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
6599 .fieldoffset
= offsetof(CPUARMState
,
6600 cp15
.c15_config_base_address
)
6602 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
6603 cbar
.access
= PL1_R
;
6604 cbar
.fieldoffset
= 0;
6605 cbar
.type
= ARM_CP_CONST
;
6607 define_one_arm_cp_reg(cpu
, &cbar
);
6611 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
6612 ARMCPRegInfo vbar_cp_reginfo
[] = {
6613 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
6614 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
6615 .access
= PL1_RW
, .writefn
= vbar_write
,
6616 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
6617 offsetof(CPUARMState
, cp15
.vbar_ns
) },
6621 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
6624 /* Generic registers whose values depend on the implementation */
6626 ARMCPRegInfo sctlr
= {
6627 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
6628 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
6630 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
6631 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
6632 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
6633 .raw_writefn
= raw_write
,
6635 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
6636 /* Normally we would always end the TB on an SCTLR write, but Linux
6637 * arch/arm/mach-pxa/sleep.S expects two instructions following
6638 * an MMU enable to execute from cache. Imitate this behaviour.
6640 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
6642 define_one_arm_cp_reg(cpu
, &sctlr
);
6645 if (cpu_isar_feature(aa64_lor
, cpu
)) {
6647 * A trivial implementation of ARMv8.1-LOR leaves all of these
6648 * registers fixed at 0, which indicates that there are zero
6649 * supported Limited Ordering regions.
6651 static const ARMCPRegInfo lor_reginfo
[] = {
6652 { .name
= "LORSA_EL1", .state
= ARM_CP_STATE_AA64
,
6653 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 0,
6654 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6655 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6656 { .name
= "LOREA_EL1", .state
= ARM_CP_STATE_AA64
,
6657 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 1,
6658 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6659 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6660 { .name
= "LORN_EL1", .state
= ARM_CP_STATE_AA64
,
6661 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 2,
6662 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6663 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6664 { .name
= "LORC_EL1", .state
= ARM_CP_STATE_AA64
,
6665 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 3,
6666 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6667 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6668 { .name
= "LORID_EL1", .state
= ARM_CP_STATE_AA64
,
6669 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 7,
6670 .access
= PL1_R
, .accessfn
= access_lorid
,
6671 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6674 define_arm_cp_regs(cpu
, lor_reginfo
);
6677 if (cpu_isar_feature(aa64_sve
, cpu
)) {
6678 define_one_arm_cp_reg(cpu
, &zcr_el1_reginfo
);
6679 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
6680 define_one_arm_cp_reg(cpu
, &zcr_el2_reginfo
);
6682 define_one_arm_cp_reg(cpu
, &zcr_no_el2_reginfo
);
6684 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6685 define_one_arm_cp_reg(cpu
, &zcr_el3_reginfo
);
6689 #ifdef TARGET_AARCH64
6690 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
6691 define_arm_cp_regs(cpu
, pauth_reginfo
);
6696 * While all v8.0 cpus support aarch64, QEMU does have configurations
6697 * that do not set ID_AA64ISAR1, e.g. user-only qemu-arm -cpu max,
6698 * which will set ID_ISAR6.
6700 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)
6701 ? cpu_isar_feature(aa64_predinv
, cpu
)
6702 : cpu_isar_feature(aa32_predinv
, cpu
)) {
6703 define_arm_cp_regs(cpu
, predinv_reginfo
);
6707 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
6709 CPUState
*cs
= CPU(cpu
);
6710 CPUARMState
*env
= &cpu
->env
;
6712 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
6713 gdb_register_coprocessor(cs
, aarch64_fpu_gdb_get_reg
,
6714 aarch64_fpu_gdb_set_reg
,
6715 34, "aarch64-fpu.xml", 0);
6716 } else if (arm_feature(env
, ARM_FEATURE_NEON
)) {
6717 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
6718 51, "arm-neon.xml", 0);
6719 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
6720 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
6721 35, "arm-vfp3.xml", 0);
6722 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
6723 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
6724 19, "arm-vfp.xml", 0);
6726 gdb_register_coprocessor(cs
, arm_gdb_get_sysreg
, arm_gdb_set_sysreg
,
6727 arm_gen_dynamic_xml(cs
),
6728 "system-registers.xml", 0);
6731 /* Sort alphabetically by type name, except for "any". */
6732 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
6734 ObjectClass
*class_a
= (ObjectClass
*)a
;
6735 ObjectClass
*class_b
= (ObjectClass
*)b
;
6736 const char *name_a
, *name_b
;
6738 name_a
= object_class_get_name(class_a
);
6739 name_b
= object_class_get_name(class_b
);
6740 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
6742 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
6745 return strcmp(name_a
, name_b
);
6749 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
6751 ObjectClass
*oc
= data
;
6752 const char *typename
;
6755 typename
= object_class_get_name(oc
);
6756 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
6757 qemu_printf(" %s\n", name
);
6761 void arm_cpu_list(void)
6765 list
= object_class_get_list(TYPE_ARM_CPU
, false);
6766 list
= g_slist_sort(list
, arm_cpu_list_compare
);
6767 qemu_printf("Available CPUs:\n");
6768 g_slist_foreach(list
, arm_cpu_list_entry
, NULL
);
6772 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
6774 ObjectClass
*oc
= data
;
6775 CpuDefinitionInfoList
**cpu_list
= user_data
;
6776 CpuDefinitionInfoList
*entry
;
6777 CpuDefinitionInfo
*info
;
6778 const char *typename
;
6780 typename
= object_class_get_name(oc
);
6781 info
= g_malloc0(sizeof(*info
));
6782 info
->name
= g_strndup(typename
,
6783 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
6784 info
->q_typename
= g_strdup(typename
);
6786 entry
= g_malloc0(sizeof(*entry
));
6787 entry
->value
= info
;
6788 entry
->next
= *cpu_list
;
6792 CpuDefinitionInfoList
*qmp_query_cpu_definitions(Error
**errp
)
6794 CpuDefinitionInfoList
*cpu_list
= NULL
;
6797 list
= object_class_get_list(TYPE_ARM_CPU
, false);
6798 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
6804 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
6805 void *opaque
, int state
, int secstate
,
6806 int crm
, int opc1
, int opc2
,
6809 /* Private utility function for define_one_arm_cp_reg_with_opaque():
6810 * add a single reginfo struct to the hash table.
6812 uint32_t *key
= g_new(uint32_t, 1);
6813 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
6814 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
6815 int ns
= (secstate
& ARM_CP_SECSTATE_NS
) ? 1 : 0;
6817 r2
->name
= g_strdup(name
);
6818 /* Reset the secure state to the specific incoming state. This is
6819 * necessary as the register may have been defined with both states.
6821 r2
->secure
= secstate
;
6823 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
6824 /* Register is banked (using both entries in array).
6825 * Overwriting fieldoffset as the array is only used to define
6826 * banked registers but later only fieldoffset is used.
6828 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
6831 if (state
== ARM_CP_STATE_AA32
) {
6832 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
6833 /* If the register is banked then we don't need to migrate or
6834 * reset the 32-bit instance in certain cases:
6836 * 1) If the register has both 32-bit and 64-bit instances then we
6837 * can count on the 64-bit instance taking care of the
6839 * 2) If ARMv8 is enabled then we can count on a 64-bit version
6840 * taking care of the secure bank. This requires that separate
6841 * 32 and 64-bit definitions are provided.
6843 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
6844 (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) && !ns
)) {
6845 r2
->type
|= ARM_CP_ALIAS
;
6847 } else if ((secstate
!= r
->secure
) && !ns
) {
6848 /* The register is not banked so we only want to allow migration of
6849 * the non-secure instance.
6851 r2
->type
|= ARM_CP_ALIAS
;
6854 if (r
->state
== ARM_CP_STATE_BOTH
) {
6855 /* We assume it is a cp15 register if the .cp field is left unset.
6861 #ifdef HOST_WORDS_BIGENDIAN
6862 if (r2
->fieldoffset
) {
6863 r2
->fieldoffset
+= sizeof(uint32_t);
6868 if (state
== ARM_CP_STATE_AA64
) {
6869 /* To allow abbreviation of ARMCPRegInfo
6870 * definitions, we treat cp == 0 as equivalent to
6871 * the value for "standard guest-visible sysreg".
6872 * STATE_BOTH definitions are also always "standard
6873 * sysreg" in their AArch64 view (the .cp value may
6874 * be non-zero for the benefit of the AArch32 view).
6876 if (r
->cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
6877 r2
->cp
= CP_REG_ARM64_SYSREG_CP
;
6879 *key
= ENCODE_AA64_CP_REG(r2
->cp
, r2
->crn
, crm
,
6880 r2
->opc0
, opc1
, opc2
);
6882 *key
= ENCODE_CP_REG(r2
->cp
, is64
, ns
, r2
->crn
, crm
, opc1
, opc2
);
6885 r2
->opaque
= opaque
;
6887 /* reginfo passed to helpers is correct for the actual access,
6888 * and is never ARM_CP_STATE_BOTH:
6891 /* Make sure reginfo passed to helpers for wildcarded regs
6892 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
6897 /* By convention, for wildcarded registers only the first
6898 * entry is used for migration; the others are marked as
6899 * ALIAS so we don't try to transfer the register
6900 * multiple times. Special registers (ie NOP/WFI) are
6901 * never migratable and not even raw-accessible.
6903 if ((r
->type
& ARM_CP_SPECIAL
)) {
6904 r2
->type
|= ARM_CP_NO_RAW
;
6906 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
6907 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
6908 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
6909 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
6912 /* Check that raw accesses are either forbidden or handled. Note that
6913 * we can't assert this earlier because the setup of fieldoffset for
6914 * banked registers has to be done first.
6916 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
6917 assert(!raw_accessors_invalid(r2
));
6920 /* Overriding of an existing definition must be explicitly
6923 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
6924 ARMCPRegInfo
*oldreg
;
6925 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
6926 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
6927 fprintf(stderr
, "Register redefined: cp=%d %d bit "
6928 "crn=%d crm=%d opc1=%d opc2=%d, "
6929 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
6930 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
6931 oldreg
->name
, r2
->name
);
6932 g_assert_not_reached();
6935 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
6939 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
6940 const ARMCPRegInfo
*r
, void *opaque
)
6942 /* Define implementations of coprocessor registers.
6943 * We store these in a hashtable because typically
6944 * there are less than 150 registers in a space which
6945 * is 16*16*16*8*8 = 262144 in size.
6946 * Wildcarding is supported for the crm, opc1 and opc2 fields.
6947 * If a register is defined twice then the second definition is
6948 * used, so this can be used to define some generic registers and
6949 * then override them with implementation specific variations.
6950 * At least one of the original and the second definition should
6951 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
6952 * against accidental use.
6954 * The state field defines whether the register is to be
6955 * visible in the AArch32 or AArch64 execution state. If the
6956 * state is set to ARM_CP_STATE_BOTH then we synthesise a
6957 * reginfo structure for the AArch32 view, which sees the lower
6958 * 32 bits of the 64 bit register.
6960 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
6961 * be wildcarded. AArch64 registers are always considered to be 64
6962 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
6963 * the register, if any.
6965 int crm
, opc1
, opc2
, state
;
6966 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
6967 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
6968 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
6969 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
6970 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
6971 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
6972 /* 64 bit registers have only CRm and Opc1 fields */
6973 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
6974 /* op0 only exists in the AArch64 encodings */
6975 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
6976 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
6977 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
6978 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
6979 * encodes a minimum access level for the register. We roll this
6980 * runtime check into our general permission check code, so check
6981 * here that the reginfo's specified permissions are strict enough
6982 * to encompass the generic architectural permission check.
6984 if (r
->state
!= ARM_CP_STATE_AA32
) {
6988 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
6989 mask
= PL0U_R
| PL1_RW
;
7004 /* unallocated encoding, so not possible */
7012 /* min_EL EL1, secure mode only (we don't check the latter) */
7016 /* broken reginfo with out-of-range opc1 */
7020 /* assert our permissions are not too lax (stricter is fine) */
7021 assert((r
->access
& ~mask
) == 0);
7024 /* Check that the register definition has enough info to handle
7025 * reads and writes if they are permitted.
7027 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
7028 if (r
->access
& PL3_R
) {
7029 assert((r
->fieldoffset
||
7030 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
7033 if (r
->access
& PL3_W
) {
7034 assert((r
->fieldoffset
||
7035 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
7039 /* Bad type field probably means missing sentinel at end of reg list */
7040 assert(cptype_valid(r
->type
));
7041 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
7042 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
7043 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
7044 for (state
= ARM_CP_STATE_AA32
;
7045 state
<= ARM_CP_STATE_AA64
; state
++) {
7046 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
7049 if (state
== ARM_CP_STATE_AA32
) {
7050 /* Under AArch32 CP registers can be common
7051 * (same for secure and non-secure world) or banked.
7055 switch (r
->secure
) {
7056 case ARM_CP_SECSTATE_S
:
7057 case ARM_CP_SECSTATE_NS
:
7058 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
7059 r
->secure
, crm
, opc1
, opc2
,
7063 name
= g_strdup_printf("%s_S", r
->name
);
7064 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
7066 crm
, opc1
, opc2
, name
);
7068 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
7070 crm
, opc1
, opc2
, r
->name
);
7074 /* AArch64 registers get mapped to non-secure instance
7076 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
7078 crm
, opc1
, opc2
, r
->name
);
7086 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
7087 const ARMCPRegInfo
*regs
, void *opaque
)
7089 /* Define a whole list of registers */
7090 const ARMCPRegInfo
*r
;
7091 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
7092 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
7097 * Modify ARMCPRegInfo for access from userspace.
7099 * This is a data driven modification directed by
7100 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
7101 * user-space cannot alter any values and dynamic values pertaining to
7102 * execution state are hidden from user space view anyway.
7104 void modify_arm_cp_regs(ARMCPRegInfo
*regs
, const ARMCPRegUserSpaceInfo
*mods
)
7106 const ARMCPRegUserSpaceInfo
*m
;
7109 for (m
= mods
; m
->name
; m
++) {
7110 GPatternSpec
*pat
= NULL
;
7112 pat
= g_pattern_spec_new(m
->name
);
7114 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
7115 if (pat
&& g_pattern_match_string(pat
, r
->name
)) {
7116 r
->type
= ARM_CP_CONST
;
7120 } else if (strcmp(r
->name
, m
->name
) == 0) {
7121 r
->type
= ARM_CP_CONST
;
7123 r
->resetvalue
&= m
->exported_bits
;
7124 r
->resetvalue
|= m
->fixed_bits
;
7129 g_pattern_spec_free(pat
);
7134 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
7136 return g_hash_table_lookup(cpregs
, &encoded_cp
);
7139 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7142 /* Helper coprocessor write function for write-ignore registers */
7145 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7147 /* Helper coprocessor write function for read-as-zero registers */
7151 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
7153 /* Helper coprocessor reset function for do-nothing-on-reset registers */
7156 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
7158 /* Return true if it is not valid for us to switch to
7159 * this CPU mode (ie all the UNPREDICTABLE cases in
7160 * the ARM ARM CPSRWriteByInstr pseudocode).
7163 /* Changes to or from Hyp via MSR and CPS are illegal. */
7164 if (write_type
== CPSRWriteByInstr
&&
7165 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
7166 mode
== ARM_CPU_MODE_HYP
)) {
7171 case ARM_CPU_MODE_USR
:
7173 case ARM_CPU_MODE_SYS
:
7174 case ARM_CPU_MODE_SVC
:
7175 case ARM_CPU_MODE_ABT
:
7176 case ARM_CPU_MODE_UND
:
7177 case ARM_CPU_MODE_IRQ
:
7178 case ARM_CPU_MODE_FIQ
:
7179 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
7180 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
7182 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
7183 * and CPS are treated as illegal mode changes.
7185 if (write_type
== CPSRWriteByInstr
&&
7186 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
7187 (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
7191 case ARM_CPU_MODE_HYP
:
7192 return !arm_feature(env
, ARM_FEATURE_EL2
)
7193 || arm_current_el(env
) < 2 || arm_is_secure_below_el3(env
);
7194 case ARM_CPU_MODE_MON
:
7195 return arm_current_el(env
) < 3;
7201 uint32_t cpsr_read(CPUARMState
*env
)
7204 ZF
= (env
->ZF
== 0);
7205 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
7206 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
7207 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
7208 | ((env
->condexec_bits
& 0xfc) << 8)
7209 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
7212 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
7213 CPSRWriteType write_type
)
7215 uint32_t changed_daif
;
7217 if (mask
& CPSR_NZCV
) {
7218 env
->ZF
= (~val
) & CPSR_Z
;
7220 env
->CF
= (val
>> 29) & 1;
7221 env
->VF
= (val
<< 3) & 0x80000000;
7224 env
->QF
= ((val
& CPSR_Q
) != 0);
7226 env
->thumb
= ((val
& CPSR_T
) != 0);
7227 if (mask
& CPSR_IT_0_1
) {
7228 env
->condexec_bits
&= ~3;
7229 env
->condexec_bits
|= (val
>> 25) & 3;
7231 if (mask
& CPSR_IT_2_7
) {
7232 env
->condexec_bits
&= 3;
7233 env
->condexec_bits
|= (val
>> 8) & 0xfc;
7235 if (mask
& CPSR_GE
) {
7236 env
->GE
= (val
>> 16) & 0xf;
7239 /* In a V7 implementation that includes the security extensions but does
7240 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
7241 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
7242 * bits respectively.
7244 * In a V8 implementation, it is permitted for privileged software to
7245 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
7247 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
7248 arm_feature(env
, ARM_FEATURE_EL3
) &&
7249 !arm_feature(env
, ARM_FEATURE_EL2
) &&
7250 !arm_is_secure(env
)) {
7252 changed_daif
= (env
->daif
^ val
) & mask
;
7254 if (changed_daif
& CPSR_A
) {
7255 /* Check to see if we are allowed to change the masking of async
7256 * abort exceptions from a non-secure state.
7258 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
7259 qemu_log_mask(LOG_GUEST_ERROR
,
7260 "Ignoring attempt to switch CPSR_A flag from "
7261 "non-secure world with SCR.AW bit clear\n");
7266 if (changed_daif
& CPSR_F
) {
7267 /* Check to see if we are allowed to change the masking of FIQ
7268 * exceptions from a non-secure state.
7270 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
7271 qemu_log_mask(LOG_GUEST_ERROR
,
7272 "Ignoring attempt to switch CPSR_F flag from "
7273 "non-secure world with SCR.FW bit clear\n");
7277 /* Check whether non-maskable FIQ (NMFI) support is enabled.
7278 * If this bit is set software is not allowed to mask
7279 * FIQs, but is allowed to set CPSR_F to 0.
7281 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
7283 qemu_log_mask(LOG_GUEST_ERROR
,
7284 "Ignoring attempt to enable CPSR_F flag "
7285 "(non-maskable FIQ [NMFI] support enabled)\n");
7291 env
->daif
&= ~(CPSR_AIF
& mask
);
7292 env
->daif
|= val
& CPSR_AIF
& mask
;
7294 if (write_type
!= CPSRWriteRaw
&&
7295 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
7296 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
7297 /* Note that we can only get here in USR mode if this is a
7298 * gdb stub write; for this case we follow the architectural
7299 * behaviour for guest writes in USR mode of ignoring an attempt
7300 * to switch mode. (Those are caught by translate.c for writes
7301 * triggered by guest instructions.)
7304 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
7305 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
7306 * v7, and has defined behaviour in v8:
7307 * + leave CPSR.M untouched
7308 * + allow changes to the other CPSR fields
7310 * For user changes via the GDB stub, we don't set PSTATE.IL,
7311 * as this would be unnecessarily harsh for a user error.
7314 if (write_type
!= CPSRWriteByGDBStub
&&
7315 arm_feature(env
, ARM_FEATURE_V8
)) {
7319 qemu_log_mask(LOG_GUEST_ERROR
,
7320 "Illegal AArch32 mode switch attempt from %s to %s\n",
7321 aarch32_mode_name(env
->uncached_cpsr
),
7322 aarch32_mode_name(val
));
7324 qemu_log_mask(CPU_LOG_INT
, "%s %s to %s PC 0x%" PRIx32
"\n",
7325 write_type
== CPSRWriteExceptionReturn
?
7326 "Exception return from AArch32" :
7327 "AArch32 mode switch from",
7328 aarch32_mode_name(env
->uncached_cpsr
),
7329 aarch32_mode_name(val
), env
->regs
[15]);
7330 switch_mode(env
, val
& CPSR_M
);
7333 mask
&= ~CACHED_CPSR_BITS
;
7334 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
7337 /* Sign/zero extend */
7338 uint32_t HELPER(sxtb16
)(uint32_t x
)
7341 res
= (uint16_t)(int8_t)x
;
7342 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
7346 uint32_t HELPER(uxtb16
)(uint32_t x
)
7349 res
= (uint16_t)(uint8_t)x
;
7350 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
7354 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
7358 if (num
== INT_MIN
&& den
== -1)
7363 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
7370 uint32_t HELPER(rbit
)(uint32_t x
)
7375 #ifdef CONFIG_USER_ONLY
7377 /* These should probably raise undefined insn exceptions. */
7378 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
7380 ARMCPU
*cpu
= arm_env_get_cpu(env
);
7382 cpu_abort(CPU(cpu
), "v7m_msr %d\n", reg
);
7385 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
7387 ARMCPU
*cpu
= arm_env_get_cpu(env
);
7389 cpu_abort(CPU(cpu
), "v7m_mrs %d\n", reg
);
7393 void HELPER(v7m_bxns
)(CPUARMState
*env
, uint32_t dest
)
7395 /* translate.c should never generate calls here in user-only mode */
7396 g_assert_not_reached();
7399 void HELPER(v7m_blxns
)(CPUARMState
*env
, uint32_t dest
)
7401 /* translate.c should never generate calls here in user-only mode */
7402 g_assert_not_reached();
7405 void HELPER(v7m_preserve_fp_state
)(CPUARMState
*env
)
7407 /* translate.c should never generate calls here in user-only mode */
7408 g_assert_not_reached();
7411 void HELPER(v7m_vlstm
)(CPUARMState
*env
, uint32_t fptr
)
7413 /* translate.c should never generate calls here in user-only mode */
7414 g_assert_not_reached();
7417 void HELPER(v7m_vlldm
)(CPUARMState
*env
, uint32_t fptr
)
7419 /* translate.c should never generate calls here in user-only mode */
7420 g_assert_not_reached();
7423 uint32_t HELPER(v7m_tt
)(CPUARMState
*env
, uint32_t addr
, uint32_t op
)
7425 /* The TT instructions can be used by unprivileged code, but in
7426 * user-only emulation we don't have the MPU.
7427 * Luckily since we know we are NonSecure unprivileged (and that in
7428 * turn means that the A flag wasn't specified), all the bits in the
7429 * register must be zero:
7430 * IREGION: 0 because IRVALID is 0
7431 * IRVALID: 0 because NS
7433 * NSRW: 0 because NS
7435 * RW: 0 because unpriv and A flag not set
7436 * R: 0 because unpriv and A flag not set
7437 * SRVALID: 0 because NS
7438 * MRVALID: 0 because unpriv and A flag not set
7439 * SREGION: 0 becaus SRVALID is 0
7440 * MREGION: 0 because MRVALID is 0
7445 static void switch_mode(CPUARMState
*env
, int mode
)
7447 ARMCPU
*cpu
= arm_env_get_cpu(env
);
7449 if (mode
!= ARM_CPU_MODE_USR
) {
7450 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
7454 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
7455 uint32_t cur_el
, bool secure
)
7460 void aarch64_sync_64_to_32(CPUARMState
*env
)
7462 g_assert_not_reached();
7467 static void switch_mode(CPUARMState
*env
, int mode
)
7472 old_mode
= env
->uncached_cpsr
& CPSR_M
;
7473 if (mode
== old_mode
)
7476 if (old_mode
== ARM_CPU_MODE_FIQ
) {
7477 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
7478 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
7479 } else if (mode
== ARM_CPU_MODE_FIQ
) {
7480 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
7481 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
7484 i
= bank_number(old_mode
);
7485 env
->banked_r13
[i
] = env
->regs
[13];
7486 env
->banked_spsr
[i
] = env
->spsr
;
7488 i
= bank_number(mode
);
7489 env
->regs
[13] = env
->banked_r13
[i
];
7490 env
->spsr
= env
->banked_spsr
[i
];
7492 env
->banked_r14
[r14_bank_number(old_mode
)] = env
->regs
[14];
7493 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
7496 /* Physical Interrupt Target EL Lookup Table
7498 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
7500 * The below multi-dimensional table is used for looking up the target
7501 * exception level given numerous condition criteria. Specifically, the
7502 * target EL is based on SCR and HCR routing controls as well as the
7503 * currently executing EL and secure state.
7506 * target_el_table[2][2][2][2][2][4]
7507 * | | | | | +--- Current EL
7508 * | | | | +------ Non-secure(0)/Secure(1)
7509 * | | | +--------- HCR mask override
7510 * | | +------------ SCR exec state control
7511 * | +--------------- SCR mask override
7512 * +------------------ 32-bit(0)/64-bit(1) EL3
7514 * The table values are as such:
7518 * The ARM ARM target EL table includes entries indicating that an "exception
7519 * is not taken". The two cases where this is applicable are:
7520 * 1) An exception is taken from EL3 but the SCR does not have the exception
7522 * 2) An exception is taken from EL2 but the HCR does not have the exception
7524 * In these two cases, the below table contain a target of EL1. This value is
7525 * returned as it is expected that the consumer of the table data will check
7526 * for "target EL >= current EL" to ensure the exception is not taken.
7530 * BIT IRQ IMO Non-secure Secure
7531 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
7533 static const int8_t target_el_table
[2][2][2][2][2][4] = {
7534 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
7535 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
7536 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
7537 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
7538 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
7539 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
7540 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
7541 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
7542 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
7543 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
7544 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
7545 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
7546 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
7547 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
7548 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
7549 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
7553 * Determine the target EL for physical exceptions
7555 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
7556 uint32_t cur_el
, bool secure
)
7558 CPUARMState
*env
= cs
->env_ptr
;
7563 /* Is the highest EL AArch64? */
7564 bool is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
7567 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7568 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
7570 /* Either EL2 is the highest EL (and so the EL2 register width
7571 * is given by is64); or there is no EL2 or EL3, in which case
7572 * the value of 'rw' does not affect the table lookup anyway.
7577 hcr_el2
= arm_hcr_el2_eff(env
);
7580 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
7581 hcr
= hcr_el2
& HCR_IMO
;
7584 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
7585 hcr
= hcr_el2
& HCR_FMO
;
7588 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
7589 hcr
= hcr_el2
& HCR_AMO
;
7593 /* Perform a table-lookup for the target EL given the current state */
7594 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
7596 assert(target_el
> 0);
7602 * Return true if the v7M CPACR permits access to the FPU for the specified
7603 * security state and privilege level.
7605 static bool v7m_cpacr_pass(CPUARMState
*env
, bool is_secure
, bool is_priv
)
7607 switch (extract32(env
->v7m
.cpacr
[is_secure
], 20, 2)) {
7609 case 2: /* UNPREDICTABLE: we treat like 0 */
7616 g_assert_not_reached();
7621 * What kind of stack write are we doing? This affects how exceptions
7622 * generated during the stacking are treated.
7624 typedef enum StackingMode
{
7630 static bool v7m_stack_write(ARMCPU
*cpu
, uint32_t addr
, uint32_t value
,
7631 ARMMMUIdx mmu_idx
, StackingMode mode
)
7633 CPUState
*cs
= CPU(cpu
);
7634 CPUARMState
*env
= &cpu
->env
;
7635 MemTxAttrs attrs
= {};
7637 target_ulong page_size
;
7640 ARMMMUFaultInfo fi
= {};
7641 bool secure
= mmu_idx
& ARM_MMU_IDX_M_S
;
7645 if (get_phys_addr(env
, addr
, MMU_DATA_STORE
, mmu_idx
, &physaddr
,
7646 &attrs
, &prot
, &page_size
, &fi
, NULL
)) {
7647 /* MPU/SAU lookup failed */
7648 if (fi
.type
== ARMFault_QEMU_SFault
) {
7649 if (mode
== STACK_LAZYFP
) {
7650 qemu_log_mask(CPU_LOG_INT
,
7651 "...SecureFault with SFSR.LSPERR "
7652 "during lazy stacking\n");
7653 env
->v7m
.sfsr
|= R_V7M_SFSR_LSPERR_MASK
;
7655 qemu_log_mask(CPU_LOG_INT
,
7656 "...SecureFault with SFSR.AUVIOL "
7657 "during stacking\n");
7658 env
->v7m
.sfsr
|= R_V7M_SFSR_AUVIOL_MASK
;
7660 env
->v7m
.sfsr
|= R_V7M_SFSR_SFARVALID_MASK
;
7661 env
->v7m
.sfar
= addr
;
7662 exc
= ARMV7M_EXCP_SECURE
;
7665 if (mode
== STACK_LAZYFP
) {
7666 qemu_log_mask(CPU_LOG_INT
,
7667 "...MemManageFault with CFSR.MLSPERR\n");
7668 env
->v7m
.cfsr
[secure
] |= R_V7M_CFSR_MLSPERR_MASK
;
7670 qemu_log_mask(CPU_LOG_INT
,
7671 "...MemManageFault with CFSR.MSTKERR\n");
7672 env
->v7m
.cfsr
[secure
] |= R_V7M_CFSR_MSTKERR_MASK
;
7674 exc
= ARMV7M_EXCP_MEM
;
7675 exc_secure
= secure
;
7679 address_space_stl_le(arm_addressspace(cs
, attrs
), physaddr
, value
,
7681 if (txres
!= MEMTX_OK
) {
7682 /* BusFault trying to write the data */
7683 if (mode
== STACK_LAZYFP
) {
7684 qemu_log_mask(CPU_LOG_INT
, "...BusFault with BFSR.LSPERR\n");
7685 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_LSPERR_MASK
;
7687 qemu_log_mask(CPU_LOG_INT
, "...BusFault with BFSR.STKERR\n");
7688 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_STKERR_MASK
;
7690 exc
= ARMV7M_EXCP_BUS
;
7697 /* By pending the exception at this point we are making
7698 * the IMPDEF choice "overridden exceptions pended" (see the
7699 * MergeExcInfo() pseudocode). The other choice would be to not
7700 * pend them now and then make a choice about which to throw away
7701 * later if we have two derived exceptions.
7702 * The only case when we must not pend the exception but instead
7703 * throw it away is if we are doing the push of the callee registers
7704 * and we've already generated a derived exception (this is indicated
7705 * by the caller passing STACK_IGNFAULTS). Even in this case we will
7706 * still update the fault status registers.
7710 armv7m_nvic_set_pending_derived(env
->nvic
, exc
, exc_secure
);
7713 armv7m_nvic_set_pending_lazyfp(env
->nvic
, exc
, exc_secure
);
7715 case STACK_IGNFAULTS
:
7721 static bool v7m_stack_read(ARMCPU
*cpu
, uint32_t *dest
, uint32_t addr
,
7724 CPUState
*cs
= CPU(cpu
);
7725 CPUARMState
*env
= &cpu
->env
;
7726 MemTxAttrs attrs
= {};
7728 target_ulong page_size
;
7731 ARMMMUFaultInfo fi
= {};
7732 bool secure
= mmu_idx
& ARM_MMU_IDX_M_S
;
7737 if (get_phys_addr(env
, addr
, MMU_DATA_LOAD
, mmu_idx
, &physaddr
,
7738 &attrs
, &prot
, &page_size
, &fi
, NULL
)) {
7739 /* MPU/SAU lookup failed */
7740 if (fi
.type
== ARMFault_QEMU_SFault
) {
7741 qemu_log_mask(CPU_LOG_INT
,
7742 "...SecureFault with SFSR.AUVIOL during unstack\n");
7743 env
->v7m
.sfsr
|= R_V7M_SFSR_AUVIOL_MASK
| R_V7M_SFSR_SFARVALID_MASK
;
7744 env
->v7m
.sfar
= addr
;
7745 exc
= ARMV7M_EXCP_SECURE
;
7748 qemu_log_mask(CPU_LOG_INT
,
7749 "...MemManageFault with CFSR.MUNSTKERR\n");
7750 env
->v7m
.cfsr
[secure
] |= R_V7M_CFSR_MUNSTKERR_MASK
;
7751 exc
= ARMV7M_EXCP_MEM
;
7752 exc_secure
= secure
;
7757 value
= address_space_ldl(arm_addressspace(cs
, attrs
), physaddr
,
7759 if (txres
!= MEMTX_OK
) {
7760 /* BusFault trying to read the data */
7761 qemu_log_mask(CPU_LOG_INT
, "...BusFault with BFSR.UNSTKERR\n");
7762 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_UNSTKERR_MASK
;
7763 exc
= ARMV7M_EXCP_BUS
;
7772 /* By pending the exception at this point we are making
7773 * the IMPDEF choice "overridden exceptions pended" (see the
7774 * MergeExcInfo() pseudocode). The other choice would be to not
7775 * pend them now and then make a choice about which to throw away
7776 * later if we have two derived exceptions.
7778 armv7m_nvic_set_pending(env
->nvic
, exc
, exc_secure
);
7782 void HELPER(v7m_preserve_fp_state
)(CPUARMState
*env
)
7785 * Preserve FP state (because LSPACT was set and we are about
7786 * to execute an FP instruction). This corresponds to the
7787 * PreserveFPState() pseudocode.
7788 * We may throw an exception if the stacking fails.
7790 ARMCPU
*cpu
= arm_env_get_cpu(env
);
7791 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
7792 bool negpri
= !(env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_HFRDY_MASK
);
7793 bool is_priv
= !(env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_USER_MASK
);
7794 bool splimviol
= env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_SPLIMVIOL_MASK
;
7795 uint32_t fpcar
= env
->v7m
.fpcar
[is_secure
];
7796 bool stacked_ok
= true;
7797 bool ts
= is_secure
&& (env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_TS_MASK
);
7798 bool take_exception
;
7800 /* Take the iothread lock as we are going to touch the NVIC */
7801 qemu_mutex_lock_iothread();
7803 /* Check the background context had access to the FPU */
7804 if (!v7m_cpacr_pass(env
, is_secure
, is_priv
)) {
7805 armv7m_nvic_set_pending_lazyfp(env
->nvic
, ARMV7M_EXCP_USAGE
, is_secure
);
7806 env
->v7m
.cfsr
[is_secure
] |= R_V7M_CFSR_NOCP_MASK
;
7808 } else if (!is_secure
&& !extract32(env
->v7m
.nsacr
, 10, 1)) {
7809 armv7m_nvic_set_pending_lazyfp(env
->nvic
, ARMV7M_EXCP_USAGE
, M_REG_S
);
7810 env
->v7m
.cfsr
[M_REG_S
] |= R_V7M_CFSR_NOCP_MASK
;
7814 if (!splimviol
&& stacked_ok
) {
7815 /* We only stack if the stack limit wasn't violated */
7819 mmu_idx
= arm_v7m_mmu_idx_all(env
, is_secure
, is_priv
, negpri
);
7820 for (i
= 0; i
< (ts
? 32 : 16); i
+= 2) {
7821 uint64_t dn
= *aa32_vfp_dreg(env
, i
/ 2);
7822 uint32_t faddr
= fpcar
+ 4 * i
;
7823 uint32_t slo
= extract64(dn
, 0, 32);
7824 uint32_t shi
= extract64(dn
, 32, 32);
7827 faddr
+= 8; /* skip the slot for the FPSCR */
7829 stacked_ok
= stacked_ok
&&
7830 v7m_stack_write(cpu
, faddr
, slo
, mmu_idx
, STACK_LAZYFP
) &&
7831 v7m_stack_write(cpu
, faddr
+ 4, shi
, mmu_idx
, STACK_LAZYFP
);
7834 stacked_ok
= stacked_ok
&&
7835 v7m_stack_write(cpu
, fpcar
+ 0x40,
7836 vfp_get_fpscr(env
), mmu_idx
, STACK_LAZYFP
);
7840 * We definitely pended an exception, but it's possible that it
7841 * might not be able to be taken now. If its priority permits us
7842 * to take it now, then we must not update the LSPACT or FP regs,
7843 * but instead jump out to take the exception immediately.
7844 * If it's just pending and won't be taken until the current
7845 * handler exits, then we do update LSPACT and the FP regs.
7847 take_exception
= !stacked_ok
&&
7848 armv7m_nvic_can_take_pending_exception(env
->nvic
);
7850 qemu_mutex_unlock_iothread();
7852 if (take_exception
) {
7853 raise_exception_ra(env
, EXCP_LAZYFP
, 0, 1, GETPC());
7856 env
->v7m
.fpccr
[is_secure
] &= ~R_V7M_FPCCR_LSPACT_MASK
;
7859 /* Clear s0 to s31 and the FPSCR */
7862 for (i
= 0; i
< 32; i
+= 2) {
7863 *aa32_vfp_dreg(env
, i
/ 2) = 0;
7865 vfp_set_fpscr(env
, 0);
7868 * Otherwise s0 to s15 and FPSCR are UNKNOWN; we choose to leave them
7873 /* Write to v7M CONTROL.SPSEL bit for the specified security bank.
7874 * This may change the current stack pointer between Main and Process
7875 * stack pointers if it is done for the CONTROL register for the current
7878 static void write_v7m_control_spsel_for_secstate(CPUARMState
*env
,
7882 bool old_is_psp
= v7m_using_psp(env
);
7884 env
->v7m
.control
[secstate
] =
7885 deposit32(env
->v7m
.control
[secstate
],
7886 R_V7M_CONTROL_SPSEL_SHIFT
,
7887 R_V7M_CONTROL_SPSEL_LENGTH
, new_spsel
);
7889 if (secstate
== env
->v7m
.secure
) {
7890 bool new_is_psp
= v7m_using_psp(env
);
7893 if (old_is_psp
!= new_is_psp
) {
7894 tmp
= env
->v7m
.other_sp
;
7895 env
->v7m
.other_sp
= env
->regs
[13];
7896 env
->regs
[13] = tmp
;
7901 /* Write to v7M CONTROL.SPSEL bit. This may change the current
7902 * stack pointer between Main and Process stack pointers.
7904 static void write_v7m_control_spsel(CPUARMState
*env
, bool new_spsel
)
7906 write_v7m_control_spsel_for_secstate(env
, new_spsel
, env
->v7m
.secure
);
7909 void write_v7m_exception(CPUARMState
*env
, uint32_t new_exc
)
7911 /* Write a new value to v7m.exception, thus transitioning into or out
7912 * of Handler mode; this may result in a change of active stack pointer.
7914 bool new_is_psp
, old_is_psp
= v7m_using_psp(env
);
7917 env
->v7m
.exception
= new_exc
;
7919 new_is_psp
= v7m_using_psp(env
);
7921 if (old_is_psp
!= new_is_psp
) {
7922 tmp
= env
->v7m
.other_sp
;
7923 env
->v7m
.other_sp
= env
->regs
[13];
7924 env
->regs
[13] = tmp
;
7928 /* Switch M profile security state between NS and S */
7929 static void switch_v7m_security_state(CPUARMState
*env
, bool new_secstate
)
7931 uint32_t new_ss_msp
, new_ss_psp
;
7933 if (env
->v7m
.secure
== new_secstate
) {
7937 /* All the banked state is accessed by looking at env->v7m.secure
7938 * except for the stack pointer; rearrange the SP appropriately.
7940 new_ss_msp
= env
->v7m
.other_ss_msp
;
7941 new_ss_psp
= env
->v7m
.other_ss_psp
;
7943 if (v7m_using_psp(env
)) {
7944 env
->v7m
.other_ss_psp
= env
->regs
[13];
7945 env
->v7m
.other_ss_msp
= env
->v7m
.other_sp
;
7947 env
->v7m
.other_ss_msp
= env
->regs
[13];
7948 env
->v7m
.other_ss_psp
= env
->v7m
.other_sp
;
7951 env
->v7m
.secure
= new_secstate
;
7953 if (v7m_using_psp(env
)) {
7954 env
->regs
[13] = new_ss_psp
;
7955 env
->v7m
.other_sp
= new_ss_msp
;
7957 env
->regs
[13] = new_ss_msp
;
7958 env
->v7m
.other_sp
= new_ss_psp
;
7962 void HELPER(v7m_bxns
)(CPUARMState
*env
, uint32_t dest
)
7965 * - if the return value is a magic value, do exception return (like BX)
7966 * - otherwise bit 0 of the return value is the target security state
7970 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
7971 /* Covers FNC_RETURN and EXC_RETURN magic */
7972 min_magic
= FNC_RETURN_MIN_MAGIC
;
7974 /* EXC_RETURN magic only */
7975 min_magic
= EXC_RETURN_MIN_MAGIC
;
7978 if (dest
>= min_magic
) {
7979 /* This is an exception return magic value; put it where
7980 * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT.
7981 * Note that if we ever add gen_ss_advance() singlestep support to
7982 * M profile this should count as an "instruction execution complete"
7983 * event (compare gen_bx_excret_final_code()).
7985 env
->regs
[15] = dest
& ~1;
7986 env
->thumb
= dest
& 1;
7987 HELPER(exception_internal
)(env
, EXCP_EXCEPTION_EXIT
);
7991 /* translate.c should have made BXNS UNDEF unless we're secure */
7992 assert(env
->v7m
.secure
);
7995 env
->v7m
.control
[M_REG_S
] &= ~R_V7M_CONTROL_SFPA_MASK
;
7997 switch_v7m_security_state(env
, dest
& 1);
7999 env
->regs
[15] = dest
& ~1;
8002 void HELPER(v7m_blxns
)(CPUARMState
*env
, uint32_t dest
)
8004 /* Handle v7M BLXNS:
8005 * - bit 0 of the destination address is the target security state
8008 /* At this point regs[15] is the address just after the BLXNS */
8009 uint32_t nextinst
= env
->regs
[15] | 1;
8010 uint32_t sp
= env
->regs
[13] - 8;
8013 /* translate.c will have made BLXNS UNDEF unless we're secure */
8014 assert(env
->v7m
.secure
);
8017 /* target is Secure, so this is just a normal BLX,
8018 * except that the low bit doesn't indicate Thumb/not.
8020 env
->regs
[14] = nextinst
;
8022 env
->regs
[15] = dest
& ~1;
8026 /* Target is non-secure: first push a stack frame */
8027 if (!QEMU_IS_ALIGNED(sp
, 8)) {
8028 qemu_log_mask(LOG_GUEST_ERROR
,
8029 "BLXNS with misaligned SP is UNPREDICTABLE\n");
8032 if (sp
< v7m_sp_limit(env
)) {
8033 raise_exception(env
, EXCP_STKOF
, 0, 1);
8036 saved_psr
= env
->v7m
.exception
;
8037 if (env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
) {
8038 saved_psr
|= XPSR_SFPA
;
8041 /* Note that these stores can throw exceptions on MPU faults */
8042 cpu_stl_data(env
, sp
, nextinst
);
8043 cpu_stl_data(env
, sp
+ 4, saved_psr
);
8046 env
->regs
[14] = 0xfeffffff;
8047 if (arm_v7m_is_handler_mode(env
)) {
8048 /* Write a dummy value to IPSR, to avoid leaking the current secure
8049 * exception number to non-secure code. This is guaranteed not
8050 * to cause write_v7m_exception() to actually change stacks.
8052 write_v7m_exception(env
, 1);
8054 env
->v7m
.control
[M_REG_S
] &= ~R_V7M_CONTROL_SFPA_MASK
;
8055 switch_v7m_security_state(env
, 0);
8057 env
->regs
[15] = dest
;
8060 static uint32_t *get_v7m_sp_ptr(CPUARMState
*env
, bool secure
, bool threadmode
,
8063 /* Return a pointer to the location where we currently store the
8064 * stack pointer for the requested security state and thread mode.
8065 * This pointer will become invalid if the CPU state is updated
8066 * such that the stack pointers are switched around (eg changing
8067 * the SPSEL control bit).
8068 * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
8069 * Unlike that pseudocode, we require the caller to pass us in the
8070 * SPSEL control bit value; this is because we also use this
8071 * function in handling of pushing of the callee-saves registers
8072 * part of the v8M stack frame (pseudocode PushCalleeStack()),
8073 * and in the tailchain codepath the SPSEL bit comes from the exception
8074 * return magic LR value from the previous exception. The pseudocode
8075 * opencodes the stack-selection in PushCalleeStack(), but we prefer
8076 * to make this utility function generic enough to do the job.
8078 bool want_psp
= threadmode
&& spsel
;
8080 if (secure
== env
->v7m
.secure
) {
8081 if (want_psp
== v7m_using_psp(env
)) {
8082 return &env
->regs
[13];
8084 return &env
->v7m
.other_sp
;
8088 return &env
->v7m
.other_ss_psp
;
8090 return &env
->v7m
.other_ss_msp
;
8095 static bool arm_v7m_load_vector(ARMCPU
*cpu
, int exc
, bool targets_secure
,
8098 CPUState
*cs
= CPU(cpu
);
8099 CPUARMState
*env
= &cpu
->env
;
8101 uint32_t addr
= env
->v7m
.vecbase
[targets_secure
] + exc
* 4;
8102 uint32_t vector_entry
;
8103 MemTxAttrs attrs
= {};
8107 mmu_idx
= arm_v7m_mmu_idx_for_secstate_and_priv(env
, targets_secure
, true);
8109 /* We don't do a get_phys_addr() here because the rules for vector
8110 * loads are special: they always use the default memory map, and
8111 * the default memory map permits reads from all addresses.
8112 * Since there's no easy way to pass through to pmsav8_mpu_lookup()
8113 * that we want this special case which would always say "yes",
8114 * we just do the SAU lookup here followed by a direct physical load.
8116 attrs
.secure
= targets_secure
;
8119 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
8120 V8M_SAttributes sattrs
= {};
8122 v8m_security_lookup(env
, addr
, MMU_DATA_LOAD
, mmu_idx
, &sattrs
);
8124 attrs
.secure
= false;
8125 } else if (!targets_secure
) {
8126 /* NS access to S memory */
8131 vector_entry
= address_space_ldl(arm_addressspace(cs
, attrs
), addr
,
8133 if (result
!= MEMTX_OK
) {
8136 *pvec
= vector_entry
;
8140 /* All vector table fetch fails are reported as HardFault, with
8141 * HFSR.VECTTBL and .FORCED set. (FORCED is set because
8142 * technically the underlying exception is a MemManage or BusFault
8143 * that is escalated to HardFault.) This is a terminal exception,
8144 * so we will either take the HardFault immediately or else enter
8145 * lockup (the latter case is handled in armv7m_nvic_set_pending_derived()).
8147 exc_secure
= targets_secure
||
8148 !(cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
);
8149 env
->v7m
.hfsr
|= R_V7M_HFSR_VECTTBL_MASK
| R_V7M_HFSR_FORCED_MASK
;
8150 armv7m_nvic_set_pending_derived(env
->nvic
, ARMV7M_EXCP_HARD
, exc_secure
);
8154 static uint32_t v7m_integrity_sig(CPUARMState
*env
, uint32_t lr
)
8157 * Return the integrity signature value for the callee-saves
8158 * stack frame section. @lr is the exception return payload/LR value
8159 * whose FType bit forms bit 0 of the signature if FP is present.
8161 uint32_t sig
= 0xfefa125a;
8163 if (!arm_feature(env
, ARM_FEATURE_VFP
) || (lr
& R_V7M_EXCRET_FTYPE_MASK
)) {
8169 static bool v7m_push_callee_stack(ARMCPU
*cpu
, uint32_t lr
, bool dotailchain
,
8172 /* For v8M, push the callee-saves register part of the stack frame.
8173 * Compare the v8M pseudocode PushCalleeStack().
8174 * In the tailchaining case this may not be the current stack.
8176 CPUARMState
*env
= &cpu
->env
;
8177 uint32_t *frame_sp_p
;
8184 StackingMode smode
= ignore_faults
? STACK_IGNFAULTS
: STACK_NORMAL
;
8187 bool mode
= lr
& R_V7M_EXCRET_MODE_MASK
;
8188 bool priv
= !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_NPRIV_MASK
) ||
8191 mmu_idx
= arm_v7m_mmu_idx_for_secstate_and_priv(env
, M_REG_S
, priv
);
8192 frame_sp_p
= get_v7m_sp_ptr(env
, M_REG_S
, mode
,
8193 lr
& R_V7M_EXCRET_SPSEL_MASK
);
8194 want_psp
= mode
&& (lr
& R_V7M_EXCRET_SPSEL_MASK
);
8196 limit
= env
->v7m
.psplim
[M_REG_S
];
8198 limit
= env
->v7m
.msplim
[M_REG_S
];
8201 mmu_idx
= arm_mmu_idx(env
);
8202 frame_sp_p
= &env
->regs
[13];
8203 limit
= v7m_sp_limit(env
);
8206 frameptr
= *frame_sp_p
- 0x28;
8207 if (frameptr
< limit
) {
8209 * Stack limit failure: set SP to the limit value, and generate
8210 * STKOF UsageFault. Stack pushes below the limit must not be
8211 * performed. It is IMPDEF whether pushes above the limit are
8212 * performed; we choose not to.
8214 qemu_log_mask(CPU_LOG_INT
,
8215 "...STKOF during callee-saves register stacking\n");
8216 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_STKOF_MASK
;
8217 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
8219 *frame_sp_p
= limit
;
8223 /* Write as much of the stack frame as we can. A write failure may
8224 * cause us to pend a derived exception.
8226 sig
= v7m_integrity_sig(env
, lr
);
8228 v7m_stack_write(cpu
, frameptr
, sig
, mmu_idx
, smode
) &&
8229 v7m_stack_write(cpu
, frameptr
+ 0x8, env
->regs
[4], mmu_idx
, smode
) &&
8230 v7m_stack_write(cpu
, frameptr
+ 0xc, env
->regs
[5], mmu_idx
, smode
) &&
8231 v7m_stack_write(cpu
, frameptr
+ 0x10, env
->regs
[6], mmu_idx
, smode
) &&
8232 v7m_stack_write(cpu
, frameptr
+ 0x14, env
->regs
[7], mmu_idx
, smode
) &&
8233 v7m_stack_write(cpu
, frameptr
+ 0x18, env
->regs
[8], mmu_idx
, smode
) &&
8234 v7m_stack_write(cpu
, frameptr
+ 0x1c, env
->regs
[9], mmu_idx
, smode
) &&
8235 v7m_stack_write(cpu
, frameptr
+ 0x20, env
->regs
[10], mmu_idx
, smode
) &&
8236 v7m_stack_write(cpu
, frameptr
+ 0x24, env
->regs
[11], mmu_idx
, smode
);
8238 /* Update SP regardless of whether any of the stack accesses failed. */
8239 *frame_sp_p
= frameptr
;
8244 static void v7m_exception_taken(ARMCPU
*cpu
, uint32_t lr
, bool dotailchain
,
8245 bool ignore_stackfaults
)
8247 /* Do the "take the exception" parts of exception entry,
8248 * but not the pushing of state to the stack. This is
8249 * similar to the pseudocode ExceptionTaken() function.
8251 CPUARMState
*env
= &cpu
->env
;
8253 bool targets_secure
;
8255 bool push_failed
= false;
8257 armv7m_nvic_get_pending_irq_info(env
->nvic
, &exc
, &targets_secure
);
8258 qemu_log_mask(CPU_LOG_INT
, "...taking pending %s exception %d\n",
8259 targets_secure
? "secure" : "nonsecure", exc
);
8262 /* Sanitize LR FType and PREFIX bits */
8263 if (!arm_feature(env
, ARM_FEATURE_VFP
)) {
8264 lr
|= R_V7M_EXCRET_FTYPE_MASK
;
8266 lr
= deposit32(lr
, 24, 8, 0xff);
8269 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8270 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
8271 (lr
& R_V7M_EXCRET_S_MASK
)) {
8272 /* The background code (the owner of the registers in the
8273 * exception frame) is Secure. This means it may either already
8274 * have or now needs to push callee-saves registers.
8276 if (targets_secure
) {
8277 if (dotailchain
&& !(lr
& R_V7M_EXCRET_ES_MASK
)) {
8278 /* We took an exception from Secure to NonSecure
8279 * (which means the callee-saved registers got stacked)
8280 * and are now tailchaining to a Secure exception.
8281 * Clear DCRS so eventual return from this Secure
8282 * exception unstacks the callee-saved registers.
8284 lr
&= ~R_V7M_EXCRET_DCRS_MASK
;
8287 /* We're going to a non-secure exception; push the
8288 * callee-saves registers to the stack now, if they're
8289 * not already saved.
8291 if (lr
& R_V7M_EXCRET_DCRS_MASK
&&
8292 !(dotailchain
&& !(lr
& R_V7M_EXCRET_ES_MASK
))) {
8293 push_failed
= v7m_push_callee_stack(cpu
, lr
, dotailchain
,
8294 ignore_stackfaults
);
8296 lr
|= R_V7M_EXCRET_DCRS_MASK
;
8300 lr
&= ~R_V7M_EXCRET_ES_MASK
;
8301 if (targets_secure
|| !arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
8302 lr
|= R_V7M_EXCRET_ES_MASK
;
8304 lr
&= ~R_V7M_EXCRET_SPSEL_MASK
;
8305 if (env
->v7m
.control
[targets_secure
] & R_V7M_CONTROL_SPSEL_MASK
) {
8306 lr
|= R_V7M_EXCRET_SPSEL_MASK
;
8309 /* Clear registers if necessary to prevent non-secure exception
8310 * code being able to see register values from secure code.
8311 * Where register values become architecturally UNKNOWN we leave
8312 * them with their previous values.
8314 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
8315 if (!targets_secure
) {
8316 /* Always clear the caller-saved registers (they have been
8317 * pushed to the stack earlier in v7m_push_stack()).
8318 * Clear callee-saved registers if the background code is
8319 * Secure (in which case these regs were saved in
8320 * v7m_push_callee_stack()).
8324 for (i
= 0; i
< 13; i
++) {
8325 /* r4..r11 are callee-saves, zero only if EXCRET.S == 1 */
8326 if (i
< 4 || i
> 11 || (lr
& R_V7M_EXCRET_S_MASK
)) {
8331 xpsr_write(env
, 0, XPSR_NZCV
| XPSR_Q
| XPSR_GE
| XPSR_IT
);
8336 if (push_failed
&& !ignore_stackfaults
) {
8337 /* Derived exception on callee-saves register stacking:
8338 * we might now want to take a different exception which
8339 * targets a different security state, so try again from the top.
8341 qemu_log_mask(CPU_LOG_INT
,
8342 "...derived exception on callee-saves register stacking");
8343 v7m_exception_taken(cpu
, lr
, true, true);
8347 if (!arm_v7m_load_vector(cpu
, exc
, targets_secure
, &addr
)) {
8348 /* Vector load failed: derived exception */
8349 qemu_log_mask(CPU_LOG_INT
, "...derived exception on vector table load");
8350 v7m_exception_taken(cpu
, lr
, true, true);
8354 /* Now we've done everything that might cause a derived exception
8355 * we can go ahead and activate whichever exception we're going to
8356 * take (which might now be the derived exception).
8358 armv7m_nvic_acknowledge_irq(env
->nvic
);
8360 /* Switch to target security state -- must do this before writing SPSEL */
8361 switch_v7m_security_state(env
, targets_secure
);
8362 write_v7m_control_spsel(env
, 0);
8363 arm_clear_exclusive(env
);
8364 /* Clear SFPA and FPCA (has no effect if no FPU) */
8365 env
->v7m
.control
[M_REG_S
] &=
8366 ~(R_V7M_CONTROL_FPCA_MASK
| R_V7M_CONTROL_SFPA_MASK
);
8368 env
->condexec_bits
= 0;
8370 env
->regs
[15] = addr
& 0xfffffffe;
8371 env
->thumb
= addr
& 1;
8374 static void v7m_update_fpccr(CPUARMState
*env
, uint32_t frameptr
,
8378 * Like the pseudocode UpdateFPCCR: save state in FPCAR and FPCCR
8379 * that we will need later in order to do lazy FP reg stacking.
8381 bool is_secure
= env
->v7m
.secure
;
8382 void *nvic
= env
->nvic
;
8384 * Some bits are unbanked and live always in fpccr[M_REG_S]; some bits
8385 * are banked and we want to update the bit in the bank for the
8386 * current security state; and in one case we want to specifically
8387 * update the NS banked version of a bit even if we are secure.
8389 uint32_t *fpccr_s
= &env
->v7m
.fpccr
[M_REG_S
];
8390 uint32_t *fpccr_ns
= &env
->v7m
.fpccr
[M_REG_NS
];
8391 uint32_t *fpccr
= &env
->v7m
.fpccr
[is_secure
];
8392 bool hfrdy
, bfrdy
, mmrdy
, ns_ufrdy
, s_ufrdy
, sfrdy
, monrdy
;
8394 env
->v7m
.fpcar
[is_secure
] = frameptr
& ~0x7;
8396 if (apply_splim
&& arm_feature(env
, ARM_FEATURE_V8
)) {
8398 uint32_t splim
= v7m_sp_limit(env
);
8399 bool ign
= armv7m_nvic_neg_prio_requested(nvic
, is_secure
) &&
8400 (env
->v7m
.ccr
[is_secure
] & R_V7M_CCR_STKOFHFNMIGN_MASK
);
8402 splimviol
= !ign
&& frameptr
< splim
;
8403 *fpccr
= FIELD_DP32(*fpccr
, V7M_FPCCR
, SPLIMVIOL
, splimviol
);
8406 *fpccr
= FIELD_DP32(*fpccr
, V7M_FPCCR
, LSPACT
, 1);
8408 *fpccr_s
= FIELD_DP32(*fpccr_s
, V7M_FPCCR
, S
, is_secure
);
8410 *fpccr
= FIELD_DP32(*fpccr
, V7M_FPCCR
, USER
, arm_current_el(env
) == 0);
8412 *fpccr
= FIELD_DP32(*fpccr
, V7M_FPCCR
, THREAD
,
8413 !arm_v7m_is_handler_mode(env
));
8415 hfrdy
= armv7m_nvic_get_ready_status(nvic
, ARMV7M_EXCP_HARD
, false);
8416 *fpccr_s
= FIELD_DP32(*fpccr_s
, V7M_FPCCR
, HFRDY
, hfrdy
);
8418 bfrdy
= armv7m_nvic_get_ready_status(nvic
, ARMV7M_EXCP_BUS
, false);
8419 *fpccr_s
= FIELD_DP32(*fpccr_s
, V7M_FPCCR
, BFRDY
, bfrdy
);
8421 mmrdy
= armv7m_nvic_get_ready_status(nvic
, ARMV7M_EXCP_MEM
, is_secure
);
8422 *fpccr
= FIELD_DP32(*fpccr
, V7M_FPCCR
, MMRDY
, mmrdy
);
8424 ns_ufrdy
= armv7m_nvic_get_ready_status(nvic
, ARMV7M_EXCP_USAGE
, false);
8425 *fpccr_ns
= FIELD_DP32(*fpccr_ns
, V7M_FPCCR
, UFRDY
, ns_ufrdy
);
8427 monrdy
= armv7m_nvic_get_ready_status(nvic
, ARMV7M_EXCP_DEBUG
, false);
8428 *fpccr_s
= FIELD_DP32(*fpccr_s
, V7M_FPCCR
, MONRDY
, monrdy
);
8430 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
8431 s_ufrdy
= armv7m_nvic_get_ready_status(nvic
, ARMV7M_EXCP_USAGE
, true);
8432 *fpccr_s
= FIELD_DP32(*fpccr_s
, V7M_FPCCR
, UFRDY
, s_ufrdy
);
8434 sfrdy
= armv7m_nvic_get_ready_status(nvic
, ARMV7M_EXCP_SECURE
, false);
8435 *fpccr_s
= FIELD_DP32(*fpccr_s
, V7M_FPCCR
, SFRDY
, sfrdy
);
8439 void HELPER(v7m_vlstm
)(CPUARMState
*env
, uint32_t fptr
)
8441 /* fptr is the value of Rn, the frame pointer we store the FP regs to */
8442 bool s
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
8443 bool lspact
= env
->v7m
.fpccr
[s
] & R_V7M_FPCCR_LSPACT_MASK
;
8445 assert(env
->v7m
.secure
);
8447 if (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)) {
8451 /* Check access to the coprocessor is permitted */
8452 if (!v7m_cpacr_pass(env
, true, arm_current_el(env
) != 0)) {
8453 raise_exception_ra(env
, EXCP_NOCP
, 0, 1, GETPC());
8457 /* LSPACT should not be active when there is active FP state */
8458 raise_exception_ra(env
, EXCP_LSERR
, 0, 1, GETPC());
8462 raise_exception_ra(env
, EXCP_UNALIGNED
, 0, 1, GETPC());
8466 * Note that we do not use v7m_stack_write() here, because the
8467 * accesses should not set the FSR bits for stacking errors if they
8468 * fail. (In pseudocode terms, they are AccType_NORMAL, not AccType_STACK
8469 * or AccType_LAZYFP). Faults in cpu_stl_data() will throw exceptions
8472 if (!(env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_LSPEN_MASK
)) {
8473 bool ts
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_TS_MASK
;
8476 for (i
= 0; i
< (ts
? 32 : 16); i
+= 2) {
8477 uint64_t dn
= *aa32_vfp_dreg(env
, i
/ 2);
8478 uint32_t faddr
= fptr
+ 4 * i
;
8479 uint32_t slo
= extract64(dn
, 0, 32);
8480 uint32_t shi
= extract64(dn
, 32, 32);
8483 faddr
+= 8; /* skip the slot for the FPSCR */
8485 cpu_stl_data(env
, faddr
, slo
);
8486 cpu_stl_data(env
, faddr
+ 4, shi
);
8488 cpu_stl_data(env
, fptr
+ 0x40, vfp_get_fpscr(env
));
8491 * If TS is 0 then s0 to s15 and FPSCR are UNKNOWN; we choose to
8492 * leave them unchanged, matching our choice in v7m_preserve_fp_state.
8495 for (i
= 0; i
< 32; i
+= 2) {
8496 *aa32_vfp_dreg(env
, i
/ 2) = 0;
8498 vfp_set_fpscr(env
, 0);
8501 v7m_update_fpccr(env
, fptr
, false);
8504 env
->v7m
.control
[M_REG_S
] &= ~R_V7M_CONTROL_FPCA_MASK
;
8507 void HELPER(v7m_vlldm
)(CPUARMState
*env
, uint32_t fptr
)
8509 /* fptr is the value of Rn, the frame pointer we load the FP regs from */
8510 assert(env
->v7m
.secure
);
8512 if (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)) {
8516 /* Check access to the coprocessor is permitted */
8517 if (!v7m_cpacr_pass(env
, true, arm_current_el(env
) != 0)) {
8518 raise_exception_ra(env
, EXCP_NOCP
, 0, 1, GETPC());
8521 if (env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_LSPACT_MASK
) {
8522 /* State in FP is still valid */
8523 env
->v7m
.fpccr
[M_REG_S
] &= ~R_V7M_FPCCR_LSPACT_MASK
;
8525 bool ts
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_TS_MASK
;
8530 raise_exception_ra(env
, EXCP_UNALIGNED
, 0, 1, GETPC());
8533 for (i
= 0; i
< (ts
? 32 : 16); i
+= 2) {
8536 uint32_t faddr
= fptr
+ 4 * i
;
8539 faddr
+= 8; /* skip the slot for the FPSCR */
8542 slo
= cpu_ldl_data(env
, faddr
);
8543 shi
= cpu_ldl_data(env
, faddr
+ 4);
8545 dn
= (uint64_t) shi
<< 32 | slo
;
8546 *aa32_vfp_dreg(env
, i
/ 2) = dn
;
8548 fpscr
= cpu_ldl_data(env
, fptr
+ 0x40);
8549 vfp_set_fpscr(env
, fpscr
);
8552 env
->v7m
.control
[M_REG_S
] |= R_V7M_CONTROL_FPCA_MASK
;
8555 static bool v7m_push_stack(ARMCPU
*cpu
)
8557 /* Do the "set up stack frame" part of exception entry,
8558 * similar to pseudocode PushStack().
8559 * Return true if we generate a derived exception (and so
8560 * should ignore further stack faults trying to process
8561 * that derived exception.)
8563 bool stacked_ok
= true, limitviol
= false;
8564 CPUARMState
*env
= &cpu
->env
;
8565 uint32_t xpsr
= xpsr_read(env
);
8566 uint32_t frameptr
= env
->regs
[13];
8567 ARMMMUIdx mmu_idx
= arm_mmu_idx(env
);
8569 bool nsacr_cp10
= extract32(env
->v7m
.nsacr
, 10, 1);
8571 if ((env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) &&
8572 (env
->v7m
.secure
|| nsacr_cp10
)) {
8573 if (env
->v7m
.secure
&&
8574 env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_TS_MASK
) {
8583 /* Align stack pointer if the guest wants that */
8584 if ((frameptr
& 4) &&
8585 (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_STKALIGN_MASK
)) {
8587 xpsr
|= XPSR_SPREALIGN
;
8591 if (env
->v7m
.secure
&&
8592 (env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)) {
8596 frameptr
-= framesize
;
8598 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8599 uint32_t limit
= v7m_sp_limit(env
);
8601 if (frameptr
< limit
) {
8603 * Stack limit failure: set SP to the limit value, and generate
8604 * STKOF UsageFault. Stack pushes below the limit must not be
8605 * performed. It is IMPDEF whether pushes above the limit are
8606 * performed; we choose not to.
8608 qemu_log_mask(CPU_LOG_INT
,
8609 "...STKOF during stacking\n");
8610 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_STKOF_MASK
;
8611 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
8613 env
->regs
[13] = limit
;
8615 * We won't try to perform any further memory accesses but
8616 * we must continue through the following code to check for
8617 * permission faults during FPU state preservation, and we
8618 * must update FPCCR if lazy stacking is enabled.
8625 /* Write as much of the stack frame as we can. If we fail a stack
8626 * write this will result in a derived exception being pended
8627 * (which may be taken in preference to the one we started with
8628 * if it has higher priority).
8630 stacked_ok
= stacked_ok
&&
8631 v7m_stack_write(cpu
, frameptr
, env
->regs
[0], mmu_idx
, STACK_NORMAL
) &&
8632 v7m_stack_write(cpu
, frameptr
+ 4, env
->regs
[1],
8633 mmu_idx
, STACK_NORMAL
) &&
8634 v7m_stack_write(cpu
, frameptr
+ 8, env
->regs
[2],
8635 mmu_idx
, STACK_NORMAL
) &&
8636 v7m_stack_write(cpu
, frameptr
+ 12, env
->regs
[3],
8637 mmu_idx
, STACK_NORMAL
) &&
8638 v7m_stack_write(cpu
, frameptr
+ 16, env
->regs
[12],
8639 mmu_idx
, STACK_NORMAL
) &&
8640 v7m_stack_write(cpu
, frameptr
+ 20, env
->regs
[14],
8641 mmu_idx
, STACK_NORMAL
) &&
8642 v7m_stack_write(cpu
, frameptr
+ 24, env
->regs
[15],
8643 mmu_idx
, STACK_NORMAL
) &&
8644 v7m_stack_write(cpu
, frameptr
+ 28, xpsr
, mmu_idx
, STACK_NORMAL
);
8646 if (env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) {
8647 /* FPU is active, try to save its registers */
8648 bool fpccr_s
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
8649 bool lspact
= env
->v7m
.fpccr
[fpccr_s
] & R_V7M_FPCCR_LSPACT_MASK
;
8651 if (lspact
&& arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
8652 qemu_log_mask(CPU_LOG_INT
,
8653 "...SecureFault because LSPACT and FPCA both set\n");
8654 env
->v7m
.sfsr
|= R_V7M_SFSR_LSERR_MASK
;
8655 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
8656 } else if (!env
->v7m
.secure
&& !nsacr_cp10
) {
8657 qemu_log_mask(CPU_LOG_INT
,
8658 "...Secure UsageFault with CFSR.NOCP because "
8659 "NSACR.CP10 prevents stacking FP regs\n");
8660 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, M_REG_S
);
8661 env
->v7m
.cfsr
[M_REG_S
] |= R_V7M_CFSR_NOCP_MASK
;
8663 if (!(env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_LSPEN_MASK
)) {
8664 /* Lazy stacking disabled, save registers now */
8666 bool cpacr_pass
= v7m_cpacr_pass(env
, env
->v7m
.secure
,
8667 arm_current_el(env
) != 0);
8669 if (stacked_ok
&& !cpacr_pass
) {
8671 * Take UsageFault if CPACR forbids access. The pseudocode
8672 * here does a full CheckCPEnabled() but we know the NSACR
8673 * check can never fail as we have already handled that.
8675 qemu_log_mask(CPU_LOG_INT
,
8676 "...UsageFault with CFSR.NOCP because "
8677 "CPACR.CP10 prevents stacking FP regs\n");
8678 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
8680 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_NOCP_MASK
;
8684 for (i
= 0; i
< ((framesize
== 0xa8) ? 32 : 16); i
+= 2) {
8685 uint64_t dn
= *aa32_vfp_dreg(env
, i
/ 2);
8686 uint32_t faddr
= frameptr
+ 0x20 + 4 * i
;
8687 uint32_t slo
= extract64(dn
, 0, 32);
8688 uint32_t shi
= extract64(dn
, 32, 32);
8691 faddr
+= 8; /* skip the slot for the FPSCR */
8693 stacked_ok
= stacked_ok
&&
8694 v7m_stack_write(cpu
, faddr
, slo
,
8695 mmu_idx
, STACK_NORMAL
) &&
8696 v7m_stack_write(cpu
, faddr
+ 4, shi
,
8697 mmu_idx
, STACK_NORMAL
);
8699 stacked_ok
= stacked_ok
&&
8700 v7m_stack_write(cpu
, frameptr
+ 0x60,
8701 vfp_get_fpscr(env
), mmu_idx
, STACK_NORMAL
);
8703 for (i
= 0; i
< ((framesize
== 0xa8) ? 32 : 16); i
+= 2) {
8704 *aa32_vfp_dreg(env
, i
/ 2) = 0;
8706 vfp_set_fpscr(env
, 0);
8709 /* Lazy stacking enabled, save necessary info to stack later */
8710 v7m_update_fpccr(env
, frameptr
+ 0x20, true);
8716 * If we broke a stack limit then SP was already updated earlier;
8717 * otherwise we update SP regardless of whether any of the stack
8718 * accesses failed or we took some other kind of fault.
8721 env
->regs
[13] = frameptr
;
8727 static void do_v7m_exception_exit(ARMCPU
*cpu
)
8729 CPUARMState
*env
= &cpu
->env
;
8731 uint32_t xpsr
, xpsr_mask
;
8732 bool ufault
= false;
8733 bool sfault
= false;
8734 bool return_to_sp_process
;
8735 bool return_to_handler
;
8736 bool rettobase
= false;
8737 bool exc_secure
= false;
8738 bool return_to_secure
;
8740 bool restore_s16_s31
;
8742 /* If we're not in Handler mode then jumps to magic exception-exit
8743 * addresses don't have magic behaviour. However for the v8M
8744 * security extensions the magic secure-function-return has to
8745 * work in thread mode too, so to avoid doing an extra check in
8746 * the generated code we allow exception-exit magic to also cause the
8747 * internal exception and bring us here in thread mode. Correct code
8748 * will never try to do this (the following insn fetch will always
8749 * fault) so we the overhead of having taken an unnecessary exception
8752 if (!arm_v7m_is_handler_mode(env
)) {
8756 /* In the spec pseudocode ExceptionReturn() is called directly
8757 * from BXWritePC() and gets the full target PC value including
8758 * bit zero. In QEMU's implementation we treat it as a normal
8759 * jump-to-register (which is then caught later on), and so split
8760 * the target value up between env->regs[15] and env->thumb in
8761 * gen_bx(). Reconstitute it.
8763 excret
= env
->regs
[15];
8768 qemu_log_mask(CPU_LOG_INT
, "Exception return: magic PC %" PRIx32
8769 " previous exception %d\n",
8770 excret
, env
->v7m
.exception
);
8772 if ((excret
& R_V7M_EXCRET_RES1_MASK
) != R_V7M_EXCRET_RES1_MASK
) {
8773 qemu_log_mask(LOG_GUEST_ERROR
, "M profile: zero high bits in exception "
8774 "exit PC value 0x%" PRIx32
" are UNPREDICTABLE\n",
8778 ftype
= excret
& R_V7M_EXCRET_FTYPE_MASK
;
8780 if (!arm_feature(env
, ARM_FEATURE_VFP
) && !ftype
) {
8781 qemu_log_mask(LOG_GUEST_ERROR
, "M profile: zero FTYPE in exception "
8782 "exit PC value 0x%" PRIx32
" is UNPREDICTABLE "
8783 "if FPU not present\n",
8788 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
8789 /* EXC_RETURN.ES validation check (R_SMFL). We must do this before
8790 * we pick which FAULTMASK to clear.
8792 if (!env
->v7m
.secure
&&
8793 ((excret
& R_V7M_EXCRET_ES_MASK
) ||
8794 !(excret
& R_V7M_EXCRET_DCRS_MASK
))) {
8796 /* For all other purposes, treat ES as 0 (R_HXSR) */
8797 excret
&= ~R_V7M_EXCRET_ES_MASK
;
8799 exc_secure
= excret
& R_V7M_EXCRET_ES_MASK
;
8802 if (env
->v7m
.exception
!= ARMV7M_EXCP_NMI
) {
8803 /* Auto-clear FAULTMASK on return from other than NMI.
8804 * If the security extension is implemented then this only
8805 * happens if the raw execution priority is >= 0; the
8806 * value of the ES bit in the exception return value indicates
8807 * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.)
8809 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
8810 if (armv7m_nvic_raw_execution_priority(env
->nvic
) >= 0) {
8811 env
->v7m
.faultmask
[exc_secure
] = 0;
8814 env
->v7m
.faultmask
[M_REG_NS
] = 0;
8818 switch (armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
,
8821 /* attempt to exit an exception that isn't active */
8825 /* still an irq active now */
8828 /* we returned to base exception level, no nesting.
8829 * (In the pseudocode this is written using "NestedActivation != 1"
8830 * where we have 'rettobase == false'.)
8835 g_assert_not_reached();
8838 return_to_handler
= !(excret
& R_V7M_EXCRET_MODE_MASK
);
8839 return_to_sp_process
= excret
& R_V7M_EXCRET_SPSEL_MASK
;
8840 return_to_secure
= arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
8841 (excret
& R_V7M_EXCRET_S_MASK
);
8843 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8844 if (!arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
8845 /* UNPREDICTABLE if S == 1 or DCRS == 0 or ES == 1 (R_XLCP);
8846 * we choose to take the UsageFault.
8848 if ((excret
& R_V7M_EXCRET_S_MASK
) ||
8849 (excret
& R_V7M_EXCRET_ES_MASK
) ||
8850 !(excret
& R_V7M_EXCRET_DCRS_MASK
)) {
8854 if (excret
& R_V7M_EXCRET_RES0_MASK
) {
8858 /* For v7M we only recognize certain combinations of the low bits */
8859 switch (excret
& 0xf) {
8860 case 1: /* Return to Handler */
8862 case 13: /* Return to Thread using Process stack */
8863 case 9: /* Return to Thread using Main stack */
8864 /* We only need to check NONBASETHRDENA for v7M, because in
8865 * v8M this bit does not exist (it is RES1).
8868 !(env
->v7m
.ccr
[env
->v7m
.secure
] &
8869 R_V7M_CCR_NONBASETHRDENA_MASK
)) {
8879 * Set CONTROL.SPSEL from excret.SPSEL. Since we're still in
8880 * Handler mode (and will be until we write the new XPSR.Interrupt
8881 * field) this does not switch around the current stack pointer.
8882 * We must do this before we do any kind of tailchaining, including
8883 * for the derived exceptions on integrity check failures, or we will
8884 * give the guest an incorrect EXCRET.SPSEL value on exception entry.
8886 write_v7m_control_spsel_for_secstate(env
, return_to_sp_process
, exc_secure
);
8889 * Clear scratch FP values left in caller saved registers; this
8890 * must happen before any kind of tail chaining.
8892 if ((env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_CLRONRET_MASK
) &&
8893 (env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
)) {
8894 if (env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_LSPACT_MASK
) {
8895 env
->v7m
.sfsr
|= R_V7M_SFSR_LSERR_MASK
;
8896 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
8897 qemu_log_mask(CPU_LOG_INT
, "...taking SecureFault on existing "
8898 "stackframe: error during lazy state deactivation\n");
8899 v7m_exception_taken(cpu
, excret
, true, false);
8902 /* Clear s0..s15 and FPSCR */
8905 for (i
= 0; i
< 16; i
+= 2) {
8906 *aa32_vfp_dreg(env
, i
/ 2) = 0;
8908 vfp_set_fpscr(env
, 0);
8913 env
->v7m
.sfsr
|= R_V7M_SFSR_INVER_MASK
;
8914 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
8915 qemu_log_mask(CPU_LOG_INT
, "...taking SecureFault on existing "
8916 "stackframe: failed EXC_RETURN.ES validity check\n");
8917 v7m_exception_taken(cpu
, excret
, true, false);
8922 /* Bad exception return: instead of popping the exception
8923 * stack, directly take a usage fault on the current stack.
8925 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
8926 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
8927 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on existing "
8928 "stackframe: failed exception return integrity check\n");
8929 v7m_exception_taken(cpu
, excret
, true, false);
8934 * Tailchaining: if there is currently a pending exception that
8935 * is high enough priority to preempt execution at the level we're
8936 * about to return to, then just directly take that exception now,
8937 * avoiding an unstack-and-then-stack. Note that now we have
8938 * deactivated the previous exception by calling armv7m_nvic_complete_irq()
8939 * our current execution priority is already the execution priority we are
8940 * returning to -- none of the state we would unstack or set based on
8941 * the EXCRET value affects it.
8943 if (armv7m_nvic_can_take_pending_exception(env
->nvic
)) {
8944 qemu_log_mask(CPU_LOG_INT
, "...tailchaining to pending exception\n");
8945 v7m_exception_taken(cpu
, excret
, true, false);
8949 switch_v7m_security_state(env
, return_to_secure
);
8952 /* The stack pointer we should be reading the exception frame from
8953 * depends on bits in the magic exception return type value (and
8954 * for v8M isn't necessarily the stack pointer we will eventually
8955 * end up resuming execution with). Get a pointer to the location
8956 * in the CPU state struct where the SP we need is currently being
8957 * stored; we will use and modify it in place.
8958 * We use this limited C variable scope so we don't accidentally
8959 * use 'frame_sp_p' after we do something that makes it invalid.
8961 uint32_t *frame_sp_p
= get_v7m_sp_ptr(env
,
8964 return_to_sp_process
);
8965 uint32_t frameptr
= *frame_sp_p
;
8968 bool return_to_priv
= return_to_handler
||
8969 !(env
->v7m
.control
[return_to_secure
] & R_V7M_CONTROL_NPRIV_MASK
);
8971 mmu_idx
= arm_v7m_mmu_idx_for_secstate_and_priv(env
, return_to_secure
,
8974 if (!QEMU_IS_ALIGNED(frameptr
, 8) &&
8975 arm_feature(env
, ARM_FEATURE_V8
)) {
8976 qemu_log_mask(LOG_GUEST_ERROR
,
8977 "M profile exception return with non-8-aligned SP "
8978 "for destination state is UNPREDICTABLE\n");
8981 /* Do we need to pop callee-saved registers? */
8982 if (return_to_secure
&&
8983 ((excret
& R_V7M_EXCRET_ES_MASK
) == 0 ||
8984 (excret
& R_V7M_EXCRET_DCRS_MASK
) == 0)) {
8985 uint32_t actual_sig
;
8987 pop_ok
= v7m_stack_read(cpu
, &actual_sig
, frameptr
, mmu_idx
);
8989 if (pop_ok
&& v7m_integrity_sig(env
, excret
) != actual_sig
) {
8990 /* Take a SecureFault on the current stack */
8991 env
->v7m
.sfsr
|= R_V7M_SFSR_INVIS_MASK
;
8992 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
8993 qemu_log_mask(CPU_LOG_INT
, "...taking SecureFault on existing "
8994 "stackframe: failed exception return integrity "
8995 "signature check\n");
8996 v7m_exception_taken(cpu
, excret
, true, false);
9001 v7m_stack_read(cpu
, &env
->regs
[4], frameptr
+ 0x8, mmu_idx
) &&
9002 v7m_stack_read(cpu
, &env
->regs
[5], frameptr
+ 0xc, mmu_idx
) &&
9003 v7m_stack_read(cpu
, &env
->regs
[6], frameptr
+ 0x10, mmu_idx
) &&
9004 v7m_stack_read(cpu
, &env
->regs
[7], frameptr
+ 0x14, mmu_idx
) &&
9005 v7m_stack_read(cpu
, &env
->regs
[8], frameptr
+ 0x18, mmu_idx
) &&
9006 v7m_stack_read(cpu
, &env
->regs
[9], frameptr
+ 0x1c, mmu_idx
) &&
9007 v7m_stack_read(cpu
, &env
->regs
[10], frameptr
+ 0x20, mmu_idx
) &&
9008 v7m_stack_read(cpu
, &env
->regs
[11], frameptr
+ 0x24, mmu_idx
);
9015 v7m_stack_read(cpu
, &env
->regs
[0], frameptr
, mmu_idx
) &&
9016 v7m_stack_read(cpu
, &env
->regs
[1], frameptr
+ 0x4, mmu_idx
) &&
9017 v7m_stack_read(cpu
, &env
->regs
[2], frameptr
+ 0x8, mmu_idx
) &&
9018 v7m_stack_read(cpu
, &env
->regs
[3], frameptr
+ 0xc, mmu_idx
) &&
9019 v7m_stack_read(cpu
, &env
->regs
[12], frameptr
+ 0x10, mmu_idx
) &&
9020 v7m_stack_read(cpu
, &env
->regs
[14], frameptr
+ 0x14, mmu_idx
) &&
9021 v7m_stack_read(cpu
, &env
->regs
[15], frameptr
+ 0x18, mmu_idx
) &&
9022 v7m_stack_read(cpu
, &xpsr
, frameptr
+ 0x1c, mmu_idx
);
9025 /* v7m_stack_read() pended a fault, so take it (as a tail
9026 * chained exception on the same stack frame)
9028 qemu_log_mask(CPU_LOG_INT
, "...derived exception on unstacking\n");
9029 v7m_exception_taken(cpu
, excret
, true, false);
9033 /* Returning from an exception with a PC with bit 0 set is defined
9034 * behaviour on v8M (bit 0 is ignored), but for v7M it was specified
9035 * to be UNPREDICTABLE. In practice actual v7M hardware seems to ignore
9036 * the lsbit, and there are several RTOSes out there which incorrectly
9037 * assume the r15 in the stack frame should be a Thumb-style "lsbit
9038 * indicates ARM/Thumb" value, so ignore the bit on v7M as well, but
9039 * complain about the badly behaved guest.
9041 if (env
->regs
[15] & 1) {
9042 env
->regs
[15] &= ~1U;
9043 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
9044 qemu_log_mask(LOG_GUEST_ERROR
,
9045 "M profile return from interrupt with misaligned "
9046 "PC is UNPREDICTABLE on v7M\n");
9050 if (arm_feature(env
, ARM_FEATURE_V8
)) {
9051 /* For v8M we have to check whether the xPSR exception field
9052 * matches the EXCRET value for return to handler/thread
9053 * before we commit to changing the SP and xPSR.
9055 bool will_be_handler
= (xpsr
& XPSR_EXCP
) != 0;
9056 if (return_to_handler
!= will_be_handler
) {
9057 /* Take an INVPC UsageFault on the current stack.
9058 * By this point we will have switched to the security state
9059 * for the background state, so this UsageFault will target
9062 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
9064 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
9065 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on existing "
9066 "stackframe: failed exception return integrity "
9068 v7m_exception_taken(cpu
, excret
, true, false);
9074 /* FP present and we need to handle it */
9075 if (!return_to_secure
&&
9076 (env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_LSPACT_MASK
)) {
9077 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
9078 env
->v7m
.sfsr
|= R_V7M_SFSR_LSERR_MASK
;
9079 qemu_log_mask(CPU_LOG_INT
,
9080 "...taking SecureFault on existing stackframe: "
9081 "Secure LSPACT set but exception return is "
9082 "not to secure state\n");
9083 v7m_exception_taken(cpu
, excret
, true, false);
9087 restore_s16_s31
= return_to_secure
&&
9088 (env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_TS_MASK
);
9090 if (env
->v7m
.fpccr
[return_to_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
9091 /* State in FPU is still valid, just clear LSPACT */
9092 env
->v7m
.fpccr
[return_to_secure
] &= ~R_V7M_FPCCR_LSPACT_MASK
;
9096 bool cpacr_pass
, nsacr_pass
;
9098 cpacr_pass
= v7m_cpacr_pass(env
, return_to_secure
,
9100 nsacr_pass
= return_to_secure
||
9101 extract32(env
->v7m
.nsacr
, 10, 1);
9104 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
9106 env
->v7m
.cfsr
[return_to_secure
] |= R_V7M_CFSR_NOCP_MASK
;
9107 qemu_log_mask(CPU_LOG_INT
,
9108 "...taking UsageFault on existing "
9109 "stackframe: CPACR.CP10 prevents unstacking "
9111 v7m_exception_taken(cpu
, excret
, true, false);
9113 } else if (!nsacr_pass
) {
9114 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, true);
9115 env
->v7m
.cfsr
[M_REG_S
] |= R_V7M_CFSR_INVPC_MASK
;
9116 qemu_log_mask(CPU_LOG_INT
,
9117 "...taking Secure UsageFault on existing "
9118 "stackframe: NSACR.CP10 prevents unstacking "
9120 v7m_exception_taken(cpu
, excret
, true, false);
9124 for (i
= 0; i
< (restore_s16_s31
? 32 : 16); i
+= 2) {
9127 uint32_t faddr
= frameptr
+ 0x20 + 4 * i
;
9130 faddr
+= 8; /* Skip the slot for the FPSCR */
9134 v7m_stack_read(cpu
, &slo
, faddr
, mmu_idx
) &&
9135 v7m_stack_read(cpu
, &shi
, faddr
+ 4, mmu_idx
);
9141 dn
= (uint64_t)shi
<< 32 | slo
;
9142 *aa32_vfp_dreg(env
, i
/ 2) = dn
;
9145 v7m_stack_read(cpu
, &fpscr
, frameptr
+ 0x60, mmu_idx
);
9147 vfp_set_fpscr(env
, fpscr
);
9151 * These regs are 0 if security extension present;
9152 * otherwise merely UNKNOWN. We zero always.
9154 for (i
= 0; i
< (restore_s16_s31
? 32 : 16); i
+= 2) {
9155 *aa32_vfp_dreg(env
, i
/ 2) = 0;
9157 vfp_set_fpscr(env
, 0);
9161 env
->v7m
.control
[M_REG_S
] = FIELD_DP32(env
->v7m
.control
[M_REG_S
],
9162 V7M_CONTROL
, FPCA
, !ftype
);
9164 /* Commit to consuming the stack frame */
9168 if (restore_s16_s31
) {
9172 /* Undo stack alignment (the SPREALIGN bit indicates that the original
9173 * pre-exception SP was not 8-aligned and we added a padding word to
9174 * align it, so we undo this by ORing in the bit that increases it
9175 * from the current 8-aligned value to the 8-unaligned value. (Adding 4
9176 * would work too but a logical OR is how the pseudocode specifies it.)
9178 if (xpsr
& XPSR_SPREALIGN
) {
9181 *frame_sp_p
= frameptr
;
9184 xpsr_mask
= ~(XPSR_SPREALIGN
| XPSR_SFPA
);
9185 if (!arm_feature(env
, ARM_FEATURE_THUMB_DSP
)) {
9186 xpsr_mask
&= ~XPSR_GE
;
9188 /* This xpsr_write() will invalidate frame_sp_p as it may switch stack */
9189 xpsr_write(env
, xpsr
, xpsr_mask
);
9191 if (env
->v7m
.secure
) {
9192 bool sfpa
= xpsr
& XPSR_SFPA
;
9194 env
->v7m
.control
[M_REG_S
] = FIELD_DP32(env
->v7m
.control
[M_REG_S
],
9195 V7M_CONTROL
, SFPA
, sfpa
);
9198 /* The restored xPSR exception field will be zero if we're
9199 * resuming in Thread mode. If that doesn't match what the
9200 * exception return excret specified then this is a UsageFault.
9201 * v7M requires we make this check here; v8M did it earlier.
9203 if (return_to_handler
!= arm_v7m_is_handler_mode(env
)) {
9204 /* Take an INVPC UsageFault by pushing the stack again;
9205 * we know we're v7M so this is never a Secure UsageFault.
9207 bool ignore_stackfaults
;
9209 assert(!arm_feature(env
, ARM_FEATURE_V8
));
9210 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, false);
9211 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
9212 ignore_stackfaults
= v7m_push_stack(cpu
);
9213 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on new stackframe: "
9214 "failed exception return integrity check\n");
9215 v7m_exception_taken(cpu
, excret
, false, ignore_stackfaults
);
9219 /* Otherwise, we have a successful exception exit. */
9220 arm_clear_exclusive(env
);
9221 qemu_log_mask(CPU_LOG_INT
, "...successful exception return\n");
9224 static bool do_v7m_function_return(ARMCPU
*cpu
)
9226 /* v8M security extensions magic function return.
9228 * (1) throw an exception (longjump)
9229 * (2) return true if we successfully handled the function return
9230 * (3) return false if we failed a consistency check and have
9231 * pended a UsageFault that needs to be taken now
9233 * At this point the magic return value is split between env->regs[15]
9234 * and env->thumb. We don't bother to reconstitute it because we don't
9235 * need it (all values are handled the same way).
9237 CPUARMState
*env
= &cpu
->env
;
9238 uint32_t newpc
, newpsr
, newpsr_exc
;
9240 qemu_log_mask(CPU_LOG_INT
, "...really v7M secure function return\n");
9243 bool threadmode
, spsel
;
9246 uint32_t *frame_sp_p
;
9249 /* Pull the return address and IPSR from the Secure stack */
9250 threadmode
= !arm_v7m_is_handler_mode(env
);
9251 spsel
= env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SPSEL_MASK
;
9253 frame_sp_p
= get_v7m_sp_ptr(env
, true, threadmode
, spsel
);
9254 frameptr
= *frame_sp_p
;
9256 /* These loads may throw an exception (for MPU faults). We want to
9257 * do them as secure, so work out what MMU index that is.
9259 mmu_idx
= arm_v7m_mmu_idx_for_secstate(env
, true);
9260 oi
= make_memop_idx(MO_LE
, arm_to_core_mmu_idx(mmu_idx
));
9261 newpc
= helper_le_ldul_mmu(env
, frameptr
, oi
, 0);
9262 newpsr
= helper_le_ldul_mmu(env
, frameptr
+ 4, oi
, 0);
9264 /* Consistency checks on new IPSR */
9265 newpsr_exc
= newpsr
& XPSR_EXCP
;
9266 if (!((env
->v7m
.exception
== 0 && newpsr_exc
== 0) ||
9267 (env
->v7m
.exception
== 1 && newpsr_exc
!= 0))) {
9268 /* Pend the fault and tell our caller to take it */
9269 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
9270 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
9272 qemu_log_mask(CPU_LOG_INT
,
9273 "...taking INVPC UsageFault: "
9274 "IPSR consistency check failed\n");
9278 *frame_sp_p
= frameptr
+ 8;
9281 /* This invalidates frame_sp_p */
9282 switch_v7m_security_state(env
, true);
9283 env
->v7m
.exception
= newpsr_exc
;
9284 env
->v7m
.control
[M_REG_S
] &= ~R_V7M_CONTROL_SFPA_MASK
;
9285 if (newpsr
& XPSR_SFPA
) {
9286 env
->v7m
.control
[M_REG_S
] |= R_V7M_CONTROL_SFPA_MASK
;
9288 xpsr_write(env
, 0, XPSR_IT
);
9289 env
->thumb
= newpc
& 1;
9290 env
->regs
[15] = newpc
& ~1;
9292 qemu_log_mask(CPU_LOG_INT
, "...function return successful\n");
9296 static void arm_log_exception(int idx
)
9298 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
9299 const char *exc
= NULL
;
9300 static const char * const excnames
[] = {
9301 [EXCP_UDEF
] = "Undefined Instruction",
9303 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
9304 [EXCP_DATA_ABORT
] = "Data Abort",
9307 [EXCP_BKPT
] = "Breakpoint",
9308 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
9309 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
9310 [EXCP_HVC
] = "Hypervisor Call",
9311 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
9312 [EXCP_SMC
] = "Secure Monitor Call",
9313 [EXCP_VIRQ
] = "Virtual IRQ",
9314 [EXCP_VFIQ
] = "Virtual FIQ",
9315 [EXCP_SEMIHOST
] = "Semihosting call",
9316 [EXCP_NOCP
] = "v7M NOCP UsageFault",
9317 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
9318 [EXCP_STKOF
] = "v8M STKOF UsageFault",
9319 [EXCP_LAZYFP
] = "v7M exception during lazy FP stacking",
9320 [EXCP_LSERR
] = "v8M LSERR UsageFault",
9321 [EXCP_UNALIGNED
] = "v7M UNALIGNED UsageFault",
9324 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
9325 exc
= excnames
[idx
];
9330 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s]\n", idx
, exc
);
9334 static bool v7m_read_half_insn(ARMCPU
*cpu
, ARMMMUIdx mmu_idx
,
9335 uint32_t addr
, uint16_t *insn
)
9337 /* Load a 16-bit portion of a v7M instruction, returning true on success,
9338 * or false on failure (in which case we will have pended the appropriate
9340 * We need to do the instruction fetch's MPU and SAU checks
9341 * like this because there is no MMU index that would allow
9342 * doing the load with a single function call. Instead we must
9343 * first check that the security attributes permit the load
9344 * and that they don't mismatch on the two halves of the instruction,
9345 * and then we do the load as a secure load (ie using the security
9346 * attributes of the address, not the CPU, as architecturally required).
9348 CPUState
*cs
= CPU(cpu
);
9349 CPUARMState
*env
= &cpu
->env
;
9350 V8M_SAttributes sattrs
= {};
9351 MemTxAttrs attrs
= {};
9352 ARMMMUFaultInfo fi
= {};
9354 target_ulong page_size
;
9358 v8m_security_lookup(env
, addr
, MMU_INST_FETCH
, mmu_idx
, &sattrs
);
9359 if (!sattrs
.nsc
|| sattrs
.ns
) {
9360 /* This must be the second half of the insn, and it straddles a
9361 * region boundary with the second half not being S&NSC.
9363 env
->v7m
.sfsr
|= R_V7M_SFSR_INVEP_MASK
;
9364 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
9365 qemu_log_mask(CPU_LOG_INT
,
9366 "...really SecureFault with SFSR.INVEP\n");
9369 if (get_phys_addr(env
, addr
, MMU_INST_FETCH
, mmu_idx
,
9370 &physaddr
, &attrs
, &prot
, &page_size
, &fi
, NULL
)) {
9371 /* the MPU lookup failed */
9372 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_IACCVIOL_MASK
;
9373 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
, env
->v7m
.secure
);
9374 qemu_log_mask(CPU_LOG_INT
, "...really MemManage with CFSR.IACCVIOL\n");
9377 *insn
= address_space_lduw_le(arm_addressspace(cs
, attrs
), physaddr
,
9379 if (txres
!= MEMTX_OK
) {
9380 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_IBUSERR_MASK
;
9381 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_BUS
, false);
9382 qemu_log_mask(CPU_LOG_INT
, "...really BusFault with CFSR.IBUSERR\n");
9388 static bool v7m_handle_execute_nsc(ARMCPU
*cpu
)
9390 /* Check whether this attempt to execute code in a Secure & NS-Callable
9391 * memory region is for an SG instruction; if so, then emulate the
9392 * effect of the SG instruction and return true. Otherwise pend
9393 * the correct kind of exception and return false.
9395 CPUARMState
*env
= &cpu
->env
;
9399 /* We should never get here unless get_phys_addr_pmsav8() caused
9400 * an exception for NS executing in S&NSC memory.
9402 assert(!env
->v7m
.secure
);
9403 assert(arm_feature(env
, ARM_FEATURE_M_SECURITY
));
9405 /* We want to do the MPU lookup as secure; work out what mmu_idx that is */
9406 mmu_idx
= arm_v7m_mmu_idx_for_secstate(env
, true);
9408 if (!v7m_read_half_insn(cpu
, mmu_idx
, env
->regs
[15], &insn
)) {
9416 if (insn
!= 0xe97f) {
9417 /* Not an SG instruction first half (we choose the IMPDEF
9418 * early-SG-check option).
9423 if (!v7m_read_half_insn(cpu
, mmu_idx
, env
->regs
[15] + 2, &insn
)) {
9427 if (insn
!= 0xe97f) {
9428 /* Not an SG instruction second half (yes, both halves of the SG
9429 * insn have the same hex value)
9434 /* OK, we have confirmed that we really have an SG instruction.
9435 * We know we're NS in S memory so don't need to repeat those checks.
9437 qemu_log_mask(CPU_LOG_INT
, "...really an SG instruction at 0x%08" PRIx32
9438 ", executing it\n", env
->regs
[15]);
9439 env
->regs
[14] &= ~1;
9440 env
->v7m
.control
[M_REG_S
] &= ~R_V7M_CONTROL_SFPA_MASK
;
9441 switch_v7m_security_state(env
, true);
9442 xpsr_write(env
, 0, XPSR_IT
);
9447 env
->v7m
.sfsr
|= R_V7M_SFSR_INVEP_MASK
;
9448 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
9449 qemu_log_mask(CPU_LOG_INT
,
9450 "...really SecureFault with SFSR.INVEP\n");
9454 void arm_v7m_cpu_do_interrupt(CPUState
*cs
)
9456 ARMCPU
*cpu
= ARM_CPU(cs
);
9457 CPUARMState
*env
= &cpu
->env
;
9459 bool ignore_stackfaults
;
9461 arm_log_exception(cs
->exception_index
);
9463 /* For exceptions we just mark as pending on the NVIC, and let that
9465 switch (cs
->exception_index
) {
9467 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
9468 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_UNDEFINSTR_MASK
;
9473 * NOCP might be directed to something other than the current
9474 * security state if this fault is because of NSACR; we indicate
9475 * the target security state using exception.target_el.
9477 int target_secstate
;
9479 if (env
->exception
.target_el
== 3) {
9480 target_secstate
= M_REG_S
;
9482 target_secstate
= env
->v7m
.secure
;
9484 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, target_secstate
);
9485 env
->v7m
.cfsr
[target_secstate
] |= R_V7M_CFSR_NOCP_MASK
;
9489 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
9490 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVSTATE_MASK
;
9493 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
9494 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_STKOF_MASK
;
9497 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
9498 env
->v7m
.sfsr
|= R_V7M_SFSR_LSERR_MASK
;
9500 case EXCP_UNALIGNED
:
9501 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
9502 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_UNALIGNED_MASK
;
9505 /* The PC already points to the next instruction. */
9506 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
, env
->v7m
.secure
);
9508 case EXCP_PREFETCH_ABORT
:
9509 case EXCP_DATA_ABORT
:
9510 /* Note that for M profile we don't have a guest facing FSR, but
9511 * the env->exception.fsr will be populated by the code that
9512 * raises the fault, in the A profile short-descriptor format.
9514 switch (env
->exception
.fsr
& 0xf) {
9515 case M_FAKE_FSR_NSC_EXEC
:
9516 /* Exception generated when we try to execute code at an address
9517 * which is marked as Secure & Non-Secure Callable and the CPU
9518 * is in the Non-Secure state. The only instruction which can
9519 * be executed like this is SG (and that only if both halves of
9520 * the SG instruction have the same security attributes.)
9521 * Everything else must generate an INVEP SecureFault, so we
9522 * emulate the SG instruction here.
9524 if (v7m_handle_execute_nsc(cpu
)) {
9528 case M_FAKE_FSR_SFAULT
:
9529 /* Various flavours of SecureFault for attempts to execute or
9530 * access data in the wrong security state.
9532 switch (cs
->exception_index
) {
9533 case EXCP_PREFETCH_ABORT
:
9534 if (env
->v7m
.secure
) {
9535 env
->v7m
.sfsr
|= R_V7M_SFSR_INVTRAN_MASK
;
9536 qemu_log_mask(CPU_LOG_INT
,
9537 "...really SecureFault with SFSR.INVTRAN\n");
9539 env
->v7m
.sfsr
|= R_V7M_SFSR_INVEP_MASK
;
9540 qemu_log_mask(CPU_LOG_INT
,
9541 "...really SecureFault with SFSR.INVEP\n");
9544 case EXCP_DATA_ABORT
:
9545 /* This must be an NS access to S memory */
9546 env
->v7m
.sfsr
|= R_V7M_SFSR_AUVIOL_MASK
;
9547 qemu_log_mask(CPU_LOG_INT
,
9548 "...really SecureFault with SFSR.AUVIOL\n");
9551 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
9553 case 0x8: /* External Abort */
9554 switch (cs
->exception_index
) {
9555 case EXCP_PREFETCH_ABORT
:
9556 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_IBUSERR_MASK
;
9557 qemu_log_mask(CPU_LOG_INT
, "...with CFSR.IBUSERR\n");
9559 case EXCP_DATA_ABORT
:
9560 env
->v7m
.cfsr
[M_REG_NS
] |=
9561 (R_V7M_CFSR_PRECISERR_MASK
| R_V7M_CFSR_BFARVALID_MASK
);
9562 env
->v7m
.bfar
= env
->exception
.vaddress
;
9563 qemu_log_mask(CPU_LOG_INT
,
9564 "...with CFSR.PRECISERR and BFAR 0x%x\n",
9568 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_BUS
, false);
9571 /* All other FSR values are either MPU faults or "can't happen
9572 * for M profile" cases.
9574 switch (cs
->exception_index
) {
9575 case EXCP_PREFETCH_ABORT
:
9576 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_IACCVIOL_MASK
;
9577 qemu_log_mask(CPU_LOG_INT
, "...with CFSR.IACCVIOL\n");
9579 case EXCP_DATA_ABORT
:
9580 env
->v7m
.cfsr
[env
->v7m
.secure
] |=
9581 (R_V7M_CFSR_DACCVIOL_MASK
| R_V7M_CFSR_MMARVALID_MASK
);
9582 env
->v7m
.mmfar
[env
->v7m
.secure
] = env
->exception
.vaddress
;
9583 qemu_log_mask(CPU_LOG_INT
,
9584 "...with CFSR.DACCVIOL and MMFAR 0x%x\n",
9585 env
->v7m
.mmfar
[env
->v7m
.secure
]);
9588 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
,
9594 if (semihosting_enabled()) {
9596 nr
= arm_lduw_code(env
, env
->regs
[15], arm_sctlr_b(env
)) & 0xff;
9599 qemu_log_mask(CPU_LOG_INT
,
9600 "...handling as semihosting call 0x%x\n",
9602 env
->regs
[0] = do_arm_semihosting(env
);
9606 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
, false);
9610 case EXCP_EXCEPTION_EXIT
:
9611 if (env
->regs
[15] < EXC_RETURN_MIN_MAGIC
) {
9612 /* Must be v8M security extension function return */
9613 assert(env
->regs
[15] >= FNC_RETURN_MIN_MAGIC
);
9614 assert(arm_feature(env
, ARM_FEATURE_M_SECURITY
));
9615 if (do_v7m_function_return(cpu
)) {
9619 do_v7m_exception_exit(cpu
);
9625 * We already pended the specific exception in the NVIC in the
9626 * v7m_preserve_fp_state() helper function.
9630 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9631 return; /* Never happens. Keep compiler happy. */
9634 if (arm_feature(env
, ARM_FEATURE_V8
)) {
9635 lr
= R_V7M_EXCRET_RES1_MASK
|
9636 R_V7M_EXCRET_DCRS_MASK
;
9637 /* The S bit indicates whether we should return to Secure
9638 * or NonSecure (ie our current state).
9639 * The ES bit indicates whether we're taking this exception
9640 * to Secure or NonSecure (ie our target state). We set it
9641 * later, in v7m_exception_taken().
9642 * The SPSEL bit is also set in v7m_exception_taken() for v8M.
9643 * This corresponds to the ARM ARM pseudocode for v8M setting
9644 * some LR bits in PushStack() and some in ExceptionTaken();
9645 * the distinction matters for the tailchain cases where we
9646 * can take an exception without pushing the stack.
9648 if (env
->v7m
.secure
) {
9649 lr
|= R_V7M_EXCRET_S_MASK
;
9651 if (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
)) {
9652 lr
|= R_V7M_EXCRET_FTYPE_MASK
;
9655 lr
= R_V7M_EXCRET_RES1_MASK
|
9656 R_V7M_EXCRET_S_MASK
|
9657 R_V7M_EXCRET_DCRS_MASK
|
9658 R_V7M_EXCRET_FTYPE_MASK
|
9659 R_V7M_EXCRET_ES_MASK
;
9660 if (env
->v7m
.control
[M_REG_NS
] & R_V7M_CONTROL_SPSEL_MASK
) {
9661 lr
|= R_V7M_EXCRET_SPSEL_MASK
;
9664 if (!arm_v7m_is_handler_mode(env
)) {
9665 lr
|= R_V7M_EXCRET_MODE_MASK
;
9668 ignore_stackfaults
= v7m_push_stack(cpu
);
9669 v7m_exception_taken(cpu
, lr
, false, ignore_stackfaults
);
9672 /* Function used to synchronize QEMU's AArch64 register set with AArch32
9673 * register set. This is necessary when switching between AArch32 and AArch64
9676 void aarch64_sync_32_to_64(CPUARMState
*env
)
9679 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
9681 /* We can blanket copy R[0:7] to X[0:7] */
9682 for (i
= 0; i
< 8; i
++) {
9683 env
->xregs
[i
] = env
->regs
[i
];
9686 /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
9687 * Otherwise, they come from the banked user regs.
9689 if (mode
== ARM_CPU_MODE_FIQ
) {
9690 for (i
= 8; i
< 13; i
++) {
9691 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
9694 for (i
= 8; i
< 13; i
++) {
9695 env
->xregs
[i
] = env
->regs
[i
];
9699 /* Registers x13-x23 are the various mode SP and FP registers. Registers
9700 * r13 and r14 are only copied if we are in that mode, otherwise we copy
9701 * from the mode banked register.
9703 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
9704 env
->xregs
[13] = env
->regs
[13];
9705 env
->xregs
[14] = env
->regs
[14];
9707 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
9708 /* HYP is an exception in that it is copied from r14 */
9709 if (mode
== ARM_CPU_MODE_HYP
) {
9710 env
->xregs
[14] = env
->regs
[14];
9712 env
->xregs
[14] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)];
9716 if (mode
== ARM_CPU_MODE_HYP
) {
9717 env
->xregs
[15] = env
->regs
[13];
9719 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
9722 if (mode
== ARM_CPU_MODE_IRQ
) {
9723 env
->xregs
[16] = env
->regs
[14];
9724 env
->xregs
[17] = env
->regs
[13];
9726 env
->xregs
[16] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)];
9727 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
9730 if (mode
== ARM_CPU_MODE_SVC
) {
9731 env
->xregs
[18] = env
->regs
[14];
9732 env
->xregs
[19] = env
->regs
[13];
9734 env
->xregs
[18] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)];
9735 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
9738 if (mode
== ARM_CPU_MODE_ABT
) {
9739 env
->xregs
[20] = env
->regs
[14];
9740 env
->xregs
[21] = env
->regs
[13];
9742 env
->xregs
[20] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)];
9743 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
9746 if (mode
== ARM_CPU_MODE_UND
) {
9747 env
->xregs
[22] = env
->regs
[14];
9748 env
->xregs
[23] = env
->regs
[13];
9750 env
->xregs
[22] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)];
9751 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
9754 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
9755 * mode, then we can copy from r8-r14. Otherwise, we copy from the
9756 * FIQ bank for r8-r14.
9758 if (mode
== ARM_CPU_MODE_FIQ
) {
9759 for (i
= 24; i
< 31; i
++) {
9760 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
9763 for (i
= 24; i
< 29; i
++) {
9764 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
9766 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
9767 env
->xregs
[30] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)];
9770 env
->pc
= env
->regs
[15];
9773 /* Function used to synchronize QEMU's AArch32 register set with AArch64
9774 * register set. This is necessary when switching between AArch32 and AArch64
9777 void aarch64_sync_64_to_32(CPUARMState
*env
)
9780 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
9782 /* We can blanket copy X[0:7] to R[0:7] */
9783 for (i
= 0; i
< 8; i
++) {
9784 env
->regs
[i
] = env
->xregs
[i
];
9787 /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
9788 * Otherwise, we copy x8-x12 into the banked user regs.
9790 if (mode
== ARM_CPU_MODE_FIQ
) {
9791 for (i
= 8; i
< 13; i
++) {
9792 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
9795 for (i
= 8; i
< 13; i
++) {
9796 env
->regs
[i
] = env
->xregs
[i
];
9800 /* Registers r13 & r14 depend on the current mode.
9801 * If we are in a given mode, we copy the corresponding x registers to r13
9802 * and r14. Otherwise, we copy the x register to the banked r13 and r14
9805 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
9806 env
->regs
[13] = env
->xregs
[13];
9807 env
->regs
[14] = env
->xregs
[14];
9809 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
9811 /* HYP is an exception in that it does not have its own banked r14 but
9812 * shares the USR r14
9814 if (mode
== ARM_CPU_MODE_HYP
) {
9815 env
->regs
[14] = env
->xregs
[14];
9817 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
9821 if (mode
== ARM_CPU_MODE_HYP
) {
9822 env
->regs
[13] = env
->xregs
[15];
9824 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
9827 if (mode
== ARM_CPU_MODE_IRQ
) {
9828 env
->regs
[14] = env
->xregs
[16];
9829 env
->regs
[13] = env
->xregs
[17];
9831 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
9832 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
9835 if (mode
== ARM_CPU_MODE_SVC
) {
9836 env
->regs
[14] = env
->xregs
[18];
9837 env
->regs
[13] = env
->xregs
[19];
9839 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
9840 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
9843 if (mode
== ARM_CPU_MODE_ABT
) {
9844 env
->regs
[14] = env
->xregs
[20];
9845 env
->regs
[13] = env
->xregs
[21];
9847 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
9848 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
9851 if (mode
== ARM_CPU_MODE_UND
) {
9852 env
->regs
[14] = env
->xregs
[22];
9853 env
->regs
[13] = env
->xregs
[23];
9855 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
9856 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
9859 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
9860 * mode, then we can copy to r8-r14. Otherwise, we copy to the
9861 * FIQ bank for r8-r14.
9863 if (mode
== ARM_CPU_MODE_FIQ
) {
9864 for (i
= 24; i
< 31; i
++) {
9865 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
9868 for (i
= 24; i
< 29; i
++) {
9869 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
9871 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
9872 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
9875 env
->regs
[15] = env
->pc
;
9878 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
9879 uint32_t mask
, uint32_t offset
,
9882 /* Change the CPU state so as to actually take the exception. */
9883 switch_mode(env
, new_mode
);
9885 * For exceptions taken to AArch32 we must clear the SS bit in both
9886 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
9888 env
->uncached_cpsr
&= ~PSTATE_SS
;
9889 env
->spsr
= cpsr_read(env
);
9890 /* Clear IT bits. */
9891 env
->condexec_bits
= 0;
9892 /* Switch to the new mode, and to the correct instruction set. */
9893 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
9894 /* Set new mode endianness */
9895 env
->uncached_cpsr
&= ~CPSR_E
;
9896 if (env
->cp15
.sctlr_el
[arm_current_el(env
)] & SCTLR_EE
) {
9897 env
->uncached_cpsr
|= CPSR_E
;
9899 /* J and IL must always be cleared for exception entry */
9900 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
9903 if (new_mode
== ARM_CPU_MODE_HYP
) {
9904 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
9905 env
->elr_el
[2] = env
->regs
[15];
9908 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
9909 * and we should just guard the thumb mode on V4
9911 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
9913 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
9915 env
->regs
[14] = env
->regs
[15] + offset
;
9917 env
->regs
[15] = newpc
;
9920 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
9923 * Handle exception entry to Hyp mode; this is sufficiently
9924 * different to entry to other AArch32 modes that we handle it
9927 * The vector table entry used is always the 0x14 Hyp mode entry point,
9928 * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp.
9929 * The offset applied to the preferred return address is always zero
9930 * (see DDI0487C.a section G1.12.3).
9931 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
9933 uint32_t addr
, mask
;
9934 ARMCPU
*cpu
= ARM_CPU(cs
);
9935 CPUARMState
*env
= &cpu
->env
;
9937 switch (cs
->exception_index
) {
9945 /* Fall through to prefetch abort. */
9946 case EXCP_PREFETCH_ABORT
:
9947 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
9948 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
9949 (uint32_t)env
->exception
.vaddress
);
9952 case EXCP_DATA_ABORT
:
9953 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
9954 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
9955 (uint32_t)env
->exception
.vaddress
);
9970 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9973 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
9974 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
9976 * QEMU syndrome values are v8-style. v7 has the IL bit
9977 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
9978 * If this is a v7 CPU, squash the IL bit in those cases.
9980 if (cs
->exception_index
== EXCP_PREFETCH_ABORT
||
9981 (cs
->exception_index
== EXCP_DATA_ABORT
&&
9982 !(env
->exception
.syndrome
& ARM_EL_ISV
)) ||
9983 syn_get_ec(env
->exception
.syndrome
) == EC_UNCATEGORIZED
) {
9984 env
->exception
.syndrome
&= ~ARM_EL_IL
;
9987 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
9990 if (arm_current_el(env
) != 2 && addr
< 0x14) {
9995 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
9998 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
10001 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
10005 addr
+= env
->cp15
.hvbar
;
10007 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
10010 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
10012 ARMCPU
*cpu
= ARM_CPU(cs
);
10013 CPUARMState
*env
= &cpu
->env
;
10020 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
10021 switch (syn_get_ec(env
->exception
.syndrome
)) {
10022 case EC_BREAKPOINT
:
10023 case EC_BREAKPOINT_SAME_EL
:
10026 case EC_WATCHPOINT
:
10027 case EC_WATCHPOINT_SAME_EL
:
10033 case EC_VECTORCATCH
:
10042 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
10045 if (env
->exception
.target_el
== 2) {
10046 arm_cpu_do_interrupt_aarch32_hyp(cs
);
10050 switch (cs
->exception_index
) {
10052 new_mode
= ARM_CPU_MODE_UND
;
10061 new_mode
= ARM_CPU_MODE_SVC
;
10064 /* The PC already points to the next instruction. */
10068 /* Fall through to prefetch abort. */
10069 case EXCP_PREFETCH_ABORT
:
10070 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
10071 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
10072 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
10073 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
10074 new_mode
= ARM_CPU_MODE_ABT
;
10076 mask
= CPSR_A
| CPSR_I
;
10079 case EXCP_DATA_ABORT
:
10080 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
10081 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
10082 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
10083 env
->exception
.fsr
,
10084 (uint32_t)env
->exception
.vaddress
);
10085 new_mode
= ARM_CPU_MODE_ABT
;
10087 mask
= CPSR_A
| CPSR_I
;
10091 new_mode
= ARM_CPU_MODE_IRQ
;
10093 /* Disable IRQ and imprecise data aborts. */
10094 mask
= CPSR_A
| CPSR_I
;
10096 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
10097 /* IRQ routed to monitor mode */
10098 new_mode
= ARM_CPU_MODE_MON
;
10103 new_mode
= ARM_CPU_MODE_FIQ
;
10105 /* Disable FIQ, IRQ and imprecise data aborts. */
10106 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10107 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
10108 /* FIQ routed to monitor mode */
10109 new_mode
= ARM_CPU_MODE_MON
;
10114 new_mode
= ARM_CPU_MODE_IRQ
;
10116 /* Disable IRQ and imprecise data aborts. */
10117 mask
= CPSR_A
| CPSR_I
;
10121 new_mode
= ARM_CPU_MODE_FIQ
;
10123 /* Disable FIQ, IRQ and imprecise data aborts. */
10124 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10128 new_mode
= ARM_CPU_MODE_MON
;
10130 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10134 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10135 return; /* Never happens. Keep compiler happy. */
10138 if (new_mode
== ARM_CPU_MODE_MON
) {
10139 addr
+= env
->cp15
.mvbar
;
10140 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
10141 /* High vectors. When enabled, base address cannot be remapped. */
10142 addr
+= 0xffff0000;
10144 /* ARM v7 architectures provide a vector base address register to remap
10145 * the interrupt vector table.
10146 * This register is only followed in non-monitor mode, and is banked.
10147 * Note: only bits 31:5 are valid.
10149 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
10152 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
10153 env
->cp15
.scr_el3
&= ~SCR_NS
;
10156 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
10159 /* Handle exception entry to a target EL which is using AArch64 */
10160 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
10162 ARMCPU
*cpu
= ARM_CPU(cs
);
10163 CPUARMState
*env
= &cpu
->env
;
10164 unsigned int new_el
= env
->exception
.target_el
;
10165 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
10166 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
10167 unsigned int cur_el
= arm_current_el(env
);
10170 * Note that new_el can never be 0. If cur_el is 0, then
10171 * el0_a64 is is_a64(), else el0_a64 is ignored.
10173 aarch64_sve_change_el(env
, cur_el
, new_el
, is_a64(env
));
10175 if (cur_el
< new_el
) {
10176 /* Entry vector offset depends on whether the implemented EL
10177 * immediately lower than the target level is using AArch32 or AArch64
10183 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
10186 is_aa64
= (env
->cp15
.hcr_el2
& HCR_RW
) != 0;
10189 is_aa64
= is_a64(env
);
10192 g_assert_not_reached();
10200 } else if (pstate_read(env
) & PSTATE_SP
) {
10204 switch (cs
->exception_index
) {
10205 case EXCP_PREFETCH_ABORT
:
10206 case EXCP_DATA_ABORT
:
10207 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
10208 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
10209 env
->cp15
.far_el
[new_el
]);
10215 case EXCP_HYP_TRAP
:
10217 if (syn_get_ec(env
->exception
.syndrome
) == EC_ADVSIMDFPACCESSTRAP
) {
10219 * QEMU internal FP/SIMD syndromes from AArch32 include the
10220 * TA and coproc fields which are only exposed if the exception
10221 * is taken to AArch32 Hyp mode. Mask them out to get a valid
10222 * AArch64 format syndrome.
10224 env
->exception
.syndrome
&= ~MAKE_64BIT_MASK(0, 20);
10226 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
10236 case EXCP_SEMIHOST
:
10237 qemu_log_mask(CPU_LOG_INT
,
10238 "...handling as semihosting call 0x%" PRIx64
"\n",
10240 env
->xregs
[0] = do_arm_semihosting(env
);
10243 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10247 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = pstate_read(env
);
10248 aarch64_save_sp(env
, arm_current_el(env
));
10249 env
->elr_el
[new_el
] = env
->pc
;
10251 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = cpsr_read(env
);
10252 env
->elr_el
[new_el
] = env
->regs
[15];
10254 aarch64_sync_32_to_64(env
);
10256 env
->condexec_bits
= 0;
10258 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
10259 env
->elr_el
[new_el
]);
10261 pstate_write(env
, PSTATE_DAIF
| new_mode
);
10263 aarch64_restore_sp(env
, new_el
);
10267 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
10268 new_el
, env
->pc
, pstate_read(env
));
10271 static inline bool check_for_semihosting(CPUState
*cs
)
10273 /* Check whether this exception is a semihosting call; if so
10274 * then handle it and return true; otherwise return false.
10276 ARMCPU
*cpu
= ARM_CPU(cs
);
10277 CPUARMState
*env
= &cpu
->env
;
10280 if (cs
->exception_index
== EXCP_SEMIHOST
) {
10281 /* This is always the 64-bit semihosting exception.
10282 * The "is this usermode" and "is semihosting enabled"
10283 * checks have been done at translate time.
10285 qemu_log_mask(CPU_LOG_INT
,
10286 "...handling as semihosting call 0x%" PRIx64
"\n",
10288 env
->xregs
[0] = do_arm_semihosting(env
);
10295 /* Only intercept calls from privileged modes, to provide some
10296 * semblance of security.
10298 if (cs
->exception_index
!= EXCP_SEMIHOST
&&
10299 (!semihosting_enabled() ||
10300 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
))) {
10304 switch (cs
->exception_index
) {
10305 case EXCP_SEMIHOST
:
10306 /* This is always a semihosting call; the "is this usermode"
10307 * and "is semihosting enabled" checks have been done at
10312 /* Check for semihosting interrupt. */
10314 imm
= arm_lduw_code(env
, env
->regs
[15] - 2, arm_sctlr_b(env
))
10320 imm
= arm_ldl_code(env
, env
->regs
[15] - 4, arm_sctlr_b(env
))
10322 if (imm
== 0x123456) {
10328 /* See if this is a semihosting syscall. */
10330 imm
= arm_lduw_code(env
, env
->regs
[15], arm_sctlr_b(env
))
10333 env
->regs
[15] += 2;
10342 qemu_log_mask(CPU_LOG_INT
,
10343 "...handling as semihosting call 0x%x\n",
10345 env
->regs
[0] = do_arm_semihosting(env
);
10350 /* Handle a CPU exception for A and R profile CPUs.
10351 * Do any appropriate logging, handle PSCI calls, and then hand off
10352 * to the AArch64-entry or AArch32-entry function depending on the
10353 * target exception level's register width.
10355 void arm_cpu_do_interrupt(CPUState
*cs
)
10357 ARMCPU
*cpu
= ARM_CPU(cs
);
10358 CPUARMState
*env
= &cpu
->env
;
10359 unsigned int new_el
= env
->exception
.target_el
;
10361 assert(!arm_feature(env
, ARM_FEATURE_M
));
10363 arm_log_exception(cs
->exception_index
);
10364 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
10366 if (qemu_loglevel_mask(CPU_LOG_INT
)
10367 && !excp_is_internal(cs
->exception_index
)) {
10368 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
10369 syn_get_ec(env
->exception
.syndrome
),
10370 env
->exception
.syndrome
);
10373 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
10374 arm_handle_psci_call(cpu
);
10375 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
10379 /* Semihosting semantics depend on the register width of the
10380 * code that caused the exception, not the target exception level,
10381 * so must be handled here.
10383 if (check_for_semihosting(cs
)) {
10387 /* Hooks may change global state so BQL should be held, also the
10388 * BQL needs to be held for any modification of
10389 * cs->interrupt_request.
10391 g_assert(qemu_mutex_iothread_locked());
10393 arm_call_pre_el_change_hook(cpu
);
10395 assert(!excp_is_internal(cs
->exception_index
));
10396 if (arm_el_is_aa64(env
, new_el
)) {
10397 arm_cpu_do_interrupt_aarch64(cs
);
10399 arm_cpu_do_interrupt_aarch32(cs
);
10402 arm_call_el_change_hook(cpu
);
10404 if (!kvm_enabled()) {
10405 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
10408 #endif /* !CONFIG_USER_ONLY */
10410 /* Return the exception level which controls this address translation regime */
10411 static inline uint32_t regime_el(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
10414 case ARMMMUIdx_S2NS
:
10415 case ARMMMUIdx_S1E2
:
10417 case ARMMMUIdx_S1E3
:
10419 case ARMMMUIdx_S1SE0
:
10420 return arm_el_is_aa64(env
, 3) ? 1 : 3;
10421 case ARMMMUIdx_S1SE1
:
10422 case ARMMMUIdx_S1NSE0
:
10423 case ARMMMUIdx_S1NSE1
:
10424 case ARMMMUIdx_MPrivNegPri
:
10425 case ARMMMUIdx_MUserNegPri
:
10426 case ARMMMUIdx_MPriv
:
10427 case ARMMMUIdx_MUser
:
10428 case ARMMMUIdx_MSPrivNegPri
:
10429 case ARMMMUIdx_MSUserNegPri
:
10430 case ARMMMUIdx_MSPriv
:
10431 case ARMMMUIdx_MSUser
:
10434 g_assert_not_reached();
10438 #ifndef CONFIG_USER_ONLY
10440 /* Return the SCTLR value which controls this address translation regime */
10441 static inline uint32_t regime_sctlr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
10443 return env
->cp15
.sctlr_el
[regime_el(env
, mmu_idx
)];
10446 /* Return true if the specified stage of address translation is disabled */
10447 static inline bool regime_translation_disabled(CPUARMState
*env
,
10450 if (arm_feature(env
, ARM_FEATURE_M
)) {
10451 switch (env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)] &
10452 (R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
)) {
10453 case R_V7M_MPU_CTRL_ENABLE_MASK
:
10454 /* Enabled, but not for HardFault and NMI */
10455 return mmu_idx
& ARM_MMU_IDX_M_NEGPRI
;
10456 case R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
:
10457 /* Enabled for all cases */
10461 /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
10462 * we warned about that in armv7m_nvic.c when the guest set it.
10468 if (mmu_idx
== ARMMMUIdx_S2NS
) {
10469 /* HCR.DC means HCR.VM behaves as 1 */
10470 return (env
->cp15
.hcr_el2
& (HCR_DC
| HCR_VM
)) == 0;
10473 if (env
->cp15
.hcr_el2
& HCR_TGE
) {
10474 /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
10475 if (!regime_is_secure(env
, mmu_idx
) && regime_el(env
, mmu_idx
) == 1) {
10480 if ((env
->cp15
.hcr_el2
& HCR_DC
) &&
10481 (mmu_idx
== ARMMMUIdx_S1NSE0
|| mmu_idx
== ARMMMUIdx_S1NSE1
)) {
10482 /* HCR.DC means SCTLR_EL1.M behaves as 0 */
10486 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
10489 static inline bool regime_translation_big_endian(CPUARMState
*env
,
10492 return (regime_sctlr(env
, mmu_idx
) & SCTLR_EE
) != 0;
10495 /* Return the TTBR associated with this translation regime */
10496 static inline uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
10499 if (mmu_idx
== ARMMMUIdx_S2NS
) {
10500 return env
->cp15
.vttbr_el2
;
10503 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
10505 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
10509 #endif /* !CONFIG_USER_ONLY */
10511 /* Return the TCR controlling this translation regime */
10512 static inline TCR
*regime_tcr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
10514 if (mmu_idx
== ARMMMUIdx_S2NS
) {
10515 return &env
->cp15
.vtcr_el2
;
10517 return &env
->cp15
.tcr_el
[regime_el(env
, mmu_idx
)];
10520 /* Convert a possible stage1+2 MMU index into the appropriate
10521 * stage 1 MMU index
10523 static inline ARMMMUIdx
stage_1_mmu_idx(ARMMMUIdx mmu_idx
)
10525 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
10526 mmu_idx
+= (ARMMMUIdx_S1NSE0
- ARMMMUIdx_S12NSE0
);
10531 /* Return true if the translation regime is using LPAE format page tables */
10532 static inline bool regime_using_lpae_format(CPUARMState
*env
,
10535 int el
= regime_el(env
, mmu_idx
);
10536 if (el
== 2 || arm_el_is_aa64(env
, el
)) {
10539 if (arm_feature(env
, ARM_FEATURE_LPAE
)
10540 && (regime_tcr(env
, mmu_idx
)->raw_tcr
& TTBCR_EAE
)) {
10546 /* Returns true if the stage 1 translation regime is using LPAE format page
10547 * tables. Used when raising alignment exceptions, whose FSR changes depending
10548 * on whether the long or short descriptor format is in use. */
10549 bool arm_s1_regime_using_lpae_format(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
10551 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
10553 return regime_using_lpae_format(env
, mmu_idx
);
10556 #ifndef CONFIG_USER_ONLY
10557 static inline bool regime_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
10560 case ARMMMUIdx_S1SE0
:
10561 case ARMMMUIdx_S1NSE0
:
10562 case ARMMMUIdx_MUser
:
10563 case ARMMMUIdx_MSUser
:
10564 case ARMMMUIdx_MUserNegPri
:
10565 case ARMMMUIdx_MSUserNegPri
:
10569 case ARMMMUIdx_S12NSE0
:
10570 case ARMMMUIdx_S12NSE1
:
10571 g_assert_not_reached();
10575 /* Translate section/page access permissions to page
10576 * R/W protection flags
10578 * @env: CPUARMState
10579 * @mmu_idx: MMU index indicating required translation regime
10580 * @ap: The 3-bit access permissions (AP[2:0])
10581 * @domain_prot: The 2-bit domain access permissions
10583 static inline int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
10584 int ap
, int domain_prot
)
10586 bool is_user
= regime_is_user(env
, mmu_idx
);
10588 if (domain_prot
== 3) {
10589 return PAGE_READ
| PAGE_WRITE
;
10594 if (arm_feature(env
, ARM_FEATURE_V7
)) {
10597 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
10599 return is_user
? 0 : PAGE_READ
;
10606 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
10611 return PAGE_READ
| PAGE_WRITE
;
10614 return PAGE_READ
| PAGE_WRITE
;
10615 case 4: /* Reserved. */
10618 return is_user
? 0 : PAGE_READ
;
10622 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
10627 g_assert_not_reached();
10631 /* Translate section/page access permissions to page
10632 * R/W protection flags.
10634 * @ap: The 2-bit simple AP (AP[2:1])
10635 * @is_user: TRUE if accessing from PL0
10637 static inline int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
10641 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
10643 return PAGE_READ
| PAGE_WRITE
;
10645 return is_user
? 0 : PAGE_READ
;
10649 g_assert_not_reached();
10654 simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
10656 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
10659 /* Translate S2 section/page access permissions to protection flags
10661 * @env: CPUARMState
10662 * @s2ap: The 2-bit stage2 access permissions (S2AP)
10663 * @xn: XN (execute-never) bit
10665 static int get_S2prot(CPUARMState
*env
, int s2ap
, int xn
)
10673 prot
|= PAGE_WRITE
;
10676 if (arm_el_is_aa64(env
, 2) || prot
& PAGE_READ
) {
10683 /* Translate section/page access permissions to protection flags
10685 * @env: CPUARMState
10686 * @mmu_idx: MMU index indicating required translation regime
10687 * @is_aa64: TRUE if AArch64
10688 * @ap: The 2-bit simple AP (AP[2:1])
10689 * @ns: NS (non-secure) bit
10690 * @xn: XN (execute-never) bit
10691 * @pxn: PXN (privileged execute-never) bit
10693 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
10694 int ap
, int ns
, int xn
, int pxn
)
10696 bool is_user
= regime_is_user(env
, mmu_idx
);
10697 int prot_rw
, user_rw
;
10701 assert(mmu_idx
!= ARMMMUIdx_S2NS
);
10703 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
10707 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
10710 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
10714 /* TODO have_wxn should be replaced with
10715 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
10716 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
10717 * compatible processors have EL2, which is required for [U]WXN.
10719 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
10722 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
10726 switch (regime_el(env
, mmu_idx
)) {
10729 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
10736 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
10737 switch (regime_el(env
, mmu_idx
)) {
10741 xn
= xn
|| !(user_rw
& PAGE_READ
);
10745 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
10747 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
10748 (uwxn
&& (user_rw
& PAGE_WRITE
));
10758 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
10761 return prot_rw
| PAGE_EXEC
;
10764 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
10765 uint32_t *table
, uint32_t address
)
10767 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
10768 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
10770 if (address
& tcr
->mask
) {
10771 if (tcr
->raw_tcr
& TTBCR_PD1
) {
10772 /* Translation table walk disabled for TTBR1 */
10775 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
10777 if (tcr
->raw_tcr
& TTBCR_PD0
) {
10778 /* Translation table walk disabled for TTBR0 */
10781 *table
= regime_ttbr(env
, mmu_idx
, 0) & tcr
->base_mask
;
10783 *table
|= (address
>> 18) & 0x3ffc;
10787 /* Translate a S1 pagetable walk through S2 if needed. */
10788 static hwaddr
S1_ptw_translate(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
10789 hwaddr addr
, MemTxAttrs txattrs
,
10790 ARMMMUFaultInfo
*fi
)
10792 if ((mmu_idx
== ARMMMUIdx_S1NSE0
|| mmu_idx
== ARMMMUIdx_S1NSE1
) &&
10793 !regime_translation_disabled(env
, ARMMMUIdx_S2NS
)) {
10794 target_ulong s2size
;
10798 ARMCacheAttrs cacheattrs
= {};
10799 ARMCacheAttrs
*pcacheattrs
= NULL
;
10801 if (env
->cp15
.hcr_el2
& HCR_PTW
) {
10803 * PTW means we must fault if this S1 walk touches S2 Device
10804 * memory; otherwise we don't care about the attributes and can
10805 * save the S2 translation the effort of computing them.
10807 pcacheattrs
= &cacheattrs
;
10810 ret
= get_phys_addr_lpae(env
, addr
, 0, ARMMMUIdx_S2NS
, &s2pa
,
10811 &txattrs
, &s2prot
, &s2size
, fi
, pcacheattrs
);
10813 assert(fi
->type
!= ARMFault_None
);
10819 if (pcacheattrs
&& (pcacheattrs
->attrs
& 0xf0) == 0) {
10820 /* Access was to Device memory: generate Permission fault */
10821 fi
->type
= ARMFault_Permission
;
10832 /* All loads done in the course of a page table walk go through here. */
10833 static uint32_t arm_ldl_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
10834 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
10836 ARMCPU
*cpu
= ARM_CPU(cs
);
10837 CPUARMState
*env
= &cpu
->env
;
10838 MemTxAttrs attrs
= {};
10839 MemTxResult result
= MEMTX_OK
;
10843 attrs
.secure
= is_secure
;
10844 as
= arm_addressspace(cs
, attrs
);
10845 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fi
);
10849 if (regime_translation_big_endian(env
, mmu_idx
)) {
10850 data
= address_space_ldl_be(as
, addr
, attrs
, &result
);
10852 data
= address_space_ldl_le(as
, addr
, attrs
, &result
);
10854 if (result
== MEMTX_OK
) {
10857 fi
->type
= ARMFault_SyncExternalOnWalk
;
10858 fi
->ea
= arm_extabort_type(result
);
10862 static uint64_t arm_ldq_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
10863 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
10865 ARMCPU
*cpu
= ARM_CPU(cs
);
10866 CPUARMState
*env
= &cpu
->env
;
10867 MemTxAttrs attrs
= {};
10868 MemTxResult result
= MEMTX_OK
;
10872 attrs
.secure
= is_secure
;
10873 as
= arm_addressspace(cs
, attrs
);
10874 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fi
);
10878 if (regime_translation_big_endian(env
, mmu_idx
)) {
10879 data
= address_space_ldq_be(as
, addr
, attrs
, &result
);
10881 data
= address_space_ldq_le(as
, addr
, attrs
, &result
);
10883 if (result
== MEMTX_OK
) {
10886 fi
->type
= ARMFault_SyncExternalOnWalk
;
10887 fi
->ea
= arm_extabort_type(result
);
10891 static bool get_phys_addr_v5(CPUARMState
*env
, uint32_t address
,
10892 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10893 hwaddr
*phys_ptr
, int *prot
,
10894 target_ulong
*page_size
,
10895 ARMMMUFaultInfo
*fi
)
10897 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
10908 /* Pagetable walk. */
10909 /* Lookup l1 descriptor. */
10910 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
10911 /* Section translation fault if page walk is disabled by PD0 or PD1 */
10912 fi
->type
= ARMFault_Translation
;
10915 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
10917 if (fi
->type
!= ARMFault_None
) {
10921 domain
= (desc
>> 5) & 0x0f;
10922 if (regime_el(env
, mmu_idx
) == 1) {
10923 dacr
= env
->cp15
.dacr_ns
;
10925 dacr
= env
->cp15
.dacr_s
;
10927 domain_prot
= (dacr
>> (domain
* 2)) & 3;
10929 /* Section translation fault. */
10930 fi
->type
= ARMFault_Translation
;
10936 if (domain_prot
== 0 || domain_prot
== 2) {
10937 fi
->type
= ARMFault_Domain
;
10942 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
10943 ap
= (desc
>> 10) & 3;
10944 *page_size
= 1024 * 1024;
10946 /* Lookup l2 entry. */
10948 /* Coarse pagetable. */
10949 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
10951 /* Fine pagetable. */
10952 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
10954 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
10956 if (fi
->type
!= ARMFault_None
) {
10959 switch (desc
& 3) {
10960 case 0: /* Page translation fault. */
10961 fi
->type
= ARMFault_Translation
;
10963 case 1: /* 64k page. */
10964 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
10965 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
10966 *page_size
= 0x10000;
10968 case 2: /* 4k page. */
10969 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
10970 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
10971 *page_size
= 0x1000;
10973 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
10975 /* ARMv6/XScale extended small page format */
10976 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
10977 || arm_feature(env
, ARM_FEATURE_V6
)) {
10978 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
10979 *page_size
= 0x1000;
10981 /* UNPREDICTABLE in ARMv5; we choose to take a
10982 * page translation fault.
10984 fi
->type
= ARMFault_Translation
;
10988 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
10989 *page_size
= 0x400;
10991 ap
= (desc
>> 4) & 3;
10994 /* Never happens, but compiler isn't smart enough to tell. */
10998 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
10999 *prot
|= *prot
? PAGE_EXEC
: 0;
11000 if (!(*prot
& (1 << access_type
))) {
11001 /* Access permission fault. */
11002 fi
->type
= ARMFault_Permission
;
11005 *phys_ptr
= phys_addr
;
11008 fi
->domain
= domain
;
11013 static bool get_phys_addr_v6(CPUARMState
*env
, uint32_t address
,
11014 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11015 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
11016 target_ulong
*page_size
, ARMMMUFaultInfo
*fi
)
11018 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
11032 /* Pagetable walk. */
11033 /* Lookup l1 descriptor. */
11034 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
11035 /* Section translation fault if page walk is disabled by PD0 or PD1 */
11036 fi
->type
= ARMFault_Translation
;
11039 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
11041 if (fi
->type
!= ARMFault_None
) {
11045 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
11046 /* Section translation fault, or attempt to use the encoding
11047 * which is Reserved on implementations without PXN.
11049 fi
->type
= ARMFault_Translation
;
11052 if ((type
== 1) || !(desc
& (1 << 18))) {
11053 /* Page or Section. */
11054 domain
= (desc
>> 5) & 0x0f;
11056 if (regime_el(env
, mmu_idx
) == 1) {
11057 dacr
= env
->cp15
.dacr_ns
;
11059 dacr
= env
->cp15
.dacr_s
;
11064 domain_prot
= (dacr
>> (domain
* 2)) & 3;
11065 if (domain_prot
== 0 || domain_prot
== 2) {
11066 /* Section or Page domain fault */
11067 fi
->type
= ARMFault_Domain
;
11071 if (desc
& (1 << 18)) {
11072 /* Supersection. */
11073 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
11074 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
11075 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
11076 *page_size
= 0x1000000;
11079 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
11080 *page_size
= 0x100000;
11082 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
11083 xn
= desc
& (1 << 4);
11085 ns
= extract32(desc
, 19, 1);
11087 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
11088 pxn
= (desc
>> 2) & 1;
11090 ns
= extract32(desc
, 3, 1);
11091 /* Lookup l2 entry. */
11092 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
11093 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
11095 if (fi
->type
!= ARMFault_None
) {
11098 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
11099 switch (desc
& 3) {
11100 case 0: /* Page translation fault. */
11101 fi
->type
= ARMFault_Translation
;
11103 case 1: /* 64k page. */
11104 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
11105 xn
= desc
& (1 << 15);
11106 *page_size
= 0x10000;
11108 case 2: case 3: /* 4k page. */
11109 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
11111 *page_size
= 0x1000;
11114 /* Never happens, but compiler isn't smart enough to tell. */
11118 if (domain_prot
== 3) {
11119 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
11121 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
11124 if (xn
&& access_type
== MMU_INST_FETCH
) {
11125 fi
->type
= ARMFault_Permission
;
11129 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
11130 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
11131 /* The simplified model uses AP[0] as an access control bit. */
11132 if ((ap
& 1) == 0) {
11133 /* Access flag fault. */
11134 fi
->type
= ARMFault_AccessFlag
;
11137 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
11139 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
11141 if (*prot
&& !xn
) {
11142 *prot
|= PAGE_EXEC
;
11144 if (!(*prot
& (1 << access_type
))) {
11145 /* Access permission fault. */
11146 fi
->type
= ARMFault_Permission
;
11151 /* The NS bit will (as required by the architecture) have no effect if
11152 * the CPU doesn't support TZ or this is a non-secure translation
11153 * regime, because the attribute will already be non-secure.
11155 attrs
->secure
= false;
11157 *phys_ptr
= phys_addr
;
11160 fi
->domain
= domain
;
11166 * check_s2_mmu_setup
11168 * @is_aa64: True if the translation regime is in AArch64 state
11169 * @startlevel: Suggested starting level
11170 * @inputsize: Bitsize of IPAs
11171 * @stride: Page-table stride (See the ARM ARM)
11173 * Returns true if the suggested S2 translation parameters are OK and
11176 static bool check_s2_mmu_setup(ARMCPU
*cpu
, bool is_aa64
, int level
,
11177 int inputsize
, int stride
)
11179 const int grainsize
= stride
+ 3;
11180 int startsizecheck
;
11182 /* Negative levels are never allowed. */
11187 startsizecheck
= inputsize
- ((3 - level
) * stride
+ grainsize
);
11188 if (startsizecheck
< 1 || startsizecheck
> stride
+ 4) {
11193 CPUARMState
*env
= &cpu
->env
;
11194 unsigned int pamax
= arm_pamax(cpu
);
11197 case 13: /* 64KB Pages. */
11198 if (level
== 0 || (level
== 1 && pamax
<= 42)) {
11202 case 11: /* 16KB Pages. */
11203 if (level
== 0 || (level
== 1 && pamax
<= 40)) {
11207 case 9: /* 4KB Pages. */
11208 if (level
== 0 && pamax
<= 42) {
11213 g_assert_not_reached();
11216 /* Inputsize checks. */
11217 if (inputsize
> pamax
&&
11218 (arm_el_is_aa64(env
, 1) || inputsize
> 40)) {
11219 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
11223 /* AArch32 only supports 4KB pages. Assert on that. */
11224 assert(stride
== 9);
11233 /* Translate from the 4-bit stage 2 representation of
11234 * memory attributes (without cache-allocation hints) to
11235 * the 8-bit representation of the stage 1 MAIR registers
11236 * (which includes allocation hints).
11238 * ref: shared/translation/attrs/S2AttrDecode()
11239 * .../S2ConvertAttrsHints()
11241 static uint8_t convert_stage2_attrs(CPUARMState
*env
, uint8_t s2attrs
)
11243 uint8_t hiattr
= extract32(s2attrs
, 2, 2);
11244 uint8_t loattr
= extract32(s2attrs
, 0, 2);
11245 uint8_t hihint
= 0, lohint
= 0;
11247 if (hiattr
!= 0) { /* normal memory */
11248 if ((env
->cp15
.hcr_el2
& HCR_CD
) != 0) { /* cache disabled */
11249 hiattr
= loattr
= 1; /* non-cacheable */
11251 if (hiattr
!= 1) { /* Write-through or write-back */
11252 hihint
= 3; /* RW allocate */
11254 if (loattr
!= 1) { /* Write-through or write-back */
11255 lohint
= 3; /* RW allocate */
11260 return (hiattr
<< 6) | (hihint
<< 4) | (loattr
<< 2) | lohint
;
11262 #endif /* !CONFIG_USER_ONLY */
11264 ARMVAParameters
aa64_va_parameters_both(CPUARMState
*env
, uint64_t va
,
11267 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
11268 uint32_t el
= regime_el(env
, mmu_idx
);
11269 bool tbi
, tbid
, epd
, hpd
, using16k
, using64k
;
11273 * Bit 55 is always between the two regions, and is canonical for
11274 * determining if address tagging is enabled.
11276 select
= extract64(va
, 55, 1);
11279 tsz
= extract32(tcr
, 0, 6);
11280 using64k
= extract32(tcr
, 14, 1);
11281 using16k
= extract32(tcr
, 15, 1);
11282 if (mmu_idx
== ARMMMUIdx_S2NS
) {
11284 tbi
= tbid
= hpd
= false;
11286 tbi
= extract32(tcr
, 20, 1);
11287 hpd
= extract32(tcr
, 24, 1);
11288 tbid
= extract32(tcr
, 29, 1);
11291 } else if (!select
) {
11292 tsz
= extract32(tcr
, 0, 6);
11293 epd
= extract32(tcr
, 7, 1);
11294 using64k
= extract32(tcr
, 14, 1);
11295 using16k
= extract32(tcr
, 15, 1);
11296 tbi
= extract64(tcr
, 37, 1);
11297 hpd
= extract64(tcr
, 41, 1);
11298 tbid
= extract64(tcr
, 51, 1);
11300 int tg
= extract32(tcr
, 30, 2);
11301 using16k
= tg
== 1;
11302 using64k
= tg
== 3;
11303 tsz
= extract32(tcr
, 16, 6);
11304 epd
= extract32(tcr
, 23, 1);
11305 tbi
= extract64(tcr
, 38, 1);
11306 hpd
= extract64(tcr
, 42, 1);
11307 tbid
= extract64(tcr
, 52, 1);
11309 tsz
= MIN(tsz
, 39); /* TODO: ARMv8.4-TTST */
11310 tsz
= MAX(tsz
, 16); /* TODO: ARMv8.2-LVA */
11312 return (ARMVAParameters
) {
11319 .using16k
= using16k
,
11320 .using64k
= using64k
,
11324 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
11325 ARMMMUIdx mmu_idx
, bool data
)
11327 ARMVAParameters ret
= aa64_va_parameters_both(env
, va
, mmu_idx
);
11329 /* Present TBI as a composite with TBID. */
11330 ret
.tbi
&= (data
|| !ret
.tbid
);
11334 #ifndef CONFIG_USER_ONLY
11335 static ARMVAParameters
aa32_va_parameters(CPUARMState
*env
, uint32_t va
,
11338 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
11339 uint32_t el
= regime_el(env
, mmu_idx
);
11343 if (mmu_idx
== ARMMMUIdx_S2NS
) {
11345 bool sext
= extract32(tcr
, 4, 1);
11346 bool sign
= extract32(tcr
, 3, 1);
11349 * If the sign-extend bit is not the same as t0sz[3], the result
11350 * is unpredictable. Flag this as a guest error.
11352 if (sign
!= sext
) {
11353 qemu_log_mask(LOG_GUEST_ERROR
,
11354 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
11356 tsz
= sextract32(tcr
, 0, 4) + 8;
11360 } else if (el
== 2) {
11362 tsz
= extract32(tcr
, 0, 3);
11364 hpd
= extract64(tcr
, 24, 1);
11367 int t0sz
= extract32(tcr
, 0, 3);
11368 int t1sz
= extract32(tcr
, 16, 3);
11371 select
= va
> (0xffffffffu
>> t0sz
);
11373 /* Note that we will detect errors later. */
11374 select
= va
>= ~(0xffffffffu
>> t1sz
);
11378 epd
= extract32(tcr
, 7, 1);
11379 hpd
= extract64(tcr
, 41, 1);
11382 epd
= extract32(tcr
, 23, 1);
11383 hpd
= extract64(tcr
, 42, 1);
11385 /* For aarch32, hpd0 is not enabled without t2e as well. */
11386 hpd
&= extract32(tcr
, 6, 1);
11389 return (ARMVAParameters
) {
11397 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
11398 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11399 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
11400 target_ulong
*page_size_ptr
,
11401 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
11403 ARMCPU
*cpu
= arm_env_get_cpu(env
);
11404 CPUState
*cs
= CPU(cpu
);
11405 /* Read an LPAE long-descriptor translation table. */
11406 ARMFaultType fault_type
= ARMFault_Translation
;
11408 ARMVAParameters param
;
11410 hwaddr descaddr
, indexmask
, indexmask_grainsize
;
11411 uint32_t tableattrs
;
11412 target_ulong page_size
;
11415 int addrsize
, inputsize
;
11416 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
11417 int ap
, ns
, xn
, pxn
;
11418 uint32_t el
= regime_el(env
, mmu_idx
);
11420 uint64_t descaddrmask
;
11421 bool aarch64
= arm_el_is_aa64(env
, el
);
11422 bool guarded
= false;
11425 * This code does not handle the different format TCR for VTCR_EL2.
11426 * This code also does not support shareability levels.
11427 * Attribute and permission bit handling should also be checked when adding
11428 * support for those page table walks.
11431 param
= aa64_va_parameters(env
, address
, mmu_idx
,
11432 access_type
!= MMU_INST_FETCH
);
11434 /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
11437 ttbr1_valid
= (el
< 2);
11438 addrsize
= 64 - 8 * param
.tbi
;
11439 inputsize
= 64 - param
.tsz
;
11441 param
= aa32_va_parameters(env
, address
, mmu_idx
);
11443 /* There is no TTBR1 for EL2 */
11444 ttbr1_valid
= (el
!= 2);
11445 addrsize
= (mmu_idx
== ARMMMUIdx_S2NS
? 40 : 32);
11446 inputsize
= addrsize
- param
.tsz
;
11450 * We determined the region when collecting the parameters, but we
11451 * have not yet validated that the address is valid for the region.
11452 * Extract the top bits and verify that they all match select.
11454 * For aa32, if inputsize == addrsize, then we have selected the
11455 * region by exclusion in aa32_va_parameters and there is no more
11456 * validation to do here.
11458 if (inputsize
< addrsize
) {
11459 target_ulong top_bits
= sextract64(address
, inputsize
,
11460 addrsize
- inputsize
);
11461 if (-top_bits
!= param
.select
|| (param
.select
&& !ttbr1_valid
)) {
11462 /* The gap between the two regions is a Translation fault */
11463 fault_type
= ARMFault_Translation
;
11468 if (param
.using64k
) {
11470 } else if (param
.using16k
) {
11476 /* Note that QEMU ignores shareability and cacheability attributes,
11477 * so we don't need to do anything with the SH, ORGN, IRGN fields
11478 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
11479 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
11480 * implement any ASID-like capability so we can ignore it (instead
11481 * we will always flush the TLB any time the ASID is changed).
11483 ttbr
= regime_ttbr(env
, mmu_idx
, param
.select
);
11485 /* Here we should have set up all the parameters for the translation:
11486 * inputsize, ttbr, epd, stride, tbi
11490 /* Translation table walk disabled => Translation fault on TLB miss
11491 * Note: This is always 0 on 64-bit EL2 and EL3.
11496 if (mmu_idx
!= ARMMMUIdx_S2NS
) {
11497 /* The starting level depends on the virtual address size (which can
11498 * be up to 48 bits) and the translation granule size. It indicates
11499 * the number of strides (stride bits at a time) needed to
11500 * consume the bits of the input address. In the pseudocode this is:
11501 * level = 4 - RoundUp((inputsize - grainsize) / stride)
11502 * where their 'inputsize' is our 'inputsize', 'grainsize' is
11503 * our 'stride + 3' and 'stride' is our 'stride'.
11504 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
11505 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
11506 * = 4 - (inputsize - 4) / stride;
11508 level
= 4 - (inputsize
- 4) / stride
;
11510 /* For stage 2 translations the starting level is specified by the
11511 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
11513 uint32_t sl0
= extract32(tcr
->raw_tcr
, 6, 2);
11514 uint32_t startlevel
;
11517 if (!aarch64
|| stride
== 9) {
11518 /* AArch32 or 4KB pages */
11519 startlevel
= 2 - sl0
;
11521 /* 16KB or 64KB pages */
11522 startlevel
= 3 - sl0
;
11525 /* Check that the starting level is valid. */
11526 ok
= check_s2_mmu_setup(cpu
, aarch64
, startlevel
,
11527 inputsize
, stride
);
11529 fault_type
= ARMFault_Translation
;
11532 level
= startlevel
;
11535 indexmask_grainsize
= (1ULL << (stride
+ 3)) - 1;
11536 indexmask
= (1ULL << (inputsize
- (stride
* (4 - level
)))) - 1;
11538 /* Now we can extract the actual base address from the TTBR */
11539 descaddr
= extract64(ttbr
, 0, 48);
11540 descaddr
&= ~indexmask
;
11542 /* The address field in the descriptor goes up to bit 39 for ARMv7
11543 * but up to bit 47 for ARMv8, but we use the descaddrmask
11544 * up to bit 39 for AArch32, because we don't need other bits in that case
11545 * to construct next descriptor address (anyway they should be all zeroes).
11547 descaddrmask
= ((1ull << (aarch64
? 48 : 40)) - 1) &
11548 ~indexmask_grainsize
;
11550 /* Secure accesses start with the page table in secure memory and
11551 * can be downgraded to non-secure at any step. Non-secure accesses
11552 * remain non-secure. We implement this by just ORing in the NSTable/NS
11553 * bits at each step.
11555 tableattrs
= regime_is_secure(env
, mmu_idx
) ? 0 : (1 << 4);
11557 uint64_t descriptor
;
11560 descaddr
|= (address
>> (stride
* (4 - level
))) & indexmask
;
11562 nstable
= extract32(tableattrs
, 4, 1);
11563 descriptor
= arm_ldq_ptw(cs
, descaddr
, !nstable
, mmu_idx
, fi
);
11564 if (fi
->type
!= ARMFault_None
) {
11568 if (!(descriptor
& 1) ||
11569 (!(descriptor
& 2) && (level
== 3))) {
11570 /* Invalid, or the Reserved level 3 encoding */
11573 descaddr
= descriptor
& descaddrmask
;
11575 if ((descriptor
& 2) && (level
< 3)) {
11576 /* Table entry. The top five bits are attributes which may
11577 * propagate down through lower levels of the table (and
11578 * which are all arranged so that 0 means "no effect", so
11579 * we can gather them up by ORing in the bits at each level).
11581 tableattrs
|= extract64(descriptor
, 59, 5);
11583 indexmask
= indexmask_grainsize
;
11586 /* Block entry at level 1 or 2, or page entry at level 3.
11587 * These are basically the same thing, although the number
11588 * of bits we pull in from the vaddr varies.
11590 page_size
= (1ULL << ((stride
* (4 - level
)) + 3));
11591 descaddr
|= (address
& (page_size
- 1));
11592 /* Extract attributes from the descriptor */
11593 attrs
= extract64(descriptor
, 2, 10)
11594 | (extract64(descriptor
, 52, 12) << 10);
11596 if (mmu_idx
== ARMMMUIdx_S2NS
) {
11597 /* Stage 2 table descriptors do not include any attribute fields */
11600 /* Merge in attributes from table descriptors */
11601 attrs
|= nstable
<< 3; /* NS */
11602 guarded
= extract64(descriptor
, 50, 1); /* GP */
11604 /* HPD disables all the table attributes except NSTable. */
11607 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
11608 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
11609 * means "force PL1 access only", which means forcing AP[1] to 0.
11611 attrs
&= ~(extract32(tableattrs
, 2, 1) << 4); /* !APT[0] => AP[1] */
11612 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APT[1] => AP[2] */
11615 /* Here descaddr is the final physical address, and attributes
11616 * are all in attrs.
11618 fault_type
= ARMFault_AccessFlag
;
11619 if ((attrs
& (1 << 8)) == 0) {
11624 ap
= extract32(attrs
, 4, 2);
11625 xn
= extract32(attrs
, 12, 1);
11627 if (mmu_idx
== ARMMMUIdx_S2NS
) {
11629 *prot
= get_S2prot(env
, ap
, xn
);
11631 ns
= extract32(attrs
, 3, 1);
11632 pxn
= extract32(attrs
, 11, 1);
11633 *prot
= get_S1prot(env
, mmu_idx
, aarch64
, ap
, ns
, xn
, pxn
);
11636 fault_type
= ARMFault_Permission
;
11637 if (!(*prot
& (1 << access_type
))) {
11642 /* The NS bit will (as required by the architecture) have no effect if
11643 * the CPU doesn't support TZ or this is a non-secure translation
11644 * regime, because the attribute will already be non-secure.
11646 txattrs
->secure
= false;
11648 /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */
11649 if (aarch64
&& guarded
&& cpu_isar_feature(aa64_bti
, cpu
)) {
11650 txattrs
->target_tlb_bit0
= true;
11653 if (cacheattrs
!= NULL
) {
11654 if (mmu_idx
== ARMMMUIdx_S2NS
) {
11655 cacheattrs
->attrs
= convert_stage2_attrs(env
,
11656 extract32(attrs
, 0, 4));
11658 /* Index into MAIR registers for cache attributes */
11659 uint8_t attrindx
= extract32(attrs
, 0, 3);
11660 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
11661 assert(attrindx
<= 7);
11662 cacheattrs
->attrs
= extract64(mair
, attrindx
* 8, 8);
11664 cacheattrs
->shareability
= extract32(attrs
, 6, 2);
11667 *phys_ptr
= descaddr
;
11668 *page_size_ptr
= page_size
;
11672 fi
->type
= fault_type
;
11674 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
11675 fi
->stage2
= fi
->s1ptw
|| (mmu_idx
== ARMMMUIdx_S2NS
);
11679 static inline void get_phys_addr_pmsav7_default(CPUARMState
*env
,
11681 int32_t address
, int *prot
)
11683 if (!arm_feature(env
, ARM_FEATURE_M
)) {
11684 *prot
= PAGE_READ
| PAGE_WRITE
;
11686 case 0xF0000000 ... 0xFFFFFFFF:
11687 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) {
11688 /* hivecs execing is ok */
11689 *prot
|= PAGE_EXEC
;
11692 case 0x00000000 ... 0x7FFFFFFF:
11693 *prot
|= PAGE_EXEC
;
11697 /* Default system address map for M profile cores.
11698 * The architecture specifies which regions are execute-never;
11699 * at the MPU level no other checks are defined.
11702 case 0x00000000 ... 0x1fffffff: /* ROM */
11703 case 0x20000000 ... 0x3fffffff: /* SRAM */
11704 case 0x60000000 ... 0x7fffffff: /* RAM */
11705 case 0x80000000 ... 0x9fffffff: /* RAM */
11706 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
11708 case 0x40000000 ... 0x5fffffff: /* Peripheral */
11709 case 0xa0000000 ... 0xbfffffff: /* Device */
11710 case 0xc0000000 ... 0xdfffffff: /* Device */
11711 case 0xe0000000 ... 0xffffffff: /* System */
11712 *prot
= PAGE_READ
| PAGE_WRITE
;
11715 g_assert_not_reached();
11720 static bool pmsav7_use_background_region(ARMCPU
*cpu
,
11721 ARMMMUIdx mmu_idx
, bool is_user
)
11723 /* Return true if we should use the default memory map as a
11724 * "background" region if there are no hits against any MPU regions.
11726 CPUARMState
*env
= &cpu
->env
;
11732 if (arm_feature(env
, ARM_FEATURE_M
)) {
11733 return env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)]
11734 & R_V7M_MPU_CTRL_PRIVDEFENA_MASK
;
11736 return regime_sctlr(env
, mmu_idx
) & SCTLR_BR
;
11740 static inline bool m_is_ppb_region(CPUARMState
*env
, uint32_t address
)
11742 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
11743 return arm_feature(env
, ARM_FEATURE_M
) &&
11744 extract32(address
, 20, 12) == 0xe00;
11747 static inline bool m_is_system_region(CPUARMState
*env
, uint32_t address
)
11749 /* True if address is in the M profile system region
11750 * 0xe0000000 - 0xffffffff
11752 return arm_feature(env
, ARM_FEATURE_M
) && extract32(address
, 29, 3) == 0x7;
11755 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
11756 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11757 hwaddr
*phys_ptr
, int *prot
,
11758 target_ulong
*page_size
,
11759 ARMMMUFaultInfo
*fi
)
11761 ARMCPU
*cpu
= arm_env_get_cpu(env
);
11763 bool is_user
= regime_is_user(env
, mmu_idx
);
11765 *phys_ptr
= address
;
11766 *page_size
= TARGET_PAGE_SIZE
;
11769 if (regime_translation_disabled(env
, mmu_idx
) ||
11770 m_is_ppb_region(env
, address
)) {
11771 /* MPU disabled or M profile PPB access: use default memory map.
11772 * The other case which uses the default memory map in the
11773 * v7M ARM ARM pseudocode is exception vector reads from the vector
11774 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
11775 * which always does a direct read using address_space_ldl(), rather
11776 * than going via this function, so we don't need to check that here.
11778 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
11779 } else { /* MPU enabled */
11780 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
11781 /* region search */
11782 uint32_t base
= env
->pmsav7
.drbar
[n
];
11783 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
11785 bool srdis
= false;
11787 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
11792 qemu_log_mask(LOG_GUEST_ERROR
,
11793 "DRSR[%d]: Rsize field cannot be 0\n", n
);
11797 rmask
= (1ull << rsize
) - 1;
11799 if (base
& rmask
) {
11800 qemu_log_mask(LOG_GUEST_ERROR
,
11801 "DRBAR[%d]: 0x%" PRIx32
" misaligned "
11802 "to DRSR region size, mask = 0x%" PRIx32
"\n",
11807 if (address
< base
|| address
> base
+ rmask
) {
11809 * Address not in this region. We must check whether the
11810 * region covers addresses in the same page as our address.
11811 * In that case we must not report a size that covers the
11812 * whole page for a subsequent hit against a different MPU
11813 * region or the background region, because it would result in
11814 * incorrect TLB hits for subsequent accesses to addresses that
11815 * are in this MPU region.
11817 if (ranges_overlap(base
, rmask
,
11818 address
& TARGET_PAGE_MASK
,
11819 TARGET_PAGE_SIZE
)) {
11825 /* Region matched */
11827 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
11829 uint32_t srdis_mask
;
11831 rsize
-= 3; /* sub region size (power of 2) */
11832 snd
= ((address
- base
) >> rsize
) & 0x7;
11833 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
11835 srdis_mask
= srdis
? 0x3 : 0x0;
11836 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
11837 /* This will check in groups of 2, 4 and then 8, whether
11838 * the subregion bits are consistent. rsize is incremented
11839 * back up to give the region size, considering consistent
11840 * adjacent subregions as one region. Stop testing if rsize
11841 * is already big enough for an entire QEMU page.
11843 int snd_rounded
= snd
& ~(i
- 1);
11844 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
11845 snd_rounded
+ 8, i
);
11846 if (srdis_mask
^ srdis_multi
) {
11849 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
11856 if (rsize
< TARGET_PAGE_BITS
) {
11857 *page_size
= 1 << rsize
;
11862 if (n
== -1) { /* no hits */
11863 if (!pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
11864 /* background fault */
11865 fi
->type
= ARMFault_Background
;
11868 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
11869 } else { /* a MPU hit! */
11870 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
11871 uint32_t xn
= extract32(env
->pmsav7
.dracr
[n
], 12, 1);
11873 if (m_is_system_region(env
, address
)) {
11874 /* System space is always execute never */
11878 if (is_user
) { /* User mode AP bit decoding */
11883 break; /* no access */
11885 *prot
|= PAGE_WRITE
;
11889 *prot
|= PAGE_READ
| PAGE_EXEC
;
11892 /* for v7M, same as 6; for R profile a reserved value */
11893 if (arm_feature(env
, ARM_FEATURE_M
)) {
11894 *prot
|= PAGE_READ
| PAGE_EXEC
;
11899 qemu_log_mask(LOG_GUEST_ERROR
,
11900 "DRACR[%d]: Bad value for AP bits: 0x%"
11901 PRIx32
"\n", n
, ap
);
11903 } else { /* Priv. mode AP bits decoding */
11906 break; /* no access */
11910 *prot
|= PAGE_WRITE
;
11914 *prot
|= PAGE_READ
| PAGE_EXEC
;
11917 /* for v7M, same as 6; for R profile a reserved value */
11918 if (arm_feature(env
, ARM_FEATURE_M
)) {
11919 *prot
|= PAGE_READ
| PAGE_EXEC
;
11924 qemu_log_mask(LOG_GUEST_ERROR
,
11925 "DRACR[%d]: Bad value for AP bits: 0x%"
11926 PRIx32
"\n", n
, ap
);
11930 /* execute never */
11932 *prot
&= ~PAGE_EXEC
;
11937 fi
->type
= ARMFault_Permission
;
11939 return !(*prot
& (1 << access_type
));
11942 static bool v8m_is_sau_exempt(CPUARMState
*env
,
11943 uint32_t address
, MMUAccessType access_type
)
11945 /* The architecture specifies that certain address ranges are
11946 * exempt from v8M SAU/IDAU checks.
11949 (access_type
== MMU_INST_FETCH
&& m_is_system_region(env
, address
)) ||
11950 (address
>= 0xe0000000 && address
<= 0xe0002fff) ||
11951 (address
>= 0xe000e000 && address
<= 0xe000efff) ||
11952 (address
>= 0xe002e000 && address
<= 0xe002efff) ||
11953 (address
>= 0xe0040000 && address
<= 0xe0041fff) ||
11954 (address
>= 0xe00ff000 && address
<= 0xe00fffff);
11957 static void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
11958 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11959 V8M_SAttributes
*sattrs
)
11961 /* Look up the security attributes for this address. Compare the
11962 * pseudocode SecurityCheck() function.
11963 * We assume the caller has zero-initialized *sattrs.
11965 ARMCPU
*cpu
= arm_env_get_cpu(env
);
11967 bool idau_exempt
= false, idau_ns
= true, idau_nsc
= true;
11968 int idau_region
= IREGION_NOTVALID
;
11969 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
11970 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
11973 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_GET_CLASS(cpu
->idau
);
11974 IDAUInterface
*ii
= IDAU_INTERFACE(cpu
->idau
);
11976 iic
->check(ii
, address
, &idau_region
, &idau_exempt
, &idau_ns
,
11980 if (access_type
== MMU_INST_FETCH
&& extract32(address
, 28, 4) == 0xf) {
11981 /* 0xf0000000..0xffffffff is always S for insn fetches */
11985 if (idau_exempt
|| v8m_is_sau_exempt(env
, address
, access_type
)) {
11986 sattrs
->ns
= !regime_is_secure(env
, mmu_idx
);
11990 if (idau_region
!= IREGION_NOTVALID
) {
11991 sattrs
->irvalid
= true;
11992 sattrs
->iregion
= idau_region
;
11995 switch (env
->sau
.ctrl
& 3) {
11996 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
11998 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
12001 default: /* SAU.ENABLE == 1 */
12002 for (r
= 0; r
< cpu
->sau_sregion
; r
++) {
12003 if (env
->sau
.rlar
[r
] & 1) {
12004 uint32_t base
= env
->sau
.rbar
[r
] & ~0x1f;
12005 uint32_t limit
= env
->sau
.rlar
[r
] | 0x1f;
12007 if (base
<= address
&& limit
>= address
) {
12008 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
12009 sattrs
->subpage
= true;
12011 if (sattrs
->srvalid
) {
12012 /* If we hit in more than one region then we must report
12013 * as Secure, not NS-Callable, with no valid region
12016 sattrs
->ns
= false;
12017 sattrs
->nsc
= false;
12018 sattrs
->sregion
= 0;
12019 sattrs
->srvalid
= false;
12022 if (env
->sau
.rlar
[r
] & 2) {
12023 sattrs
->nsc
= true;
12027 sattrs
->srvalid
= true;
12028 sattrs
->sregion
= r
;
12032 * Address not in this region. We must check whether the
12033 * region covers addresses in the same page as our address.
12034 * In that case we must not report a size that covers the
12035 * whole page for a subsequent hit against a different MPU
12036 * region or the background region, because it would result
12037 * in incorrect TLB hits for subsequent accesses to
12038 * addresses that are in this MPU region.
12040 if (limit
>= base
&&
12041 ranges_overlap(base
, limit
- base
+ 1,
12043 TARGET_PAGE_SIZE
)) {
12044 sattrs
->subpage
= true;
12053 * The IDAU will override the SAU lookup results if it specifies
12054 * higher security than the SAU does.
12057 if (sattrs
->ns
|| (!idau_nsc
&& sattrs
->nsc
)) {
12058 sattrs
->ns
= false;
12059 sattrs
->nsc
= idau_nsc
;
12064 static bool pmsav8_mpu_lookup(CPUARMState
*env
, uint32_t address
,
12065 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
12066 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
12067 int *prot
, bool *is_subpage
,
12068 ARMMMUFaultInfo
*fi
, uint32_t *mregion
)
12070 /* Perform a PMSAv8 MPU lookup (without also doing the SAU check
12071 * that a full phys-to-virt translation does).
12072 * mregion is (if not NULL) set to the region number which matched,
12073 * or -1 if no region number is returned (MPU off, address did not
12074 * hit a region, address hit in multiple regions).
12075 * We set is_subpage to true if the region hit doesn't cover the
12076 * entire TARGET_PAGE the address is within.
12078 ARMCPU
*cpu
= arm_env_get_cpu(env
);
12079 bool is_user
= regime_is_user(env
, mmu_idx
);
12080 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
12082 int matchregion
= -1;
12084 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
12085 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
12087 *is_subpage
= false;
12088 *phys_ptr
= address
;
12094 /* Unlike the ARM ARM pseudocode, we don't need to check whether this
12095 * was an exception vector read from the vector table (which is always
12096 * done using the default system address map), because those accesses
12097 * are done in arm_v7m_load_vector(), which always does a direct
12098 * read using address_space_ldl(), rather than going via this function.
12100 if (regime_translation_disabled(env
, mmu_idx
)) { /* MPU disabled */
12102 } else if (m_is_ppb_region(env
, address
)) {
12105 if (pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
12109 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
12110 /* region search */
12111 /* Note that the base address is bits [31:5] from the register
12112 * with bits [4:0] all zeroes, but the limit address is bits
12113 * [31:5] from the register with bits [4:0] all ones.
12115 uint32_t base
= env
->pmsav8
.rbar
[secure
][n
] & ~0x1f;
12116 uint32_t limit
= env
->pmsav8
.rlar
[secure
][n
] | 0x1f;
12118 if (!(env
->pmsav8
.rlar
[secure
][n
] & 0x1)) {
12119 /* Region disabled */
12123 if (address
< base
|| address
> limit
) {
12125 * Address not in this region. We must check whether the
12126 * region covers addresses in the same page as our address.
12127 * In that case we must not report a size that covers the
12128 * whole page for a subsequent hit against a different MPU
12129 * region or the background region, because it would result in
12130 * incorrect TLB hits for subsequent accesses to addresses that
12131 * are in this MPU region.
12133 if (limit
>= base
&&
12134 ranges_overlap(base
, limit
- base
+ 1,
12136 TARGET_PAGE_SIZE
)) {
12137 *is_subpage
= true;
12142 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
12143 *is_subpage
= true;
12146 if (matchregion
!= -1) {
12147 /* Multiple regions match -- always a failure (unlike
12148 * PMSAv7 where highest-numbered-region wins)
12150 fi
->type
= ARMFault_Permission
;
12161 /* background fault */
12162 fi
->type
= ARMFault_Background
;
12166 if (matchregion
== -1) {
12167 /* hit using the background region */
12168 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
12170 uint32_t ap
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 1, 2);
12171 uint32_t xn
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 0, 1);
12173 if (m_is_system_region(env
, address
)) {
12174 /* System space is always execute never */
12178 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
);
12179 if (*prot
&& !xn
) {
12180 *prot
|= PAGE_EXEC
;
12182 /* We don't need to look the attribute up in the MAIR0/MAIR1
12183 * registers because that only tells us about cacheability.
12186 *mregion
= matchregion
;
12190 fi
->type
= ARMFault_Permission
;
12192 return !(*prot
& (1 << access_type
));
12196 static bool get_phys_addr_pmsav8(CPUARMState
*env
, uint32_t address
,
12197 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
12198 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
12199 int *prot
, target_ulong
*page_size
,
12200 ARMMMUFaultInfo
*fi
)
12202 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
12203 V8M_SAttributes sattrs
= {};
12205 bool mpu_is_subpage
;
12207 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
12208 v8m_security_lookup(env
, address
, access_type
, mmu_idx
, &sattrs
);
12209 if (access_type
== MMU_INST_FETCH
) {
12210 /* Instruction fetches always use the MMU bank and the
12211 * transaction attribute determined by the fetch address,
12212 * regardless of CPU state. This is painful for QEMU
12213 * to handle, because it would mean we need to encode
12214 * into the mmu_idx not just the (user, negpri) information
12215 * for the current security state but also that for the
12216 * other security state, which would balloon the number
12217 * of mmu_idx values needed alarmingly.
12218 * Fortunately we can avoid this because it's not actually
12219 * possible to arbitrarily execute code from memory with
12220 * the wrong security attribute: it will always generate
12221 * an exception of some kind or another, apart from the
12222 * special case of an NS CPU executing an SG instruction
12223 * in S&NSC memory. So we always just fail the translation
12224 * here and sort things out in the exception handler
12225 * (including possibly emulating an SG instruction).
12227 if (sattrs
.ns
!= !secure
) {
12229 fi
->type
= ARMFault_QEMU_NSCExec
;
12231 fi
->type
= ARMFault_QEMU_SFault
;
12233 *page_size
= sattrs
.subpage
? 1 : TARGET_PAGE_SIZE
;
12234 *phys_ptr
= address
;
12239 /* For data accesses we always use the MMU bank indicated
12240 * by the current CPU state, but the security attributes
12241 * might downgrade a secure access to nonsecure.
12244 txattrs
->secure
= false;
12245 } else if (!secure
) {
12246 /* NS access to S memory must fault.
12247 * Architecturally we should first check whether the
12248 * MPU information for this address indicates that we
12249 * are doing an unaligned access to Device memory, which
12250 * should generate a UsageFault instead. QEMU does not
12251 * currently check for that kind of unaligned access though.
12252 * If we added it we would need to do so as a special case
12253 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
12255 fi
->type
= ARMFault_QEMU_SFault
;
12256 *page_size
= sattrs
.subpage
? 1 : TARGET_PAGE_SIZE
;
12257 *phys_ptr
= address
;
12264 ret
= pmsav8_mpu_lookup(env
, address
, access_type
, mmu_idx
, phys_ptr
,
12265 txattrs
, prot
, &mpu_is_subpage
, fi
, NULL
);
12266 *page_size
= sattrs
.subpage
|| mpu_is_subpage
? 1 : TARGET_PAGE_SIZE
;
12270 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
12271 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
12272 hwaddr
*phys_ptr
, int *prot
,
12273 ARMMMUFaultInfo
*fi
)
12278 bool is_user
= regime_is_user(env
, mmu_idx
);
12280 if (regime_translation_disabled(env
, mmu_idx
)) {
12281 /* MPU disabled. */
12282 *phys_ptr
= address
;
12283 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
12287 *phys_ptr
= address
;
12288 for (n
= 7; n
>= 0; n
--) {
12289 base
= env
->cp15
.c6_region
[n
];
12290 if ((base
& 1) == 0) {
12293 mask
= 1 << ((base
>> 1) & 0x1f);
12294 /* Keep this shift separate from the above to avoid an
12295 (undefined) << 32. */
12296 mask
= (mask
<< 1) - 1;
12297 if (((base
^ address
) & ~mask
) == 0) {
12302 fi
->type
= ARMFault_Background
;
12306 if (access_type
== MMU_INST_FETCH
) {
12307 mask
= env
->cp15
.pmsav5_insn_ap
;
12309 mask
= env
->cp15
.pmsav5_data_ap
;
12311 mask
= (mask
>> (n
* 4)) & 0xf;
12314 fi
->type
= ARMFault_Permission
;
12319 fi
->type
= ARMFault_Permission
;
12323 *prot
= PAGE_READ
| PAGE_WRITE
;
12328 *prot
|= PAGE_WRITE
;
12332 *prot
= PAGE_READ
| PAGE_WRITE
;
12336 fi
->type
= ARMFault_Permission
;
12346 /* Bad permission. */
12347 fi
->type
= ARMFault_Permission
;
12351 *prot
|= PAGE_EXEC
;
12355 /* Combine either inner or outer cacheability attributes for normal
12356 * memory, according to table D4-42 and pseudocode procedure
12357 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
12359 * NB: only stage 1 includes allocation hints (RW bits), leading to
12362 static uint8_t combine_cacheattr_nibble(uint8_t s1
, uint8_t s2
)
12364 if (s1
== 4 || s2
== 4) {
12365 /* non-cacheable has precedence */
12367 } else if (extract32(s1
, 2, 2) == 0 || extract32(s1
, 2, 2) == 2) {
12368 /* stage 1 write-through takes precedence */
12370 } else if (extract32(s2
, 2, 2) == 2) {
12371 /* stage 2 write-through takes precedence, but the allocation hint
12372 * is still taken from stage 1
12374 return (2 << 2) | extract32(s1
, 0, 2);
12375 } else { /* write-back */
12380 /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
12381 * and CombineS1S2Desc()
12383 * @s1: Attributes from stage 1 walk
12384 * @s2: Attributes from stage 2 walk
12386 static ARMCacheAttrs
combine_cacheattrs(ARMCacheAttrs s1
, ARMCacheAttrs s2
)
12388 uint8_t s1lo
= extract32(s1
.attrs
, 0, 4), s2lo
= extract32(s2
.attrs
, 0, 4);
12389 uint8_t s1hi
= extract32(s1
.attrs
, 4, 4), s2hi
= extract32(s2
.attrs
, 4, 4);
12392 /* Combine shareability attributes (table D4-43) */
12393 if (s1
.shareability
== 2 || s2
.shareability
== 2) {
12394 /* if either are outer-shareable, the result is outer-shareable */
12395 ret
.shareability
= 2;
12396 } else if (s1
.shareability
== 3 || s2
.shareability
== 3) {
12397 /* if either are inner-shareable, the result is inner-shareable */
12398 ret
.shareability
= 3;
12400 /* both non-shareable */
12401 ret
.shareability
= 0;
12404 /* Combine memory type and cacheability attributes */
12405 if (s1hi
== 0 || s2hi
== 0) {
12406 /* Device has precedence over normal */
12407 if (s1lo
== 0 || s2lo
== 0) {
12408 /* nGnRnE has precedence over anything */
12410 } else if (s1lo
== 4 || s2lo
== 4) {
12411 /* non-Reordering has precedence over Reordering */
12412 ret
.attrs
= 4; /* nGnRE */
12413 } else if (s1lo
== 8 || s2lo
== 8) {
12414 /* non-Gathering has precedence over Gathering */
12415 ret
.attrs
= 8; /* nGRE */
12417 ret
.attrs
= 0xc; /* GRE */
12420 /* Any location for which the resultant memory type is any
12421 * type of Device memory is always treated as Outer Shareable.
12423 ret
.shareability
= 2;
12424 } else { /* Normal memory */
12425 /* Outer/inner cacheability combine independently */
12426 ret
.attrs
= combine_cacheattr_nibble(s1hi
, s2hi
) << 4
12427 | combine_cacheattr_nibble(s1lo
, s2lo
);
12429 if (ret
.attrs
== 0x44) {
12430 /* Any location for which the resultant memory type is Normal
12431 * Inner Non-cacheable, Outer Non-cacheable is always treated
12432 * as Outer Shareable.
12434 ret
.shareability
= 2;
12442 /* get_phys_addr - get the physical address for this virtual address
12444 * Find the physical address corresponding to the given virtual address,
12445 * by doing a translation table walk on MMU based systems or using the
12446 * MPU state on MPU based systems.
12448 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
12449 * prot and page_size may not be filled in, and the populated fsr value provides
12450 * information on why the translation aborted, in the format of a
12451 * DFSR/IFSR fault register, with the following caveats:
12452 * * we honour the short vs long DFSR format differences.
12453 * * the WnR bit is never set (the caller must do this).
12454 * * for PSMAv5 based systems we don't bother to return a full FSR format
12457 * @env: CPUARMState
12458 * @address: virtual address to get physical address for
12459 * @access_type: 0 for read, 1 for write, 2 for execute
12460 * @mmu_idx: MMU index indicating required translation regime
12461 * @phys_ptr: set to the physical address corresponding to the virtual address
12462 * @attrs: set to the memory transaction attributes to use
12463 * @prot: set to the permissions for the page containing phys_ptr
12464 * @page_size: set to the size of the page containing phys_ptr
12465 * @fi: set to fault info if the translation fails
12466 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
12468 static bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
12469 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
12470 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
12471 target_ulong
*page_size
,
12472 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
12474 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
12475 /* Call ourselves recursively to do the stage 1 and then stage 2
12478 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
12482 ARMCacheAttrs cacheattrs2
= {};
12484 ret
= get_phys_addr(env
, address
, access_type
,
12485 stage_1_mmu_idx(mmu_idx
), &ipa
, attrs
,
12486 prot
, page_size
, fi
, cacheattrs
);
12488 /* If S1 fails or S2 is disabled, return early. */
12489 if (ret
|| regime_translation_disabled(env
, ARMMMUIdx_S2NS
)) {
12494 /* S1 is done. Now do S2 translation. */
12495 ret
= get_phys_addr_lpae(env
, ipa
, access_type
, ARMMMUIdx_S2NS
,
12496 phys_ptr
, attrs
, &s2_prot
,
12498 cacheattrs
!= NULL
? &cacheattrs2
: NULL
);
12500 /* Combine the S1 and S2 perms. */
12503 /* Combine the S1 and S2 cache attributes, if needed */
12504 if (!ret
&& cacheattrs
!= NULL
) {
12505 if (env
->cp15
.hcr_el2
& HCR_DC
) {
12507 * HCR.DC forces the first stage attributes to
12508 * Normal Non-Shareable,
12509 * Inner Write-Back Read-Allocate Write-Allocate,
12510 * Outer Write-Back Read-Allocate Write-Allocate.
12512 cacheattrs
->attrs
= 0xff;
12513 cacheattrs
->shareability
= 0;
12515 *cacheattrs
= combine_cacheattrs(*cacheattrs
, cacheattrs2
);
12521 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
12523 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
12527 /* The page table entries may downgrade secure to non-secure, but
12528 * cannot upgrade an non-secure translation regime's attributes
12531 attrs
->secure
= regime_is_secure(env
, mmu_idx
);
12532 attrs
->user
= regime_is_user(env
, mmu_idx
);
12534 /* Fast Context Switch Extension. This doesn't exist at all in v8.
12535 * In v7 and earlier it affects all stage 1 translations.
12537 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_S2NS
12538 && !arm_feature(env
, ARM_FEATURE_V8
)) {
12539 if (regime_el(env
, mmu_idx
) == 3) {
12540 address
+= env
->cp15
.fcseidr_s
;
12542 address
+= env
->cp15
.fcseidr_ns
;
12546 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
12548 *page_size
= TARGET_PAGE_SIZE
;
12550 if (arm_feature(env
, ARM_FEATURE_V8
)) {
12552 ret
= get_phys_addr_pmsav8(env
, address
, access_type
, mmu_idx
,
12553 phys_ptr
, attrs
, prot
, page_size
, fi
);
12554 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
12556 ret
= get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
12557 phys_ptr
, prot
, page_size
, fi
);
12560 ret
= get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
12561 phys_ptr
, prot
, fi
);
12563 qemu_log_mask(CPU_LOG_MMU
, "PMSA MPU lookup for %s at 0x%08" PRIx32
12564 " mmu_idx %u -> %s (prot %c%c%c)\n",
12565 access_type
== MMU_DATA_LOAD
? "reading" :
12566 (access_type
== MMU_DATA_STORE
? "writing" : "execute"),
12567 (uint32_t)address
, mmu_idx
,
12568 ret
? "Miss" : "Hit",
12569 *prot
& PAGE_READ
? 'r' : '-',
12570 *prot
& PAGE_WRITE
? 'w' : '-',
12571 *prot
& PAGE_EXEC
? 'x' : '-');
12576 /* Definitely a real MMU, not an MPU */
12578 if (regime_translation_disabled(env
, mmu_idx
)) {
12579 /* MMU disabled. */
12580 *phys_ptr
= address
;
12581 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
12582 *page_size
= TARGET_PAGE_SIZE
;
12586 if (regime_using_lpae_format(env
, mmu_idx
)) {
12587 return get_phys_addr_lpae(env
, address
, access_type
, mmu_idx
,
12588 phys_ptr
, attrs
, prot
, page_size
,
12590 } else if (regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
12591 return get_phys_addr_v6(env
, address
, access_type
, mmu_idx
,
12592 phys_ptr
, attrs
, prot
, page_size
, fi
);
12594 return get_phys_addr_v5(env
, address
, access_type
, mmu_idx
,
12595 phys_ptr
, prot
, page_size
, fi
);
12599 /* Walk the page table and (if the mapping exists) add the page
12600 * to the TLB. Return false on success, or true on failure. Populate
12601 * fsr with ARM DFSR/IFSR fault register format value on failure.
12603 bool arm_tlb_fill(CPUState
*cs
, vaddr address
,
12604 MMUAccessType access_type
, int mmu_idx
,
12605 ARMMMUFaultInfo
*fi
)
12607 ARMCPU
*cpu
= ARM_CPU(cs
);
12608 CPUARMState
*env
= &cpu
->env
;
12610 target_ulong page_size
;
12613 MemTxAttrs attrs
= {};
12615 ret
= get_phys_addr(env
, address
, access_type
,
12616 core_to_arm_mmu_idx(env
, mmu_idx
), &phys_addr
,
12617 &attrs
, &prot
, &page_size
, fi
, NULL
);
12620 * Map a single [sub]page. Regions smaller than our declared
12621 * target page size are handled specially, so for those we
12622 * pass in the exact addresses.
12624 if (page_size
>= TARGET_PAGE_SIZE
) {
12625 phys_addr
&= TARGET_PAGE_MASK
;
12626 address
&= TARGET_PAGE_MASK
;
12628 tlb_set_page_with_attrs(cs
, address
, phys_addr
, attrs
,
12629 prot
, mmu_idx
, page_size
);
12636 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cs
, vaddr addr
,
12639 ARMCPU
*cpu
= ARM_CPU(cs
);
12640 CPUARMState
*env
= &cpu
->env
;
12642 target_ulong page_size
;
12645 ARMMMUFaultInfo fi
= {};
12646 ARMMMUIdx mmu_idx
= arm_mmu_idx(env
);
12648 *attrs
= (MemTxAttrs
) {};
12650 ret
= get_phys_addr(env
, addr
, 0, mmu_idx
, &phys_addr
,
12651 attrs
, &prot
, &page_size
, &fi
, NULL
);
12659 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
12662 unsigned el
= arm_current_el(env
);
12664 /* First handle registers which unprivileged can read */
12667 case 0 ... 7: /* xPSR sub-fields */
12669 if ((reg
& 1) && el
) {
12670 mask
|= XPSR_EXCP
; /* IPSR (unpriv. reads as zero) */
12673 mask
|= XPSR_NZCV
| XPSR_Q
; /* APSR */
12674 if (arm_feature(env
, ARM_FEATURE_THUMB_DSP
)) {
12678 /* EPSR reads as zero */
12679 return xpsr_read(env
) & mask
;
12681 case 20: /* CONTROL */
12683 uint32_t value
= env
->v7m
.control
[env
->v7m
.secure
];
12684 if (!env
->v7m
.secure
) {
12685 /* SFPA is RAZ/WI from NS; FPCA is stored in the M_REG_S bank */
12686 value
|= env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
;
12690 case 0x94: /* CONTROL_NS */
12691 /* We have to handle this here because unprivileged Secure code
12692 * can read the NS CONTROL register.
12694 if (!env
->v7m
.secure
) {
12697 return env
->v7m
.control
[M_REG_NS
] |
12698 (env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
);
12702 return 0; /* unprivileged reads others as zero */
12705 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
12707 case 0x88: /* MSP_NS */
12708 if (!env
->v7m
.secure
) {
12711 return env
->v7m
.other_ss_msp
;
12712 case 0x89: /* PSP_NS */
12713 if (!env
->v7m
.secure
) {
12716 return env
->v7m
.other_ss_psp
;
12717 case 0x8a: /* MSPLIM_NS */
12718 if (!env
->v7m
.secure
) {
12721 return env
->v7m
.msplim
[M_REG_NS
];
12722 case 0x8b: /* PSPLIM_NS */
12723 if (!env
->v7m
.secure
) {
12726 return env
->v7m
.psplim
[M_REG_NS
];
12727 case 0x90: /* PRIMASK_NS */
12728 if (!env
->v7m
.secure
) {
12731 return env
->v7m
.primask
[M_REG_NS
];
12732 case 0x91: /* BASEPRI_NS */
12733 if (!env
->v7m
.secure
) {
12736 return env
->v7m
.basepri
[M_REG_NS
];
12737 case 0x93: /* FAULTMASK_NS */
12738 if (!env
->v7m
.secure
) {
12741 return env
->v7m
.faultmask
[M_REG_NS
];
12742 case 0x98: /* SP_NS */
12744 /* This gives the non-secure SP selected based on whether we're
12745 * currently in handler mode or not, using the NS CONTROL.SPSEL.
12747 bool spsel
= env
->v7m
.control
[M_REG_NS
] & R_V7M_CONTROL_SPSEL_MASK
;
12749 if (!env
->v7m
.secure
) {
12752 if (!arm_v7m_is_handler_mode(env
) && spsel
) {
12753 return env
->v7m
.other_ss_psp
;
12755 return env
->v7m
.other_ss_msp
;
12765 return v7m_using_psp(env
) ? env
->v7m
.other_sp
: env
->regs
[13];
12767 return v7m_using_psp(env
) ? env
->regs
[13] : env
->v7m
.other_sp
;
12768 case 10: /* MSPLIM */
12769 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
12772 return env
->v7m
.msplim
[env
->v7m
.secure
];
12773 case 11: /* PSPLIM */
12774 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
12777 return env
->v7m
.psplim
[env
->v7m
.secure
];
12778 case 16: /* PRIMASK */
12779 return env
->v7m
.primask
[env
->v7m
.secure
];
12780 case 17: /* BASEPRI */
12781 case 18: /* BASEPRI_MAX */
12782 return env
->v7m
.basepri
[env
->v7m
.secure
];
12783 case 19: /* FAULTMASK */
12784 return env
->v7m
.faultmask
[env
->v7m
.secure
];
12787 qemu_log_mask(LOG_GUEST_ERROR
, "Attempt to read unknown special"
12788 " register %d\n", reg
);
12793 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t maskreg
, uint32_t val
)
12795 /* We're passed bits [11..0] of the instruction; extract
12796 * SYSm and the mask bits.
12797 * Invalid combinations of SYSm and mask are UNPREDICTABLE;
12798 * we choose to treat them as if the mask bits were valid.
12799 * NB that the pseudocode 'mask' variable is bits [11..10],
12800 * whereas ours is [11..8].
12802 uint32_t mask
= extract32(maskreg
, 8, 4);
12803 uint32_t reg
= extract32(maskreg
, 0, 8);
12804 int cur_el
= arm_current_el(env
);
12806 if (cur_el
== 0 && reg
> 7 && reg
!= 20) {
12808 * only xPSR sub-fields and CONTROL.SFPA may be written by
12809 * unprivileged code
12814 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
12816 case 0x88: /* MSP_NS */
12817 if (!env
->v7m
.secure
) {
12820 env
->v7m
.other_ss_msp
= val
;
12822 case 0x89: /* PSP_NS */
12823 if (!env
->v7m
.secure
) {
12826 env
->v7m
.other_ss_psp
= val
;
12828 case 0x8a: /* MSPLIM_NS */
12829 if (!env
->v7m
.secure
) {
12832 env
->v7m
.msplim
[M_REG_NS
] = val
& ~7;
12834 case 0x8b: /* PSPLIM_NS */
12835 if (!env
->v7m
.secure
) {
12838 env
->v7m
.psplim
[M_REG_NS
] = val
& ~7;
12840 case 0x90: /* PRIMASK_NS */
12841 if (!env
->v7m
.secure
) {
12844 env
->v7m
.primask
[M_REG_NS
] = val
& 1;
12846 case 0x91: /* BASEPRI_NS */
12847 if (!env
->v7m
.secure
|| !arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
12850 env
->v7m
.basepri
[M_REG_NS
] = val
& 0xff;
12852 case 0x93: /* FAULTMASK_NS */
12853 if (!env
->v7m
.secure
|| !arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
12856 env
->v7m
.faultmask
[M_REG_NS
] = val
& 1;
12858 case 0x94: /* CONTROL_NS */
12859 if (!env
->v7m
.secure
) {
12862 write_v7m_control_spsel_for_secstate(env
,
12863 val
& R_V7M_CONTROL_SPSEL_MASK
,
12865 if (arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
12866 env
->v7m
.control
[M_REG_NS
] &= ~R_V7M_CONTROL_NPRIV_MASK
;
12867 env
->v7m
.control
[M_REG_NS
] |= val
& R_V7M_CONTROL_NPRIV_MASK
;
12870 * SFPA is RAZ/WI from NS. FPCA is RO if NSACR.CP10 == 0,
12871 * RES0 if the FPU is not present, and is stored in the S bank
12873 if (arm_feature(env
, ARM_FEATURE_VFP
) &&
12874 extract32(env
->v7m
.nsacr
, 10, 1)) {
12875 env
->v7m
.control
[M_REG_S
] &= ~R_V7M_CONTROL_FPCA_MASK
;
12876 env
->v7m
.control
[M_REG_S
] |= val
& R_V7M_CONTROL_FPCA_MASK
;
12879 case 0x98: /* SP_NS */
12881 /* This gives the non-secure SP selected based on whether we're
12882 * currently in handler mode or not, using the NS CONTROL.SPSEL.
12884 bool spsel
= env
->v7m
.control
[M_REG_NS
] & R_V7M_CONTROL_SPSEL_MASK
;
12885 bool is_psp
= !arm_v7m_is_handler_mode(env
) && spsel
;
12888 if (!env
->v7m
.secure
) {
12892 limit
= is_psp
? env
->v7m
.psplim
[false] : env
->v7m
.msplim
[false];
12895 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
12897 cpu_restore_state(cs
, GETPC(), true);
12898 raise_exception(env
, EXCP_STKOF
, 0, 1);
12902 env
->v7m
.other_ss_psp
= val
;
12904 env
->v7m
.other_ss_msp
= val
;
12914 case 0 ... 7: /* xPSR sub-fields */
12915 /* only APSR is actually writable */
12917 uint32_t apsrmask
= 0;
12920 apsrmask
|= XPSR_NZCV
| XPSR_Q
;
12922 if ((mask
& 4) && arm_feature(env
, ARM_FEATURE_THUMB_DSP
)) {
12923 apsrmask
|= XPSR_GE
;
12925 xpsr_write(env
, val
, apsrmask
);
12929 if (v7m_using_psp(env
)) {
12930 env
->v7m
.other_sp
= val
;
12932 env
->regs
[13] = val
;
12936 if (v7m_using_psp(env
)) {
12937 env
->regs
[13] = val
;
12939 env
->v7m
.other_sp
= val
;
12942 case 10: /* MSPLIM */
12943 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
12946 env
->v7m
.msplim
[env
->v7m
.secure
] = val
& ~7;
12948 case 11: /* PSPLIM */
12949 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
12952 env
->v7m
.psplim
[env
->v7m
.secure
] = val
& ~7;
12954 case 16: /* PRIMASK */
12955 env
->v7m
.primask
[env
->v7m
.secure
] = val
& 1;
12957 case 17: /* BASEPRI */
12958 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
12961 env
->v7m
.basepri
[env
->v7m
.secure
] = val
& 0xff;
12963 case 18: /* BASEPRI_MAX */
12964 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
12968 if (val
!= 0 && (val
< env
->v7m
.basepri
[env
->v7m
.secure
]
12969 || env
->v7m
.basepri
[env
->v7m
.secure
] == 0)) {
12970 env
->v7m
.basepri
[env
->v7m
.secure
] = val
;
12973 case 19: /* FAULTMASK */
12974 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
12977 env
->v7m
.faultmask
[env
->v7m
.secure
] = val
& 1;
12979 case 20: /* CONTROL */
12981 * Writing to the SPSEL bit only has an effect if we are in
12982 * thread mode; other bits can be updated by any privileged code.
12983 * write_v7m_control_spsel() deals with updating the SPSEL bit in
12984 * env->v7m.control, so we only need update the others.
12985 * For v7M, we must just ignore explicit writes to SPSEL in handler
12986 * mode; for v8M the write is permitted but will have no effect.
12987 * All these bits are writes-ignored from non-privileged code,
12990 if (cur_el
> 0 && (arm_feature(env
, ARM_FEATURE_V8
) ||
12991 !arm_v7m_is_handler_mode(env
))) {
12992 write_v7m_control_spsel(env
, (val
& R_V7M_CONTROL_SPSEL_MASK
) != 0);
12994 if (cur_el
> 0 && arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
12995 env
->v7m
.control
[env
->v7m
.secure
] &= ~R_V7M_CONTROL_NPRIV_MASK
;
12996 env
->v7m
.control
[env
->v7m
.secure
] |= val
& R_V7M_CONTROL_NPRIV_MASK
;
12998 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
13000 * SFPA is RAZ/WI from NS or if no FPU.
13001 * FPCA is RO if NSACR.CP10 == 0, RES0 if the FPU is not present.
13002 * Both are stored in the S bank.
13004 if (env
->v7m
.secure
) {
13005 env
->v7m
.control
[M_REG_S
] &= ~R_V7M_CONTROL_SFPA_MASK
;
13006 env
->v7m
.control
[M_REG_S
] |= val
& R_V7M_CONTROL_SFPA_MASK
;
13009 (env
->v7m
.secure
|| !arm_feature(env
, ARM_FEATURE_M_SECURITY
) ||
13010 extract32(env
->v7m
.nsacr
, 10, 1))) {
13011 env
->v7m
.control
[M_REG_S
] &= ~R_V7M_CONTROL_FPCA_MASK
;
13012 env
->v7m
.control
[M_REG_S
] |= val
& R_V7M_CONTROL_FPCA_MASK
;
13018 qemu_log_mask(LOG_GUEST_ERROR
, "Attempt to write unknown special"
13019 " register %d\n", reg
);
13024 uint32_t HELPER(v7m_tt
)(CPUARMState
*env
, uint32_t addr
, uint32_t op
)
13026 /* Implement the TT instruction. op is bits [7:6] of the insn. */
13027 bool forceunpriv
= op
& 1;
13029 V8M_SAttributes sattrs
= {};
13031 bool r
, rw
, nsr
, nsrw
, mrvalid
;
13033 ARMMMUFaultInfo fi
= {};
13034 MemTxAttrs attrs
= {};
13039 bool targetsec
= env
->v7m
.secure
;
13042 /* Work out what the security state and privilege level we're
13043 * interested in is...
13046 targetsec
= !targetsec
;
13050 targetpriv
= false;
13052 targetpriv
= arm_v7m_is_handler_mode(env
) ||
13053 !(env
->v7m
.control
[targetsec
] & R_V7M_CONTROL_NPRIV_MASK
);
13056 /* ...and then figure out which MMU index this is */
13057 mmu_idx
= arm_v7m_mmu_idx_for_secstate_and_priv(env
, targetsec
, targetpriv
);
13059 /* We know that the MPU and SAU don't care about the access type
13060 * for our purposes beyond that we don't want to claim to be
13061 * an insn fetch, so we arbitrarily call this a read.
13064 /* MPU region info only available for privileged or if
13065 * inspecting the other MPU state.
13067 if (arm_current_el(env
) != 0 || alt
) {
13068 /* We can ignore the return value as prot is always set */
13069 pmsav8_mpu_lookup(env
, addr
, MMU_DATA_LOAD
, mmu_idx
,
13070 &phys_addr
, &attrs
, &prot
, &is_subpage
,
13072 if (mregion
== -1) {
13078 r
= prot
& PAGE_READ
;
13079 rw
= prot
& PAGE_WRITE
;
13087 if (env
->v7m
.secure
) {
13088 v8m_security_lookup(env
, addr
, MMU_DATA_LOAD
, mmu_idx
, &sattrs
);
13089 nsr
= sattrs
.ns
&& r
;
13090 nsrw
= sattrs
.ns
&& rw
;
13097 tt_resp
= (sattrs
.iregion
<< 24) |
13098 (sattrs
.irvalid
<< 23) |
13099 ((!sattrs
.ns
) << 22) |
13104 (sattrs
.srvalid
<< 17) |
13106 (sattrs
.sregion
<< 8) |
13114 void HELPER(dc_zva
)(CPUARMState
*env
, uint64_t vaddr_in
)
13116 /* Implement DC ZVA, which zeroes a fixed-length block of memory.
13117 * Note that we do not implement the (architecturally mandated)
13118 * alignment fault for attempts to use this on Device memory
13119 * (which matches the usual QEMU behaviour of not implementing either
13120 * alignment faults or any memory attribute handling).
13123 ARMCPU
*cpu
= arm_env_get_cpu(env
);
13124 uint64_t blocklen
= 4 << cpu
->dcz_blocksize
;
13125 uint64_t vaddr
= vaddr_in
& ~(blocklen
- 1);
13127 #ifndef CONFIG_USER_ONLY
13129 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
13130 * the block size so we might have to do more than one TLB lookup.
13131 * We know that in fact for any v8 CPU the page size is at least 4K
13132 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
13133 * 1K as an artefact of legacy v5 subpage support being present in the
13134 * same QEMU executable. So in practice the hostaddr[] array has
13135 * two entries, given the current setting of TARGET_PAGE_BITS_MIN.
13137 int maxidx
= DIV_ROUND_UP(blocklen
, TARGET_PAGE_SIZE
);
13138 void *hostaddr
[DIV_ROUND_UP(2 * KiB
, 1 << TARGET_PAGE_BITS_MIN
)];
13140 unsigned mmu_idx
= cpu_mmu_index(env
, false);
13141 TCGMemOpIdx oi
= make_memop_idx(MO_UB
, mmu_idx
);
13143 assert(maxidx
<= ARRAY_SIZE(hostaddr
));
13145 for (try = 0; try < 2; try++) {
13147 for (i
= 0; i
< maxidx
; i
++) {
13148 hostaddr
[i
] = tlb_vaddr_to_host(env
,
13149 vaddr
+ TARGET_PAGE_SIZE
* i
,
13151 if (!hostaddr
[i
]) {
13156 /* If it's all in the TLB it's fair game for just writing to;
13157 * we know we don't need to update dirty status, etc.
13159 for (i
= 0; i
< maxidx
- 1; i
++) {
13160 memset(hostaddr
[i
], 0, TARGET_PAGE_SIZE
);
13162 memset(hostaddr
[i
], 0, blocklen
- (i
* TARGET_PAGE_SIZE
));
13165 /* OK, try a store and see if we can populate the tlb. This
13166 * might cause an exception if the memory isn't writable,
13167 * in which case we will longjmp out of here. We must for
13168 * this purpose use the actual register value passed to us
13169 * so that we get the fault address right.
13171 helper_ret_stb_mmu(env
, vaddr_in
, 0, oi
, GETPC());
13172 /* Now we can populate the other TLB entries, if any */
13173 for (i
= 0; i
< maxidx
; i
++) {
13174 uint64_t va
= vaddr
+ TARGET_PAGE_SIZE
* i
;
13175 if (va
!= (vaddr_in
& TARGET_PAGE_MASK
)) {
13176 helper_ret_stb_mmu(env
, va
, 0, oi
, GETPC());
13181 /* Slow path (probably attempt to do this to an I/O device or
13182 * similar, or clearing of a block of code we have translations
13183 * cached for). Just do a series of byte writes as the architecture
13184 * demands. It's not worth trying to use a cpu_physical_memory_map(),
13185 * memset(), unmap() sequence here because:
13186 * + we'd need to account for the blocksize being larger than a page
13187 * + the direct-RAM access case is almost always going to be dealt
13188 * with in the fastpath code above, so there's no speed benefit
13189 * + we would have to deal with the map returning NULL because the
13190 * bounce buffer was in use
13192 for (i
= 0; i
< blocklen
; i
++) {
13193 helper_ret_stb_mmu(env
, vaddr
+ i
, 0, oi
, GETPC());
13197 memset(g2h(vaddr
), 0, blocklen
);
13201 /* Note that signed overflow is undefined in C. The following routines are
13202 careful to use unsigned types where modulo arithmetic is required.
13203 Failure to do so _will_ break on newer gcc. */
13205 /* Signed saturating arithmetic. */
13207 /* Perform 16-bit signed saturating addition. */
13208 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
13213 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
13222 /* Perform 8-bit signed saturating addition. */
13223 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
13228 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
13237 /* Perform 16-bit signed saturating subtraction. */
13238 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
13243 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
13252 /* Perform 8-bit signed saturating subtraction. */
13253 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
13258 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
13267 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
13268 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
13269 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
13270 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
13273 #include "op_addsub.h"
13275 /* Unsigned saturating arithmetic. */
13276 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
13285 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
13293 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
13302 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
13310 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
13311 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
13312 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
13313 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
13316 #include "op_addsub.h"
13318 /* Signed modulo arithmetic. */
13319 #define SARITH16(a, b, n, op) do { \
13321 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
13322 RESULT(sum, n, 16); \
13324 ge |= 3 << (n * 2); \
13327 #define SARITH8(a, b, n, op) do { \
13329 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
13330 RESULT(sum, n, 8); \
13336 #define ADD16(a, b, n) SARITH16(a, b, n, +)
13337 #define SUB16(a, b, n) SARITH16(a, b, n, -)
13338 #define ADD8(a, b, n) SARITH8(a, b, n, +)
13339 #define SUB8(a, b, n) SARITH8(a, b, n, -)
13343 #include "op_addsub.h"
13345 /* Unsigned modulo arithmetic. */
13346 #define ADD16(a, b, n) do { \
13348 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
13349 RESULT(sum, n, 16); \
13350 if ((sum >> 16) == 1) \
13351 ge |= 3 << (n * 2); \
13354 #define ADD8(a, b, n) do { \
13356 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
13357 RESULT(sum, n, 8); \
13358 if ((sum >> 8) == 1) \
13362 #define SUB16(a, b, n) do { \
13364 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
13365 RESULT(sum, n, 16); \
13366 if ((sum >> 16) == 0) \
13367 ge |= 3 << (n * 2); \
13370 #define SUB8(a, b, n) do { \
13372 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
13373 RESULT(sum, n, 8); \
13374 if ((sum >> 8) == 0) \
13381 #include "op_addsub.h"
13383 /* Halved signed arithmetic. */
13384 #define ADD16(a, b, n) \
13385 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
13386 #define SUB16(a, b, n) \
13387 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
13388 #define ADD8(a, b, n) \
13389 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
13390 #define SUB8(a, b, n) \
13391 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
13394 #include "op_addsub.h"
13396 /* Halved unsigned arithmetic. */
13397 #define ADD16(a, b, n) \
13398 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
13399 #define SUB16(a, b, n) \
13400 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
13401 #define ADD8(a, b, n) \
13402 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
13403 #define SUB8(a, b, n) \
13404 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
13407 #include "op_addsub.h"
13409 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
13417 /* Unsigned sum of absolute byte differences. */
13418 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
13421 sum
= do_usad(a
, b
);
13422 sum
+= do_usad(a
>> 8, b
>> 8);
13423 sum
+= do_usad(a
>> 16, b
>>16);
13424 sum
+= do_usad(a
>> 24, b
>> 24);
13428 /* For ARMv6 SEL instruction. */
13429 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
13441 mask
|= 0xff000000;
13442 return (a
& mask
) | (b
& ~mask
);
13446 * The upper bytes of val (above the number specified by 'bytes') must have
13447 * been zeroed out by the caller.
13449 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
13453 stl_le_p(buf
, val
);
13455 /* zlib crc32 converts the accumulator and output to one's complement. */
13456 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
13459 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
13463 stl_le_p(buf
, val
);
13465 /* Linux crc32c converts the output to one's complement. */
13466 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
13469 /* Return the exception level to which FP-disabled exceptions should
13470 * be taken, or 0 if FP is enabled.
13472 int fp_exception_el(CPUARMState
*env
, int cur_el
)
13474 #ifndef CONFIG_USER_ONLY
13477 /* CPACR and the CPTR registers don't exist before v6, so FP is
13478 * always accessible
13480 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
13484 if (arm_feature(env
, ARM_FEATURE_M
)) {
13485 /* CPACR can cause a NOCP UsageFault taken to current security state */
13486 if (!v7m_cpacr_pass(env
, env
->v7m
.secure
, cur_el
!= 0)) {
13490 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && !env
->v7m
.secure
) {
13491 if (!extract32(env
->v7m
.nsacr
, 10, 1)) {
13492 /* FP insns cause a NOCP UsageFault taken to Secure */
13500 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
13501 * 0, 2 : trap EL0 and EL1/PL1 accesses
13502 * 1 : trap only EL0 accesses
13503 * 3 : trap no accesses
13505 fpen
= extract32(env
->cp15
.cpacr_el1
, 20, 2);
13509 if (cur_el
== 0 || cur_el
== 1) {
13510 /* Trap to PL1, which might be EL1 or EL3 */
13511 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
13516 if (cur_el
== 3 && !is_a64(env
)) {
13517 /* Secure PL1 running at EL3 */
13530 /* For the CPTR registers we don't need to guard with an ARM_FEATURE
13531 * check because zero bits in the registers mean "don't trap".
13534 /* CPTR_EL2 : present in v7VE or v8 */
13535 if (cur_el
<= 2 && extract32(env
->cp15
.cptr_el
[2], 10, 1)
13536 && !arm_is_secure_below_el3(env
)) {
13537 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
13541 /* CPTR_EL3 : present in v8 */
13542 if (extract32(env
->cp15
.cptr_el
[3], 10, 1)) {
13543 /* Trap all FP ops to EL3 */
13550 ARMMMUIdx
arm_v7m_mmu_idx_all(CPUARMState
*env
,
13551 bool secstate
, bool priv
, bool negpri
)
13553 ARMMMUIdx mmu_idx
= ARM_MMU_IDX_M
;
13556 mmu_idx
|= ARM_MMU_IDX_M_PRIV
;
13560 mmu_idx
|= ARM_MMU_IDX_M_NEGPRI
;
13564 mmu_idx
|= ARM_MMU_IDX_M_S
;
13570 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState
*env
,
13571 bool secstate
, bool priv
)
13573 bool negpri
= armv7m_nvic_neg_prio_requested(env
->nvic
, secstate
);
13575 return arm_v7m_mmu_idx_all(env
, secstate
, priv
, negpri
);
13578 /* Return the MMU index for a v7M CPU in the specified security state */
13579 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
13581 bool priv
= arm_current_el(env
) != 0;
13583 return arm_v7m_mmu_idx_for_secstate_and_priv(env
, secstate
, priv
);
13586 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
)
13590 if (arm_feature(env
, ARM_FEATURE_M
)) {
13591 return arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
13594 el
= arm_current_el(env
);
13595 if (el
< 2 && arm_is_secure_below_el3(env
)) {
13596 return ARMMMUIdx_S1SE0
+ el
;
13598 return ARMMMUIdx_S12NSE0
+ el
;
13602 int cpu_mmu_index(CPUARMState
*env
, bool ifetch
)
13604 return arm_to_core_mmu_idx(arm_mmu_idx(env
));
13607 #ifndef CONFIG_USER_ONLY
13608 ARMMMUIdx
arm_stage1_mmu_idx(CPUARMState
*env
)
13610 return stage_1_mmu_idx(arm_mmu_idx(env
));
13614 void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
13615 target_ulong
*cs_base
, uint32_t *pflags
)
13617 ARMMMUIdx mmu_idx
= arm_mmu_idx(env
);
13618 int current_el
= arm_current_el(env
);
13619 int fp_el
= fp_exception_el(env
, current_el
);
13620 uint32_t flags
= 0;
13623 ARMCPU
*cpu
= arm_env_get_cpu(env
);
13627 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, AARCH64_STATE
, 1);
13629 /* Get control bits for tagged addresses. */
13631 ARMMMUIdx stage1
= stage_1_mmu_idx(mmu_idx
);
13632 ARMVAParameters p0
= aa64_va_parameters_both(env
, 0, stage1
);
13635 /* FIXME: ARMv8.1-VHE S2 translation regime. */
13636 if (regime_el(env
, stage1
) < 2) {
13637 ARMVAParameters p1
= aa64_va_parameters_both(env
, -1, stage1
);
13638 tbid
= (p1
.tbi
<< 1) | p0
.tbi
;
13639 tbii
= tbid
& ~((p1
.tbid
<< 1) | p0
.tbid
);
13642 tbii
= tbid
& !p0
.tbid
;
13645 flags
= FIELD_DP32(flags
, TBFLAG_A64
, TBII
, tbii
);
13646 flags
= FIELD_DP32(flags
, TBFLAG_A64
, TBID
, tbid
);
13649 if (cpu_isar_feature(aa64_sve
, cpu
)) {
13650 int sve_el
= sve_exception_el(env
, current_el
);
13653 /* If SVE is disabled, but FP is enabled,
13654 * then the effective len is 0.
13656 if (sve_el
!= 0 && fp_el
== 0) {
13659 zcr_len
= sve_zcr_len_for_el(env
, current_el
);
13661 flags
= FIELD_DP32(flags
, TBFLAG_A64
, SVEEXC_EL
, sve_el
);
13662 flags
= FIELD_DP32(flags
, TBFLAG_A64
, ZCR_LEN
, zcr_len
);
13665 sctlr
= arm_sctlr(env
, current_el
);
13667 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
13669 * In order to save space in flags, we record only whether
13670 * pauth is "inactive", meaning all insns are implemented as
13671 * a nop, or "active" when some action must be performed.
13672 * The decision of which action to take is left to a helper.
13674 if (sctlr
& (SCTLR_EnIA
| SCTLR_EnIB
| SCTLR_EnDA
| SCTLR_EnDB
)) {
13675 flags
= FIELD_DP32(flags
, TBFLAG_A64
, PAUTH_ACTIVE
, 1);
13679 if (cpu_isar_feature(aa64_bti
, cpu
)) {
13680 /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
13681 if (sctlr
& (current_el
== 0 ? SCTLR_BT0
: SCTLR_BT1
)) {
13682 flags
= FIELD_DP32(flags
, TBFLAG_A64
, BT
, 1);
13684 flags
= FIELD_DP32(flags
, TBFLAG_A64
, BTYPE
, env
->btype
);
13687 *pc
= env
->regs
[15];
13688 flags
= FIELD_DP32(flags
, TBFLAG_A32
, THUMB
, env
->thumb
);
13689 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VECLEN
, env
->vfp
.vec_len
);
13690 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VECSTRIDE
, env
->vfp
.vec_stride
);
13691 flags
= FIELD_DP32(flags
, TBFLAG_A32
, CONDEXEC
, env
->condexec_bits
);
13692 flags
= FIELD_DP32(flags
, TBFLAG_A32
, SCTLR_B
, arm_sctlr_b(env
));
13693 flags
= FIELD_DP32(flags
, TBFLAG_A32
, NS
, !access_secure_reg(env
));
13694 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)
13695 || arm_el_is_aa64(env
, 1) || arm_feature(env
, ARM_FEATURE_M
)) {
13696 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VFPEN
, 1);
13698 /* Note that XSCALE_CPAR shares bits with VECSTRIDE */
13699 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
13700 flags
= FIELD_DP32(flags
, TBFLAG_A32
,
13701 XSCALE_CPAR
, env
->cp15
.c15_cpar
);
13705 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, MMUIDX
, arm_to_core_mmu_idx(mmu_idx
));
13707 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
13708 * states defined in the ARM ARM for software singlestep:
13709 * SS_ACTIVE PSTATE.SS State
13710 * 0 x Inactive (the TB flag for SS is always 0)
13711 * 1 0 Active-pending
13712 * 1 1 Active-not-pending
13714 if (arm_singlestep_active(env
)) {
13715 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, SS_ACTIVE
, 1);
13717 if (env
->pstate
& PSTATE_SS
) {
13718 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, PSTATE_SS
, 1);
13721 if (env
->uncached_cpsr
& PSTATE_SS
) {
13722 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, PSTATE_SS
, 1);
13726 if (arm_cpu_data_is_big_endian(env
)) {
13727 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, BE_DATA
, 1);
13729 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, FPEXC_EL
, fp_el
);
13731 if (arm_v7m_is_handler_mode(env
)) {
13732 flags
= FIELD_DP32(flags
, TBFLAG_A32
, HANDLER
, 1);
13735 /* v8M always applies stack limit checks unless CCR.STKOFHFNMIGN is
13736 * suppressing them because the requested execution priority is less than 0.
13738 if (arm_feature(env
, ARM_FEATURE_V8
) &&
13739 arm_feature(env
, ARM_FEATURE_M
) &&
13740 !((mmu_idx
& ARM_MMU_IDX_M_NEGPRI
) &&
13741 (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_STKOFHFNMIGN_MASK
))) {
13742 flags
= FIELD_DP32(flags
, TBFLAG_A32
, STACKCHECK
, 1);
13745 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
13746 FIELD_EX32(env
->v7m
.fpccr
[M_REG_S
], V7M_FPCCR
, S
) != env
->v7m
.secure
) {
13747 flags
= FIELD_DP32(flags
, TBFLAG_A32
, FPCCR_S_WRONG
, 1);
13750 if (arm_feature(env
, ARM_FEATURE_M
) &&
13751 (env
->v7m
.fpccr
[env
->v7m
.secure
] & R_V7M_FPCCR_ASPEN_MASK
) &&
13752 (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) ||
13753 (env
->v7m
.secure
&&
13754 !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)))) {
13756 * ASPEN is set, but FPCA/SFPA indicate that there is no active
13757 * FP context; we must create a new FP context before executing
13760 flags
= FIELD_DP32(flags
, TBFLAG_A32
, NEW_FP_CTXT_NEEDED
, 1);
13763 if (arm_feature(env
, ARM_FEATURE_M
)) {
13764 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
13766 if (env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
13767 flags
= FIELD_DP32(flags
, TBFLAG_A32
, LSPACT
, 1);
13775 #ifdef TARGET_AARCH64
13777 * The manual says that when SVE is enabled and VQ is widened the
13778 * implementation is allowed to zero the previously inaccessible
13779 * portion of the registers. The corollary to that is that when
13780 * SVE is enabled and VQ is narrowed we are also allowed to zero
13781 * the now inaccessible portion of the registers.
13783 * The intent of this is that no predicate bit beyond VQ is ever set.
13784 * Which means that some operations on predicate registers themselves
13785 * may operate on full uint64_t or even unrolled across the maximum
13786 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
13787 * may well be cheaper than conditionals to restrict the operation
13788 * to the relevant portion of a uint16_t[16].
13790 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
13795 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
13796 assert(vq
<= arm_env_get_cpu(env
)->sve_max_vq
);
13798 /* Zap the high bits of the zregs. */
13799 for (i
= 0; i
< 32; i
++) {
13800 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
13803 /* Zap the high bits of the pregs and ffr. */
13806 pmask
= ~(-1ULL << (16 * (vq
& 3)));
13808 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
13809 for (i
= 0; i
< 17; ++i
) {
13810 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
13817 * Notice a change in SVE vector size when changing EL.
13819 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
,
13820 int new_el
, bool el0_a64
)
13822 ARMCPU
*cpu
= arm_env_get_cpu(env
);
13823 int old_len
, new_len
;
13824 bool old_a64
, new_a64
;
13826 /* Nothing to do if no SVE. */
13827 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
13831 /* Nothing to do if FP is disabled in either EL. */
13832 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
13837 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
13838 * at ELx, or not available because the EL is in AArch32 state, then
13839 * for all purposes other than a direct read, the ZCR_ELx.LEN field
13840 * has an effective value of 0".
13842 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
13843 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
13844 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
13845 * we already have the correct register contents when encountering the
13846 * vq0->vq0 transition between EL0->EL1.
13848 old_a64
= old_el
? arm_el_is_aa64(env
, old_el
) : el0_a64
;
13849 old_len
= (old_a64
&& !sve_exception_el(env
, old_el
)
13850 ? sve_zcr_len_for_el(env
, old_el
) : 0);
13851 new_a64
= new_el
? arm_el_is_aa64(env
, new_el
) : el0_a64
;
13852 new_len
= (new_a64
&& !sve_exception_el(env
, new_el
)
13853 ? sve_zcr_len_for_el(env
, new_el
) : 0);
13855 /* When changing vector length, clear inaccessible state. */
13856 if (new_len
< old_len
) {
13857 aarch64_sve_narrow_vq(env
, new_len
+ 1);