hw/ppc/sam460ex.c

   1 /*
   2  * QEMU aCube Sam460ex board emulation
   3  *
   4  * Copyright (c) 2012 François Revol
   5  * Copyright (c) 2016-2019 BALATON Zoltan
   6  *
   7  * This file is derived from hw/ppc440_bamboo.c,
   8  * the copyright for that material belongs to the original owners.
   9  *
  10  * This work is licensed under the GNU GPL license version 2 or later.
  11  *
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "qemu/units.h"
  16 #include "qemu/datadir.h"
  17 #include "qemu/error-report.h"
  18 #include "qapi/error.h"
  19 #include "hw/boards.h"
  20 #include "sysemu/kvm.h"
  21 #include "kvm_ppc.h"
  22 #include "sysemu/device_tree.h"
  23 #include "sysemu/block-backend.h"
  24 #include "hw/loader.h"
  25 #include "elf.h"
  26 #include "exec/memory.h"
  27 #include "ppc440.h"
  28 #include "hw/pci-host/ppc4xx.h"
  29 #include "hw/block/flash.h"
  30 #include "sysemu/sysemu.h"
  31 #include "sysemu/reset.h"
  32 #include "hw/sysbus.h"
  33 #include "hw/char/serial.h"
  34 #include "hw/i2c/ppc4xx_i2c.h"
  35 #include "hw/i2c/smbus_eeprom.h"
  36 #include "hw/usb/hcd-ehci.h"
  37 #include "hw/ppc/fdt.h"
  38 #include "hw/qdev-properties.h"
  39 #include "hw/intc/ppc-uic.h"
  40
  41 #include <libfdt.h>
  42
  43 #define BINARY_DEVICE_TREE_FILE "canyonlands.dtb"
  44 #define UBOOT_FILENAME "u-boot-sam460-20100605.bin"
  45 /* to extract the official U-Boot bin from the updater: */
  46 /* dd bs=1 skip=$(($(stat -c '%s' updater/updater-460) - 0x80000)) \
  47      if=updater/updater-460 of=u-boot-sam460-20100605.bin */
  48
  49 #define PCIE0_DCRN_BASE 0x100
  50 #define PCIE1_DCRN_BASE 0x120
  51
  52 /* from Sam460 U-Boot include/configs/Sam460ex.h */
  53 #define FLASH_BASE             0xfff00000
  54 #define FLASH_BASE_H           0x4
  55 #define FLASH_SIZE             (1 * MiB)
  56 #define UBOOT_LOAD_BASE        0xfff80000
  57 #define UBOOT_SIZE             0x00080000
  58 #define UBOOT_ENTRY            0xfffffffc
  59
  60 /* from U-Boot */
  61 #define EPAPR_MAGIC           (0x45504150)
  62 #define KERNEL_ADDR           0x1000000
  63 #define FDT_ADDR              0x1800000
  64 #define RAMDISK_ADDR          0x1900000
  65
  66 /* Sam460ex IRQ MAP:
  67    IRQ0  = ETH_INT
  68    IRQ1  = FPGA_INT
  69    IRQ2  = PCI_INT (PCIA, PCIB, PCIC, PCIB)
  70    IRQ3  = FPGA_INT2
  71    IRQ11 = RTC_INT
  72    IRQ12 = SM502_INT
  73 */
  74
  75 #define CPU_FREQ 1150000000
  76 #define PLB_FREQ 230000000
  77 #define OPB_FREQ 115000000
  78 #define EBC_FREQ 115000000
  79 #define UART_FREQ 11059200
  80
  81 struct boot_info {
  82     uint32_t dt_base;
  83     uint32_t dt_size;
  84     uint32_t entry;
  85 };
  86
  87 static int sam460ex_load_uboot(void)
  88 {
  89     /*
  90      * This first creates 1MiB of flash memory mapped at the end of
  91      * the 32-bit address space (0xFFF00000..0xFFFFFFFF).
  92      *
  93      * If_PFLASH unit 0 is defined, the flash memory is initialized
  94      * from that block backend.
  95      *
  96      * Else, it's initialized to zero.  And then 512KiB of ROM get
  97      * mapped on top of its second half (0xFFF80000..0xFFFFFFFF),
  98      * initialized from u-boot-sam460-20100605.bin.
  99      *
 100      * This doesn't smell right.
 101      *
 102      * The physical hardware appears to have 512KiB flash memory.
 103      *
 104      * TODO Figure out what we really need here, and clean this up.
 105      */
 106
 107     DriveInfo *dinfo;
 108
 109     dinfo = drive_get(IF_PFLASH, 0, 0);
 110     if (!pflash_cfi01_register(FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32),
 111                                "sam460ex.flash", FLASH_SIZE,
 112                                dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 113                                64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1)) {
 114         error_report("Error registering flash memory");
 115         /* XXX: return an error instead? */
 116         exit(1);
 117     }
 118
 119     if (!dinfo) {
 120         /*error_report("No flash image given with the 'pflash' parameter,"
 121                 " using default u-boot image");*/
 122         rom_add_file_fixed(UBOOT_FILENAME,
 123                            UBOOT_LOAD_BASE | ((hwaddr)FLASH_BASE_H << 32),
 124                            -1);
 125     }
 126
 127     return 0;
 128 }
 129
 130 static int sam460ex_load_device_tree(MachineState *machine,
 131                                      hwaddr addr,
 132                                      hwaddr initrd_base,
 133                                      hwaddr initrd_size)
 134 {
 135     uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(machine->ram_size) };
 136     char *filename;
 137     int fdt_size;
 138     void *fdt;
 139     uint32_t tb_freq = CPU_FREQ;
 140     uint32_t clock_freq = CPU_FREQ;
 141     int offset;
 142
 143     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
 144     if (!filename) {
 145         error_report("Couldn't find dtb file `%s'", BINARY_DEVICE_TREE_FILE);
 146         exit(1);
 147     }
 148     fdt = load_device_tree(filename, &fdt_size);
 149     if (!fdt) {
 150         error_report("Couldn't load dtb file `%s'", filename);
 151         g_free(filename);
 152         exit(1);
 153     }
 154     g_free(filename);
 155
 156     /* Manipulate device tree in memory. */
 157
 158     qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
 159                      sizeof(mem_reg_property));
 160
 161     /* default FDT doesn't have a /chosen node... */
 162     qemu_fdt_add_subnode(fdt, "/chosen");
 163
 164     qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", initrd_base);
 165
 166     qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
 167                           (initrd_base + initrd_size));
 168
 169     qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
 170                             machine->kernel_cmdline);
 171
 172     /* Copy data from the host device tree into the guest. Since the guest can
 173      * directly access the timebase without host involvement, we must expose
 174      * the correct frequencies. */
 175     if (kvm_enabled()) {
 176         tb_freq = kvmppc_get_tbfreq();
 177         clock_freq = kvmppc_get_clockfreq();
 178     }
 179
 180     qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency",
 181                               clock_freq);
 182     qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency",
 183                               tb_freq);
 184
 185     /* Remove cpm node if it exists (it is not emulated) */
 186     offset = fdt_path_offset(fdt, "/cpm");
 187     if (offset >= 0) {
 188         _FDT(fdt_nop_node(fdt, offset));
 189     }
 190
 191     /* set serial port clocks */
 192     offset = fdt_node_offset_by_compatible(fdt, -1, "ns16550");
 193     while (offset >= 0) {
 194         _FDT(fdt_setprop_cell(fdt, offset, "clock-frequency", UART_FREQ));
 195         offset = fdt_node_offset_by_compatible(fdt, offset, "ns16550");
 196     }
 197
 198     /* some more clocks */
 199     qemu_fdt_setprop_cell(fdt, "/plb", "clock-frequency",
 200                               PLB_FREQ);
 201     qemu_fdt_setprop_cell(fdt, "/plb/opb", "clock-frequency",
 202                               OPB_FREQ);
 203     qemu_fdt_setprop_cell(fdt, "/plb/opb/ebc", "clock-frequency",
 204                               EBC_FREQ);
 205
 206     rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
 207
 208     /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
 209     machine->fdt = fdt;
 210
 211     return fdt_size;
 212 }
 213
 214 /* Create reset TLB entries for BookE, mapping only the flash memory.  */
 215 static void mmubooke_create_initial_mapping_uboot(CPUPPCState *env)
 216 {
 217     ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
 218
 219     /* on reset the flash is mapped by a shadow TLB,
 220      * but since we don't implement them we need to use
 221      * the same values U-Boot will use to avoid a fault.
 222      */
 223     tlb->attr = 0;
 224     tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
 225     tlb->size = 0x10000000; /* up to 0xffffffff  */
 226     tlb->EPN = 0xf0000000 & TARGET_PAGE_MASK;
 227     tlb->RPN = (0xf0000000 & TARGET_PAGE_MASK) | 0x4;
 228     tlb->PID = 0;
 229 }
 230
 231 /* Create reset TLB entries for BookE, spanning the 32bit addr space.  */
 232 static void mmubooke_create_initial_mapping(CPUPPCState *env,
 233                                      target_ulong va,
 234                                      hwaddr pa)
 235 {
 236     ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
 237
 238     tlb->attr = 0;
 239     tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
 240     tlb->size = 1 << 31; /* up to 0x80000000  */
 241     tlb->EPN = va & TARGET_PAGE_MASK;
 242     tlb->RPN = pa & TARGET_PAGE_MASK;
 243     tlb->PID = 0;
 244 }
 245
 246 static void main_cpu_reset(void *opaque)
 247 {
 248     PowerPCCPU *cpu = opaque;
 249     CPUPPCState *env = &cpu->env;
 250     struct boot_info *bi = env->load_info;
 251
 252     cpu_reset(CPU(cpu));
 253
 254     /* either we have a kernel to boot or we jump to U-Boot */
 255     if (bi->entry != UBOOT_ENTRY) {
 256         env->gpr[1] = (16 * MiB) - 8;
 257         env->gpr[3] = FDT_ADDR;
 258         env->nip = bi->entry;
 259
 260         /* Create a mapping for the kernel.  */
 261         mmubooke_create_initial_mapping(env, 0, 0);
 262         env->gpr[6] = tswap32(EPAPR_MAGIC);
 263         env->gpr[7] = (16 * MiB) - 8; /* bi->ima_size; */
 264
 265     } else {
 266         env->nip = UBOOT_ENTRY;
 267         mmubooke_create_initial_mapping_uboot(env);
 268     }
 269 }
 270
 271 static void sam460ex_init(MachineState *machine)
 272 {
 273     MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
 274     DeviceState *uic[4];
 275     int i;
 276     PCIBus *pci_bus;
 277     PowerPCCPU *cpu;
 278     CPUPPCState *env;
 279     I2CBus *i2c;
 280     hwaddr entry = UBOOT_ENTRY;
 281     target_long initrd_size = 0;
 282     DeviceState *dev;
 283     SysBusDevice *sbdev;
 284     struct boot_info *boot_info;
 285     uint8_t *spd_data;
 286     int success;
 287
 288     cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
 289     env = &cpu->env;
 290     if (env->mmu_model != POWERPC_MMU_BOOKE) {
 291         error_report("Only MMU model BookE is supported by this machine.");
 292         exit(1);
 293     }
 294
 295     qemu_register_reset(main_cpu_reset, cpu);
 296     boot_info = g_malloc0(sizeof(*boot_info));
 297     env->load_info = boot_info;
 298
 299     ppc_booke_timers_init(cpu, CPU_FREQ, 0);
 300     ppc_dcr_init(env, NULL, NULL);
 301
 302     /* PLB arbitrer */
 303     dev = qdev_new(TYPE_PPC4xx_PLB);
 304     ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
 305     object_unref(OBJECT(dev));
 306
 307     /* interrupt controllers */
 308     for (i = 0; i < ARRAY_SIZE(uic); i++) {
 309         /*
 310          * UICs 1, 2 and 3 are cascaded through UIC 0.
 311          * input_ints[n] is the interrupt number on UIC 0 which
 312          * the INT output of UIC n is connected to. The CINT output
 313          * of UIC n connects to input_ints[n] + 1.
 314          * The entry in input_ints[] for UIC 0 is ignored, because UIC 0's
 315          * INT and CINT outputs are connected to the CPU.
 316          */
 317         const int input_ints[] = { -1, 30, 10, 16 };
 318
 319         uic[i] = qdev_new(TYPE_PPC_UIC);
 320         qdev_prop_set_uint32(uic[i], "dcr-base", 0xc0 + i * 0x10);
 321         ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uic[i]), cpu, &error_fatal);
 322         object_unref(OBJECT(uic[i]));
 323
 324         sbdev = SYS_BUS_DEVICE(uic[i]);
 325         if (i == 0) {
 326             sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_INT,
 327                              qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT));
 328             sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_CINT,
 329                              qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
 330         } else {
 331             sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_INT,
 332                                qdev_get_gpio_in(uic[0], input_ints[i]));
 333             sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_CINT,
 334                                qdev_get_gpio_in(uic[0], input_ints[i] + 1));
 335         }
 336     }
 337
 338     /* SDRAM controller */
 339     /* The SoC could also handle 4 GiB but firmware does not work with that. */
 340     if (machine->ram_size > 2 * GiB) {
 341         error_report("Memory over 2 GiB is not supported");
 342         exit(1);
 343     }
 344     /* Firmware needs at least 64 MiB */
 345     if (machine->ram_size < 64 * MiB) {
 346         error_report("Memory below 64 MiB is not supported");
 347         exit(1);
 348     }
 349     dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR2);
 350     object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram),
 351                              &error_abort);
 352     /*
 353      * Put all RAM on first bank because board has one slot
 354      * and firmware only checks that
 355      */
 356     object_property_set_int(OBJECT(dev), "nbanks", 1, &error_abort);
 357     ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
 358     object_unref(OBJECT(dev));
 359     /* FIXME: does 460EX have ECC interrupts? */
 360     /* Enable SDRAM memory regions as we may boot without firmware */
 361     ppc4xx_sdram_ddr2_enable(PPC4xx_SDRAM_DDR2(dev));
 362
 363     /* IIC controllers and devices */
 364     dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700,
 365                                qdev_get_gpio_in(uic[0], 2));
 366     i2c = PPC4xx_I2C(dev)->bus;
 367     /* SPD EEPROM on RAM module */
 368     spd_data = spd_data_generate(machine->ram_size < 128 * MiB ? DDR : DDR2,
 369                                  machine->ram_size);
 370     spd_data[20] = 4; /* SO-DIMM module */
 371     smbus_eeprom_init_one(i2c, 0x50, spd_data);
 372     /* RTC */
 373     i2c_slave_create_simple(i2c, "m41t80", 0x68);
 374
 375     dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800,
 376                                qdev_get_gpio_in(uic[0], 3));
 377
 378     /* External bus controller */
 379     dev = qdev_new(TYPE_PPC4xx_EBC);
 380     ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
 381     object_unref(OBJECT(dev));
 382
 383     /* CPR */
 384     ppc4xx_cpr_init(env);
 385
 386     /* PLB to AHB bridge */
 387     ppc4xx_ahb_init(env);
 388
 389     /* System DCRs */
 390     ppc4xx_sdr_init(env);
 391
 392     /* MAL */
 393     dev = qdev_new(TYPE_PPC4xx_MAL);
 394     qdev_prop_set_uint8(dev, "txc-num", 4);
 395     qdev_prop_set_uint8(dev, "rxc-num", 16);
 396     ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
 397     object_unref(OBJECT(dev));
 398     sbdev = SYS_BUS_DEVICE(dev);
 399     for (i = 0; i < ARRAY_SIZE(PPC4xx_MAL(dev)->irqs); i++) {
 400         sysbus_connect_irq(sbdev, i, qdev_get_gpio_in(uic[2], 3 + i));
 401     }
 402
 403     /* DMA */
 404     ppc4xx_dma_init(env, 0x200);
 405
 406     /* 256K of L2 cache as memory */
 407     ppc4xx_l2sram_init(env);
 408     /* FIXME: remove this after fixing l2sram mapping in ppc440_uc.c? */
 409     memory_region_init_ram(l2cache_ram, NULL, "ppc440.l2cache_ram", 256 * KiB,
 410                            &error_abort);
 411     memory_region_add_subregion(get_system_memory(), 0x400000000LL,
 412                                 l2cache_ram);
 413
 414     /* USB */
 415     sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400,
 416                          qdev_get_gpio_in(uic[2], 29));
 417     dev = qdev_new("sysbus-ohci");
 418     qdev_prop_set_string(dev, "masterbus", "usb-bus.0");
 419     qdev_prop_set_uint32(dev, "num-ports", 6);
 420     sbdev = SYS_BUS_DEVICE(dev);
 421     sysbus_realize_and_unref(sbdev, &error_fatal);
 422     sysbus_mmio_map(sbdev, 0, 0x4bffd0000);
 423     sysbus_connect_irq(sbdev, 0, qdev_get_gpio_in(uic[2], 30));
 424     usb_create_simple(usb_bus_find(-1), "usb-kbd");
 425     usb_create_simple(usb_bus_find(-1), "usb-mouse");
 426
 427     /* PCIe buses */
 428     dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
 429     qdev_prop_set_int32(dev, "busnum", 0);
 430     qdev_prop_set_int32(dev, "dcrn-base", PCIE0_DCRN_BASE);
 431     object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
 432     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 433
 434     dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
 435     qdev_prop_set_int32(dev, "busnum", 1);
 436     qdev_prop_set_int32(dev, "dcrn-base", PCIE1_DCRN_BASE);
 437     object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
 438     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 439
 440     /* PCI bus */
 441     /* All PCI irqs are connected to the same UIC pin (cf. UBoot source) */
 442     dev = sysbus_create_simple(TYPE_PPC440_PCIX_HOST, 0xc0ec00000,
 443                                qdev_get_gpio_in(uic[1], 0));
 444     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, 0xc08000000);
 445     pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
 446
 447     /* PCI devices */
 448     pci_create_simple(pci_bus, PCI_DEVFN(6, 0), "sm501");
 449     /* SoC has a single SATA port but we don't emulate that yet
 450      * However, firmware and usual clients have driver for SiI311x
 451      * so add one for convenience by default */
 452     if (defaults_enabled()) {
 453         pci_create_simple(pci_bus, -1, "sii3112");
 454     }
 455
 456     /* SoC has 4 UARTs
 457      * but board has only one wired and two are present in fdt */
 458     if (serial_hd(0) != NULL) {
 459         serial_mm_init(get_system_memory(), 0x4ef600300, 0,
 460                        qdev_get_gpio_in(uic[1], 1),
 461                        PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
 462                        DEVICE_BIG_ENDIAN);
 463     }
 464     if (serial_hd(1) != NULL) {
 465         serial_mm_init(get_system_memory(), 0x4ef600400, 0,
 466                        qdev_get_gpio_in(uic[0], 1),
 467                        PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
 468                        DEVICE_BIG_ENDIAN);
 469     }
 470
 471     /* Load U-Boot image. */
 472     if (!machine->kernel_filename) {
 473         success = sam460ex_load_uboot();
 474         if (success < 0) {
 475             error_report("could not load firmware");
 476             exit(1);
 477         }
 478     }
 479
 480     /* Load kernel. */
 481     if (machine->kernel_filename) {
 482         hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID;
 483         success = load_uimage(machine->kernel_filename, &entry, &loadaddr,
 484                               NULL, NULL, NULL);
 485         if (success < 0) {
 486             uint64_t elf_entry;
 487
 488             success = load_elf(machine->kernel_filename, NULL, NULL, NULL,
 489                                &elf_entry, NULL, NULL, NULL,
 490                                1, PPC_ELF_MACHINE, 0, 0);
 491             entry = elf_entry;
 492         }
 493         /* XXX try again as binary */
 494         if (success < 0) {
 495             error_report("could not load kernel '%s'",
 496                     machine->kernel_filename);
 497             exit(1);
 498         }
 499     }
 500
 501     /* Load initrd. */
 502     if (machine->initrd_filename) {
 503         initrd_size = load_image_targphys(machine->initrd_filename,
 504                                           RAMDISK_ADDR,
 505                                           machine->ram_size - RAMDISK_ADDR);
 506         if (initrd_size < 0) {
 507             error_report("could not load ram disk '%s' at %x",
 508                     machine->initrd_filename, RAMDISK_ADDR);
 509             exit(1);
 510         }
 511     }
 512
 513     /* If we're loading a kernel directly, we must load the device tree too. */
 514     if (machine->kernel_filename) {
 515         int dt_size;
 516
 517         dt_size = sam460ex_load_device_tree(machine, FDT_ADDR,
 518                                             RAMDISK_ADDR, initrd_size);
 519
 520         boot_info->dt_base = FDT_ADDR;
 521         boot_info->dt_size = dt_size;
 522     }
 523
 524     boot_info->entry = entry;
 525 }
 526
 527 static void sam460ex_machine_init(MachineClass *mc)
 528 {
 529     mc->desc = "aCube Sam460ex";
 530     mc->init = sam460ex_init;
 531     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb");
 532     mc->default_ram_size = 512 * MiB;
 533     mc->default_ram_id = "ppc4xx.sdram";
 534 }
 535
 536 DEFINE_MACHINE("sam460ex", sam460ex_machine_init)