?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
nsis: Add missing qemu-nbd.exe
[qemu/ar7.git] / softmmu / memory.c
blob50b5fe5f22afe08bf0598f95a80a2f2ba09eeede
1 /*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
14 */
15
16 #include "qemu/osdep.h"
17 #include "qemu/log.h"
18 #include "qapi/error.h"
19 #include "cpu.h"
20 #include "exec/exec-all.h" /* qemu_sprint_backtrace */
21 #include "exec/memory.h"
22 #include "exec/address-spaces.h"
23 #include "qapi/visitor.h"
24 #include "qemu/bitops.h"
25 #include "qemu/error-report.h"
26 #include "qemu/main-loop.h"
27 #include "qemu/qemu-print.h"
28 #include "qemu-common.h" /* trace_unassigned */
29 #include "qom/object.h"
30 #include "trace.h"
31
32 #include "exec/memory-internal.h"
33 #include "exec/ram_addr.h"
34 #include "sysemu/kvm.h"
35 #include "sysemu/runstate.h"
36 #include "sysemu/tcg.h"
37 #include "qemu/accel.h"
38 #include "hw/boards.h"
39 #include "migration/vmstate.h"
40
41 //#define DEBUG_UNASSIGNED
42
43 static unsigned memory_region_transaction_depth;
44 static bool memory_region_update_pending;
45 static bool ioeventfd_update_pending;
46 bool global_dirty_log;
47
48 static QTAILQ_HEAD(, MemoryListener) memory_listeners
49 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
50
51 static QTAILQ_HEAD(, AddressSpace) address_spaces
52 = QTAILQ_HEAD_INITIALIZER(address_spaces);
53
54 static GHashTable *flat_views;
55
56 typedef struct AddrRange AddrRange;
57
58 /*
59 * Note that signed integers are needed for negative offsetting in aliases
60 * (large MemoryRegion::alias_offset).
61 */
62 struct AddrRange {
63 Int128 start;
64 Int128 size;
65 };
66
67 static AddrRange addrrange_make(Int128 start, Int128 size)
68 {
69 return (AddrRange) { start, size };
70 }
71
72 static bool addrrange_equal(AddrRange r1, AddrRange r2)
73 {
74 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
75 }
76
77 static Int128 addrrange_end(AddrRange r)
78 {
79 return int128_add(r.start, r.size);
80 }
81
82 static AddrRange addrrange_shift(AddrRange range, Int128 delta)
83 {
84 int128_addto(&range.start, delta);
85 return range;
86 }
87
88 static bool addrrange_contains(AddrRange range, Int128 addr)
89 {
90 return int128_ge(addr, range.start)
91 && int128_lt(addr, addrrange_end(range));
92 }
93
94 static bool addrrange_intersects(AddrRange r1, AddrRange r2)
95 {
96 return addrrange_contains(r1, r2.start)
97 || addrrange_contains(r2, r1.start);
98 }
99
100 static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
101 {
102 Int128 start = int128_max(r1.start, r2.start);
103 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
104 return addrrange_make(start, int128_sub(end, start));
105 }
106
107 enum ListenerDirection { Forward, Reverse };
108
109 #define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
110 do { \
111 MemoryListener *_listener; \
112 \
113 switch (_direction) { \
114 case Forward: \
115 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
116 if (_listener->_callback) { \
117 _listener->_callback(_listener, ##_args); \
118 } \
119 } \
120 break; \
121 case Reverse: \
122 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, link) { \
123 if (_listener->_callback) { \
124 _listener->_callback(_listener, ##_args); \
125 } \
126 } \
127 break; \
128 default: \
129 abort(); \
130 } \
131 } while (0)
132
133 #define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
134 do { \
135 MemoryListener *_listener; \
136 \
137 switch (_direction) { \
138 case Forward: \
139 QTAILQ_FOREACH(_listener, &(_as)->listeners, link_as) { \
140 if (_listener->_callback) { \
141 _listener->_callback(_listener, _section, ##_args); \
142 } \
143 } \
144 break; \
145 case Reverse: \
146 QTAILQ_FOREACH_REVERSE(_listener, &(_as)->listeners, link_as) { \
147 if (_listener->_callback) { \
148 _listener->_callback(_listener, _section, ##_args); \
149 } \
150 } \
151 break; \
152 default: \
153 abort(); \
154 } \
155 } while (0)
156
157 /* No need to ref/unref .mr, the FlatRange keeps it alive. */
158 #define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
159 do { \
160 MemoryRegionSection mrs = section_from_flat_range(fr, \
161 address_space_to_flatview(as)); \
162 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
163 } while(0)
164
165 struct CoalescedMemoryRange {
166 AddrRange addr;
167 QTAILQ_ENTRY(CoalescedMemoryRange) link;
168 };
169
170 struct MemoryRegionIoeventfd {
171 AddrRange addr;
172 bool match_data;
173 uint64_t data;
174 EventNotifier *e;
175 };
176
177 static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd *a,
178 MemoryRegionIoeventfd *b)
179 {
180 if (int128_lt(a->addr.start, b->addr.start)) {
181 return true;
182 } else if (int128_gt(a->addr.start, b->addr.start)) {
183 return false;
184 } else if (int128_lt(a->addr.size, b->addr.size)) {
185 return true;
186 } else if (int128_gt(a->addr.size, b->addr.size)) {
187 return false;
188 } else if (a->match_data < b->match_data) {
189 return true;
190 } else if (a->match_data > b->match_data) {
191 return false;
192 } else if (a->match_data) {
193 if (a->data < b->data) {
194 return true;
195 } else if (a->data > b->data) {
196 return false;
197 }
198 }
199 if (a->e < b->e) {
200 return true;
201 } else if (a->e > b->e) {
202 return false;
203 }
204 return false;
205 }
206
207 static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd *a,
208 MemoryRegionIoeventfd *b)
209 {
210 if (int128_eq(a->addr.start, b->addr.start) &&
211 (!int128_nz(a->addr.size) || !int128_nz(b->addr.size) ||
212 (int128_eq(a->addr.size, b->addr.size) &&
213 (a->match_data == b->match_data) &&
214 ((a->match_data && (a->data == b->data)) || !a->match_data) &&
215 (a->e == b->e))))
216 return true;
217
218 return false;
219 }
220
221 /* Range of memory in the global map. Addresses are absolute. */
222 struct FlatRange {
223 MemoryRegion *mr;
224 hwaddr offset_in_region;
225 AddrRange addr;
226 uint8_t dirty_log_mask;
227 bool romd_mode;
228 bool readonly;
229 bool nonvolatile;
230 };
231
232 #define FOR_EACH_FLAT_RANGE(var, view) \
233 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
234
235 static inline MemoryRegionSection
236 section_from_flat_range(FlatRange *fr, FlatView *fv)
237 {
238 return (MemoryRegionSection) {
239 .mr = fr->mr,
240 .fv = fv,
241 .offset_within_region = fr->offset_in_region,
242 .size = fr->addr.size,
243 .offset_within_address_space = int128_get64(fr->addr.start),
244 .readonly = fr->readonly,
245 .nonvolatile = fr->nonvolatile,
246 };
247 }
248
249 static bool flatrange_equal(FlatRange *a, FlatRange *b)
250 {
251 return a->mr == b->mr
252 && addrrange_equal(a->addr, b->addr)
253 && a->offset_in_region == b->offset_in_region
254 && a->romd_mode == b->romd_mode
255 && a->readonly == b->readonly
256 && a->nonvolatile == b->nonvolatile;
257 }
258
259 static FlatView *flatview_new(MemoryRegion *mr_root)
260 {
261 FlatView *view;
262
263 view = g_new0(FlatView, 1);
264 view->ref = 1;
265 view->root = mr_root;
266 memory_region_ref(mr_root);
267 trace_flatview_new(view, mr_root);
268
269 return view;
270 }
271
272 /* Insert a range into a given position. Caller is responsible for maintaining
273 * sorting order.
274 */
275 static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
276 {
277 if (view->nr == view->nr_allocated) {
278 view->nr_allocated = MAX(2 * view->nr, 10);
279 view->ranges = g_realloc(view->ranges,
280 view->nr_allocated * sizeof(*view->ranges));
281 }
282 memmove(view->ranges + pos + 1, view->ranges + pos,
283 (view->nr - pos) * sizeof(FlatRange));
284 view->ranges[pos] = *range;
285 memory_region_ref(range->mr);
286 ++view->nr;
287 }
288
289 static void flatview_destroy(FlatView *view)
290 {
291 int i;
292
293 trace_flatview_destroy(view, view->root);
294 if (view->dispatch) {
295 address_space_dispatch_free(view->dispatch);
296 }
297 for (i = 0; i < view->nr; i++) {
298 memory_region_unref(view->ranges[i].mr);
299 }
300 g_free(view->ranges);
301 memory_region_unref(view->root);
302 g_free(view);
303 }
304
305 static bool flatview_ref(FlatView *view)
306 {
307 return qatomic_fetch_inc_nonzero(&view->ref) > 0;
308 }
309
310 void flatview_unref(FlatView *view)
311 {
312 if (qatomic_fetch_dec(&view->ref) == 1) {
313 trace_flatview_destroy_rcu(view, view->root);
314 assert(view->root);
315 call_rcu(view, flatview_destroy, rcu);
316 }
317 }
318
319 static bool can_merge(FlatRange *r1, FlatRange *r2)
320 {
321 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
322 && r1->mr == r2->mr
323 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
324 r1->addr.size),
325 int128_make64(r2->offset_in_region))
326 && r1->dirty_log_mask == r2->dirty_log_mask
327 && r1->romd_mode == r2->romd_mode
328 && r1->readonly == r2->readonly
329 && r1->nonvolatile == r2->nonvolatile;
330 }
331
332 /* Attempt to simplify a view by merging adjacent ranges */
333 static void flatview_simplify(FlatView *view)
334 {
335 unsigned i, j, k;
336
337 i = 0;
338 while (i < view->nr) {
339 j = i + 1;
340 while (j < view->nr
341 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
342 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
343 ++j;
344 }
345 ++i;
346 for (k = i; k < j; k++) {
347 memory_region_unref(view->ranges[k].mr);
348 }
349 memmove(&view->ranges[i], &view->ranges[j],
350 (view->nr - j) * sizeof(view->ranges[j]));
351 view->nr -= j - i;
352 }
353 }
354
355 static bool memory_region_big_endian(MemoryRegion *mr)
356 {
357 #ifdef TARGET_WORDS_BIGENDIAN
358 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
359 #else
360 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
361 #endif
362 }
363
364 static void adjust_endianness(MemoryRegion *mr, uint64_t *data, MemOp op)
365 {
366 if ((op & MO_BSWAP) != devend_memop(mr->ops->endianness)) {
367 switch (op & MO_SIZE) {
368 case MO_8:
369 break;
370 case MO_16:
371 *data = bswap16(*data);
372 break;
373 case MO_32:
374 *data = bswap32(*data);
375 break;
376 case MO_64:
377 *data = bswap64(*data);
378 break;
379 default:
380 g_assert_not_reached();
381 }
382 }
383 }
384
385 static inline void memory_region_shift_read_access(uint64_t *value,
386 signed shift,
387 uint64_t mask,
388 uint64_t tmp)
389 {
390 if (shift >= 0) {
391 *value |= (tmp & mask) << shift;
392 } else {
393 *value |= (tmp & mask) >> -shift;
394 }
395 }
396
397 static inline uint64_t memory_region_shift_write_access(uint64_t *value,
398 signed shift,
399 uint64_t mask)
400 {
401 uint64_t tmp;
402
403 if (shift >= 0) {
404 tmp = (*value >> shift) & mask;
405 } else {
406 tmp = (*value << -shift) & mask;
407 }
408
409 return tmp;
410 }
411
412 static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
413 {
414 MemoryRegion *root;
415 hwaddr abs_addr = offset;
416
417 abs_addr += mr->addr;
418 for (root = mr; root->container; ) {
419 root = root->container;
420 abs_addr += root->addr;
421 }
422
423 return abs_addr;
424 }
425
426 static int get_cpu_index(void)
427 {
428 if (current_cpu) {
429 return current_cpu->cpu_index;
430 }
431 return -1;
432 }
433
434 static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
435 hwaddr addr,
436 uint64_t *value,
437 unsigned size,
438 signed shift,
439 uint64_t mask,
440 MemTxAttrs attrs)
441 {
442 uint64_t tmp;
443
444 tmp = mr->ops->read(mr->opaque, addr, size);
445 if (mr->subpage) {
446 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
447 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_READ)) {
448 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
449 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
450 }
451 memory_region_shift_read_access(value, shift, mask, tmp);
452 return MEMTX_OK;
453 }
454
455 static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
456 hwaddr addr,
457 uint64_t *value,
458 unsigned size,
459 signed shift,
460 uint64_t mask,
461 MemTxAttrs attrs)
462 {
463 uint64_t tmp = 0;
464 MemTxResult r;
465
466 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
467 if (mr->subpage) {
468 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
469 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_READ)) {
470 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
471 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
472 }
473 memory_region_shift_read_access(value, shift, mask, tmp);
474 return r;
475 }
476
477 static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
478 hwaddr addr,
479 uint64_t *value,
480 unsigned size,
481 signed shift,
482 uint64_t mask,
483 MemTxAttrs attrs)
484 {
485 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
486
487 if (mr->subpage) {
488 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
489 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_WRITE)) {
490 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
491 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
492 }
493 mr->ops->write(mr->opaque, addr, tmp, size);
494 return MEMTX_OK;
495 }
496
497 static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
498 hwaddr addr,
499 uint64_t *value,
500 unsigned size,
501 signed shift,
502 uint64_t mask,
503 MemTxAttrs attrs)
504 {
505 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
506
507 if (mr->subpage) {
508 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
509 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_WRITE)) {
510 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
511 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
512 }
513 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
514 }
515
516 static MemTxResult access_with_adjusted_size(hwaddr addr,
517 uint64_t *value,
518 unsigned size,
519 unsigned access_size_min,
520 unsigned access_size_max,
521 MemTxResult (*access_fn)
522 (MemoryRegion *mr,
523 hwaddr addr,
524 uint64_t *value,
525 unsigned size,
526 signed shift,
527 uint64_t mask,
528 MemTxAttrs attrs),
529 MemoryRegion *mr,
530 MemTxAttrs attrs)
531 {
532 uint64_t access_mask;
533 unsigned access_size;
534 unsigned i;
535 MemTxResult r = MEMTX_OK;
536
537 if (!access_size_min) {
538 access_size_min = 1;
539 }
540 if (!access_size_max) {
541 access_size_max = 4;
542 }
543
544 /* FIXME: support unaligned access? */
545 access_size = MAX(MIN(size, access_size_max), access_size_min);
546 access_mask = MAKE_64BIT_MASK(0, access_size * 8);
547 if (memory_region_big_endian(mr)) {
548 for (i = 0; i < size; i += access_size) {
549 r |= access_fn(mr, addr + i, value, access_size,
550 (size - access_size - i) * 8, access_mask, attrs);
551 }
552 } else {
553 for (i = 0; i < size; i += access_size) {
554 r |= access_fn(mr, addr + i, value, access_size, i * 8,
555 access_mask, attrs);
556 }
557 }
558 return r;
559 }
560
561 static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
562 {
563 AddressSpace *as;
564
565 while (mr->container) {
566 mr = mr->container;
567 }
568 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
569 if (mr == as->root) {
570 return as;
571 }
572 }
573 return NULL;
574 }
575
576 /* Render a memory region into the global view. Ranges in @view obscure
577 * ranges in @mr.
578 */
579 static void render_memory_region(FlatView *view,
580 MemoryRegion *mr,
581 Int128 base,
582 AddrRange clip,
583 bool readonly,
584 bool nonvolatile)
585 {
586 MemoryRegion *subregion;
587 unsigned i;
588 hwaddr offset_in_region;
589 Int128 remain;
590 Int128 now;
591 FlatRange fr;
592 AddrRange tmp;
593
594 if (!mr->enabled) {
595 return;
596 }
597
598 int128_addto(&base, int128_make64(mr->addr));
599 readonly |= mr->readonly;
600 nonvolatile |= mr->nonvolatile;
601
602 tmp = addrrange_make(base, mr->size);
603
604 if (!addrrange_intersects(tmp, clip)) {
605 return;
606 }
607
608 clip = addrrange_intersection(tmp, clip);
609
610 if (mr->alias) {
611 int128_subfrom(&base, int128_make64(mr->alias->addr));
612 int128_subfrom(&base, int128_make64(mr->alias_offset));
613 render_memory_region(view, mr->alias, base, clip,
614 readonly, nonvolatile);
615 return;
616 }
617
618 /* Render subregions in priority order. */
619 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
620 render_memory_region(view, subregion, base, clip,
621 readonly, nonvolatile);
622 }
623
624 if (!mr->terminates) {
625 return;
626 }
627
628 offset_in_region = int128_get64(int128_sub(clip.start, base));
629 base = clip.start;
630 remain = clip.size;
631
632 fr.mr = mr;
633 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
634 fr.romd_mode = mr->romd_mode;
635 fr.readonly = readonly;
636 fr.nonvolatile = nonvolatile;
637
638 /* Render the region itself into any gaps left by the current view. */
639 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
640 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
641 continue;
642 }
643 if (int128_lt(base, view->ranges[i].addr.start)) {
644 now = int128_min(remain,
645 int128_sub(view->ranges[i].addr.start, base));
646 fr.offset_in_region = offset_in_region;
647 fr.addr = addrrange_make(base, now);
648 flatview_insert(view, i, &fr);
649 ++i;
650 int128_addto(&base, now);
651 offset_in_region += int128_get64(now);
652 int128_subfrom(&remain, now);
653 }
654 now = int128_sub(int128_min(int128_add(base, remain),
655 addrrange_end(view->ranges[i].addr)),
656 base);
657 int128_addto(&base, now);
658 offset_in_region += int128_get64(now);
659 int128_subfrom(&remain, now);
660 }
661 if (int128_nz(remain)) {
662 fr.offset_in_region = offset_in_region;
663 fr.addr = addrrange_make(base, remain);
664 flatview_insert(view, i, &fr);
665 }
666 }
667
668 void flatview_for_each_range(FlatView *fv, flatview_cb cb , void *opaque)
669 {
670 FlatRange *fr;
671
672 assert(fv);
673 assert(cb);
674
675 FOR_EACH_FLAT_RANGE(fr, fv) {
676 if (cb(fr->addr.start, fr->addr.size, fr->mr,
677 fr->offset_in_region, opaque)) {
678 break;
679 }
680 }
681 }
682
683 static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
684 {
685 while (mr->enabled) {
686 if (mr->alias) {
687 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
688 /* The alias is included in its entirety. Use it as
689 * the "real" root, so that we can share more FlatViews.
690 */
691 mr = mr->alias;
692 continue;
693 }
694 } else if (!mr->terminates) {
695 unsigned int found = 0;
696 MemoryRegion *child, *next = NULL;
697 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
698 if (child->enabled) {
699 if (++found > 1) {
700 next = NULL;
701 break;
702 }
703 if (!child->addr && int128_ge(mr->size, child->size)) {
704 /* A child is included in its entirety. If it's the only
705 * enabled one, use it in the hope of finding an alias down the
706 * way. This will also let us share FlatViews.
707 */
708 next = child;
709 }
710 }
711 }
712 if (found == 0) {
713 return NULL;
714 }
715 if (next) {
716 mr = next;
717 continue;
718 }
719 }
720
721 return mr;
722 }
723
724 return NULL;
725 }
726
727 /* Render a memory topology into a list of disjoint absolute ranges. */
728 static FlatView *generate_memory_topology(MemoryRegion *mr)
729 {
730 int i;
731 FlatView *view;
732
733 view = flatview_new(mr);
734
735 if (mr) {
736 render_memory_region(view, mr, int128_zero(),
737 addrrange_make(int128_zero(), int128_2_64()),
738 false, false);
739 }
740 flatview_simplify(view);
741
742 view->dispatch = address_space_dispatch_new(view);
743 for (i = 0; i < view->nr; i++) {
744 MemoryRegionSection mrs =
745 section_from_flat_range(&view->ranges[i], view);
746 flatview_add_to_dispatch(view, &mrs);
747 }
748 address_space_dispatch_compact(view->dispatch);
749 g_hash_table_replace(flat_views, mr, view);
750
751 return view;
752 }
753
754 static void address_space_add_del_ioeventfds(AddressSpace *as,
755 MemoryRegionIoeventfd *fds_new,
756 unsigned fds_new_nb,
757 MemoryRegionIoeventfd *fds_old,
758 unsigned fds_old_nb)
759 {
760 unsigned iold, inew;
761 MemoryRegionIoeventfd *fd;
762 MemoryRegionSection section;
763
764 /* Generate a symmetric difference of the old and new fd sets, adding
765 * and deleting as necessary.
766 */
767
768 iold = inew = 0;
769 while (iold < fds_old_nb || inew < fds_new_nb) {
770 if (iold < fds_old_nb
771 && (inew == fds_new_nb
772 || memory_region_ioeventfd_before(&fds_old[iold],
773 &fds_new[inew]))) {
774 fd = &fds_old[iold];
775 section = (MemoryRegionSection) {
776 .fv = address_space_to_flatview(as),
777 .offset_within_address_space = int128_get64(fd->addr.start),
778 .size = fd->addr.size,
779 };
780 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
781 fd->match_data, fd->data, fd->e);
782 ++iold;
783 } else if (inew < fds_new_nb
784 && (iold == fds_old_nb
785 || memory_region_ioeventfd_before(&fds_new[inew],
786 &fds_old[iold]))) {
787 fd = &fds_new[inew];
788 section = (MemoryRegionSection) {
789 .fv = address_space_to_flatview(as),
790 .offset_within_address_space = int128_get64(fd->addr.start),
791 .size = fd->addr.size,
792 };
793 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
794 fd->match_data, fd->data, fd->e);
795 ++inew;
796 } else {
797 ++iold;
798 ++inew;
799 }
800 }
801 }
802
803 FlatView *address_space_get_flatview(AddressSpace *as)
804 {
805 FlatView *view;
806
807 RCU_READ_LOCK_GUARD();
808 do {
809 view = address_space_to_flatview(as);
810 /* If somebody has replaced as->current_map concurrently,
811 * flatview_ref returns false.
812 */
813 } while (!flatview_ref(view));
814 return view;
815 }
816
817 static void address_space_update_ioeventfds(AddressSpace *as)
818 {
819 FlatView *view;
820 FlatRange *fr;
821 unsigned ioeventfd_nb = 0;
822 unsigned ioeventfd_max;
823 MemoryRegionIoeventfd *ioeventfds;
824 AddrRange tmp;
825 unsigned i;
826
827 /*
828 * It is likely that the number of ioeventfds hasn't changed much, so use
829 * the previous size as the starting value, with some headroom to avoid
830 * gratuitous reallocations.
831 */
832 ioeventfd_max = QEMU_ALIGN_UP(as->ioeventfd_nb, 4);
833 ioeventfds = g_new(MemoryRegionIoeventfd, ioeventfd_max);
834
835 view = address_space_get_flatview(as);
836 FOR_EACH_FLAT_RANGE(fr, view) {
837 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
838 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
839 int128_sub(fr->addr.start,
840 int128_make64(fr->offset_in_region)));
841 if (addrrange_intersects(fr->addr, tmp)) {
842 ++ioeventfd_nb;
843 if (ioeventfd_nb > ioeventfd_max) {
844 ioeventfd_max = MAX(ioeventfd_max * 2, 4);
845 ioeventfds = g_realloc(ioeventfds,
846 ioeventfd_max * sizeof(*ioeventfds));
847 }
848 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
849 ioeventfds[ioeventfd_nb-1].addr = tmp;
850 }
851 }
852 }
853
854 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
855 as->ioeventfds, as->ioeventfd_nb);
856
857 g_free(as->ioeventfds);
858 as->ioeventfds = ioeventfds;
859 as->ioeventfd_nb = ioeventfd_nb;
860 flatview_unref(view);
861 }
862
863 /*
864 * Notify the memory listeners about the coalesced IO change events of
865 * range `cmr'. Only the part that has intersection of the specified
866 * FlatRange will be sent.
867 */
868 static void flat_range_coalesced_io_notify(FlatRange *fr, AddressSpace *as,
869 CoalescedMemoryRange *cmr, bool add)
870 {
871 AddrRange tmp;
872
873 tmp = addrrange_shift(cmr->addr,
874 int128_sub(fr->addr.start,
875 int128_make64(fr->offset_in_region)));
876 if (!addrrange_intersects(tmp, fr->addr)) {
877 return;
878 }
879 tmp = addrrange_intersection(tmp, fr->addr);
880
881 if (add) {
882 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, coalesced_io_add,
883 int128_get64(tmp.start),
884 int128_get64(tmp.size));
885 } else {
886 MEMORY_LISTENER_UPDATE_REGION(fr, as, Reverse, coalesced_io_del,
887 int128_get64(tmp.start),
888 int128_get64(tmp.size));
889 }
890 }
891
892 static void flat_range_coalesced_io_del(FlatRange *fr, AddressSpace *as)
893 {
894 CoalescedMemoryRange *cmr;
895
896 QTAILQ_FOREACH(cmr, &fr->mr->coalesced, link) {
897 flat_range_coalesced_io_notify(fr, as, cmr, false);
898 }
899 }
900
901 static void flat_range_coalesced_io_add(FlatRange *fr, AddressSpace *as)
902 {
903 MemoryRegion *mr = fr->mr;
904 CoalescedMemoryRange *cmr;
905
906 if (QTAILQ_EMPTY(&mr->coalesced)) {
907 return;
908 }
909
910 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
911 flat_range_coalesced_io_notify(fr, as, cmr, true);
912 }
913 }
914
915 static void address_space_update_topology_pass(AddressSpace *as,
916 const FlatView *old_view,
917 const FlatView *new_view,
918 bool adding)
919 {
920 unsigned iold, inew;
921 FlatRange *frold, *frnew;
922
923 /* Generate a symmetric difference of the old and new memory maps.
924 * Kill ranges in the old map, and instantiate ranges in the new map.
925 */
926 iold = inew = 0;
927 while (iold < old_view->nr || inew < new_view->nr) {
928 if (iold < old_view->nr) {
929 frold = &old_view->ranges[iold];
930 } else {
931 frold = NULL;
932 }
933 if (inew < new_view->nr) {
934 frnew = &new_view->ranges[inew];
935 } else {
936 frnew = NULL;
937 }
938
939 if (frold
940 && (!frnew
941 || int128_lt(frold->addr.start, frnew->addr.start)
942 || (int128_eq(frold->addr.start, frnew->addr.start)
943 && !flatrange_equal(frold, frnew)))) {
944 /* In old but not in new, or in both but attributes changed. */
945
946 if (!adding) {
947 flat_range_coalesced_io_del(frold, as);
948 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
949 }
950
951 ++iold;
952 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
953 /* In both and unchanged (except logging may have changed) */
954
955 if (adding) {
956 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
957 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
958 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
959 frold->dirty_log_mask,
960 frnew->dirty_log_mask);
961 }
962 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
963 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
964 frold->dirty_log_mask,
965 frnew->dirty_log_mask);
966 }
967 }
968
969 ++iold;
970 ++inew;
971 } else {
972 /* In new */
973
974 if (adding) {
975 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
976 flat_range_coalesced_io_add(frnew, as);
977 }
978
979 ++inew;
980 }
981 }
982 }
983
984 static void flatviews_init(void)
985 {
986 static FlatView *empty_view;
987
988 if (flat_views) {
989 return;
990 }
991
992 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
993 (GDestroyNotify) flatview_unref);
994 if (!empty_view) {
995 empty_view = generate_memory_topology(NULL);
996 /* We keep it alive forever in the global variable. */
997 flatview_ref(empty_view);
998 } else {
999 g_hash_table_replace(flat_views, NULL, empty_view);
1000 flatview_ref(empty_view);
1001 }
1002 }
1003
1004 static void flatviews_reset(void)
1005 {
1006 AddressSpace *as;
1007
1008 if (flat_views) {
1009 g_hash_table_unref(flat_views);
1010 flat_views = NULL;
1011 }
1012 flatviews_init();
1013
1014 /* Render unique FVs */
1015 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1016 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1017
1018 if (g_hash_table_lookup(flat_views, physmr)) {
1019 continue;
1020 }
1021
1022 generate_memory_topology(physmr);
1023 }
1024 }
1025
1026 static void address_space_set_flatview(AddressSpace *as)
1027 {
1028 FlatView *old_view = address_space_to_flatview(as);
1029 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1030 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
1031
1032 assert(new_view);
1033
1034 if (old_view == new_view) {
1035 return;
1036 }
1037
1038 if (old_view) {
1039 flatview_ref(old_view);
1040 }
1041
1042 flatview_ref(new_view);
1043
1044 if (!QTAILQ_EMPTY(&as->listeners)) {
1045 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1046
1047 if (!old_view2) {
1048 old_view2 = &tmpview;
1049 }
1050 address_space_update_topology_pass(as, old_view2, new_view, false);
1051 address_space_update_topology_pass(as, old_view2, new_view, true);
1052 }
1053
1054 /* Writes are protected by the BQL. */
1055 qatomic_rcu_set(&as->current_map, new_view);
1056 if (old_view) {
1057 flatview_unref(old_view);
1058 }
1059
1060 /* Note that all the old MemoryRegions are still alive up to this
1061 * point. This relieves most MemoryListeners from the need to
1062 * ref/unref the MemoryRegions they get---unless they use them
1063 * outside the iothread mutex, in which case precise reference
1064 * counting is necessary.
1065 */
1066 if (old_view) {
1067 flatview_unref(old_view);
1068 }
1069 }
1070
1071 static void address_space_update_topology(AddressSpace *as)
1072 {
1073 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1074
1075 flatviews_init();
1076 if (!g_hash_table_lookup(flat_views, physmr)) {
1077 generate_memory_topology(physmr);
1078 }
1079 address_space_set_flatview(as);
1080 }
1081
1082 void memory_region_transaction_begin(void)
1083 {
1084 qemu_flush_coalesced_mmio_buffer();
1085 ++memory_region_transaction_depth;
1086 }
1087
1088 void memory_region_transaction_commit(void)
1089 {
1090 AddressSpace *as;
1091
1092 assert(memory_region_transaction_depth);
1093 assert(qemu_mutex_iothread_locked());
1094
1095 --memory_region_transaction_depth;
1096 if (!memory_region_transaction_depth) {
1097 if (memory_region_update_pending) {
1098 flatviews_reset();
1099
1100 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
1101
1102 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1103 address_space_set_flatview(as);
1104 address_space_update_ioeventfds(as);
1105 }
1106 memory_region_update_pending = false;
1107 ioeventfd_update_pending = false;
1108 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1109 } else if (ioeventfd_update_pending) {
1110 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1111 address_space_update_ioeventfds(as);
1112 }
1113 ioeventfd_update_pending = false;
1114 }
1115 }
1116 }
1117
1118 static void memory_region_destructor_none(MemoryRegion *mr)
1119 {
1120 }
1121
1122 static void memory_region_destructor_ram(MemoryRegion *mr)
1123 {
1124 qemu_ram_free(mr->ram_block);
1125 }
1126
1127 static bool memory_region_need_escape(char c)
1128 {
1129 return c == '/' || c == '[' || c == '\\' || c == ']';
1130 }
1131
1132 static char *memory_region_escape_name(const char *name)
1133 {
1134 const char *p;
1135 char *escaped, *q;
1136 uint8_t c;
1137 size_t bytes = 0;
1138
1139 for (p = name; *p; p++) {
1140 bytes += memory_region_need_escape(*p) ? 4 : 1;
1141 }
1142 if (bytes == p - name) {
1143 return g_memdup(name, bytes + 1);
1144 }
1145
1146 escaped = g_malloc(bytes + 1);
1147 for (p = name, q = escaped; *p; p++) {
1148 c = *p;
1149 if (unlikely(memory_region_need_escape(c))) {
1150 *q++ = '\\';
1151 *q++ = 'x';
1152 *q++ = "0123456789abcdef"[c >> 4];
1153 c = "0123456789abcdef"[c & 15];
1154 }
1155 *q++ = c;
1156 }
1157 *q = 0;
1158 return escaped;
1159 }
1160
1161 static void memory_region_do_init(MemoryRegion *mr,
1162 Object *owner,
1163 const char *name,
1164 uint64_t size)
1165 {
1166 mr->size = int128_make64(size);
1167 if (size == UINT64_MAX) {
1168 mr->size = int128_2_64();
1169 }
1170 mr->name = g_strdup(name);
1171 mr->owner = owner;
1172 mr->ram_block = NULL;
1173
1174 if (name) {
1175 char *escaped_name = memory_region_escape_name(name);
1176 char *name_array = g_strdup_printf("%s[*]", escaped_name);
1177
1178 if (!owner) {
1179 owner = container_get(qdev_get_machine(), "/unattached");
1180 }
1181
1182 object_property_add_child(owner, name_array, OBJECT(mr));
1183 object_unref(OBJECT(mr));
1184 g_free(name_array);
1185 g_free(escaped_name);
1186 }
1187 }
1188
1189 void memory_region_init(MemoryRegion *mr,
1190 Object *owner,
1191 const char *name,
1192 uint64_t size)
1193 {
1194 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1195 memory_region_do_init(mr, owner, name, size);
1196 }
1197
1198 static void memory_region_get_container(Object *obj, Visitor *v,
1199 const char *name, void *opaque,
1200 Error **errp)
1201 {
1202 MemoryRegion *mr = MEMORY_REGION(obj);
1203 char *path = (char *)"";
1204
1205 if (mr->container) {
1206 path = object_get_canonical_path(OBJECT(mr->container));
1207 }
1208 visit_type_str(v, name, &path, errp);
1209 if (mr->container) {
1210 g_free(path);
1211 }
1212 }
1213
1214 static Object *memory_region_resolve_container(Object *obj, void *opaque,
1215 const char *part)
1216 {
1217 MemoryRegion *mr = MEMORY_REGION(obj);
1218
1219 return OBJECT(mr->container);
1220 }
1221
1222 static void memory_region_get_priority(Object *obj, Visitor *v,
1223 const char *name, void *opaque,
1224 Error **errp)
1225 {
1226 MemoryRegion *mr = MEMORY_REGION(obj);
1227 int32_t value = mr->priority;
1228
1229 visit_type_int32(v, name, &value, errp);
1230 }
1231
1232 static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1233 void *opaque, Error **errp)
1234 {
1235 MemoryRegion *mr = MEMORY_REGION(obj);
1236 uint64_t value = memory_region_size(mr);
1237
1238 visit_type_uint64(v, name, &value, errp);
1239 }
1240
1241 static void memory_region_initfn(Object *obj)
1242 {
1243 MemoryRegion *mr = MEMORY_REGION(obj);
1244 ObjectProperty *op;
1245
1246 mr->ops = &unassigned_mem_ops;
1247 mr->enabled = true;
1248 mr->romd_mode = true;
1249 mr->destructor = memory_region_destructor_none;
1250 QTAILQ_INIT(&mr->subregions);
1251 QTAILQ_INIT(&mr->coalesced);
1252
1253 op = object_property_add(OBJECT(mr), "container",
1254 "link<" TYPE_MEMORY_REGION ">",
1255 memory_region_get_container,
1256 NULL, /* memory_region_set_container */
1257 NULL, NULL);
1258 op->resolve = memory_region_resolve_container;
1259
1260 object_property_add_uint64_ptr(OBJECT(mr), "addr",
1261 &mr->addr, OBJ_PROP_FLAG_READ);
1262 object_property_add(OBJECT(mr), "priority", "uint32",
1263 memory_region_get_priority,
1264 NULL, /* memory_region_set_priority */
1265 NULL, NULL);
1266 object_property_add(OBJECT(mr), "size", "uint64",
1267 memory_region_get_size,
1268 NULL, /* memory_region_set_size, */
1269 NULL, NULL);
1270 }
1271
1272 static int qemu_target_backtrace(target_ulong *array, size_t size)
1273 {
1274 int n = 0;
1275 if (size >= 2) {
1276 #if defined(TARGET_ARM)
1277 CPUArchState *env = current_cpu->env_ptr;
1278 array[0] = env->regs[15];
1279 array[1] = env->regs[14];
1280 #elif defined(TARGET_MIPS)
1281 CPUArchState *env = current_cpu->env_ptr;
1282 array[0] = env->active_tc.PC;
1283 array[1] = env->active_tc.gpr[31];
1284 #else
1285 array[0] = 0;
1286 array[1] = 0;
1287 #endif
1288 n = 2;
1289 }
1290 return n;
1291 }
1292
1293 #include "disas/disas.h"
1294 const char *qemu_sprint_backtrace(char *buffer, size_t length)
1295 {
1296 char *p = buffer;
1297 if (current_cpu) {
1298 target_ulong caller[2];
1299 const char *symbol;
1300 qemu_target_backtrace(caller, 2);
1301 symbol = lookup_symbol(caller[0]);
1302 p += sprintf(p, "[%s]", symbol);
1303 symbol = lookup_symbol(caller[1]);
1304 p += sprintf(p, "[%s]", symbol);
1305 } else {
1306 p += sprintf(p, "[cpu not running]");
1307 }
1308 assert((p - buffer) < length);
1309 return buffer;
1310 }
1311
1312 static void iommu_memory_region_initfn(Object *obj)
1313 {
1314 MemoryRegion *mr = MEMORY_REGION(obj);
1315
1316 mr->is_iommu = true;
1317 }
1318
1319 static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1320 unsigned size)
1321 {
1322 if (trace_unassigned) {
1323 char buffer[256];
1324 fprintf(stderr, "Unassigned mem read " TARGET_FMT_plx " %s\n",
1325 addr, qemu_sprint_backtrace(buffer, sizeof(buffer)));
1326 }
1327 //~ vm_stop(0);
1328 return 0;
1329 }
1330
1331 static void unassigned_mem_write(void *opaque, hwaddr addr,
1332 uint64_t val, unsigned size)
1333 {
1334 if (trace_unassigned) {
1335 char buffer[256];
1336 fprintf(stderr, "Unassigned mem write " TARGET_FMT_plx
1337 " = 0x%" PRIx64 " %s\n",
1338 addr, val, qemu_sprint_backtrace(buffer, sizeof(buffer)));
1339 }
1340 }
1341
1342 static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1343 unsigned size, bool is_write,
1344 MemTxAttrs attrs)
1345 {
1346 return false;
1347 }
1348
1349 const MemoryRegionOps unassigned_mem_ops = {
1350 .valid.accepts = unassigned_mem_accepts,
1351 .endianness = DEVICE_NATIVE_ENDIAN,
1352 };
1353
1354 static uint64_t memory_region_ram_device_read(void *opaque,
1355 hwaddr addr, unsigned size)
1356 {
1357 MemoryRegion *mr = opaque;
1358 uint64_t data = (uint64_t)~0;
1359
1360 switch (size) {
1361 case 1:
1362 data = *(uint8_t *)(mr->ram_block->host + addr);
1363 break;
1364 case 2:
1365 data = *(uint16_t *)(mr->ram_block->host + addr);
1366 break;
1367 case 4:
1368 data = *(uint32_t *)(mr->ram_block->host + addr);
1369 break;
1370 case 8:
1371 data = *(uint64_t *)(mr->ram_block->host + addr);
1372 break;
1373 }
1374
1375 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1376
1377 return data;
1378 }
1379
1380 static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1381 uint64_t data, unsigned size)
1382 {
1383 MemoryRegion *mr = opaque;
1384
1385 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1386
1387 switch (size) {
1388 case 1:
1389 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1390 break;
1391 case 2:
1392 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1393 break;
1394 case 4:
1395 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1396 break;
1397 case 8:
1398 *(uint64_t *)(mr->ram_block->host + addr) = data;
1399 break;
1400 }
1401 }
1402
1403 static const MemoryRegionOps ram_device_mem_ops = {
1404 .read = memory_region_ram_device_read,
1405 .write = memory_region_ram_device_write,
1406 .endianness = DEVICE_HOST_ENDIAN,
1407 .valid = {
1408 .min_access_size = 1,
1409 .max_access_size = 8,
1410 .unaligned = true,
1411 },
1412 .impl = {
1413 .min_access_size = 1,
1414 .max_access_size = 8,
1415 .unaligned = true,
1416 },
1417 };
1418
1419 bool memory_region_access_valid(MemoryRegion *mr,
1420 hwaddr addr,
1421 unsigned size,
1422 bool is_write,
1423 MemTxAttrs attrs)
1424 {
1425 if (mr->ops->valid.accepts
1426 && !mr->ops->valid.accepts(mr->opaque, addr, size, is_write, attrs)) {
1427 qemu_log_mask(LOG_GUEST_ERROR, "Invalid access at addr "
1428 "0x%" HWADDR_PRIX ", size %u, "
1429 "region '%s', reason: rejected\n",
1430 addr, size, memory_region_name(mr));
1431 return false;
1432 }
1433
1434 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1435 qemu_log_mask(LOG_GUEST_ERROR, "Invalid access at addr "
1436 "0x%" HWADDR_PRIX ", size %u, "
1437 "region '%s', reason: unaligned\n",
1438 addr, size, memory_region_name(mr));
1439 return false;
1440 }
1441
1442 /* Treat zero as compatibility all valid */
1443 if (!mr->ops->valid.max_access_size) {
1444 return true;
1445 }
1446
1447 if (size > mr->ops->valid.max_access_size
1448 || size < mr->ops->valid.min_access_size) {
1449 qemu_log_mask(LOG_GUEST_ERROR, "Invalid access at addr "
1450 "0x%" HWADDR_PRIX ", size %u, "
1451 "region '%s', reason: invalid size "
1452 "(min:%u max:%u)\n",
1453 addr, size, memory_region_name(mr),
1454 mr->ops->valid.min_access_size,
1455 mr->ops->valid.max_access_size);
1456 return false;
1457 }
1458 return true;
1459 }
1460
1461 static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1462 hwaddr addr,
1463 uint64_t *pval,
1464 unsigned size,
1465 MemTxAttrs attrs)
1466 {
1467 *pval = 0;
1468
1469 if (mr->ops->read) {
1470 return access_with_adjusted_size(addr, pval, size,
1471 mr->ops->impl.min_access_size,
1472 mr->ops->impl.max_access_size,
1473 memory_region_read_accessor,
1474 mr, attrs);
1475 } else {
1476 return access_with_adjusted_size(addr, pval, size,
1477 mr->ops->impl.min_access_size,
1478 mr->ops->impl.max_access_size,
1479 memory_region_read_with_attrs_accessor,
1480 mr, attrs);
1481 }
1482 }
1483
1484 MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1485 hwaddr addr,
1486 uint64_t *pval,
1487 MemOp op,
1488 MemTxAttrs attrs)
1489 {
1490 unsigned size = memop_size(op);
1491 MemTxResult r;
1492
1493 if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
1494 *pval = unassigned_mem_read(mr, addr, size);
1495 return MEMTX_DECODE_ERROR;
1496 }
1497
1498 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
1499 adjust_endianness(mr, pval, op);
1500 return r;
1501 }
1502
1503 /* Return true if an eventfd was signalled */
1504 static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1505 hwaddr addr,
1506 uint64_t data,
1507 unsigned size,
1508 MemTxAttrs attrs)
1509 {
1510 MemoryRegionIoeventfd ioeventfd = {
1511 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1512 .data = data,
1513 };
1514 unsigned i;
1515
1516 for (i = 0; i < mr->ioeventfd_nb; i++) {
1517 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1518 ioeventfd.e = mr->ioeventfds[i].e;
1519
1520 if (memory_region_ioeventfd_equal(&ioeventfd, &mr->ioeventfds[i])) {
1521 event_notifier_set(ioeventfd.e);
1522 return true;
1523 }
1524 }
1525
1526 return false;
1527 }
1528
1529 MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1530 hwaddr addr,
1531 uint64_t data,
1532 MemOp op,
1533 MemTxAttrs attrs)
1534 {
1535 unsigned size = memop_size(op);
1536
1537 if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
1538 unassigned_mem_write(mr, addr, data, size);
1539 return MEMTX_DECODE_ERROR;
1540 }
1541
1542 adjust_endianness(mr, &data, op);
1543
1544 if ((!kvm_eventfds_enabled()) &&
1545 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1546 return MEMTX_OK;
1547 }
1548
1549 if (mr->ops->write) {
1550 return access_with_adjusted_size(addr, &data, size,
1551 mr->ops->impl.min_access_size,
1552 mr->ops->impl.max_access_size,
1553 memory_region_write_accessor, mr,
1554 attrs);
1555 } else {
1556 return
1557 access_with_adjusted_size(addr, &data, size,
1558 mr->ops->impl.min_access_size,
1559 mr->ops->impl.max_access_size,
1560 memory_region_write_with_attrs_accessor,
1561 mr, attrs);
1562 }
1563 }
1564
1565 void memory_region_init_io(MemoryRegion *mr,
1566 Object *owner,
1567 const MemoryRegionOps *ops,
1568 void *opaque,
1569 const char *name,
1570 uint64_t size)
1571 {
1572 memory_region_init(mr, owner, name, size);
1573 mr->ops = ops ? ops : &unassigned_mem_ops;
1574 mr->opaque = opaque;
1575 mr->terminates = true;
1576 }
1577
1578 void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1579 Object *owner,
1580 const char *name,
1581 uint64_t size,
1582 Error **errp)
1583 {
1584 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1585 }
1586
1587 void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr,
1588 Object *owner,
1589 const char *name,
1590 uint64_t size,
1591 bool share,
1592 Error **errp)
1593 {
1594 Error *err = NULL;
1595 memory_region_init(mr, owner, name, size);
1596 mr->ram = true;
1597 mr->terminates = true;
1598 mr->destructor = memory_region_destructor_ram;
1599 mr->ram_block = qemu_ram_alloc(size, share, mr, &err);
1600 if (err) {
1601 mr->size = int128_zero();
1602 object_unparent(OBJECT(mr));
1603 error_propagate(errp, err);
1604 }
1605 }
1606
1607 void memory_region_init_resizeable_ram(MemoryRegion *mr,
1608 Object *owner,
1609 const char *name,
1610 uint64_t size,
1611 uint64_t max_size,
1612 void (*resized)(const char*,
1613 uint64_t length,
1614 void *host),
1615 Error **errp)
1616 {
1617 Error *err = NULL;
1618 memory_region_init(mr, owner, name, size);
1619 mr->ram = true;
1620 mr->terminates = true;
1621 mr->destructor = memory_region_destructor_ram;
1622 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1623 mr, &err);
1624 if (err) {
1625 mr->size = int128_zero();
1626 object_unparent(OBJECT(mr));
1627 error_propagate(errp, err);
1628 }
1629 }
1630
1631 #ifdef CONFIG_POSIX
1632 void memory_region_init_ram_from_file(MemoryRegion *mr,
1633 Object *owner,
1634 const char *name,
1635 uint64_t size,
1636 uint64_t align,
1637 uint32_t ram_flags,
1638 const char *path,
1639 bool readonly,
1640 Error **errp)
1641 {
1642 Error *err = NULL;
1643 memory_region_init(mr, owner, name, size);
1644 mr->ram = true;
1645 mr->readonly = readonly;
1646 mr->terminates = true;
1647 mr->destructor = memory_region_destructor_ram;
1648 mr->align = align;
1649 mr->ram_block = qemu_ram_alloc_from_file(size, mr, ram_flags, path,
1650 readonly, &err);
1651 if (err) {
1652 mr->size = int128_zero();
1653 object_unparent(OBJECT(mr));
1654 error_propagate(errp, err);
1655 }
1656 }
1657
1658 void memory_region_init_ram_from_fd(MemoryRegion *mr,
1659 Object *owner,
1660 const char *name,
1661 uint64_t size,
1662 bool share,
1663 int fd,
1664 ram_addr_t offset,
1665 Error **errp)
1666 {
1667 Error *err = NULL;
1668 memory_region_init(mr, owner, name, size);
1669 mr->ram = true;
1670 mr->terminates = true;
1671 mr->destructor = memory_region_destructor_ram;
1672 mr->ram_block = qemu_ram_alloc_from_fd(size, mr,
1673 share ? RAM_SHARED : 0,
1674 fd, offset, false, &err);
1675 if (err) {
1676 mr->size = int128_zero();
1677 object_unparent(OBJECT(mr));
1678 error_propagate(errp, err);
1679 }
1680 }
1681 #endif
1682
1683 void memory_region_init_ram_ptr(MemoryRegion *mr,
1684 Object *owner,
1685 const char *name,
1686 uint64_t size,
1687 void *ptr)
1688 {
1689 memory_region_init(mr, owner, name, size);
1690 mr->ram = true;
1691 mr->terminates = true;
1692 mr->destructor = memory_region_destructor_ram;
1693
1694 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1695 assert(ptr != NULL);
1696 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
1697 }
1698
1699 void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1700 Object *owner,
1701 const char *name,
1702 uint64_t size,
1703 void *ptr)
1704 {
1705 memory_region_init(mr, owner, name, size);
1706 mr->ram = true;
1707 mr->terminates = true;
1708 mr->ram_device = true;
1709 mr->ops = &ram_device_mem_ops;
1710 mr->opaque = mr;
1711 mr->destructor = memory_region_destructor_ram;
1712
1713 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1714 assert(ptr != NULL);
1715 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
1716 }
1717
1718 void memory_region_init_alias(MemoryRegion *mr,
1719 Object *owner,
1720 const char *name,
1721 MemoryRegion *orig,
1722 hwaddr offset,
1723 uint64_t size)
1724 {
1725 memory_region_init(mr, owner, name, size);
1726 mr->alias = orig;
1727 mr->alias_offset = offset;
1728 }
1729
1730 void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1731 Object *owner,
1732 const char *name,
1733 uint64_t size,
1734 Error **errp)
1735 {
1736 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1737 mr->readonly = true;
1738 }
1739
1740 void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1741 Object *owner,
1742 const MemoryRegionOps *ops,
1743 void *opaque,
1744 const char *name,
1745 uint64_t size,
1746 Error **errp)
1747 {
1748 Error *err = NULL;
1749 assert(ops);
1750 memory_region_init(mr, owner, name, size);
1751 mr->ops = ops;
1752 mr->opaque = opaque;
1753 mr->terminates = true;
1754 mr->rom_device = true;
1755 mr->destructor = memory_region_destructor_ram;
1756 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1757 if (err) {
1758 mr->size = int128_zero();
1759 object_unparent(OBJECT(mr));
1760 error_propagate(errp, err);
1761 }
1762 }
1763
1764 void memory_region_init_iommu(void *_iommu_mr,
1765 size_t instance_size,
1766 const char *mrtypename,
1767 Object *owner,
1768 const char *name,
1769 uint64_t size)
1770 {
1771 struct IOMMUMemoryRegion *iommu_mr;
1772 struct MemoryRegion *mr;
1773
1774 object_initialize(_iommu_mr, instance_size, mrtypename);
1775 mr = MEMORY_REGION(_iommu_mr);
1776 memory_region_do_init(mr, owner, name, size);
1777 iommu_mr = IOMMU_MEMORY_REGION(mr);
1778 mr->terminates = true; /* then re-forwards */
1779 QLIST_INIT(&iommu_mr->iommu_notify);
1780 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
1781 }
1782
1783 static void memory_region_finalize(Object *obj)
1784 {
1785 MemoryRegion *mr = MEMORY_REGION(obj);
1786
1787 assert(!mr->container);
1788
1789 /* We know the region is not visible in any address space (it
1790 * does not have a container and cannot be a root either because
1791 * it has no references, so we can blindly clear mr->enabled.
1792 * memory_region_set_enabled instead could trigger a transaction
1793 * and cause an infinite loop.
1794 */
1795 mr->enabled = false;
1796 memory_region_transaction_begin();
1797 while (!QTAILQ_EMPTY(&mr->subregions)) {
1798 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1799 memory_region_del_subregion(mr, subregion);
1800 }
1801 memory_region_transaction_commit();
1802
1803 mr->destructor(mr);
1804 memory_region_clear_coalescing(mr);
1805 g_free((char *)mr->name);
1806 g_free(mr->ioeventfds);
1807 }
1808
1809 Object *memory_region_owner(MemoryRegion *mr)
1810 {
1811 Object *obj = OBJECT(mr);
1812 return obj->parent;
1813 }
1814
1815 void memory_region_ref(MemoryRegion *mr)
1816 {
1817 /* MMIO callbacks most likely will access data that belongs
1818 * to the owner, hence the need to ref/unref the owner whenever
1819 * the memory region is in use.
1820 *
1821 * The memory region is a child of its owner. As long as the
1822 * owner doesn't call unparent itself on the memory region,
1823 * ref-ing the owner will also keep the memory region alive.
1824 * Memory regions without an owner are supposed to never go away;
1825 * we do not ref/unref them because it slows down DMA sensibly.
1826 */
1827 if (mr && mr->owner) {
1828 object_ref(mr->owner);
1829 }
1830 }
1831
1832 void memory_region_unref(MemoryRegion *mr)
1833 {
1834 if (mr && mr->owner) {
1835 object_unref(mr->owner);
1836 }
1837 }
1838
1839 uint64_t memory_region_size(MemoryRegion *mr)
1840 {
1841 if (int128_eq(mr->size, int128_2_64())) {
1842 return UINT64_MAX;
1843 }
1844 return int128_get64(mr->size);
1845 }
1846
1847 const char *memory_region_name(const MemoryRegion *mr)
1848 {
1849 if (!mr->name) {
1850 ((MemoryRegion *)mr)->name =
1851 g_strdup(object_get_canonical_path_component(OBJECT(mr)));
1852 }
1853 return mr->name;
1854 }
1855
1856 bool memory_region_is_ram_device(MemoryRegion *mr)
1857 {
1858 return mr->ram_device;
1859 }
1860
1861 uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
1862 {
1863 uint8_t mask = mr->dirty_log_mask;
1864 RAMBlock *rb = mr->ram_block;
1865
1866 if (global_dirty_log && ((rb && qemu_ram_is_migratable(rb)) ||
1867 memory_region_is_iommu(mr))) {
1868 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1869 }
1870
1871 if (tcg_enabled() && rb) {
1872 /* TCG only cares about dirty memory logging for RAM, not IOMMU. */
1873 mask |= (1 << DIRTY_MEMORY_CODE);
1874 }
1875 return mask;
1876 }
1877
1878 bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1879 {
1880 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1881 }
1882
1883 static int memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr,
1884 Error **errp)
1885 {
1886 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1887 IOMMUNotifier *iommu_notifier;
1888 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1889 int ret = 0;
1890
1891 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1892 flags |= iommu_notifier->notifier_flags;
1893 }
1894
1895 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1896 ret = imrc->notify_flag_changed(iommu_mr,
1897 iommu_mr->iommu_notify_flags,
1898 flags, errp);
1899 }
1900
1901 if (!ret) {
1902 iommu_mr->iommu_notify_flags = flags;
1903 }
1904 return ret;
1905 }
1906
1907 int memory_region_iommu_set_page_size_mask(IOMMUMemoryRegion *iommu_mr,
1908 uint64_t page_size_mask,
1909 Error **errp)
1910 {
1911 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1912 int ret = 0;
1913
1914 if (imrc->iommu_set_page_size_mask) {
1915 ret = imrc->iommu_set_page_size_mask(iommu_mr, page_size_mask, errp);
1916 }
1917 return ret;
1918 }
1919
1920 int memory_region_register_iommu_notifier(MemoryRegion *mr,
1921 IOMMUNotifier *n, Error **errp)
1922 {
1923 IOMMUMemoryRegion *iommu_mr;
1924 int ret;
1925
1926 if (mr->alias) {
1927 return memory_region_register_iommu_notifier(mr->alias, n, errp);
1928 }
1929
1930 /* We need to register for at least one bitfield */
1931 iommu_mr = IOMMU_MEMORY_REGION(mr);
1932 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
1933 assert(n->start <= n->end);
1934 assert(n->iommu_idx >= 0 &&
1935 n->iommu_idx < memory_region_iommu_num_indexes(iommu_mr));
1936
1937 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1938 ret = memory_region_update_iommu_notify_flags(iommu_mr, errp);
1939 if (ret) {
1940 QLIST_REMOVE(n, node);
1941 }
1942 return ret;
1943 }
1944
1945 uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
1946 {
1947 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1948
1949 if (imrc->get_min_page_size) {
1950 return imrc->get_min_page_size(iommu_mr);
1951 }
1952 return TARGET_PAGE_SIZE;
1953 }
1954
1955 void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
1956 {
1957 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1958 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1959 hwaddr addr, granularity;
1960 IOMMUTLBEntry iotlb;
1961
1962 /* If the IOMMU has its own replay callback, override */
1963 if (imrc->replay) {
1964 imrc->replay(iommu_mr, n);
1965 return;
1966 }
1967
1968 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
1969
1970 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1971 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
1972 if (iotlb.perm != IOMMU_NONE) {
1973 n->notify(n, &iotlb);
1974 }
1975
1976 /* if (2^64 - MR size) < granularity, it's possible to get an
1977 * infinite loop here. This should catch such a wraparound */
1978 if ((addr + granularity) < addr) {
1979 break;
1980 }
1981 }
1982 }
1983
1984 void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1985 IOMMUNotifier *n)
1986 {
1987 IOMMUMemoryRegion *iommu_mr;
1988
1989 if (mr->alias) {
1990 memory_region_unregister_iommu_notifier(mr->alias, n);
1991 return;
1992 }
1993 QLIST_REMOVE(n, node);
1994 iommu_mr = IOMMU_MEMORY_REGION(mr);
1995 memory_region_update_iommu_notify_flags(iommu_mr, NULL);
1996 }
1997
1998 void memory_region_notify_iommu_one(IOMMUNotifier *notifier,
1999 IOMMUTLBEvent *event)
2000 {
2001 IOMMUTLBEntry *entry = &event->entry;
2002 hwaddr entry_end = entry->iova + entry->addr_mask;
2003 IOMMUTLBEntry tmp = *entry;
2004
2005 if (event->type == IOMMU_NOTIFIER_UNMAP) {
2006 assert(entry->perm == IOMMU_NONE);
2007 }
2008
2009 /*
2010 * Skip the notification if the notification does not overlap
2011 * with registered range.
2012 */
2013 if (notifier->start > entry_end || notifier->end < entry->iova) {
2014 return;
2015 }
2016
2017 if (notifier->notifier_flags & IOMMU_NOTIFIER_DEVIOTLB_UNMAP) {
2018 /* Crop (iova, addr_mask) to range */
2019 tmp.iova = MAX(tmp.iova, notifier->start);
2020 tmp.addr_mask = MIN(entry_end, notifier->end) - tmp.iova;
2021 } else {
2022 assert(entry->iova >= notifier->start && entry_end <= notifier->end);
2023 }
2024
2025 if (event->type & notifier->notifier_flags) {
2026 notifier->notify(notifier, &tmp);
2027 }
2028 }
2029
2030 void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
2031 int iommu_idx,
2032 IOMMUTLBEvent event)
2033 {
2034 IOMMUNotifier *iommu_notifier;
2035
2036 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
2037
2038 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
2039 if (iommu_notifier->iommu_idx == iommu_idx) {
2040 memory_region_notify_iommu_one(iommu_notifier, &event);
2041 }
2042 }
2043 }
2044
2045 int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
2046 enum IOMMUMemoryRegionAttr attr,
2047 void *data)
2048 {
2049 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2050
2051 if (!imrc->get_attr) {
2052 return -EINVAL;
2053 }
2054
2055 return imrc->get_attr(iommu_mr, attr, data);
2056 }
2057
2058 int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr,
2059 MemTxAttrs attrs)
2060 {
2061 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2062
2063 if (!imrc->attrs_to_index) {
2064 return 0;
2065 }
2066
2067 return imrc->attrs_to_index(iommu_mr, attrs);
2068 }
2069
2070 int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr)
2071 {
2072 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2073
2074 if (!imrc->num_indexes) {
2075 return 1;
2076 }
2077
2078 return imrc->num_indexes(iommu_mr);
2079 }
2080
2081 void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
2082 {
2083 uint8_t mask = 1 << client;
2084 uint8_t old_logging;
2085
2086 assert(client == DIRTY_MEMORY_VGA);
2087 old_logging = mr->vga_logging_count;
2088 mr->vga_logging_count += log ? 1 : -1;
2089 if (!!old_logging == !!mr->vga_logging_count) {
2090 return;
2091 }
2092
2093 memory_region_transaction_begin();
2094 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
2095 memory_region_update_pending |= mr->enabled;
2096 memory_region_transaction_commit();
2097 }
2098
2099 void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
2100 hwaddr size)
2101 {
2102 assert(mr->ram_block);
2103 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
2104 size,
2105 memory_region_get_dirty_log_mask(mr));
2106 }
2107
2108 static void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
2109 {
2110 MemoryListener *listener;
2111 AddressSpace *as;
2112 FlatView *view;
2113 FlatRange *fr;
2114
2115 /* If the same address space has multiple log_sync listeners, we
2116 * visit that address space's FlatView multiple times. But because
2117 * log_sync listeners are rare, it's still cheaper than walking each
2118 * address space once.
2119 */
2120 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2121 if (!listener->log_sync) {
2122 continue;
2123 }
2124 as = listener->address_space;
2125 view = address_space_get_flatview(as);
2126 FOR_EACH_FLAT_RANGE(fr, view) {
2127 if (fr->dirty_log_mask && (!mr || fr->mr == mr)) {
2128 MemoryRegionSection mrs = section_from_flat_range(fr, view);
2129 listener->log_sync(listener, &mrs);
2130 }
2131 }
2132 flatview_unref(view);
2133 }
2134 }
2135
2136 void memory_region_clear_dirty_bitmap(MemoryRegion *mr, hwaddr start,
2137 hwaddr len)
2138 {
2139 MemoryRegionSection mrs;
2140 MemoryListener *listener;
2141 AddressSpace *as;
2142 FlatView *view;
2143 FlatRange *fr;
2144 hwaddr sec_start, sec_end, sec_size;
2145
2146 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2147 if (!listener->log_clear) {
2148 continue;
2149 }
2150 as = listener->address_space;
2151 view = address_space_get_flatview(as);
2152 FOR_EACH_FLAT_RANGE(fr, view) {
2153 if (!fr->dirty_log_mask || fr->mr != mr) {
2154 /*
2155 * Clear dirty bitmap operation only applies to those
2156 * regions whose dirty logging is at least enabled
2157 */
2158 continue;
2159 }
2160
2161 mrs = section_from_flat_range(fr, view);
2162
2163 sec_start = MAX(mrs.offset_within_region, start);
2164 sec_end = mrs.offset_within_region + int128_get64(mrs.size);
2165 sec_end = MIN(sec_end, start + len);
2166
2167 if (sec_start >= sec_end) {
2168 /*
2169 * If this memory region section has no intersection
2170 * with the requested range, skip.
2171 */
2172 continue;
2173 }
2174
2175 /* Valid case; shrink the section if needed */
2176 mrs.offset_within_address_space +=
2177 sec_start - mrs.offset_within_region;
2178 mrs.offset_within_region = sec_start;
2179 sec_size = sec_end - sec_start;
2180 mrs.size = int128_make64(sec_size);
2181 listener->log_clear(listener, &mrs);
2182 }
2183 flatview_unref(view);
2184 }
2185 }
2186
2187 DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
2188 hwaddr addr,
2189 hwaddr size,
2190 unsigned client)
2191 {
2192 DirtyBitmapSnapshot *snapshot;
2193 assert(mr->ram_block);
2194 memory_region_sync_dirty_bitmap(mr);
2195 snapshot = cpu_physical_memory_snapshot_and_clear_dirty(mr, addr, size, client);
2196 memory_global_after_dirty_log_sync();
2197 return snapshot;
2198 }
2199
2200 bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
2201 hwaddr addr, hwaddr size)
2202 {
2203 assert(mr->ram_block);
2204 return cpu_physical_memory_snapshot_get_dirty(snap,
2205 memory_region_get_ram_addr(mr) + addr, size);
2206 }
2207
2208 void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2209 {
2210 if (mr->readonly != readonly) {
2211 memory_region_transaction_begin();
2212 mr->readonly = readonly;
2213 memory_region_update_pending |= mr->enabled;
2214 memory_region_transaction_commit();
2215 }
2216 }
2217
2218 void memory_region_set_nonvolatile(MemoryRegion *mr, bool nonvolatile)
2219 {
2220 if (mr->nonvolatile != nonvolatile) {
2221 memory_region_transaction_begin();
2222 mr->nonvolatile = nonvolatile;
2223 memory_region_update_pending |= mr->enabled;
2224 memory_region_transaction_commit();
2225 }
2226 }
2227
2228 void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
2229 {
2230 if (mr->romd_mode != romd_mode) {
2231 memory_region_transaction_begin();
2232 mr->romd_mode = romd_mode;
2233 memory_region_update_pending |= mr->enabled;
2234 memory_region_transaction_commit();
2235 }
2236 }
2237
2238 void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2239 hwaddr size, unsigned client)
2240 {
2241 assert(mr->ram_block);
2242 cpu_physical_memory_test_and_clear_dirty(
2243 memory_region_get_ram_addr(mr) + addr, size, client);
2244 }
2245
2246 int memory_region_get_fd(MemoryRegion *mr)
2247 {
2248 int fd;
2249
2250 RCU_READ_LOCK_GUARD();
2251 while (mr->alias) {
2252 mr = mr->alias;
2253 }
2254 fd = mr->ram_block->fd;
2255
2256 return fd;
2257 }
2258
2259 void *memory_region_get_ram_ptr(MemoryRegion *mr)
2260 {
2261 void *ptr;
2262 uint64_t offset = 0;
2263
2264 RCU_READ_LOCK_GUARD();
2265 while (mr->alias) {
2266 offset += mr->alias_offset;
2267 mr = mr->alias;
2268 }
2269 assert(mr->ram_block);
2270 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
2271
2272 return ptr;
2273 }
2274
2275 MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2276 {
2277 RAMBlock *block;
2278
2279 block = qemu_ram_block_from_host(ptr, false, offset);
2280 if (!block) {
2281 return NULL;
2282 }
2283
2284 return block->mr;
2285 }
2286
2287 ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2288 {
2289 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2290 }
2291
2292 void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2293 {
2294 assert(mr->ram_block);
2295
2296 qemu_ram_resize(mr->ram_block, newsize, errp);
2297 }
2298
2299 void memory_region_msync(MemoryRegion *mr, hwaddr addr, hwaddr size)
2300 {
2301 if (mr->ram_block) {
2302 qemu_ram_msync(mr->ram_block, addr, size);
2303 }
2304 }
2305
2306 void memory_region_writeback(MemoryRegion *mr, hwaddr addr, hwaddr size)
2307 {
2308 /*
2309 * Might be extended case needed to cover
2310 * different types of memory regions
2311 */
2312 if (mr->dirty_log_mask) {
2313 memory_region_msync(mr, addr, size);
2314 }
2315 }
2316
2317 /*
2318 * Call proper memory listeners about the change on the newly
2319 * added/removed CoalescedMemoryRange.
2320 */
2321 static void memory_region_update_coalesced_range(MemoryRegion *mr,
2322 CoalescedMemoryRange *cmr,
2323 bool add)
2324 {
2325 AddressSpace *as;
2326 FlatView *view;
2327 FlatRange *fr;
2328
2329 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2330 view = address_space_get_flatview(as);
2331 FOR_EACH_FLAT_RANGE(fr, view) {
2332 if (fr->mr == mr) {
2333 flat_range_coalesced_io_notify(fr, as, cmr, add);
2334 }
2335 }
2336 flatview_unref(view);
2337 }
2338 }
2339
2340 void memory_region_set_coalescing(MemoryRegion *mr)
2341 {
2342 memory_region_clear_coalescing(mr);
2343 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
2344 }
2345
2346 void memory_region_add_coalescing(MemoryRegion *mr,
2347 hwaddr offset,
2348 uint64_t size)
2349 {
2350 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
2351
2352 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
2353 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2354 memory_region_update_coalesced_range(mr, cmr, true);
2355 memory_region_set_flush_coalesced(mr);
2356 }
2357
2358 void memory_region_clear_coalescing(MemoryRegion *mr)
2359 {
2360 CoalescedMemoryRange *cmr;
2361
2362 if (QTAILQ_EMPTY(&mr->coalesced)) {
2363 return;
2364 }
2365
2366 qemu_flush_coalesced_mmio_buffer();
2367 mr->flush_coalesced_mmio = false;
2368
2369 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2370 cmr = QTAILQ_FIRST(&mr->coalesced);
2371 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
2372 memory_region_update_coalesced_range(mr, cmr, false);
2373 g_free(cmr);
2374 }
2375 }
2376
2377 void memory_region_set_flush_coalesced(MemoryRegion *mr)
2378 {
2379 mr->flush_coalesced_mmio = true;
2380 }
2381
2382 void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2383 {
2384 qemu_flush_coalesced_mmio_buffer();
2385 if (QTAILQ_EMPTY(&mr->coalesced)) {
2386 mr->flush_coalesced_mmio = false;
2387 }
2388 }
2389
2390 static bool userspace_eventfd_warning;
2391
2392 void memory_region_add_eventfd(MemoryRegion *mr,
2393 hwaddr addr,
2394 unsigned size,
2395 bool match_data,
2396 uint64_t data,
2397 EventNotifier *e)
2398 {
2399 MemoryRegionIoeventfd mrfd = {
2400 .addr.start = int128_make64(addr),
2401 .addr.size = int128_make64(size),
2402 .match_data = match_data,
2403 .data = data,
2404 .e = e,
2405 };
2406 unsigned i;
2407
2408 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2409 userspace_eventfd_warning))) {
2410 userspace_eventfd_warning = true;
2411 error_report("Using eventfd without MMIO binding in KVM. "
2412 "Suboptimal performance expected");
2413 }
2414
2415 if (size) {
2416 adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE);
2417 }
2418 memory_region_transaction_begin();
2419 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2420 if (memory_region_ioeventfd_before(&mrfd, &mr->ioeventfds[i])) {
2421 break;
2422 }
2423 }
2424 ++mr->ioeventfd_nb;
2425 mr->ioeventfds = g_realloc(mr->ioeventfds,
2426 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2427 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2428 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2429 mr->ioeventfds[i] = mrfd;
2430 ioeventfd_update_pending |= mr->enabled;
2431 memory_region_transaction_commit();
2432 }
2433
2434 void memory_region_del_eventfd(MemoryRegion *mr,
2435 hwaddr addr,
2436 unsigned size,
2437 bool match_data,
2438 uint64_t data,
2439 EventNotifier *e)
2440 {
2441 MemoryRegionIoeventfd mrfd = {
2442 .addr.start = int128_make64(addr),
2443 .addr.size = int128_make64(size),
2444 .match_data = match_data,
2445 .data = data,
2446 .e = e,
2447 };
2448 unsigned i;
2449
2450 if (size) {
2451 adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE);
2452 }
2453 memory_region_transaction_begin();
2454 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2455 if (memory_region_ioeventfd_equal(&mrfd, &mr->ioeventfds[i])) {
2456 break;
2457 }
2458 }
2459 assert(i != mr->ioeventfd_nb);
2460 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2461 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2462 --mr->ioeventfd_nb;
2463 mr->ioeventfds = g_realloc(mr->ioeventfds,
2464 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
2465 ioeventfd_update_pending |= mr->enabled;
2466 memory_region_transaction_commit();
2467 }
2468
2469 static void memory_region_update_container_subregions(MemoryRegion *subregion)
2470 {
2471 MemoryRegion *mr = subregion->container;
2472 MemoryRegion *other;
2473
2474 memory_region_transaction_begin();
2475
2476 memory_region_ref(subregion);
2477 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2478 if (subregion->priority >= other->priority) {
2479 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2480 goto done;
2481 }
2482 }
2483 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2484 done:
2485 memory_region_update_pending |= mr->enabled && subregion->enabled;
2486 memory_region_transaction_commit();
2487 }
2488
2489 static void memory_region_add_subregion_common(MemoryRegion *mr,
2490 hwaddr offset,
2491 MemoryRegion *subregion)
2492 {
2493 assert(!subregion->container);
2494 subregion->container = mr;
2495 subregion->addr = offset;
2496 memory_region_update_container_subregions(subregion);
2497 }
2498
2499 void memory_region_add_subregion(MemoryRegion *mr,
2500 hwaddr offset,
2501 MemoryRegion *subregion)
2502 {
2503 subregion->priority = 0;
2504 memory_region_add_subregion_common(mr, offset, subregion);
2505 }
2506
2507 void memory_region_add_subregion_overlap(MemoryRegion *mr,
2508 hwaddr offset,
2509 MemoryRegion *subregion,
2510 int priority)
2511 {
2512 subregion->priority = priority;
2513 memory_region_add_subregion_common(mr, offset, subregion);
2514 }
2515
2516 void memory_region_del_subregion(MemoryRegion *mr,
2517 MemoryRegion *subregion)
2518 {
2519 memory_region_transaction_begin();
2520 assert(subregion->container == mr);
2521 subregion->container = NULL;
2522 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
2523 memory_region_unref(subregion);
2524 memory_region_update_pending |= mr->enabled && subregion->enabled;
2525 memory_region_transaction_commit();
2526 }
2527
2528 void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2529 {
2530 if (enabled == mr->enabled) {
2531 return;
2532 }
2533 memory_region_transaction_begin();
2534 mr->enabled = enabled;
2535 memory_region_update_pending = true;
2536 memory_region_transaction_commit();
2537 }
2538
2539 void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2540 {
2541 Int128 s = int128_make64(size);
2542
2543 if (size == UINT64_MAX) {
2544 s = int128_2_64();
2545 }
2546 if (int128_eq(s, mr->size)) {
2547 return;
2548 }
2549 memory_region_transaction_begin();
2550 mr->size = s;
2551 memory_region_update_pending = true;
2552 memory_region_transaction_commit();
2553 }
2554
2555 static void memory_region_readd_subregion(MemoryRegion *mr)
2556 {
2557 MemoryRegion *container = mr->container;
2558
2559 if (container) {
2560 memory_region_transaction_begin();
2561 memory_region_ref(mr);
2562 memory_region_del_subregion(container, mr);
2563 mr->container = container;
2564 memory_region_update_container_subregions(mr);
2565 memory_region_unref(mr);
2566 memory_region_transaction_commit();
2567 }
2568 }
2569
2570 void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2571 {
2572 if (addr != mr->addr) {
2573 mr->addr = addr;
2574 memory_region_readd_subregion(mr);
2575 }
2576 }
2577
2578 void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
2579 {
2580 assert(mr->alias);
2581
2582 if (offset == mr->alias_offset) {
2583 return;
2584 }
2585
2586 memory_region_transaction_begin();
2587 mr->alias_offset = offset;
2588 memory_region_update_pending |= mr->enabled;
2589 memory_region_transaction_commit();
2590 }
2591
2592 uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2593 {
2594 return mr->align;
2595 }
2596
2597 static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2598 {
2599 const AddrRange *addr = addr_;
2600 const FlatRange *fr = fr_;
2601
2602 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2603 return -1;
2604 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2605 return 1;
2606 }
2607 return 0;
2608 }
2609
2610 static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
2611 {
2612 return bsearch(&addr, view->ranges, view->nr,
2613 sizeof(FlatRange), cmp_flatrange_addr);
2614 }
2615
2616 bool memory_region_is_mapped(MemoryRegion *mr)
2617 {
2618 return mr->container ? true : false;
2619 }
2620
2621 /* Same as memory_region_find, but it does not add a reference to the
2622 * returned region. It must be called from an RCU critical section.
2623 */
2624 static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2625 hwaddr addr, uint64_t size)
2626 {
2627 MemoryRegionSection ret = { .mr = NULL };
2628 MemoryRegion *root;
2629 AddressSpace *as;
2630 AddrRange range;
2631 FlatView *view;
2632 FlatRange *fr;
2633
2634 addr += mr->addr;
2635 for (root = mr; root->container; ) {
2636 root = root->container;
2637 addr += root->addr;
2638 }
2639
2640 as = memory_region_to_address_space(root);
2641 if (!as) {
2642 return ret;
2643 }
2644 range = addrrange_make(int128_make64(addr), int128_make64(size));
2645
2646 view = address_space_to_flatview(as);
2647 fr = flatview_lookup(view, range);
2648 if (!fr) {
2649 return ret;
2650 }
2651
2652 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
2653 --fr;
2654 }
2655
2656 ret.mr = fr->mr;
2657 ret.fv = view;
2658 range = addrrange_intersection(range, fr->addr);
2659 ret.offset_within_region = fr->offset_in_region;
2660 ret.offset_within_region += int128_get64(int128_sub(range.start,
2661 fr->addr.start));
2662 ret.size = range.size;
2663 ret.offset_within_address_space = int128_get64(range.start);
2664 ret.readonly = fr->readonly;
2665 ret.nonvolatile = fr->nonvolatile;
2666 return ret;
2667 }
2668
2669 MemoryRegionSection memory_region_find(MemoryRegion *mr,
2670 hwaddr addr, uint64_t size)
2671 {
2672 MemoryRegionSection ret;
2673 RCU_READ_LOCK_GUARD();
2674 ret = memory_region_find_rcu(mr, addr, size);
2675 if (ret.mr) {
2676 memory_region_ref(ret.mr);
2677 }
2678 return ret;
2679 }
2680
2681 bool memory_region_present(MemoryRegion *container, hwaddr addr)
2682 {
2683 MemoryRegion *mr;
2684
2685 RCU_READ_LOCK_GUARD();
2686 mr = memory_region_find_rcu(container, addr, 1).mr;
2687 return mr && mr != container;
2688 }
2689
2690 void memory_global_dirty_log_sync(void)
2691 {
2692 memory_region_sync_dirty_bitmap(NULL);
2693 }
2694
2695 void memory_global_after_dirty_log_sync(void)
2696 {
2697 MEMORY_LISTENER_CALL_GLOBAL(log_global_after_sync, Forward);
2698 }
2699
2700 static VMChangeStateEntry *vmstate_change;
2701
2702 void memory_global_dirty_log_start(void)
2703 {
2704 if (vmstate_change) {
2705 qemu_del_vm_change_state_handler(vmstate_change);
2706 vmstate_change = NULL;
2707 }
2708
2709 global_dirty_log = true;
2710
2711 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
2712
2713 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
2714 memory_region_transaction_begin();
2715 memory_region_update_pending = true;
2716 memory_region_transaction_commit();
2717 }
2718
2719 static void memory_global_dirty_log_do_stop(void)
2720 {
2721 global_dirty_log = false;
2722
2723 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
2724 memory_region_transaction_begin();
2725 memory_region_update_pending = true;
2726 memory_region_transaction_commit();
2727
2728 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
2729 }
2730
2731 static void memory_vm_change_state_handler(void *opaque, bool running,
2732 RunState state)
2733 {
2734 if (running) {
2735 memory_global_dirty_log_do_stop();
2736
2737 if (vmstate_change) {
2738 qemu_del_vm_change_state_handler(vmstate_change);
2739 vmstate_change = NULL;
2740 }
2741 }
2742 }
2743
2744 void memory_global_dirty_log_stop(void)
2745 {
2746 if (!runstate_is_running()) {
2747 if (vmstate_change) {
2748 return;
2749 }
2750 vmstate_change = qemu_add_vm_change_state_handler(
2751 memory_vm_change_state_handler, NULL);
2752 return;
2753 }
2754
2755 memory_global_dirty_log_do_stop();
2756 }
2757
2758 static void listener_add_address_space(MemoryListener *listener,
2759 AddressSpace *as)
2760 {
2761 FlatView *view;
2762 FlatRange *fr;
2763
2764 if (listener->begin) {
2765 listener->begin(listener);
2766 }
2767 if (global_dirty_log) {
2768 if (listener->log_global_start) {
2769 listener->log_global_start(listener);
2770 }
2771 }
2772
2773 view = address_space_get_flatview(as);
2774 FOR_EACH_FLAT_RANGE(fr, view) {
2775 MemoryRegionSection section = section_from_flat_range(fr, view);
2776
2777 if (listener->region_add) {
2778 listener->region_add(listener, &section);
2779 }
2780 if (fr->dirty_log_mask && listener->log_start) {
2781 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2782 }
2783 }
2784 if (listener->commit) {
2785 listener->commit(listener);
2786 }
2787 flatview_unref(view);
2788 }
2789
2790 static void listener_del_address_space(MemoryListener *listener,
2791 AddressSpace *as)
2792 {
2793 FlatView *view;
2794 FlatRange *fr;
2795
2796 if (listener->begin) {
2797 listener->begin(listener);
2798 }
2799 view = address_space_get_flatview(as);
2800 FOR_EACH_FLAT_RANGE(fr, view) {
2801 MemoryRegionSection section = section_from_flat_range(fr, view);
2802
2803 if (fr->dirty_log_mask && listener->log_stop) {
2804 listener->log_stop(listener, &section, fr->dirty_log_mask, 0);
2805 }
2806 if (listener->region_del) {
2807 listener->region_del(listener, &section);
2808 }
2809 }
2810 if (listener->commit) {
2811 listener->commit(listener);
2812 }
2813 flatview_unref(view);
2814 }
2815
2816 void memory_listener_register(MemoryListener *listener, AddressSpace *as)
2817 {
2818 MemoryListener *other = NULL;
2819
2820 listener->address_space = as;
2821 if (QTAILQ_EMPTY(&memory_listeners)
2822 || listener->priority >= QTAILQ_LAST(&memory_listeners)->priority) {
2823 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2824 } else {
2825 QTAILQ_FOREACH(other, &memory_listeners, link) {
2826 if (listener->priority < other->priority) {
2827 break;
2828 }
2829 }
2830 QTAILQ_INSERT_BEFORE(other, listener, link);
2831 }
2832
2833 if (QTAILQ_EMPTY(&as->listeners)
2834 || listener->priority >= QTAILQ_LAST(&as->listeners)->priority) {
2835 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2836 } else {
2837 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2838 if (listener->priority < other->priority) {
2839 break;
2840 }
2841 }
2842 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2843 }
2844
2845 listener_add_address_space(listener, as);
2846 }
2847
2848 void memory_listener_unregister(MemoryListener *listener)
2849 {
2850 if (!listener->address_space) {
2851 return;
2852 }
2853
2854 listener_del_address_space(listener, listener->address_space);
2855 QTAILQ_REMOVE(&memory_listeners, listener, link);
2856 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
2857 listener->address_space = NULL;
2858 }
2859
2860 void address_space_remove_listeners(AddressSpace *as)
2861 {
2862 while (!QTAILQ_EMPTY(&as->listeners)) {
2863 memory_listener_unregister(QTAILQ_FIRST(&as->listeners));
2864 }
2865 }
2866
2867 void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
2868 {
2869 memory_region_ref(root);
2870 as->root = root;
2871 as->current_map = NULL;
2872 as->ioeventfd_nb = 0;
2873 as->ioeventfds = NULL;
2874 QTAILQ_INIT(&as->listeners);
2875 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
2876 as->name = g_strdup(name ? name : "anonymous");
2877 address_space_update_topology(as);
2878 address_space_update_ioeventfds(as);
2879 }
2880
2881 static void do_address_space_destroy(AddressSpace *as)
2882 {
2883 assert(QTAILQ_EMPTY(&as->listeners));
2884
2885 flatview_unref(as->current_map);
2886 g_free(as->name);
2887 g_free(as->ioeventfds);
2888 memory_region_unref(as->root);
2889 }
2890
2891 void address_space_destroy(AddressSpace *as)
2892 {
2893 MemoryRegion *root = as->root;
2894
2895 /* Flush out anything from MemoryListeners listening in on this */
2896 memory_region_transaction_begin();
2897 as->root = NULL;
2898 memory_region_transaction_commit();
2899 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2900
2901 /* At this point, as->dispatch and as->current_map are dummy
2902 * entries that the guest should never use. Wait for the old
2903 * values to expire before freeing the data.
2904 */
2905 as->root = root;
2906 call_rcu(as, do_address_space_destroy, rcu);
2907 }
2908
2909 static const char *memory_region_type(MemoryRegion *mr)
2910 {
2911 if (mr->alias) {
2912 return memory_region_type(mr->alias);
2913 }
2914 if (memory_region_is_ram_device(mr)) {
2915 return "ramd";
2916 } else if (memory_region_is_romd(mr)) {
2917 return "romd";
2918 } else if (memory_region_is_rom(mr)) {
2919 return "rom";
2920 } else if (memory_region_is_ram(mr)) {
2921 return "ram";
2922 } else {
2923 return "i/o";
2924 }
2925 }
2926
2927 typedef struct MemoryRegionList MemoryRegionList;
2928
2929 struct MemoryRegionList {
2930 const MemoryRegion *mr;
2931 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
2932 };
2933
2934 typedef QTAILQ_HEAD(, MemoryRegionList) MemoryRegionListHead;
2935
2936 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2937 int128_sub((size), int128_one())) : 0)
2938 #define MTREE_INDENT " "
2939
2940 static void mtree_expand_owner(const char *label, Object *obj)
2941 {
2942 DeviceState *dev = (DeviceState *) object_dynamic_cast(obj, TYPE_DEVICE);
2943
2944 qemu_printf(" %s:{%s", label, dev ? "dev" : "obj");
2945 if (dev && dev->id) {
2946 qemu_printf(" id=%s", dev->id);
2947 } else {
2948 char *canonical_path = object_get_canonical_path(obj);
2949 if (canonical_path) {
2950 qemu_printf(" path=%s", canonical_path);
2951 g_free(canonical_path);
2952 } else {
2953 qemu_printf(" type=%s", object_get_typename(obj));
2954 }
2955 }
2956 qemu_printf("}");
2957 }
2958
2959 static void mtree_print_mr_owner(const MemoryRegion *mr)
2960 {
2961 Object *owner = mr->owner;
2962 Object *parent = memory_region_owner((MemoryRegion *)mr);
2963
2964 if (!owner && !parent) {
2965 qemu_printf(" orphan");
2966 return;
2967 }
2968 if (owner) {
2969 mtree_expand_owner("owner", owner);
2970 }
2971 if (parent && parent != owner) {
2972 mtree_expand_owner("parent", parent);
2973 }
2974 }
2975
2976 static void mtree_print_mr(const MemoryRegion *mr, unsigned int level,
2977 hwaddr base,
2978 MemoryRegionListHead *alias_print_queue,
2979 bool owner, bool display_disabled)
2980 {
2981 MemoryRegionList *new_ml, *ml, *next_ml;
2982 MemoryRegionListHead submr_print_queue;
2983 const MemoryRegion *submr;
2984 unsigned int i;
2985 hwaddr cur_start, cur_end;
2986
2987 if (!mr) {
2988 return;
2989 }
2990
2991 cur_start = base + mr->addr;
2992 cur_end = cur_start + MR_SIZE(mr->size);
2993
2994 /*
2995 * Try to detect overflow of memory region. This should never
2996 * happen normally. When it happens, we dump something to warn the
2997 * user who is observing this.
2998 */
2999 if (cur_start < base || cur_end < cur_start) {
3000 qemu_printf("[DETECTED OVERFLOW!] ");
3001 }
3002
3003 if (mr->alias) {
3004 MemoryRegionList *ml;
3005 bool found = false;
3006
3007 /* check if the alias is already in the queue */
3008 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
3009 if (ml->mr == mr->alias) {
3010 found = true;
3011 }
3012 }
3013
3014 if (!found) {
3015 ml = g_new(MemoryRegionList, 1);
3016 ml->mr = mr->alias;
3017 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
3018 }
3019 if (mr->enabled || display_disabled) {
3020 for (i = 0; i < level; i++) {
3021 qemu_printf(MTREE_INDENT);
3022 }
3023 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
3024 " (prio %d, %s%s): alias %s @%s " TARGET_FMT_plx
3025 "-" TARGET_FMT_plx "%s",
3026 cur_start, cur_end,
3027 mr->priority,
3028 mr->nonvolatile ? "nv-" : "",
3029 memory_region_type((MemoryRegion *)mr),
3030 memory_region_name(mr),
3031 memory_region_name(mr->alias),
3032 mr->alias_offset,
3033 mr->alias_offset + MR_SIZE(mr->size),
3034 mr->enabled ? "" : " [disabled]");
3035 if (owner) {
3036 mtree_print_mr_owner(mr);
3037 }
3038 qemu_printf("\n");
3039 }
3040 } else {
3041 if (mr->enabled || display_disabled) {
3042 for (i = 0; i < level; i++) {
3043 qemu_printf(MTREE_INDENT);
3044 }
3045 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
3046 " (prio %d, %s%s): %s%s",
3047 cur_start, cur_end,
3048 mr->priority,
3049 mr->nonvolatile ? "nv-" : "",
3050 memory_region_type((MemoryRegion *)mr),
3051 memory_region_name(mr),
3052 mr->enabled ? "" : " [disabled]");
3053 if (owner) {
3054 mtree_print_mr_owner(mr);
3055 }
3056 qemu_printf("\n");
3057 }
3058 }
3059
3060 QTAILQ_INIT(&submr_print_queue);
3061
3062 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
3063 new_ml = g_new(MemoryRegionList, 1);
3064 new_ml->mr = submr;
3065 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
3066 if (new_ml->mr->addr < ml->mr->addr ||
3067 (new_ml->mr->addr == ml->mr->addr &&
3068 new_ml->mr->priority > ml->mr->priority)) {
3069 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
3070 new_ml = NULL;
3071 break;
3072 }
3073 }
3074 if (new_ml) {
3075 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
3076 }
3077 }
3078
3079 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
3080 mtree_print_mr(ml->mr, level + 1, cur_start,
3081 alias_print_queue, owner, display_disabled);
3082 }
3083
3084 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
3085 g_free(ml);
3086 }
3087 }
3088
3089 struct FlatViewInfo {
3090 int counter;
3091 bool dispatch_tree;
3092 bool owner;
3093 AccelClass *ac;
3094 };
3095
3096 static void mtree_print_flatview(gpointer key, gpointer value,
3097 gpointer user_data)
3098 {
3099 FlatView *view = key;
3100 GArray *fv_address_spaces = value;
3101 struct FlatViewInfo *fvi = user_data;
3102 FlatRange *range = &view->ranges[0];
3103 MemoryRegion *mr;
3104 int n = view->nr;
3105 int i;
3106 AddressSpace *as;
3107
3108 qemu_printf("FlatView #%d\n", fvi->counter);
3109 ++fvi->counter;
3110
3111 for (i = 0; i < fv_address_spaces->len; ++i) {
3112 as = g_array_index(fv_address_spaces, AddressSpace*, i);
3113 qemu_printf(" AS \"%s\", root: %s",
3114 as->name, memory_region_name(as->root));
3115 if (as->root->alias) {
3116 qemu_printf(", alias %s", memory_region_name(as->root->alias));
3117 }
3118 qemu_printf("\n");
3119 }
3120
3121 qemu_printf(" Root memory region: %s\n",
3122 view->root ? memory_region_name(view->root) : "(none)");
3123
3124 if (n <= 0) {
3125 qemu_printf(MTREE_INDENT "No rendered FlatView\n\n");
3126 return;
3127 }
3128
3129 while (n--) {
3130 mr = range->mr;
3131 if (range->offset_in_region) {
3132 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3133 " (prio %d, %s%s): %s @" TARGET_FMT_plx,
3134 int128_get64(range->addr.start),
3135 int128_get64(range->addr.start)
3136 + MR_SIZE(range->addr.size),
3137 mr->priority,
3138 range->nonvolatile ? "nv-" : "",
3139 range->readonly ? "rom" : memory_region_type(mr),
3140 memory_region_name(mr),
3141 range->offset_in_region);
3142 } else {
3143 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3144 " (prio %d, %s%s): %s",
3145 int128_get64(range->addr.start),
3146 int128_get64(range->addr.start)
3147 + MR_SIZE(range->addr.size),
3148 mr->priority,
3149 range->nonvolatile ? "nv-" : "",
3150 range->readonly ? "rom" : memory_region_type(mr),
3151 memory_region_name(mr));
3152 }
3153 if (fvi->owner) {
3154 mtree_print_mr_owner(mr);
3155 }
3156
3157 if (fvi->ac) {
3158 for (i = 0; i < fv_address_spaces->len; ++i) {
3159 as = g_array_index(fv_address_spaces, AddressSpace*, i);
3160 if (fvi->ac->has_memory(current_machine, as,
3161 int128_get64(range->addr.start),
3162 MR_SIZE(range->addr.size) + 1)) {
3163 qemu_printf(" %s", fvi->ac->name);
3164 }
3165 }
3166 }
3167 qemu_printf("\n");
3168 range++;
3169 }
3170
3171 #if !defined(CONFIG_USER_ONLY)
3172 if (fvi->dispatch_tree && view->root) {
3173 mtree_print_dispatch(view->dispatch, view->root);
3174 }
3175 #endif
3176
3177 qemu_printf("\n");
3178 }
3179
3180 static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3181 gpointer user_data)
3182 {
3183 FlatView *view = key;
3184 GArray *fv_address_spaces = value;
3185
3186 g_array_unref(fv_address_spaces);
3187 flatview_unref(view);
3188
3189 return true;
3190 }
3191
3192 void mtree_info(bool flatview, bool dispatch_tree, bool owner, bool disabled)
3193 {
3194 MemoryRegionListHead ml_head;
3195 MemoryRegionList *ml, *ml2;
3196 AddressSpace *as;
3197
3198 if (flatview) {
3199 FlatView *view;
3200 struct FlatViewInfo fvi = {
3201 .counter = 0,
3202 .dispatch_tree = dispatch_tree,
3203 .owner = owner,
3204 };
3205 GArray *fv_address_spaces;
3206 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
3207 AccelClass *ac = ACCEL_GET_CLASS(current_accel());
3208
3209 if (ac->has_memory) {
3210 fvi.ac = ac;
3211 }
3212
3213 /* Gather all FVs in one table */
3214 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3215 view = address_space_get_flatview(as);
3216
3217 fv_address_spaces = g_hash_table_lookup(views, view);
3218 if (!fv_address_spaces) {
3219 fv_address_spaces = g_array_new(false, false, sizeof(as));
3220 g_hash_table_insert(views, view, fv_address_spaces);
3221 }
3222
3223 g_array_append_val(fv_address_spaces, as);
3224 }
3225
3226 /* Print */
3227 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3228
3229 /* Free */
3230 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3231 g_hash_table_unref(views);
3232
3233 return;
3234 }
3235
3236 QTAILQ_INIT(&ml_head);
3237
3238 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3239 qemu_printf("address-space: %s\n", as->name);
3240 mtree_print_mr(as->root, 1, 0, &ml_head, owner, disabled);
3241 qemu_printf("\n");
3242 }
3243
3244 /* print aliased regions */
3245 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
3246 qemu_printf("memory-region: %s\n", memory_region_name(ml->mr));
3247 mtree_print_mr(ml->mr, 1, 0, &ml_head, owner, disabled);
3248 qemu_printf("\n");
3249 }
3250
3251 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
3252 g_free(ml);
3253 }
3254 }
3255
3256 void memory_region_init_ram(MemoryRegion *mr,
3257 Object *owner,
3258 const char *name,
3259 uint64_t size,
3260 Error **errp)
3261 {
3262 DeviceState *owner_dev;
3263 Error *err = NULL;
3264
3265 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3266 if (err) {
3267 error_propagate(errp, err);
3268 return;
3269 }
3270 /* This will assert if owner is neither NULL nor a DeviceState.
3271 * We only want the owner here for the purposes of defining a
3272 * unique name for migration. TODO: Ideally we should implement
3273 * a naming scheme for Objects which are not DeviceStates, in
3274 * which case we can relax this restriction.
3275 */
3276 owner_dev = DEVICE(owner);
3277 vmstate_register_ram(mr, owner_dev);
3278 }
3279
3280 void memory_region_init_rom(MemoryRegion *mr,
3281 Object *owner,
3282 const char *name,
3283 uint64_t size,
3284 Error **errp)
3285 {
3286 DeviceState *owner_dev;
3287 Error *err = NULL;
3288
3289 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3290 if (err) {
3291 error_propagate(errp, err);
3292 return;
3293 }
3294 /* This will assert if owner is neither NULL nor a DeviceState.
3295 * We only want the owner here for the purposes of defining a
3296 * unique name for migration. TODO: Ideally we should implement
3297 * a naming scheme for Objects which are not DeviceStates, in
3298 * which case we can relax this restriction.
3299 */
3300 owner_dev = DEVICE(owner);
3301 vmstate_register_ram(mr, owner_dev);
3302 }
3303
3304 void memory_region_init_rom_device(MemoryRegion *mr,
3305 Object *owner,
3306 const MemoryRegionOps *ops,
3307 void *opaque,
3308 const char *name,
3309 uint64_t size,
3310 Error **errp)
3311 {
3312 DeviceState *owner_dev;
3313 Error *err = NULL;
3314
3315 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3316 name, size, &err);
3317 if (err) {
3318 error_propagate(errp, err);
3319 return;
3320 }
3321 /* This will assert if owner is neither NULL nor a DeviceState.
3322 * We only want the owner here for the purposes of defining a
3323 * unique name for migration. TODO: Ideally we should implement
3324 * a naming scheme for Objects which are not DeviceStates, in
3325 * which case we can relax this restriction.
3326 */
3327 owner_dev = DEVICE(owner);
3328 vmstate_register_ram(mr, owner_dev);
3329 }
3330
3331 /*
3332 * Support softmmu builds with CONFIG_FUZZ using a weak symbol and a stub for
3333 * the fuzz_dma_read_cb callback
3334 */
3335 #ifdef CONFIG_FUZZ
3336 void __attribute__((weak)) fuzz_dma_read_cb(size_t addr,
3337 size_t len,
3338 MemoryRegion *mr)
3339 {
3340 }
3341 #endif
3342
3343 static const TypeInfo memory_region_info = {
3344 .parent = TYPE_OBJECT,
3345 .name = TYPE_MEMORY_REGION,
3346 .class_size = sizeof(MemoryRegionClass),
3347 .instance_size = sizeof(MemoryRegion),
3348 .instance_init = memory_region_initfn,
3349 .instance_finalize = memory_region_finalize,
3350 };
3351
3352 static const TypeInfo iommu_memory_region_info = {
3353 .parent = TYPE_MEMORY_REGION,
3354 .name = TYPE_IOMMU_MEMORY_REGION,
3355 .class_size = sizeof(IOMMUMemoryRegionClass),
3356 .instance_size = sizeof(IOMMUMemoryRegion),
3357 .instance_init = iommu_memory_region_initfn,
3358 .abstract = true,
3359 };
3360
3361 static void memory_register_types(void)
3362 {
3363 type_register_static(&memory_region_info);
3364 type_register_static(&iommu_memory_region_info);
3365 }
3366
3367 type_init(memory_register_types)
AR7 emulation for QEMU