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target/xtensa: implement MPU option
[qemu/ar7.git] / target / xtensa / translate.c
blob782f2ec62099d3b17bb5ec0ee145b20a9047b671
1 /*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include "qemu/osdep.h"
32
33 #include "cpu.h"
34 #include "exec/exec-all.h"
35 #include "disas/disas.h"
36 #include "tcg-op.h"
37 #include "qemu/log.h"
38 #include "qemu/qemu-print.h"
39 #include "sysemu/sysemu.h"
40 #include "exec/cpu_ldst.h"
41 #include "exec/semihost.h"
42 #include "exec/translator.h"
43
44 #include "exec/helper-proto.h"
45 #include "exec/helper-gen.h"
46
47 #include "trace-tcg.h"
48 #include "exec/log.h"
49
50
51 struct DisasContext {
52 DisasContextBase base;
53 const XtensaConfig *config;
54 uint32_t pc;
55 int cring;
56 int ring;
57 uint32_t lbeg_off;
58 uint32_t lend;
59
60 bool sar_5bit;
61 bool sar_m32_5bit;
62 bool sar_m32_allocated;
63 TCGv_i32 sar_m32;
64
65 unsigned window;
66 unsigned callinc;
67 bool cwoe;
68
69 bool debug;
70 bool icount;
71 TCGv_i32 next_icount;
72
73 unsigned cpenable;
74
75 uint32_t op_flags;
76 xtensa_insnbuf insnbuf;
77 xtensa_insnbuf slotbuf;
78 };
79
80 static TCGv_i32 cpu_pc;
81 static TCGv_i32 cpu_R[16];
82 static TCGv_i32 cpu_FR[16];
83 static TCGv_i32 cpu_MR[4];
84 static TCGv_i32 cpu_BR[16];
85 static TCGv_i32 cpu_BR4[4];
86 static TCGv_i32 cpu_BR8[2];
87 static TCGv_i32 cpu_SR[256];
88 static TCGv_i32 cpu_UR[256];
89 static TCGv_i32 cpu_windowbase_next;
90
91 static GHashTable *xtensa_regfile_table;
92
93 #include "exec/gen-icount.h"
94
95 static char *sr_name[256];
96 static char *ur_name[256];
97
98 void xtensa_collect_sr_names(const XtensaConfig *config)
99 {
100 xtensa_isa isa = config->isa;
101 int n = xtensa_isa_num_sysregs(isa);
102 int i;
103
104 for (i = 0; i < n; ++i) {
105 int sr = xtensa_sysreg_number(isa, i);
106
107 if (sr >= 0 && sr < 256) {
108 const char *name = xtensa_sysreg_name(isa, i);
109 char **pname =
110 (xtensa_sysreg_is_user(isa, i) ? ur_name : sr_name) + sr;
111
112 if (*pname) {
113 if (strstr(*pname, name) == NULL) {
114 char *new_name =
115 malloc(strlen(*pname) + strlen(name) + 2);
116
117 strcpy(new_name, *pname);
118 strcat(new_name, "/");
119 strcat(new_name, name);
120 free(*pname);
121 *pname = new_name;
122 }
123 } else {
124 *pname = strdup(name);
125 }
126 }
127 }
128 }
129
130 void xtensa_translate_init(void)
131 {
132 static const char * const regnames[] = {
133 "ar0", "ar1", "ar2", "ar3",
134 "ar4", "ar5", "ar6", "ar7",
135 "ar8", "ar9", "ar10", "ar11",
136 "ar12", "ar13", "ar14", "ar15",
137 };
138 static const char * const fregnames[] = {
139 "f0", "f1", "f2", "f3",
140 "f4", "f5", "f6", "f7",
141 "f8", "f9", "f10", "f11",
142 "f12", "f13", "f14", "f15",
143 };
144 static const char * const mregnames[] = {
145 "m0", "m1", "m2", "m3",
146 };
147 static const char * const bregnames[] = {
148 "b0", "b1", "b2", "b3",
149 "b4", "b5", "b6", "b7",
150 "b8", "b9", "b10", "b11",
151 "b12", "b13", "b14", "b15",
152 };
153 int i;
154
155 cpu_pc = tcg_global_mem_new_i32(cpu_env,
156 offsetof(CPUXtensaState, pc), "pc");
157
158 for (i = 0; i < 16; i++) {
159 cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
160 offsetof(CPUXtensaState, regs[i]),
161 regnames[i]);
162 }
163
164 for (i = 0; i < 16; i++) {
165 cpu_FR[i] = tcg_global_mem_new_i32(cpu_env,
166 offsetof(CPUXtensaState,
167 fregs[i].f32[FP_F32_LOW]),
168 fregnames[i]);
169 }
170
171 for (i = 0; i < 4; i++) {
172 cpu_MR[i] = tcg_global_mem_new_i32(cpu_env,
173 offsetof(CPUXtensaState,
174 sregs[MR + i]),
175 mregnames[i]);
176 }
177
178 for (i = 0; i < 16; i++) {
179 cpu_BR[i] = tcg_global_mem_new_i32(cpu_env,
180 offsetof(CPUXtensaState,
181 sregs[BR]),
182 bregnames[i]);
183 if (i % 4 == 0) {
184 cpu_BR4[i / 4] = tcg_global_mem_new_i32(cpu_env,
185 offsetof(CPUXtensaState,
186 sregs[BR]),
187 bregnames[i]);
188 }
189 if (i % 8 == 0) {
190 cpu_BR8[i / 8] = tcg_global_mem_new_i32(cpu_env,
191 offsetof(CPUXtensaState,
192 sregs[BR]),
193 bregnames[i]);
194 }
195 }
196
197 for (i = 0; i < 256; ++i) {
198 if (sr_name[i]) {
199 cpu_SR[i] = tcg_global_mem_new_i32(cpu_env,
200 offsetof(CPUXtensaState,
201 sregs[i]),
202 sr_name[i]);
203 }
204 }
205
206 for (i = 0; i < 256; ++i) {
207 if (ur_name[i]) {
208 cpu_UR[i] = tcg_global_mem_new_i32(cpu_env,
209 offsetof(CPUXtensaState,
210 uregs[i]),
211 ur_name[i]);
212 }
213 }
214
215 cpu_windowbase_next =
216 tcg_global_mem_new_i32(cpu_env,
217 offsetof(CPUXtensaState, windowbase_next),
218 "windowbase_next");
219 }
220
221 void **xtensa_get_regfile_by_name(const char *name)
222 {
223 if (xtensa_regfile_table == NULL) {
224 xtensa_regfile_table = g_hash_table_new(g_str_hash, g_str_equal);
225 g_hash_table_insert(xtensa_regfile_table,
226 (void *)"AR", (void *)cpu_R);
227 g_hash_table_insert(xtensa_regfile_table,
228 (void *)"MR", (void *)cpu_MR);
229 g_hash_table_insert(xtensa_regfile_table,
230 (void *)"FR", (void *)cpu_FR);
231 g_hash_table_insert(xtensa_regfile_table,
232 (void *)"BR", (void *)cpu_BR);
233 g_hash_table_insert(xtensa_regfile_table,
234 (void *)"BR4", (void *)cpu_BR4);
235 g_hash_table_insert(xtensa_regfile_table,
236 (void *)"BR8", (void *)cpu_BR8);
237 }
238 return (void **)g_hash_table_lookup(xtensa_regfile_table, (void *)name);
239 }
240
241 static inline bool option_enabled(DisasContext *dc, int opt)
242 {
243 return xtensa_option_enabled(dc->config, opt);
244 }
245
246 static void init_sar_tracker(DisasContext *dc)
247 {
248 dc->sar_5bit = false;
249 dc->sar_m32_5bit = false;
250 dc->sar_m32_allocated = false;
251 }
252
253 static void reset_sar_tracker(DisasContext *dc)
254 {
255 if (dc->sar_m32_allocated) {
256 tcg_temp_free(dc->sar_m32);
257 }
258 }
259
260 static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
261 {
262 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
263 if (dc->sar_m32_5bit) {
264 tcg_gen_discard_i32(dc->sar_m32);
265 }
266 dc->sar_5bit = true;
267 dc->sar_m32_5bit = false;
268 }
269
270 static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
271 {
272 TCGv_i32 tmp = tcg_const_i32(32);
273 if (!dc->sar_m32_allocated) {
274 dc->sar_m32 = tcg_temp_local_new_i32();
275 dc->sar_m32_allocated = true;
276 }
277 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
278 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
279 dc->sar_5bit = false;
280 dc->sar_m32_5bit = true;
281 tcg_temp_free(tmp);
282 }
283
284 static void gen_exception(DisasContext *dc, int excp)
285 {
286 TCGv_i32 tmp = tcg_const_i32(excp);
287 gen_helper_exception(cpu_env, tmp);
288 tcg_temp_free(tmp);
289 }
290
291 static void gen_exception_cause(DisasContext *dc, uint32_t cause)
292 {
293 TCGv_i32 tpc = tcg_const_i32(dc->pc);
294 TCGv_i32 tcause = tcg_const_i32(cause);
295 gen_helper_exception_cause(cpu_env, tpc, tcause);
296 tcg_temp_free(tpc);
297 tcg_temp_free(tcause);
298 if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
299 cause == SYSCALL_CAUSE) {
300 dc->base.is_jmp = DISAS_NORETURN;
301 }
302 }
303
304 static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
305 TCGv_i32 vaddr)
306 {
307 TCGv_i32 tpc = tcg_const_i32(dc->pc);
308 TCGv_i32 tcause = tcg_const_i32(cause);
309 gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr);
310 tcg_temp_free(tpc);
311 tcg_temp_free(tcause);
312 }
313
314 static void gen_debug_exception(DisasContext *dc, uint32_t cause)
315 {
316 TCGv_i32 tpc = tcg_const_i32(dc->pc);
317 TCGv_i32 tcause = tcg_const_i32(cause);
318 gen_helper_debug_exception(cpu_env, tpc, tcause);
319 tcg_temp_free(tpc);
320 tcg_temp_free(tcause);
321 if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
322 dc->base.is_jmp = DISAS_NORETURN;
323 }
324 }
325
326 static bool gen_check_privilege(DisasContext *dc)
327 {
328 #ifndef CONFIG_USER_ONLY
329 if (!dc->cring) {
330 return true;
331 }
332 #endif
333 gen_exception_cause(dc, PRIVILEGED_CAUSE);
334 dc->base.is_jmp = DISAS_NORETURN;
335 return false;
336 }
337
338 static bool gen_check_cpenable(DisasContext *dc, uint32_t cp_mask)
339 {
340 cp_mask &= ~dc->cpenable;
341
342 if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) && cp_mask) {
343 gen_exception_cause(dc, COPROCESSOR0_DISABLED + ctz32(cp_mask));
344 dc->base.is_jmp = DISAS_NORETURN;
345 return false;
346 }
347 return true;
348 }
349
350 static int gen_postprocess(DisasContext *dc, int slot);
351
352 static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
353 {
354 tcg_gen_mov_i32(cpu_pc, dest);
355 if (dc->icount) {
356 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
357 }
358 if (dc->base.singlestep_enabled) {
359 gen_exception(dc, EXCP_DEBUG);
360 } else {
361 if (dc->op_flags & XTENSA_OP_POSTPROCESS) {
362 slot = gen_postprocess(dc, slot);
363 }
364 if (slot >= 0) {
365 tcg_gen_goto_tb(slot);
366 tcg_gen_exit_tb(dc->base.tb, slot);
367 } else {
368 tcg_gen_exit_tb(NULL, 0);
369 }
370 }
371 dc->base.is_jmp = DISAS_NORETURN;
372 }
373
374 static void gen_jump(DisasContext *dc, TCGv dest)
375 {
376 gen_jump_slot(dc, dest, -1);
377 }
378
379 static int adjust_jump_slot(DisasContext *dc, uint32_t dest, int slot)
380 {
381 if (((dc->base.pc_first ^ dest) & TARGET_PAGE_MASK) != 0) {
382 return -1;
383 } else {
384 return slot;
385 }
386 }
387
388 static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
389 {
390 TCGv_i32 tmp = tcg_const_i32(dest);
391 gen_jump_slot(dc, tmp, adjust_jump_slot(dc, dest, slot));
392 tcg_temp_free(tmp);
393 }
394
395 static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
396 int slot)
397 {
398 TCGv_i32 tcallinc = tcg_const_i32(callinc);
399
400 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
401 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
402 tcg_temp_free(tcallinc);
403 tcg_gen_movi_i32(cpu_R[callinc << 2],
404 (callinc << 30) | (dc->base.pc_next & 0x3fffffff));
405 gen_jump_slot(dc, dest, slot);
406 }
407
408 static bool gen_check_loop_end(DisasContext *dc, int slot)
409 {
410 if (dc->base.pc_next == dc->lend) {
411 TCGLabel *label = gen_new_label();
412
413 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
414 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
415 if (dc->lbeg_off) {
416 gen_jumpi(dc, dc->base.pc_next - dc->lbeg_off, slot);
417 } else {
418 gen_jump(dc, cpu_SR[LBEG]);
419 }
420 gen_set_label(label);
421 gen_jumpi(dc, dc->base.pc_next, -1);
422 return true;
423 }
424 return false;
425 }
426
427 static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
428 {
429 if (!gen_check_loop_end(dc, slot)) {
430 gen_jumpi(dc, dc->base.pc_next, slot);
431 }
432 }
433
434 static void gen_brcond(DisasContext *dc, TCGCond cond,
435 TCGv_i32 t0, TCGv_i32 t1, uint32_t addr)
436 {
437 TCGLabel *label = gen_new_label();
438
439 tcg_gen_brcond_i32(cond, t0, t1, label);
440 gen_jumpi_check_loop_end(dc, 0);
441 gen_set_label(label);
442 gen_jumpi(dc, addr, 1);
443 }
444
445 static void gen_brcondi(DisasContext *dc, TCGCond cond,
446 TCGv_i32 t0, uint32_t t1, uint32_t addr)
447 {
448 TCGv_i32 tmp = tcg_const_i32(t1);
449 gen_brcond(dc, cond, t0, tmp, addr);
450 tcg_temp_free(tmp);
451 }
452
453 static bool test_ill_sr(DisasContext *dc, const OpcodeArg arg[],
454 const uint32_t par[])
455 {
456 return !xtensa_option_enabled(dc->config, par[1]);
457 }
458
459 static bool test_ill_ccompare(DisasContext *dc, const OpcodeArg arg[],
460 const uint32_t par[])
461 {
462 unsigned n = par[0] - CCOMPARE;
463
464 return test_ill_sr(dc, arg, par) || n >= dc->config->nccompare;
465 }
466
467 static bool test_ill_dbreak(DisasContext *dc, const OpcodeArg arg[],
468 const uint32_t par[])
469 {
470 unsigned n = MAX_NDBREAK;
471
472 if (par[0] >= DBREAKA && par[0] < DBREAKA + MAX_NDBREAK) {
473 n = par[0] - DBREAKA;
474 }
475 if (par[0] >= DBREAKC && par[0] < DBREAKC + MAX_NDBREAK) {
476 n = par[0] - DBREAKC;
477 }
478 return test_ill_sr(dc, arg, par) || n >= dc->config->ndbreak;
479 }
480
481 static bool test_ill_ibreak(DisasContext *dc, const OpcodeArg arg[],
482 const uint32_t par[])
483 {
484 unsigned n = par[0] - IBREAKA;
485
486 return test_ill_sr(dc, arg, par) || n >= dc->config->nibreak;
487 }
488
489 static bool test_ill_hpi(DisasContext *dc, const OpcodeArg arg[],
490 const uint32_t par[])
491 {
492 unsigned n = MAX_NLEVEL + 1;
493
494 if (par[0] >= EXCSAVE1 && par[0] < EXCSAVE1 + MAX_NLEVEL) {
495 n = par[0] - EXCSAVE1 + 1;
496 }
497 if (par[0] >= EPC1 && par[0] < EPC1 + MAX_NLEVEL) {
498 n = par[0] - EPC1 + 1;
499 }
500 if (par[0] >= EPS2 && par[0] < EPS2 + MAX_NLEVEL - 1) {
501 n = par[0] - EPS2 + 2;
502 }
503 return test_ill_sr(dc, arg, par) || n > dc->config->nlevel;
504 }
505
506 static void gen_load_store_alignment(DisasContext *dc, int shift,
507 TCGv_i32 addr, bool no_hw_alignment)
508 {
509 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
510 tcg_gen_andi_i32(addr, addr, ~0 << shift);
511 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
512 no_hw_alignment) {
513 TCGLabel *label = gen_new_label();
514 TCGv_i32 tmp = tcg_temp_new_i32();
515 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
516 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
517 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
518 gen_set_label(label);
519 tcg_temp_free(tmp);
520 }
521 }
522
523 #ifndef CONFIG_USER_ONLY
524 static void gen_waiti(DisasContext *dc, uint32_t imm4)
525 {
526 TCGv_i32 pc = tcg_const_i32(dc->base.pc_next);
527 TCGv_i32 intlevel = tcg_const_i32(imm4);
528
529 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
530 gen_io_start();
531 }
532 gen_helper_waiti(cpu_env, pc, intlevel);
533 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
534 gen_io_end();
535 }
536 tcg_temp_free(pc);
537 tcg_temp_free(intlevel);
538 }
539 #endif
540
541 static bool gen_window_check(DisasContext *dc, uint32_t mask)
542 {
543 unsigned r = 31 - clz32(mask);
544
545 if (r / 4 > dc->window) {
546 TCGv_i32 pc = tcg_const_i32(dc->pc);
547 TCGv_i32 w = tcg_const_i32(r / 4);
548
549 gen_helper_window_check(cpu_env, pc, w);
550 dc->base.is_jmp = DISAS_NORETURN;
551 return false;
552 }
553 return true;
554 }
555
556 static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
557 {
558 TCGv_i32 m = tcg_temp_new_i32();
559
560 if (hi) {
561 (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
562 } else {
563 (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
564 }
565 return m;
566 }
567
568 static void gen_zero_check(DisasContext *dc, const OpcodeArg arg[])
569 {
570 TCGLabel *label = gen_new_label();
571
572 tcg_gen_brcondi_i32(TCG_COND_NE, arg[2].in, 0, label);
573 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
574 gen_set_label(label);
575 }
576
577 static inline unsigned xtensa_op0_insn_len(DisasContext *dc, uint8_t op0)
578 {
579 return xtensa_isa_length_from_chars(dc->config->isa, &op0);
580 }
581
582 static int gen_postprocess(DisasContext *dc, int slot)
583 {
584 uint32_t op_flags = dc->op_flags;
585
586 #ifndef CONFIG_USER_ONLY
587 if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) {
588 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
589 gen_io_start();
590 }
591 gen_helper_check_interrupts(cpu_env);
592 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
593 gen_io_end();
594 }
595 }
596 #endif
597 if (op_flags & XTENSA_OP_SYNC_REGISTER_WINDOW) {
598 gen_helper_sync_windowbase(cpu_env);
599 }
600 if (op_flags & XTENSA_OP_EXIT_TB_M1) {
601 slot = -1;
602 }
603 return slot;
604 }
605
606 struct opcode_arg_copy {
607 uint32_t resource;
608 void *temp;
609 OpcodeArg *arg;
610 };
611
612 struct opcode_arg_info {
613 uint32_t resource;
614 int index;
615 };
616
617 struct slot_prop {
618 XtensaOpcodeOps *ops;
619 OpcodeArg arg[MAX_OPCODE_ARGS];
620 struct opcode_arg_info in[MAX_OPCODE_ARGS];
621 struct opcode_arg_info out[MAX_OPCODE_ARGS];
622 unsigned n_in;
623 unsigned n_out;
624 uint32_t op_flags;
625 };
626
627 enum resource_type {
628 RES_REGFILE,
629 RES_STATE,
630 RES_MAX,
631 };
632
633 static uint32_t encode_resource(enum resource_type r, unsigned g, unsigned n)
634 {
635 assert(r < RES_MAX && g < 256 && n < 65536);
636 return (r << 24) | (g << 16) | n;
637 }
638
639 static enum resource_type get_resource_type(uint32_t resource)
640 {
641 return resource >> 24;
642 }
643
644 /*
645 * a depends on b if b must be executed before a,
646 * because a's side effects will destroy b's inputs.
647 */
648 static bool op_depends_on(const struct slot_prop *a,
649 const struct slot_prop *b)
650 {
651 unsigned i = 0;
652 unsigned j = 0;
653
654 if (a->op_flags & XTENSA_OP_CONTROL_FLOW) {
655 return true;
656 }
657 if ((a->op_flags & XTENSA_OP_LOAD_STORE) <
658 (b->op_flags & XTENSA_OP_LOAD_STORE)) {
659 return true;
660 }
661 while (i < a->n_out && j < b->n_in) {
662 if (a->out[i].resource < b->in[j].resource) {
663 ++i;
664 } else if (a->out[i].resource > b->in[j].resource) {
665 ++j;
666 } else {
667 return true;
668 }
669 }
670 return false;
671 }
672
673 /*
674 * Try to break a dependency on b, append temporary register copy records
675 * to the end of copy and update n_copy in case of success.
676 * This is not always possible: e.g. control flow must always be the last,
677 * load/store must be first and state dependencies are not supported yet.
678 */
679 static bool break_dependency(struct slot_prop *a,
680 struct slot_prop *b,
681 struct opcode_arg_copy *copy,
682 unsigned *n_copy)
683 {
684 unsigned i = 0;
685 unsigned j = 0;
686 unsigned n = *n_copy;
687 bool rv = false;
688
689 if (a->op_flags & XTENSA_OP_CONTROL_FLOW) {
690 return false;
691 }
692 if ((a->op_flags & XTENSA_OP_LOAD_STORE) <
693 (b->op_flags & XTENSA_OP_LOAD_STORE)) {
694 return false;
695 }
696 while (i < a->n_out && j < b->n_in) {
697 if (a->out[i].resource < b->in[j].resource) {
698 ++i;
699 } else if (a->out[i].resource > b->in[j].resource) {
700 ++j;
701 } else {
702 int index = b->in[j].index;
703
704 if (get_resource_type(a->out[i].resource) != RES_REGFILE ||
705 index < 0) {
706 return false;
707 }
708 copy[n].resource = b->in[j].resource;
709 copy[n].arg = b->arg + index;
710 ++n;
711 ++j;
712 rv = true;
713 }
714 }
715 *n_copy = n;
716 return rv;
717 }
718
719 /*
720 * Calculate evaluation order for slot opcodes.
721 * Build opcode order graph and output its nodes in topological sort order.
722 * An edge a -> b in the graph means that opcode a must be followed by
723 * opcode b.
724 */
725 static bool tsort(struct slot_prop *slot,
726 struct slot_prop *sorted[],
727 unsigned n,
728 struct opcode_arg_copy *copy,
729 unsigned *n_copy)
730 {
731 struct tsnode {
732 unsigned n_in_edge;
733 unsigned n_out_edge;
734 unsigned out_edge[MAX_INSN_SLOTS];
735 } node[MAX_INSN_SLOTS];
736
737 unsigned in[MAX_INSN_SLOTS];
738 unsigned i, j;
739 unsigned n_in = 0;
740 unsigned n_out = 0;
741 unsigned n_edge = 0;
742 unsigned in_idx = 0;
743 unsigned node_idx = 0;
744
745 for (i = 0; i < n; ++i) {
746 node[i].n_in_edge = 0;
747 node[i].n_out_edge = 0;
748 }
749
750 for (i = 0; i < n; ++i) {
751 unsigned n_out_edge = 0;
752
753 for (j = 0; j < n; ++j) {
754 if (i != j && op_depends_on(slot + j, slot + i)) {
755 node[i].out_edge[n_out_edge] = j;
756 ++node[j].n_in_edge;
757 ++n_out_edge;
758 ++n_edge;
759 }
760 }
761 node[i].n_out_edge = n_out_edge;
762 }
763
764 for (i = 0; i < n; ++i) {
765 if (!node[i].n_in_edge) {
766 in[n_in] = i;
767 ++n_in;
768 }
769 }
770
771 again:
772 for (; in_idx < n_in; ++in_idx) {
773 i = in[in_idx];
774 sorted[n_out] = slot + i;
775 ++n_out;
776 for (j = 0; j < node[i].n_out_edge; ++j) {
777 --n_edge;
778 if (--node[node[i].out_edge[j]].n_in_edge == 0) {
779 in[n_in] = node[i].out_edge[j];
780 ++n_in;
781 }
782 }
783 }
784 if (n_edge) {
785 for (; node_idx < n; ++node_idx) {
786 struct tsnode *cnode = node + node_idx;
787
788 if (cnode->n_in_edge) {
789 for (j = 0; j < cnode->n_out_edge; ++j) {
790 unsigned k = cnode->out_edge[j];
791
792 if (break_dependency(slot + k, slot + node_idx,
793 copy, n_copy) &&
794 --node[k].n_in_edge == 0) {
795 in[n_in] = k;
796 ++n_in;
797 --n_edge;
798 cnode->out_edge[j] =
799 cnode->out_edge[cnode->n_out_edge - 1];
800 --cnode->n_out_edge;
801 goto again;
802 }
803 }
804 }
805 }
806 }
807 return n_edge == 0;
808 }
809
810 static void opcode_add_resource(struct slot_prop *op,
811 uint32_t resource, char direction,
812 int index)
813 {
814 switch (direction) {
815 case 'm':
816 case 'i':
817 assert(op->n_in < ARRAY_SIZE(op->in));
818 op->in[op->n_in].resource = resource;
819 op->in[op->n_in].index = index;
820 ++op->n_in;
821 /* fall through */
822 case 'o':
823 if (direction == 'm' || direction == 'o') {
824 assert(op->n_out < ARRAY_SIZE(op->out));
825 op->out[op->n_out].resource = resource;
826 op->out[op->n_out].index = index;
827 ++op->n_out;
828 }
829 break;
830 default:
831 g_assert_not_reached();
832 }
833 }
834
835 static int resource_compare(const void *a, const void *b)
836 {
837 const struct opcode_arg_info *pa = a;
838 const struct opcode_arg_info *pb = b;
839
840 return pa->resource < pb->resource ?
841 -1 : (pa->resource > pb->resource ? 1 : 0);
842 }
843
844 static int arg_copy_compare(const void *a, const void *b)
845 {
846 const struct opcode_arg_copy *pa = a;
847 const struct opcode_arg_copy *pb = b;
848
849 return pa->resource < pb->resource ?
850 -1 : (pa->resource > pb->resource ? 1 : 0);
851 }
852
853 static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
854 {
855 xtensa_isa isa = dc->config->isa;
856 unsigned char b[MAX_INSN_LENGTH] = {cpu_ldub_code(env, dc->pc)};
857 unsigned len = xtensa_op0_insn_len(dc, b[0]);
858 xtensa_format fmt;
859 int slot, slots;
860 unsigned i;
861 uint32_t op_flags = 0;
862 struct slot_prop slot_prop[MAX_INSN_SLOTS];
863 struct slot_prop *ordered[MAX_INSN_SLOTS];
864 struct opcode_arg_copy arg_copy[MAX_INSN_SLOTS * MAX_OPCODE_ARGS];
865 unsigned n_arg_copy = 0;
866 uint32_t debug_cause = 0;
867 uint32_t windowed_register = 0;
868 uint32_t coprocessor = 0;
869
870 if (len == XTENSA_UNDEFINED) {
871 qemu_log_mask(LOG_GUEST_ERROR,
872 "unknown instruction length (pc = %08x)\n",
873 dc->pc);
874 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
875 return;
876 }
877
878 dc->base.pc_next = dc->pc + len;
879 for (i = 1; i < len; ++i) {
880 b[i] = cpu_ldub_code(env, dc->pc + i);
881 }
882 xtensa_insnbuf_from_chars(isa, dc->insnbuf, b, len);
883 fmt = xtensa_format_decode(isa, dc->insnbuf);
884 if (fmt == XTENSA_UNDEFINED) {
885 qemu_log_mask(LOG_GUEST_ERROR,
886 "unrecognized instruction format (pc = %08x)\n",
887 dc->pc);
888 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
889 return;
890 }
891 slots = xtensa_format_num_slots(isa, fmt);
892 for (slot = 0; slot < slots; ++slot) {
893 xtensa_opcode opc;
894 int opnd, vopnd, opnds;
895 OpcodeArg *arg = slot_prop[slot].arg;
896 XtensaOpcodeOps *ops;
897
898 xtensa_format_get_slot(isa, fmt, slot, dc->insnbuf, dc->slotbuf);
899 opc = xtensa_opcode_decode(isa, fmt, slot, dc->slotbuf);
900 if (opc == XTENSA_UNDEFINED) {
901 qemu_log_mask(LOG_GUEST_ERROR,
902 "unrecognized opcode in slot %d (pc = %08x)\n",
903 slot, dc->pc);
904 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
905 return;
906 }
907 opnds = xtensa_opcode_num_operands(isa, opc);
908
909 for (opnd = vopnd = 0; opnd < opnds; ++opnd) {
910 void **register_file = NULL;
911
912 if (xtensa_operand_is_register(isa, opc, opnd)) {
913 xtensa_regfile rf = xtensa_operand_regfile(isa, opc, opnd);
914
915 register_file = dc->config->regfile[rf];
916
917 if (rf == dc->config->a_regfile) {
918 uint32_t v;
919
920 xtensa_operand_get_field(isa, opc, opnd, fmt, slot,
921 dc->slotbuf, &v);
922 xtensa_operand_decode(isa, opc, opnd, &v);
923 windowed_register |= 1u << v;
924 }
925 }
926 if (xtensa_operand_is_visible(isa, opc, opnd)) {
927 uint32_t v;
928
929 xtensa_operand_get_field(isa, opc, opnd, fmt, slot,
930 dc->slotbuf, &v);
931 xtensa_operand_decode(isa, opc, opnd, &v);
932 arg[vopnd].raw_imm = v;
933 if (xtensa_operand_is_PCrelative(isa, opc, opnd)) {
934 xtensa_operand_undo_reloc(isa, opc, opnd, &v, dc->pc);
935 }
936 arg[vopnd].imm = v;
937 if (register_file) {
938 arg[vopnd].in = register_file[v];
939 arg[vopnd].out = register_file[v];
940 }
941 ++vopnd;
942 }
943 }
944 ops = dc->config->opcode_ops[opc];
945 slot_prop[slot].ops = ops;
946
947 if (ops) {
948 op_flags |= ops->op_flags;
949 } else {
950 qemu_log_mask(LOG_UNIMP,
951 "unimplemented opcode '%s' in slot %d (pc = %08x)\n",
952 xtensa_opcode_name(isa, opc), slot, dc->pc);
953 op_flags |= XTENSA_OP_ILL;
954 }
955 if ((op_flags & XTENSA_OP_ILL) ||
956 (ops && ops->test_ill && ops->test_ill(dc, arg, ops->par))) {
957 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
958 return;
959 }
960 if (ops->op_flags & XTENSA_OP_DEBUG_BREAK) {
961 debug_cause |= ops->par[0];
962 }
963 if (ops->test_overflow) {
964 windowed_register |= ops->test_overflow(dc, arg, ops->par);
965 }
966 coprocessor |= ops->coprocessor;
967
968 if (slots > 1) {
969 slot_prop[slot].n_in = 0;
970 slot_prop[slot].n_out = 0;
971 slot_prop[slot].op_flags = ops->op_flags & XTENSA_OP_LOAD_STORE;
972
973 opnds = xtensa_opcode_num_operands(isa, opc);
974
975 for (opnd = vopnd = 0; opnd < opnds; ++opnd) {
976 bool visible = xtensa_operand_is_visible(isa, opc, opnd);
977
978 if (xtensa_operand_is_register(isa, opc, opnd)) {
979 xtensa_regfile rf = xtensa_operand_regfile(isa, opc, opnd);
980 uint32_t v = 0;
981
982 xtensa_operand_get_field(isa, opc, opnd, fmt, slot,
983 dc->slotbuf, &v);
984 xtensa_operand_decode(isa, opc, opnd, &v);
985 opcode_add_resource(slot_prop + slot,
986 encode_resource(RES_REGFILE, rf, v),
987 xtensa_operand_inout(isa, opc, opnd),
988 visible ? vopnd : -1);
989 }
990 if (visible) {
991 ++vopnd;
992 }
993 }
994
995 opnds = xtensa_opcode_num_stateOperands(isa, opc);
996
997 for (opnd = 0; opnd < opnds; ++opnd) {
998 xtensa_state state = xtensa_stateOperand_state(isa, opc, opnd);
999
1000 opcode_add_resource(slot_prop + slot,
1001 encode_resource(RES_STATE, 0, state),
1002 xtensa_stateOperand_inout(isa, opc, opnd),
1003 -1);
1004 }
1005 if (xtensa_opcode_is_branch(isa, opc) ||
1006 xtensa_opcode_is_jump(isa, opc) ||
1007 xtensa_opcode_is_loop(isa, opc) ||
1008 xtensa_opcode_is_call(isa, opc)) {
1009 slot_prop[slot].op_flags |= XTENSA_OP_CONTROL_FLOW;
1010 }
1011
1012 qsort(slot_prop[slot].in, slot_prop[slot].n_in,
1013 sizeof(slot_prop[slot].in[0]), resource_compare);
1014 qsort(slot_prop[slot].out, slot_prop[slot].n_out,
1015 sizeof(slot_prop[slot].out[0]), resource_compare);
1016 }
1017 }
1018
1019 if (slots > 1) {
1020 if (!tsort(slot_prop, ordered, slots, arg_copy, &n_arg_copy)) {
1021 qemu_log_mask(LOG_UNIMP,
1022 "Circular resource dependencies (pc = %08x)\n",
1023 dc->pc);
1024 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1025 return;
1026 }
1027 } else {
1028 ordered[0] = slot_prop + 0;
1029 }
1030
1031 if ((op_flags & XTENSA_OP_PRIVILEGED) &&
1032 !gen_check_privilege(dc)) {
1033 return;
1034 }
1035
1036 if (op_flags & XTENSA_OP_SYSCALL) {
1037 gen_exception_cause(dc, SYSCALL_CAUSE);
1038 return;
1039 }
1040
1041 if ((op_flags & XTENSA_OP_DEBUG_BREAK) && dc->debug) {
1042 gen_debug_exception(dc, debug_cause);
1043 return;
1044 }
1045
1046 if (windowed_register && !gen_window_check(dc, windowed_register)) {
1047 return;
1048 }
1049
1050 if (op_flags & XTENSA_OP_UNDERFLOW) {
1051 TCGv_i32 tmp = tcg_const_i32(dc->pc);
1052
1053 gen_helper_test_underflow_retw(cpu_env, tmp);
1054 tcg_temp_free(tmp);
1055 }
1056
1057 if (op_flags & XTENSA_OP_ALLOCA) {
1058 TCGv_i32 tmp = tcg_const_i32(dc->pc);
1059
1060 gen_helper_movsp(cpu_env, tmp);
1061 tcg_temp_free(tmp);
1062 }
1063
1064 if (coprocessor && !gen_check_cpenable(dc, coprocessor)) {
1065 return;
1066 }
1067
1068 if (n_arg_copy) {
1069 uint32_t resource;
1070 void *temp;
1071 unsigned j;
1072
1073 qsort(arg_copy, n_arg_copy, sizeof(*arg_copy), arg_copy_compare);
1074 for (i = j = 0; i < n_arg_copy; ++i) {
1075 if (i == 0 || arg_copy[i].resource != resource) {
1076 resource = arg_copy[i].resource;
1077 temp = tcg_temp_local_new();
1078 tcg_gen_mov_i32(temp, arg_copy[i].arg->in);
1079 arg_copy[i].temp = temp;
1080
1081 if (i != j) {
1082 arg_copy[j] = arg_copy[i];
1083 }
1084 ++j;
1085 }
1086 arg_copy[i].arg->in = temp;
1087 }
1088 n_arg_copy = j;
1089 }
1090
1091 if (op_flags & XTENSA_OP_DIVIDE_BY_ZERO) {
1092 for (slot = 0; slot < slots; ++slot) {
1093 if (slot_prop[slot].ops->op_flags & XTENSA_OP_DIVIDE_BY_ZERO) {
1094 gen_zero_check(dc, slot_prop[slot].arg);
1095 }
1096 }
1097 }
1098
1099 dc->op_flags = op_flags;
1100
1101 for (slot = 0; slot < slots; ++slot) {
1102 struct slot_prop *pslot = ordered[slot];
1103 XtensaOpcodeOps *ops = pslot->ops;
1104
1105 ops->translate(dc, pslot->arg, ops->par);
1106 }
1107
1108 for (i = 0; i < n_arg_copy; ++i) {
1109 tcg_temp_free(arg_copy[i].temp);
1110 }
1111
1112 if (dc->base.is_jmp == DISAS_NEXT) {
1113 gen_postprocess(dc, 0);
1114 dc->op_flags = 0;
1115 if (op_flags & XTENSA_OP_EXIT_TB_M1) {
1116 /* Change in mmu index, memory mapping or tb->flags; exit tb */
1117 gen_jumpi_check_loop_end(dc, -1);
1118 } else if (op_flags & XTENSA_OP_EXIT_TB_0) {
1119 gen_jumpi_check_loop_end(dc, 0);
1120 } else {
1121 gen_check_loop_end(dc, 0);
1122 }
1123 }
1124 dc->pc = dc->base.pc_next;
1125 }
1126
1127 static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc)
1128 {
1129 uint8_t b0 = cpu_ldub_code(env, dc->pc);
1130 return xtensa_op0_insn_len(dc, b0);
1131 }
1132
1133 static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
1134 {
1135 unsigned i;
1136
1137 for (i = 0; i < dc->config->nibreak; ++i) {
1138 if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
1139 env->sregs[IBREAKA + i] == dc->pc) {
1140 gen_debug_exception(dc, DEBUGCAUSE_IB);
1141 break;
1142 }
1143 }
1144 }
1145
1146 static void xtensa_tr_init_disas_context(DisasContextBase *dcbase,
1147 CPUState *cpu)
1148 {
1149 DisasContext *dc = container_of(dcbase, DisasContext, base);
1150 CPUXtensaState *env = cpu->env_ptr;
1151 uint32_t tb_flags = dc->base.tb->flags;
1152
1153 dc->config = env->config;
1154 dc->pc = dc->base.pc_first;
1155 dc->ring = tb_flags & XTENSA_TBFLAG_RING_MASK;
1156 dc->cring = (tb_flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring;
1157 dc->lbeg_off = (dc->base.tb->cs_base & XTENSA_CSBASE_LBEG_OFF_MASK) >>
1158 XTENSA_CSBASE_LBEG_OFF_SHIFT;
1159 dc->lend = (dc->base.tb->cs_base & XTENSA_CSBASE_LEND_MASK) +
1160 (dc->base.pc_first & TARGET_PAGE_MASK);
1161 dc->debug = tb_flags & XTENSA_TBFLAG_DEBUG;
1162 dc->icount = tb_flags & XTENSA_TBFLAG_ICOUNT;
1163 dc->cpenable = (tb_flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
1164 XTENSA_TBFLAG_CPENABLE_SHIFT;
1165 dc->window = ((tb_flags & XTENSA_TBFLAG_WINDOW_MASK) >>
1166 XTENSA_TBFLAG_WINDOW_SHIFT);
1167 dc->cwoe = tb_flags & XTENSA_TBFLAG_CWOE;
1168 dc->callinc = ((tb_flags & XTENSA_TBFLAG_CALLINC_MASK) >>
1169 XTENSA_TBFLAG_CALLINC_SHIFT);
1170
1171 if (dc->config->isa) {
1172 dc->insnbuf = xtensa_insnbuf_alloc(dc->config->isa);
1173 dc->slotbuf = xtensa_insnbuf_alloc(dc->config->isa);
1174 }
1175 init_sar_tracker(dc);
1176 }
1177
1178 static void xtensa_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
1179 {
1180 DisasContext *dc = container_of(dcbase, DisasContext, base);
1181
1182 if (dc->icount) {
1183 dc->next_icount = tcg_temp_local_new_i32();
1184 }
1185 }
1186
1187 static void xtensa_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
1188 {
1189 tcg_gen_insn_start(dcbase->pc_next);
1190 }
1191
1192 static bool xtensa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
1193 const CPUBreakpoint *bp)
1194 {
1195 DisasContext *dc = container_of(dcbase, DisasContext, base);
1196
1197 tcg_gen_movi_i32(cpu_pc, dc->base.pc_next);
1198 gen_exception(dc, EXCP_DEBUG);
1199 dc->base.is_jmp = DISAS_NORETURN;
1200 /* The address covered by the breakpoint must be included in
1201 [tb->pc, tb->pc + tb->size) in order to for it to be
1202 properly cleared -- thus we increment the PC here so that
1203 the logic setting tb->size below does the right thing. */
1204 dc->base.pc_next += 2;
1205 return true;
1206 }
1207
1208 static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
1209 {
1210 DisasContext *dc = container_of(dcbase, DisasContext, base);
1211 CPUXtensaState *env = cpu->env_ptr;
1212 target_ulong page_start;
1213
1214 /* These two conditions only apply to the first insn in the TB,
1215 but this is the first TranslateOps hook that allows exiting. */
1216 if ((tb_cflags(dc->base.tb) & CF_USE_ICOUNT)
1217 && (dc->base.tb->flags & XTENSA_TBFLAG_YIELD)) {
1218 gen_exception(dc, EXCP_YIELD);
1219 dc->base.is_jmp = DISAS_NORETURN;
1220 return;
1221 }
1222 if (dc->base.tb->flags & XTENSA_TBFLAG_EXCEPTION) {
1223 gen_exception(dc, EXCP_DEBUG);
1224 dc->base.is_jmp = DISAS_NORETURN;
1225 return;
1226 }
1227
1228 if (dc->icount) {
1229 TCGLabel *label = gen_new_label();
1230
1231 tcg_gen_addi_i32(dc->next_icount, cpu_SR[ICOUNT], 1);
1232 tcg_gen_brcondi_i32(TCG_COND_NE, dc->next_icount, 0, label);
1233 tcg_gen_mov_i32(dc->next_icount, cpu_SR[ICOUNT]);
1234 if (dc->debug) {
1235 gen_debug_exception(dc, DEBUGCAUSE_IC);
1236 }
1237 gen_set_label(label);
1238 }
1239
1240 if (dc->debug) {
1241 gen_ibreak_check(env, dc);
1242 }
1243
1244 disas_xtensa_insn(env, dc);
1245
1246 if (dc->icount) {
1247 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
1248 }
1249
1250 /* End the TB if the next insn will cross into the next page. */
1251 page_start = dc->base.pc_first & TARGET_PAGE_MASK;
1252 if (dc->base.is_jmp == DISAS_NEXT &&
1253 (dc->pc - page_start >= TARGET_PAGE_SIZE ||
1254 dc->pc - page_start + xtensa_insn_len(env, dc) > TARGET_PAGE_SIZE)) {
1255 dc->base.is_jmp = DISAS_TOO_MANY;
1256 }
1257 }
1258
1259 static void xtensa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
1260 {
1261 DisasContext *dc = container_of(dcbase, DisasContext, base);
1262
1263 reset_sar_tracker(dc);
1264 if (dc->config->isa) {
1265 xtensa_insnbuf_free(dc->config->isa, dc->insnbuf);
1266 xtensa_insnbuf_free(dc->config->isa, dc->slotbuf);
1267 }
1268 if (dc->icount) {
1269 tcg_temp_free(dc->next_icount);
1270 }
1271
1272 switch (dc->base.is_jmp) {
1273 case DISAS_NORETURN:
1274 break;
1275 case DISAS_TOO_MANY:
1276 if (dc->base.singlestep_enabled) {
1277 tcg_gen_movi_i32(cpu_pc, dc->pc);
1278 gen_exception(dc, EXCP_DEBUG);
1279 } else {
1280 gen_jumpi(dc, dc->pc, 0);
1281 }
1282 break;
1283 default:
1284 g_assert_not_reached();
1285 }
1286 }
1287
1288 static void xtensa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
1289 {
1290 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
1291 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
1292 }
1293
1294 static const TranslatorOps xtensa_translator_ops = {
1295 .init_disas_context = xtensa_tr_init_disas_context,
1296 .tb_start = xtensa_tr_tb_start,
1297 .insn_start = xtensa_tr_insn_start,
1298 .breakpoint_check = xtensa_tr_breakpoint_check,
1299 .translate_insn = xtensa_tr_translate_insn,
1300 .tb_stop = xtensa_tr_tb_stop,
1301 .disas_log = xtensa_tr_disas_log,
1302 };
1303
1304 void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
1305 {
1306 DisasContext dc = {};
1307 translator_loop(&xtensa_translator_ops, &dc.base, cpu, tb, max_insns);
1308 }
1309
1310 void xtensa_cpu_dump_state(CPUState *cs, FILE *f, int flags)
1311 {
1312 XtensaCPU *cpu = XTENSA_CPU(cs);
1313 CPUXtensaState *env = &cpu->env;
1314 xtensa_isa isa = env->config->isa;
1315 int i, j;
1316
1317 qemu_fprintf(f, "PC=%08x\n\n", env->pc);
1318
1319 for (i = j = 0; i < xtensa_isa_num_sysregs(isa); ++i) {
1320 const uint32_t *reg =
1321 xtensa_sysreg_is_user(isa, i) ? env->uregs : env->sregs;
1322 int regno = xtensa_sysreg_number(isa, i);
1323
1324 if (regno >= 0) {
1325 qemu_fprintf(f, "%12s=%08x%c",
1326 xtensa_sysreg_name(isa, i),
1327 reg[regno],
1328 (j++ % 4) == 3 ? '\n' : ' ');
1329 }
1330 }
1331
1332 qemu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
1333
1334 for (i = 0; i < 16; ++i) {
1335 qemu_fprintf(f, " A%02d=%08x%c",
1336 i, env->regs[i], (i % 4) == 3 ? '\n' : ' ');
1337 }
1338
1339 xtensa_sync_phys_from_window(env);
1340 qemu_fprintf(f, "\n");
1341
1342 for (i = 0; i < env->config->nareg; ++i) {
1343 qemu_fprintf(f, "AR%02d=%08x ", i, env->phys_regs[i]);
1344 if (i % 4 == 3) {
1345 bool ws = (env->sregs[WINDOW_START] & (1 << (i / 4))) != 0;
1346 bool cw = env->sregs[WINDOW_BASE] == i / 4;
1347
1348 qemu_fprintf(f, "%c%c\n", ws ? '<' : ' ', cw ? '=' : ' ');
1349 }
1350 }
1351
1352 if ((flags & CPU_DUMP_FPU) &&
1353 xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
1354 qemu_fprintf(f, "\n");
1355
1356 for (i = 0; i < 16; ++i) {
1357 qemu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i,
1358 float32_val(env->fregs[i].f32[FP_F32_LOW]),
1359 *(float *)(env->fregs[i].f32 + FP_F32_LOW),
1360 (i % 2) == 1 ? '\n' : ' ');
1361 }
1362 }
1363 }
1364
1365 void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb,
1366 target_ulong *data)
1367 {
1368 env->pc = data[0];
1369 }
1370
1371 static void translate_abs(DisasContext *dc, const OpcodeArg arg[],
1372 const uint32_t par[])
1373 {
1374 TCGv_i32 zero = tcg_const_i32(0);
1375 TCGv_i32 neg = tcg_temp_new_i32();
1376
1377 tcg_gen_neg_i32(neg, arg[1].in);
1378 tcg_gen_movcond_i32(TCG_COND_GE, arg[0].out,
1379 arg[1].in, zero, arg[1].in, neg);
1380 tcg_temp_free(neg);
1381 tcg_temp_free(zero);
1382 }
1383
1384 static void translate_add(DisasContext *dc, const OpcodeArg arg[],
1385 const uint32_t par[])
1386 {
1387 tcg_gen_add_i32(arg[0].out, arg[1].in, arg[2].in);
1388 }
1389
1390 static void translate_addi(DisasContext *dc, const OpcodeArg arg[],
1391 const uint32_t par[])
1392 {
1393 tcg_gen_addi_i32(arg[0].out, arg[1].in, arg[2].imm);
1394 }
1395
1396 static void translate_addx(DisasContext *dc, const OpcodeArg arg[],
1397 const uint32_t par[])
1398 {
1399 TCGv_i32 tmp = tcg_temp_new_i32();
1400 tcg_gen_shli_i32(tmp, arg[1].in, par[0]);
1401 tcg_gen_add_i32(arg[0].out, tmp, arg[2].in);
1402 tcg_temp_free(tmp);
1403 }
1404
1405 static void translate_all(DisasContext *dc, const OpcodeArg arg[],
1406 const uint32_t par[])
1407 {
1408 uint32_t shift = par[1];
1409 TCGv_i32 mask = tcg_const_i32(((1 << shift) - 1) << arg[1].imm);
1410 TCGv_i32 tmp = tcg_temp_new_i32();
1411
1412 tcg_gen_and_i32(tmp, arg[1].in, mask);
1413 if (par[0]) {
1414 tcg_gen_addi_i32(tmp, tmp, 1 << arg[1].imm);
1415 } else {
1416 tcg_gen_add_i32(tmp, tmp, mask);
1417 }
1418 tcg_gen_shri_i32(tmp, tmp, arg[1].imm + shift);
1419 tcg_gen_deposit_i32(arg[0].out, arg[0].out,
1420 tmp, arg[0].imm, 1);
1421 tcg_temp_free(mask);
1422 tcg_temp_free(tmp);
1423 }
1424
1425 static void translate_and(DisasContext *dc, const OpcodeArg arg[],
1426 const uint32_t par[])
1427 {
1428 tcg_gen_and_i32(arg[0].out, arg[1].in, arg[2].in);
1429 }
1430
1431 static void translate_ball(DisasContext *dc, const OpcodeArg arg[],
1432 const uint32_t par[])
1433 {
1434 TCGv_i32 tmp = tcg_temp_new_i32();
1435 tcg_gen_and_i32(tmp, arg[0].in, arg[1].in);
1436 gen_brcond(dc, par[0], tmp, arg[1].in, arg[2].imm);
1437 tcg_temp_free(tmp);
1438 }
1439
1440 static void translate_bany(DisasContext *dc, const OpcodeArg arg[],
1441 const uint32_t par[])
1442 {
1443 TCGv_i32 tmp = tcg_temp_new_i32();
1444 tcg_gen_and_i32(tmp, arg[0].in, arg[1].in);
1445 gen_brcondi(dc, par[0], tmp, 0, arg[2].imm);
1446 tcg_temp_free(tmp);
1447 }
1448
1449 static void translate_b(DisasContext *dc, const OpcodeArg arg[],
1450 const uint32_t par[])
1451 {
1452 gen_brcond(dc, par[0], arg[0].in, arg[1].in, arg[2].imm);
1453 }
1454
1455 static void translate_bb(DisasContext *dc, const OpcodeArg arg[],
1456 const uint32_t par[])
1457 {
1458 #ifdef TARGET_WORDS_BIGENDIAN
1459 TCGv_i32 bit = tcg_const_i32(0x80000000u);
1460 #else
1461 TCGv_i32 bit = tcg_const_i32(0x00000001u);
1462 #endif
1463 TCGv_i32 tmp = tcg_temp_new_i32();
1464 tcg_gen_andi_i32(tmp, arg[1].in, 0x1f);
1465 #ifdef TARGET_WORDS_BIGENDIAN
1466 tcg_gen_shr_i32(bit, bit, tmp);
1467 #else
1468 tcg_gen_shl_i32(bit, bit, tmp);
1469 #endif
1470 tcg_gen_and_i32(tmp, arg[0].in, bit);
1471 gen_brcondi(dc, par[0], tmp, 0, arg[2].imm);
1472 tcg_temp_free(tmp);
1473 tcg_temp_free(bit);
1474 }
1475
1476 static void translate_bbi(DisasContext *dc, const OpcodeArg arg[],
1477 const uint32_t par[])
1478 {
1479 TCGv_i32 tmp = tcg_temp_new_i32();
1480 #ifdef TARGET_WORDS_BIGENDIAN
1481 tcg_gen_andi_i32(tmp, arg[0].in, 0x80000000u >> arg[1].imm);
1482 #else
1483 tcg_gen_andi_i32(tmp, arg[0].in, 0x00000001u << arg[1].imm);
1484 #endif
1485 gen_brcondi(dc, par[0], tmp, 0, arg[2].imm);
1486 tcg_temp_free(tmp);
1487 }
1488
1489 static void translate_bi(DisasContext *dc, const OpcodeArg arg[],
1490 const uint32_t par[])
1491 {
1492 gen_brcondi(dc, par[0], arg[0].in, arg[1].imm, arg[2].imm);
1493 }
1494
1495 static void translate_bz(DisasContext *dc, const OpcodeArg arg[],
1496 const uint32_t par[])
1497 {
1498 gen_brcondi(dc, par[0], arg[0].in, 0, arg[1].imm);
1499 }
1500
1501 enum {
1502 BOOLEAN_AND,
1503 BOOLEAN_ANDC,
1504 BOOLEAN_OR,
1505 BOOLEAN_ORC,
1506 BOOLEAN_XOR,
1507 };
1508
1509 static void translate_boolean(DisasContext *dc, const OpcodeArg arg[],
1510 const uint32_t par[])
1511 {
1512 static void (* const op[])(TCGv_i32, TCGv_i32, TCGv_i32) = {
1513 [BOOLEAN_AND] = tcg_gen_and_i32,
1514 [BOOLEAN_ANDC] = tcg_gen_andc_i32,
1515 [BOOLEAN_OR] = tcg_gen_or_i32,
1516 [BOOLEAN_ORC] = tcg_gen_orc_i32,
1517 [BOOLEAN_XOR] = tcg_gen_xor_i32,
1518 };
1519
1520 TCGv_i32 tmp1 = tcg_temp_new_i32();
1521 TCGv_i32 tmp2 = tcg_temp_new_i32();
1522
1523 tcg_gen_shri_i32(tmp1, arg[1].in, arg[1].imm);
1524 tcg_gen_shri_i32(tmp2, arg[2].in, arg[2].imm);
1525 op[par[0]](tmp1, tmp1, tmp2);
1526 tcg_gen_deposit_i32(arg[0].out, arg[0].out, tmp1, arg[0].imm, 1);
1527 tcg_temp_free(tmp1);
1528 tcg_temp_free(tmp2);
1529 }
1530
1531 static void translate_bp(DisasContext *dc, const OpcodeArg arg[],
1532 const uint32_t par[])
1533 {
1534 TCGv_i32 tmp = tcg_temp_new_i32();
1535
1536 tcg_gen_andi_i32(tmp, arg[0].in, 1 << arg[0].imm);
1537 gen_brcondi(dc, par[0], tmp, 0, arg[1].imm);
1538 tcg_temp_free(tmp);
1539 }
1540
1541 static void translate_call0(DisasContext *dc, const OpcodeArg arg[],
1542 const uint32_t par[])
1543 {
1544 tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next);
1545 gen_jumpi(dc, arg[0].imm, 0);
1546 }
1547
1548 static void translate_callw(DisasContext *dc, const OpcodeArg arg[],
1549 const uint32_t par[])
1550 {
1551 TCGv_i32 tmp = tcg_const_i32(arg[0].imm);
1552 gen_callw_slot(dc, par[0], tmp, adjust_jump_slot(dc, arg[0].imm, 0));
1553 tcg_temp_free(tmp);
1554 }
1555
1556 static void translate_callx0(DisasContext *dc, const OpcodeArg arg[],
1557 const uint32_t par[])
1558 {
1559 TCGv_i32 tmp = tcg_temp_new_i32();
1560 tcg_gen_mov_i32(tmp, arg[0].in);
1561 tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next);
1562 gen_jump(dc, tmp);
1563 tcg_temp_free(tmp);
1564 }
1565
1566 static void translate_callxw(DisasContext *dc, const OpcodeArg arg[],
1567 const uint32_t par[])
1568 {
1569 TCGv_i32 tmp = tcg_temp_new_i32();
1570
1571 tcg_gen_mov_i32(tmp, arg[0].in);
1572 gen_callw_slot(dc, par[0], tmp, -1);
1573 tcg_temp_free(tmp);
1574 }
1575
1576 static void translate_clamps(DisasContext *dc, const OpcodeArg arg[],
1577 const uint32_t par[])
1578 {
1579 TCGv_i32 tmp1 = tcg_const_i32(-1u << arg[2].imm);
1580 TCGv_i32 tmp2 = tcg_const_i32((1 << arg[2].imm) - 1);
1581
1582 tcg_gen_smax_i32(tmp1, tmp1, arg[1].in);
1583 tcg_gen_smin_i32(arg[0].out, tmp1, tmp2);
1584 tcg_temp_free(tmp1);
1585 tcg_temp_free(tmp2);
1586 }
1587
1588 static void translate_clrb_expstate(DisasContext *dc, const OpcodeArg arg[],
1589 const uint32_t par[])
1590 {
1591 /* TODO: GPIO32 may be a part of coprocessor */
1592 tcg_gen_andi_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], ~(1u << arg[0].imm));
1593 }
1594
1595 static void translate_const16(DisasContext *dc, const OpcodeArg arg[],
1596 const uint32_t par[])
1597 {
1598 TCGv_i32 c = tcg_const_i32(arg[1].imm);
1599
1600 tcg_gen_deposit_i32(arg[0].out, c, arg[0].in, 16, 16);
1601 tcg_temp_free(c);
1602 }
1603
1604 static void translate_dcache(DisasContext *dc, const OpcodeArg arg[],
1605 const uint32_t par[])
1606 {
1607 TCGv_i32 addr = tcg_temp_new_i32();
1608 TCGv_i32 res = tcg_temp_new_i32();
1609
1610 tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm);
1611 tcg_gen_qemu_ld8u(res, addr, dc->cring);
1612 tcg_temp_free(addr);
1613 tcg_temp_free(res);
1614 }
1615
1616 static void translate_depbits(DisasContext *dc, const OpcodeArg arg[],
1617 const uint32_t par[])
1618 {
1619 tcg_gen_deposit_i32(arg[1].out, arg[1].in, arg[0].in,
1620 arg[2].imm, arg[3].imm);
1621 }
1622
1623 static bool test_ill_entry(DisasContext *dc, const OpcodeArg arg[],
1624 const uint32_t par[])
1625 {
1626 if (arg[0].imm > 3 || !dc->cwoe) {
1627 qemu_log_mask(LOG_GUEST_ERROR,
1628 "Illegal entry instruction(pc = %08x)\n", dc->pc);
1629 return true;
1630 } else {
1631 return false;
1632 }
1633 }
1634
1635 static uint32_t test_overflow_entry(DisasContext *dc, const OpcodeArg arg[],
1636 const uint32_t par[])
1637 {
1638 return 1 << (dc->callinc * 4);
1639 }
1640
1641 static void translate_entry(DisasContext *dc, const OpcodeArg arg[],
1642 const uint32_t par[])
1643 {
1644 TCGv_i32 pc = tcg_const_i32(dc->pc);
1645 TCGv_i32 s = tcg_const_i32(arg[0].imm);
1646 TCGv_i32 imm = tcg_const_i32(arg[1].imm);
1647 gen_helper_entry(cpu_env, pc, s, imm);
1648 tcg_temp_free(imm);
1649 tcg_temp_free(s);
1650 tcg_temp_free(pc);
1651 }
1652
1653 static void translate_extui(DisasContext *dc, const OpcodeArg arg[],
1654 const uint32_t par[])
1655 {
1656 int maskimm = (1 << arg[3].imm) - 1;
1657
1658 TCGv_i32 tmp = tcg_temp_new_i32();
1659 tcg_gen_shri_i32(tmp, arg[1].in, arg[2].imm);
1660 tcg_gen_andi_i32(arg[0].out, tmp, maskimm);
1661 tcg_temp_free(tmp);
1662 }
1663
1664 static void translate_icache(DisasContext *dc, const OpcodeArg arg[],
1665 const uint32_t par[])
1666 {
1667 #ifndef CONFIG_USER_ONLY
1668 TCGv_i32 addr = tcg_temp_new_i32();
1669
1670 tcg_gen_movi_i32(cpu_pc, dc->pc);
1671 tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm);
1672 gen_helper_itlb_hit_test(cpu_env, addr);
1673 tcg_temp_free(addr);
1674 #endif
1675 }
1676
1677 static void translate_itlb(DisasContext *dc, const OpcodeArg arg[],
1678 const uint32_t par[])
1679 {
1680 #ifndef CONFIG_USER_ONLY
1681 TCGv_i32 dtlb = tcg_const_i32(par[0]);
1682
1683 gen_helper_itlb(cpu_env, arg[0].in, dtlb);
1684 tcg_temp_free(dtlb);
1685 #endif
1686 }
1687
1688 static void translate_j(DisasContext *dc, const OpcodeArg arg[],
1689 const uint32_t par[])
1690 {
1691 gen_jumpi(dc, arg[0].imm, 0);
1692 }
1693
1694 static void translate_jx(DisasContext *dc, const OpcodeArg arg[],
1695 const uint32_t par[])
1696 {
1697 gen_jump(dc, arg[0].in);
1698 }
1699
1700 static void translate_l32e(DisasContext *dc, const OpcodeArg arg[],
1701 const uint32_t par[])
1702 {
1703 TCGv_i32 addr = tcg_temp_new_i32();
1704
1705 tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
1706 gen_load_store_alignment(dc, 2, addr, false);
1707 tcg_gen_qemu_ld_tl(arg[0].out, addr, dc->ring, MO_TEUL);
1708 tcg_temp_free(addr);
1709 }
1710
1711 static void translate_ldst(DisasContext *dc, const OpcodeArg arg[],
1712 const uint32_t par[])
1713 {
1714 TCGv_i32 addr = tcg_temp_new_i32();
1715
1716 tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
1717 if (par[0] & MO_SIZE) {
1718 gen_load_store_alignment(dc, par[0] & MO_SIZE, addr, par[1]);
1719 }
1720 if (par[2]) {
1721 if (par[1]) {
1722 tcg_gen_mb(TCG_BAR_STRL | TCG_MO_ALL);
1723 }
1724 tcg_gen_qemu_st_tl(arg[0].in, addr, dc->cring, par[0]);
1725 } else {
1726 tcg_gen_qemu_ld_tl(arg[0].out, addr, dc->cring, par[0]);
1727 if (par[1]) {
1728 tcg_gen_mb(TCG_BAR_LDAQ | TCG_MO_ALL);
1729 }
1730 }
1731 tcg_temp_free(addr);
1732 }
1733
1734 static void translate_l32r(DisasContext *dc, const OpcodeArg arg[],
1735 const uint32_t par[])
1736 {
1737 TCGv_i32 tmp;
1738
1739 if (dc->base.tb->flags & XTENSA_TBFLAG_LITBASE) {
1740 tmp = tcg_const_i32(arg[1].raw_imm - 1);
1741 tcg_gen_add_i32(tmp, cpu_SR[LITBASE], tmp);
1742 } else {
1743 tmp = tcg_const_i32(arg[1].imm);
1744 }
1745 tcg_gen_qemu_ld32u(arg[0].out, tmp, dc->cring);
1746 tcg_temp_free(tmp);
1747 }
1748
1749 static void translate_loop(DisasContext *dc, const OpcodeArg arg[],
1750 const uint32_t par[])
1751 {
1752 uint32_t lend = arg[1].imm;
1753
1754 tcg_gen_subi_i32(cpu_SR[LCOUNT], arg[0].in, 1);
1755 tcg_gen_movi_i32(cpu_SR[LBEG], dc->base.pc_next);
1756 tcg_gen_movi_i32(cpu_SR[LEND], lend);
1757
1758 if (par[0] != TCG_COND_NEVER) {
1759 TCGLabel *label = gen_new_label();
1760 tcg_gen_brcondi_i32(par[0], arg[0].in, 0, label);
1761 gen_jumpi(dc, lend, 1);
1762 gen_set_label(label);
1763 }
1764
1765 gen_jumpi(dc, dc->base.pc_next, 0);
1766 }
1767
1768 enum {
1769 MAC16_UMUL,
1770 MAC16_MUL,
1771 MAC16_MULA,
1772 MAC16_MULS,
1773 MAC16_NONE,
1774 };
1775
1776 enum {
1777 MAC16_LL,
1778 MAC16_HL,
1779 MAC16_LH,
1780 MAC16_HH,
1781
1782 MAC16_HX = 0x1,
1783 MAC16_XH = 0x2,
1784 };
1785
1786 static void translate_mac16(DisasContext *dc, const OpcodeArg arg[],
1787 const uint32_t par[])
1788 {
1789 int op = par[0];
1790 unsigned half = par[1];
1791 uint32_t ld_offset = par[2];
1792 unsigned off = ld_offset ? 2 : 0;
1793 TCGv_i32 vaddr = tcg_temp_new_i32();
1794 TCGv_i32 mem32 = tcg_temp_new_i32();
1795
1796 if (ld_offset) {
1797 tcg_gen_addi_i32(vaddr, arg[1].in, ld_offset);
1798 gen_load_store_alignment(dc, 2, vaddr, false);
1799 tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
1800 }
1801 if (op != MAC16_NONE) {
1802 TCGv_i32 m1 = gen_mac16_m(arg[off].in,
1803 half & MAC16_HX, op == MAC16_UMUL);
1804 TCGv_i32 m2 = gen_mac16_m(arg[off + 1].in,
1805 half & MAC16_XH, op == MAC16_UMUL);
1806
1807 if (op == MAC16_MUL || op == MAC16_UMUL) {
1808 tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
1809 if (op == MAC16_UMUL) {
1810 tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
1811 } else {
1812 tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
1813 }
1814 } else {
1815 TCGv_i32 lo = tcg_temp_new_i32();
1816 TCGv_i32 hi = tcg_temp_new_i32();
1817
1818 tcg_gen_mul_i32(lo, m1, m2);
1819 tcg_gen_sari_i32(hi, lo, 31);
1820 if (op == MAC16_MULA) {
1821 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
1822 cpu_SR[ACCLO], cpu_SR[ACCHI],
1823 lo, hi);
1824 } else {
1825 tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
1826 cpu_SR[ACCLO], cpu_SR[ACCHI],
1827 lo, hi);
1828 }
1829 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
1830
1831 tcg_temp_free_i32(lo);
1832 tcg_temp_free_i32(hi);
1833 }
1834 tcg_temp_free(m1);
1835 tcg_temp_free(m2);
1836 }
1837 if (ld_offset) {
1838 tcg_gen_mov_i32(arg[1].out, vaddr);
1839 tcg_gen_mov_i32(cpu_SR[MR + arg[0].imm], mem32);
1840 }
1841 tcg_temp_free(vaddr);
1842 tcg_temp_free(mem32);
1843 }
1844
1845 static void translate_memw(DisasContext *dc, const OpcodeArg arg[],
1846 const uint32_t par[])
1847 {
1848 tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);
1849 }
1850
1851 static void translate_smin(DisasContext *dc, const OpcodeArg arg[],
1852 const uint32_t par[])
1853 {
1854 tcg_gen_smin_i32(arg[0].out, arg[1].in, arg[2].in);
1855 }
1856
1857 static void translate_umin(DisasContext *dc, const OpcodeArg arg[],
1858 const uint32_t par[])
1859 {
1860 tcg_gen_umin_i32(arg[0].out, arg[1].in, arg[2].in);
1861 }
1862
1863 static void translate_smax(DisasContext *dc, const OpcodeArg arg[],
1864 const uint32_t par[])
1865 {
1866 tcg_gen_smax_i32(arg[0].out, arg[1].in, arg[2].in);
1867 }
1868
1869 static void translate_umax(DisasContext *dc, const OpcodeArg arg[],
1870 const uint32_t par[])
1871 {
1872 tcg_gen_umax_i32(arg[0].out, arg[1].in, arg[2].in);
1873 }
1874
1875 static void translate_mov(DisasContext *dc, const OpcodeArg arg[],
1876 const uint32_t par[])
1877 {
1878 tcg_gen_mov_i32(arg[0].out, arg[1].in);
1879 }
1880
1881 static void translate_movcond(DisasContext *dc, const OpcodeArg arg[],
1882 const uint32_t par[])
1883 {
1884 TCGv_i32 zero = tcg_const_i32(0);
1885
1886 tcg_gen_movcond_i32(par[0], arg[0].out,
1887 arg[2].in, zero, arg[1].in, arg[0].in);
1888 tcg_temp_free(zero);
1889 }
1890
1891 static void translate_movi(DisasContext *dc, const OpcodeArg arg[],
1892 const uint32_t par[])
1893 {
1894 tcg_gen_movi_i32(arg[0].out, arg[1].imm);
1895 }
1896
1897 static void translate_movp(DisasContext *dc, const OpcodeArg arg[],
1898 const uint32_t par[])
1899 {
1900 TCGv_i32 zero = tcg_const_i32(0);
1901 TCGv_i32 tmp = tcg_temp_new_i32();
1902
1903 tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm);
1904 tcg_gen_movcond_i32(par[0],
1905 arg[0].out, tmp, zero,
1906 arg[1].in, arg[0].in);
1907 tcg_temp_free(tmp);
1908 tcg_temp_free(zero);
1909 }
1910
1911 static void translate_movsp(DisasContext *dc, const OpcodeArg arg[],
1912 const uint32_t par[])
1913 {
1914 tcg_gen_mov_i32(arg[0].out, arg[1].in);
1915 }
1916
1917 static void translate_mul16(DisasContext *dc, const OpcodeArg arg[],
1918 const uint32_t par[])
1919 {
1920 TCGv_i32 v1 = tcg_temp_new_i32();
1921 TCGv_i32 v2 = tcg_temp_new_i32();
1922
1923 if (par[0]) {
1924 tcg_gen_ext16s_i32(v1, arg[1].in);
1925 tcg_gen_ext16s_i32(v2, arg[2].in);
1926 } else {
1927 tcg_gen_ext16u_i32(v1, arg[1].in);
1928 tcg_gen_ext16u_i32(v2, arg[2].in);
1929 }
1930 tcg_gen_mul_i32(arg[0].out, v1, v2);
1931 tcg_temp_free(v2);
1932 tcg_temp_free(v1);
1933 }
1934
1935 static void translate_mull(DisasContext *dc, const OpcodeArg arg[],
1936 const uint32_t par[])
1937 {
1938 tcg_gen_mul_i32(arg[0].out, arg[1].in, arg[2].in);
1939 }
1940
1941 static void translate_mulh(DisasContext *dc, const OpcodeArg arg[],
1942 const uint32_t par[])
1943 {
1944 TCGv_i32 lo = tcg_temp_new();
1945
1946 if (par[0]) {
1947 tcg_gen_muls2_i32(lo, arg[0].out, arg[1].in, arg[2].in);
1948 } else {
1949 tcg_gen_mulu2_i32(lo, arg[0].out, arg[1].in, arg[2].in);
1950 }
1951 tcg_temp_free(lo);
1952 }
1953
1954 static void translate_neg(DisasContext *dc, const OpcodeArg arg[],
1955 const uint32_t par[])
1956 {
1957 tcg_gen_neg_i32(arg[0].out, arg[1].in);
1958 }
1959
1960 static void translate_nop(DisasContext *dc, const OpcodeArg arg[],
1961 const uint32_t par[])
1962 {
1963 }
1964
1965 static void translate_nsa(DisasContext *dc, const OpcodeArg arg[],
1966 const uint32_t par[])
1967 {
1968 tcg_gen_clrsb_i32(arg[0].out, arg[1].in);
1969 }
1970
1971 static void translate_nsau(DisasContext *dc, const OpcodeArg arg[],
1972 const uint32_t par[])
1973 {
1974 tcg_gen_clzi_i32(arg[0].out, arg[1].in, 32);
1975 }
1976
1977 static void translate_or(DisasContext *dc, const OpcodeArg arg[],
1978 const uint32_t par[])
1979 {
1980 tcg_gen_or_i32(arg[0].out, arg[1].in, arg[2].in);
1981 }
1982
1983 static void translate_ptlb(DisasContext *dc, const OpcodeArg arg[],
1984 const uint32_t par[])
1985 {
1986 #ifndef CONFIG_USER_ONLY
1987 TCGv_i32 dtlb = tcg_const_i32(par[0]);
1988
1989 tcg_gen_movi_i32(cpu_pc, dc->pc);
1990 gen_helper_ptlb(arg[0].out, cpu_env, arg[1].in, dtlb);
1991 tcg_temp_free(dtlb);
1992 #endif
1993 }
1994
1995 static void translate_pptlb(DisasContext *dc, const OpcodeArg arg[],
1996 const uint32_t par[])
1997 {
1998 #ifndef CONFIG_USER_ONLY
1999 tcg_gen_movi_i32(cpu_pc, dc->pc);
2000 gen_helper_pptlb(arg[0].out, cpu_env, arg[1].in);
2001 #endif
2002 }
2003
2004 static void translate_quos(DisasContext *dc, const OpcodeArg arg[],
2005 const uint32_t par[])
2006 {
2007 TCGLabel *label1 = gen_new_label();
2008 TCGLabel *label2 = gen_new_label();
2009
2010 tcg_gen_brcondi_i32(TCG_COND_NE, arg[1].in, 0x80000000,
2011 label1);
2012 tcg_gen_brcondi_i32(TCG_COND_NE, arg[2].in, 0xffffffff,
2013 label1);
2014 tcg_gen_movi_i32(arg[0].out,
2015 par[0] ? 0x80000000 : 0);
2016 tcg_gen_br(label2);
2017 gen_set_label(label1);
2018 if (par[0]) {
2019 tcg_gen_div_i32(arg[0].out,
2020 arg[1].in, arg[2].in);
2021 } else {
2022 tcg_gen_rem_i32(arg[0].out,
2023 arg[1].in, arg[2].in);
2024 }
2025 gen_set_label(label2);
2026 }
2027
2028 static void translate_quou(DisasContext *dc, const OpcodeArg arg[],
2029 const uint32_t par[])
2030 {
2031 tcg_gen_divu_i32(arg[0].out,
2032 arg[1].in, arg[2].in);
2033 }
2034
2035 static void translate_read_impwire(DisasContext *dc, const OpcodeArg arg[],
2036 const uint32_t par[])
2037 {
2038 /* TODO: GPIO32 may be a part of coprocessor */
2039 tcg_gen_movi_i32(arg[0].out, 0);
2040 }
2041
2042 static void translate_remu(DisasContext *dc, const OpcodeArg arg[],
2043 const uint32_t par[])
2044 {
2045 tcg_gen_remu_i32(arg[0].out,
2046 arg[1].in, arg[2].in);
2047 }
2048
2049 static void translate_rer(DisasContext *dc, const OpcodeArg arg[],
2050 const uint32_t par[])
2051 {
2052 gen_helper_rer(arg[0].out, cpu_env, arg[1].in);
2053 }
2054
2055 static void translate_ret(DisasContext *dc, const OpcodeArg arg[],
2056 const uint32_t par[])
2057 {
2058 gen_jump(dc, cpu_R[0]);
2059 }
2060
2061 static bool test_ill_retw(DisasContext *dc, const OpcodeArg arg[],
2062 const uint32_t par[])
2063 {
2064 if (!dc->cwoe) {
2065 qemu_log_mask(LOG_GUEST_ERROR,
2066 "Illegal retw instruction(pc = %08x)\n", dc->pc);
2067 return true;
2068 } else {
2069 TCGv_i32 tmp = tcg_const_i32(dc->pc);
2070
2071 gen_helper_test_ill_retw(cpu_env, tmp);
2072 tcg_temp_free(tmp);
2073 return false;
2074 }
2075 }
2076
2077 static void translate_retw(DisasContext *dc, const OpcodeArg arg[],
2078 const uint32_t par[])
2079 {
2080 TCGv_i32 tmp = tcg_const_i32(1);
2081 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
2082 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
2083 cpu_SR[WINDOW_START], tmp);
2084 tcg_gen_movi_i32(tmp, dc->pc);
2085 tcg_gen_deposit_i32(tmp, tmp, cpu_R[0], 0, 30);
2086 gen_helper_retw(cpu_env, cpu_R[0]);
2087 gen_jump(dc, tmp);
2088 tcg_temp_free(tmp);
2089 }
2090
2091 static void translate_rfde(DisasContext *dc, const OpcodeArg arg[],
2092 const uint32_t par[])
2093 {
2094 gen_jump(dc, cpu_SR[dc->config->ndepc ? DEPC : EPC1]);
2095 }
2096
2097 static void translate_rfe(DisasContext *dc, const OpcodeArg arg[],
2098 const uint32_t par[])
2099 {
2100 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
2101 gen_jump(dc, cpu_SR[EPC1]);
2102 }
2103
2104 static void translate_rfi(DisasContext *dc, const OpcodeArg arg[],
2105 const uint32_t par[])
2106 {
2107 tcg_gen_mov_i32(cpu_SR[PS], cpu_SR[EPS2 + arg[0].imm - 2]);
2108 gen_jump(dc, cpu_SR[EPC1 + arg[0].imm - 1]);
2109 }
2110
2111 static void translate_rfw(DisasContext *dc, const OpcodeArg arg[],
2112 const uint32_t par[])
2113 {
2114 TCGv_i32 tmp = tcg_const_i32(1);
2115
2116 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
2117 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
2118
2119 if (par[0]) {
2120 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
2121 cpu_SR[WINDOW_START], tmp);
2122 } else {
2123 tcg_gen_or_i32(cpu_SR[WINDOW_START],
2124 cpu_SR[WINDOW_START], tmp);
2125 }
2126
2127 tcg_temp_free(tmp);
2128 gen_helper_restore_owb(cpu_env);
2129 gen_jump(dc, cpu_SR[EPC1]);
2130 }
2131
2132 static void translate_rotw(DisasContext *dc, const OpcodeArg arg[],
2133 const uint32_t par[])
2134 {
2135 tcg_gen_addi_i32(cpu_windowbase_next, cpu_SR[WINDOW_BASE], arg[0].imm);
2136 }
2137
2138 static void translate_rsil(DisasContext *dc, const OpcodeArg arg[],
2139 const uint32_t par[])
2140 {
2141 tcg_gen_mov_i32(arg[0].out, cpu_SR[PS]);
2142 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
2143 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], arg[1].imm);
2144 }
2145
2146 static void translate_rsr(DisasContext *dc, const OpcodeArg arg[],
2147 const uint32_t par[])
2148 {
2149 tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
2150 }
2151
2152 static void translate_rsr_ccount(DisasContext *dc, const OpcodeArg arg[],
2153 const uint32_t par[])
2154 {
2155 #ifndef CONFIG_USER_ONLY
2156 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
2157 gen_io_start();
2158 }
2159 gen_helper_update_ccount(cpu_env);
2160 tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
2161 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
2162 gen_io_end();
2163 }
2164 #endif
2165 }
2166
2167 static void translate_rsr_ptevaddr(DisasContext *dc, const OpcodeArg arg[],
2168 const uint32_t par[])
2169 {
2170 #ifndef CONFIG_USER_ONLY
2171 TCGv_i32 tmp = tcg_temp_new_i32();
2172
2173 tcg_gen_shri_i32(tmp, cpu_SR[EXCVADDR], 10);
2174 tcg_gen_or_i32(tmp, tmp, cpu_SR[PTEVADDR]);
2175 tcg_gen_andi_i32(arg[0].out, tmp, 0xfffffffc);
2176 tcg_temp_free(tmp);
2177 #endif
2178 }
2179
2180 static void translate_rtlb(DisasContext *dc, const OpcodeArg arg[],
2181 const uint32_t par[])
2182 {
2183 #ifndef CONFIG_USER_ONLY
2184 static void (* const helper[])(TCGv_i32 r, TCGv_env env, TCGv_i32 a1,
2185 TCGv_i32 a2) = {
2186 gen_helper_rtlb0,
2187 gen_helper_rtlb1,
2188 };
2189 TCGv_i32 dtlb = tcg_const_i32(par[0]);
2190
2191 helper[par[1]](arg[0].out, cpu_env, arg[1].in, dtlb);
2192 tcg_temp_free(dtlb);
2193 #endif
2194 }
2195
2196 static void translate_rptlb0(DisasContext *dc, const OpcodeArg arg[],
2197 const uint32_t par[])
2198 {
2199 #ifndef CONFIG_USER_ONLY
2200 gen_helper_rptlb0(arg[0].out, cpu_env, arg[1].in);
2201 #endif
2202 }
2203
2204 static void translate_rptlb1(DisasContext *dc, const OpcodeArg arg[],
2205 const uint32_t par[])
2206 {
2207 #ifndef CONFIG_USER_ONLY
2208 gen_helper_rptlb1(arg[0].out, cpu_env, arg[1].in);
2209 #endif
2210 }
2211
2212 static void translate_rur(DisasContext *dc, const OpcodeArg arg[],
2213 const uint32_t par[])
2214 {
2215 tcg_gen_mov_i32(arg[0].out, cpu_UR[par[0]]);
2216 }
2217
2218 static void translate_setb_expstate(DisasContext *dc, const OpcodeArg arg[],
2219 const uint32_t par[])
2220 {
2221 /* TODO: GPIO32 may be a part of coprocessor */
2222 tcg_gen_ori_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], 1u << arg[0].imm);
2223 }
2224
2225 #ifdef CONFIG_USER_ONLY
2226 static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr)
2227 {
2228 }
2229 #else
2230 static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr)
2231 {
2232 TCGv_i32 tpc = tcg_const_i32(dc->pc);
2233
2234 gen_helper_check_atomctl(cpu_env, tpc, addr);
2235 tcg_temp_free(tpc);
2236 }
2237 #endif
2238
2239 static void translate_s32c1i(DisasContext *dc, const OpcodeArg arg[],
2240 const uint32_t par[])
2241 {
2242 TCGv_i32 tmp = tcg_temp_local_new_i32();
2243 TCGv_i32 addr = tcg_temp_local_new_i32();
2244
2245 tcg_gen_mov_i32(tmp, arg[0].in);
2246 tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
2247 gen_load_store_alignment(dc, 2, addr, true);
2248 gen_check_atomctl(dc, addr);
2249 tcg_gen_atomic_cmpxchg_i32(arg[0].out, addr, cpu_SR[SCOMPARE1],
2250 tmp, dc->cring, MO_TEUL);
2251 tcg_temp_free(addr);
2252 tcg_temp_free(tmp);
2253 }
2254
2255 static void translate_s32e(DisasContext *dc, const OpcodeArg arg[],
2256 const uint32_t par[])
2257 {
2258 TCGv_i32 addr = tcg_temp_new_i32();
2259
2260 tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
2261 gen_load_store_alignment(dc, 2, addr, false);
2262 tcg_gen_qemu_st_tl(arg[0].in, addr, dc->ring, MO_TEUL);
2263 tcg_temp_free(addr);
2264 }
2265
2266 static void translate_salt(DisasContext *dc, const OpcodeArg arg[],
2267 const uint32_t par[])
2268 {
2269 tcg_gen_setcond_i32(par[0],
2270 arg[0].out,
2271 arg[1].in, arg[2].in);
2272 }
2273
2274 static void translate_sext(DisasContext *dc, const OpcodeArg arg[],
2275 const uint32_t par[])
2276 {
2277 int shift = 31 - arg[2].imm;
2278
2279 if (shift == 24) {
2280 tcg_gen_ext8s_i32(arg[0].out, arg[1].in);
2281 } else if (shift == 16) {
2282 tcg_gen_ext16s_i32(arg[0].out, arg[1].in);
2283 } else {
2284 TCGv_i32 tmp = tcg_temp_new_i32();
2285 tcg_gen_shli_i32(tmp, arg[1].in, shift);
2286 tcg_gen_sari_i32(arg[0].out, tmp, shift);
2287 tcg_temp_free(tmp);
2288 }
2289 }
2290
2291 static bool test_ill_simcall(DisasContext *dc, const OpcodeArg arg[],
2292 const uint32_t par[])
2293 {
2294 #ifdef CONFIG_USER_ONLY
2295 bool ill = true;
2296 #else
2297 bool ill = !semihosting_enabled();
2298 #endif
2299 if (ill) {
2300 qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n");
2301 }
2302 return ill;
2303 }
2304
2305 static void translate_simcall(DisasContext *dc, const OpcodeArg arg[],
2306 const uint32_t par[])
2307 {
2308 #ifndef CONFIG_USER_ONLY
2309 gen_helper_simcall(cpu_env);
2310 #endif
2311 }
2312
2313 /*
2314 * Note: 64 bit ops are used here solely because SAR values
2315 * have range 0..63
2316 */
2317 #define gen_shift_reg(cmd, reg) do { \
2318 TCGv_i64 tmp = tcg_temp_new_i64(); \
2319 tcg_gen_extu_i32_i64(tmp, reg); \
2320 tcg_gen_##cmd##_i64(v, v, tmp); \
2321 tcg_gen_extrl_i64_i32(arg[0].out, v); \
2322 tcg_temp_free_i64(v); \
2323 tcg_temp_free_i64(tmp); \
2324 } while (0)
2325
2326 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
2327
2328 static void translate_sll(DisasContext *dc, const OpcodeArg arg[],
2329 const uint32_t par[])
2330 {
2331 if (dc->sar_m32_5bit) {
2332 tcg_gen_shl_i32(arg[0].out, arg[1].in, dc->sar_m32);
2333 } else {
2334 TCGv_i64 v = tcg_temp_new_i64();
2335 TCGv_i32 s = tcg_const_i32(32);
2336 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
2337 tcg_gen_andi_i32(s, s, 0x3f);
2338 tcg_gen_extu_i32_i64(v, arg[1].in);
2339 gen_shift_reg(shl, s);
2340 tcg_temp_free(s);
2341 }
2342 }
2343
2344 static void translate_slli(DisasContext *dc, const OpcodeArg arg[],
2345 const uint32_t par[])
2346 {
2347 if (arg[2].imm == 32) {
2348 qemu_log_mask(LOG_GUEST_ERROR, "slli a%d, a%d, 32 is undefined\n",
2349 arg[0].imm, arg[1].imm);
2350 }
2351 tcg_gen_shli_i32(arg[0].out, arg[1].in, arg[2].imm & 0x1f);
2352 }
2353
2354 static void translate_sra(DisasContext *dc, const OpcodeArg arg[],
2355 const uint32_t par[])
2356 {
2357 if (dc->sar_m32_5bit) {
2358 tcg_gen_sar_i32(arg[0].out, arg[1].in, cpu_SR[SAR]);
2359 } else {
2360 TCGv_i64 v = tcg_temp_new_i64();
2361 tcg_gen_ext_i32_i64(v, arg[1].in);
2362 gen_shift(sar);
2363 }
2364 }
2365
2366 static void translate_srai(DisasContext *dc, const OpcodeArg arg[],
2367 const uint32_t par[])
2368 {
2369 tcg_gen_sari_i32(arg[0].out, arg[1].in, arg[2].imm);
2370 }
2371
2372 static void translate_src(DisasContext *dc, const OpcodeArg arg[],
2373 const uint32_t par[])
2374 {
2375 TCGv_i64 v = tcg_temp_new_i64();
2376 tcg_gen_concat_i32_i64(v, arg[2].in, arg[1].in);
2377 gen_shift(shr);
2378 }
2379
2380 static void translate_srl(DisasContext *dc, const OpcodeArg arg[],
2381 const uint32_t par[])
2382 {
2383 if (dc->sar_m32_5bit) {
2384 tcg_gen_shr_i32(arg[0].out, arg[1].in, cpu_SR[SAR]);
2385 } else {
2386 TCGv_i64 v = tcg_temp_new_i64();
2387 tcg_gen_extu_i32_i64(v, arg[1].in);
2388 gen_shift(shr);
2389 }
2390 }
2391
2392 #undef gen_shift
2393 #undef gen_shift_reg
2394
2395 static void translate_srli(DisasContext *dc, const OpcodeArg arg[],
2396 const uint32_t par[])
2397 {
2398 tcg_gen_shri_i32(arg[0].out, arg[1].in, arg[2].imm);
2399 }
2400
2401 static void translate_ssa8b(DisasContext *dc, const OpcodeArg arg[],
2402 const uint32_t par[])
2403 {
2404 TCGv_i32 tmp = tcg_temp_new_i32();
2405 tcg_gen_shli_i32(tmp, arg[0].in, 3);
2406 gen_left_shift_sar(dc, tmp);
2407 tcg_temp_free(tmp);
2408 }
2409
2410 static void translate_ssa8l(DisasContext *dc, const OpcodeArg arg[],
2411 const uint32_t par[])
2412 {
2413 TCGv_i32 tmp = tcg_temp_new_i32();
2414 tcg_gen_shli_i32(tmp, arg[0].in, 3);
2415 gen_right_shift_sar(dc, tmp);
2416 tcg_temp_free(tmp);
2417 }
2418
2419 static void translate_ssai(DisasContext *dc, const OpcodeArg arg[],
2420 const uint32_t par[])
2421 {
2422 TCGv_i32 tmp = tcg_const_i32(arg[0].imm);
2423 gen_right_shift_sar(dc, tmp);
2424 tcg_temp_free(tmp);
2425 }
2426
2427 static void translate_ssl(DisasContext *dc, const OpcodeArg arg[],
2428 const uint32_t par[])
2429 {
2430 gen_left_shift_sar(dc, arg[0].in);
2431 }
2432
2433 static void translate_ssr(DisasContext *dc, const OpcodeArg arg[],
2434 const uint32_t par[])
2435 {
2436 gen_right_shift_sar(dc, arg[0].in);
2437 }
2438
2439 static void translate_sub(DisasContext *dc, const OpcodeArg arg[],
2440 const uint32_t par[])
2441 {
2442 tcg_gen_sub_i32(arg[0].out, arg[1].in, arg[2].in);
2443 }
2444
2445 static void translate_subx(DisasContext *dc, const OpcodeArg arg[],
2446 const uint32_t par[])
2447 {
2448 TCGv_i32 tmp = tcg_temp_new_i32();
2449 tcg_gen_shli_i32(tmp, arg[1].in, par[0]);
2450 tcg_gen_sub_i32(arg[0].out, tmp, arg[2].in);
2451 tcg_temp_free(tmp);
2452 }
2453
2454 static void translate_waiti(DisasContext *dc, const OpcodeArg arg[],
2455 const uint32_t par[])
2456 {
2457 #ifndef CONFIG_USER_ONLY
2458 gen_waiti(dc, arg[0].imm);
2459 #endif
2460 }
2461
2462 static void translate_wtlb(DisasContext *dc, const OpcodeArg arg[],
2463 const uint32_t par[])
2464 {
2465 #ifndef CONFIG_USER_ONLY
2466 TCGv_i32 dtlb = tcg_const_i32(par[0]);
2467
2468 gen_helper_wtlb(cpu_env, arg[0].in, arg[1].in, dtlb);
2469 tcg_temp_free(dtlb);
2470 #endif
2471 }
2472
2473 static void translate_wptlb(DisasContext *dc, const OpcodeArg arg[],
2474 const uint32_t par[])
2475 {
2476 #ifndef CONFIG_USER_ONLY
2477 gen_helper_wptlb(cpu_env, arg[0].in, arg[1].in);
2478 #endif
2479 }
2480
2481 static void translate_wer(DisasContext *dc, const OpcodeArg arg[],
2482 const uint32_t par[])
2483 {
2484 gen_helper_wer(cpu_env, arg[0].in, arg[1].in);
2485 }
2486
2487 static void translate_wrmsk_expstate(DisasContext *dc, const OpcodeArg arg[],
2488 const uint32_t par[])
2489 {
2490 /* TODO: GPIO32 may be a part of coprocessor */
2491 tcg_gen_and_i32(cpu_UR[EXPSTATE], arg[0].in, arg[1].in);
2492 }
2493
2494 static void translate_wsr(DisasContext *dc, const OpcodeArg arg[],
2495 const uint32_t par[])
2496 {
2497 tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
2498 }
2499
2500 static void translate_wsr_mask(DisasContext *dc, const OpcodeArg arg[],
2501 const uint32_t par[])
2502 {
2503 tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, par[2]);
2504 }
2505
2506 static void translate_wsr_acchi(DisasContext *dc, const OpcodeArg arg[],
2507 const uint32_t par[])
2508 {
2509 tcg_gen_ext8s_i32(cpu_SR[par[0]], arg[0].in);
2510 }
2511
2512 static void translate_wsr_ccompare(DisasContext *dc, const OpcodeArg arg[],
2513 const uint32_t par[])
2514 {
2515 #ifndef CONFIG_USER_ONLY
2516 uint32_t id = par[0] - CCOMPARE;
2517 TCGv_i32 tmp = tcg_const_i32(id);
2518
2519 assert(id < dc->config->nccompare);
2520 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
2521 gen_io_start();
2522 }
2523 tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
2524 gen_helper_update_ccompare(cpu_env, tmp);
2525 tcg_temp_free(tmp);
2526 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
2527 gen_io_end();
2528 }
2529 #endif
2530 }
2531
2532 static void translate_wsr_ccount(DisasContext *dc, const OpcodeArg arg[],
2533 const uint32_t par[])
2534 {
2535 #ifndef CONFIG_USER_ONLY
2536 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
2537 gen_io_start();
2538 }
2539 gen_helper_wsr_ccount(cpu_env, arg[0].in);
2540 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
2541 gen_io_end();
2542 }
2543 #endif
2544 }
2545
2546 static void translate_wsr_dbreaka(DisasContext *dc, const OpcodeArg arg[],
2547 const uint32_t par[])
2548 {
2549 #ifndef CONFIG_USER_ONLY
2550 unsigned id = par[0] - DBREAKA;
2551 TCGv_i32 tmp = tcg_const_i32(id);
2552
2553 assert(id < dc->config->ndbreak);
2554 gen_helper_wsr_dbreaka(cpu_env, tmp, arg[0].in);
2555 tcg_temp_free(tmp);
2556 #endif
2557 }
2558
2559 static void translate_wsr_dbreakc(DisasContext *dc, const OpcodeArg arg[],
2560 const uint32_t par[])
2561 {
2562 #ifndef CONFIG_USER_ONLY
2563 unsigned id = par[0] - DBREAKC;
2564 TCGv_i32 tmp = tcg_const_i32(id);
2565
2566 assert(id < dc->config->ndbreak);
2567 gen_helper_wsr_dbreakc(cpu_env, tmp, arg[0].in);
2568 tcg_temp_free(tmp);
2569 #endif
2570 }
2571
2572 static void translate_wsr_ibreaka(DisasContext *dc, const OpcodeArg arg[],
2573 const uint32_t par[])
2574 {
2575 #ifndef CONFIG_USER_ONLY
2576 unsigned id = par[0] - IBREAKA;
2577 TCGv_i32 tmp = tcg_const_i32(id);
2578
2579 assert(id < dc->config->nibreak);
2580 gen_helper_wsr_ibreaka(cpu_env, tmp, arg[0].in);
2581 tcg_temp_free(tmp);
2582 #endif
2583 }
2584
2585 static void translate_wsr_ibreakenable(DisasContext *dc, const OpcodeArg arg[],
2586 const uint32_t par[])
2587 {
2588 #ifndef CONFIG_USER_ONLY
2589 gen_helper_wsr_ibreakenable(cpu_env, arg[0].in);
2590 #endif
2591 }
2592
2593 static void translate_wsr_icount(DisasContext *dc, const OpcodeArg arg[],
2594 const uint32_t par[])
2595 {
2596 #ifndef CONFIG_USER_ONLY
2597 if (dc->icount) {
2598 tcg_gen_mov_i32(dc->next_icount, arg[0].in);
2599 } else {
2600 tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
2601 }
2602 #endif
2603 }
2604
2605 static void translate_wsr_intclear(DisasContext *dc, const OpcodeArg arg[],
2606 const uint32_t par[])
2607 {
2608 #ifndef CONFIG_USER_ONLY
2609 gen_helper_intclear(cpu_env, arg[0].in);
2610 #endif
2611 }
2612
2613 static void translate_wsr_intset(DisasContext *dc, const OpcodeArg arg[],
2614 const uint32_t par[])
2615 {
2616 #ifndef CONFIG_USER_ONLY
2617 gen_helper_intset(cpu_env, arg[0].in);
2618 #endif
2619 }
2620
2621 static void translate_wsr_memctl(DisasContext *dc, const OpcodeArg arg[],
2622 const uint32_t par[])
2623 {
2624 #ifndef CONFIG_USER_ONLY
2625 gen_helper_wsr_memctl(cpu_env, arg[0].in);
2626 #endif
2627 }
2628
2629 static void translate_wsr_mpuenb(DisasContext *dc, const OpcodeArg arg[],
2630 const uint32_t par[])
2631 {
2632 #ifndef CONFIG_USER_ONLY
2633 gen_helper_wsr_mpuenb(cpu_env, arg[0].in);
2634 #endif
2635 }
2636
2637 static void translate_wsr_ps(DisasContext *dc, const OpcodeArg arg[],
2638 const uint32_t par[])
2639 {
2640 #ifndef CONFIG_USER_ONLY
2641 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
2642 PS_UM | PS_EXCM | PS_INTLEVEL;
2643
2644 if (option_enabled(dc, XTENSA_OPTION_MMU)) {
2645 mask |= PS_RING;
2646 }
2647 tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, mask);
2648 #endif
2649 }
2650
2651 static void translate_wsr_rasid(DisasContext *dc, const OpcodeArg arg[],
2652 const uint32_t par[])
2653 {
2654 #ifndef CONFIG_USER_ONLY
2655 gen_helper_wsr_rasid(cpu_env, arg[0].in);
2656 #endif
2657 }
2658
2659 static void translate_wsr_sar(DisasContext *dc, const OpcodeArg arg[],
2660 const uint32_t par[])
2661 {
2662 tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, 0x3f);
2663 if (dc->sar_m32_5bit) {
2664 tcg_gen_discard_i32(dc->sar_m32);
2665 }
2666 dc->sar_5bit = false;
2667 dc->sar_m32_5bit = false;
2668 }
2669
2670 static void translate_wsr_windowbase(DisasContext *dc, const OpcodeArg arg[],
2671 const uint32_t par[])
2672 {
2673 #ifndef CONFIG_USER_ONLY
2674 tcg_gen_mov_i32(cpu_windowbase_next, arg[0].in);
2675 #endif
2676 }
2677
2678 static void translate_wsr_windowstart(DisasContext *dc, const OpcodeArg arg[],
2679 const uint32_t par[])
2680 {
2681 #ifndef CONFIG_USER_ONLY
2682 tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in,
2683 (1 << dc->config->nareg / 4) - 1);
2684 #endif
2685 }
2686
2687 static void translate_wur(DisasContext *dc, const OpcodeArg arg[],
2688 const uint32_t par[])
2689 {
2690 tcg_gen_mov_i32(cpu_UR[par[0]], arg[0].in);
2691 }
2692
2693 static void translate_wur_fcr(DisasContext *dc, const OpcodeArg arg[],
2694 const uint32_t par[])
2695 {
2696 gen_helper_wur_fcr(cpu_env, arg[0].in);
2697 }
2698
2699 static void translate_wur_fsr(DisasContext *dc, const OpcodeArg arg[],
2700 const uint32_t par[])
2701 {
2702 tcg_gen_andi_i32(cpu_UR[par[0]], arg[0].in, 0xffffff80);
2703 }
2704
2705 static void translate_xor(DisasContext *dc, const OpcodeArg arg[],
2706 const uint32_t par[])
2707 {
2708 tcg_gen_xor_i32(arg[0].out, arg[1].in, arg[2].in);
2709 }
2710
2711 static void translate_xsr(DisasContext *dc, const OpcodeArg arg[],
2712 const uint32_t par[])
2713 {
2714 TCGv_i32 tmp = tcg_temp_new_i32();
2715
2716 tcg_gen_mov_i32(tmp, arg[0].in);
2717 tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
2718 tcg_gen_mov_i32(cpu_SR[par[0]], tmp);
2719 tcg_temp_free(tmp);
2720 }
2721
2722 static void translate_xsr_mask(DisasContext *dc, const OpcodeArg arg[],
2723 const uint32_t par[])
2724 {
2725 TCGv_i32 tmp = tcg_temp_new_i32();
2726
2727 tcg_gen_mov_i32(tmp, arg[0].in);
2728 tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
2729 tcg_gen_andi_i32(cpu_SR[par[0]], tmp, par[2]);
2730 tcg_temp_free(tmp);
2731 }
2732
2733 static void translate_xsr_ccount(DisasContext *dc, const OpcodeArg arg[],
2734 const uint32_t par[])
2735 {
2736 #ifndef CONFIG_USER_ONLY
2737 TCGv_i32 tmp = tcg_temp_new_i32();
2738
2739 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
2740 gen_io_start();
2741 }
2742
2743 gen_helper_update_ccount(cpu_env);
2744 tcg_gen_mov_i32(tmp, cpu_SR[par[0]]);
2745 gen_helper_wsr_ccount(cpu_env, arg[0].in);
2746 tcg_gen_mov_i32(arg[0].out, tmp);
2747 tcg_temp_free(tmp);
2748
2749 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
2750 gen_io_end();
2751 }
2752 #endif
2753 }
2754
2755 #define gen_translate_xsr(name) \
2756 static void translate_xsr_##name(DisasContext *dc, const OpcodeArg arg[], \
2757 const uint32_t par[]) \
2758 { \
2759 TCGv_i32 tmp = tcg_temp_new_i32(); \
2760 \
2761 tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); \
2762 translate_wsr_##name(dc, arg, par); \
2763 tcg_gen_mov_i32(arg[0].out, tmp); \
2764 tcg_temp_free(tmp); \
2765 }
2766
2767 gen_translate_xsr(acchi)
2768 gen_translate_xsr(ccompare)
2769 gen_translate_xsr(dbreaka)
2770 gen_translate_xsr(dbreakc)
2771 gen_translate_xsr(ibreaka)
2772 gen_translate_xsr(ibreakenable)
2773 gen_translate_xsr(icount)
2774 gen_translate_xsr(memctl)
2775 gen_translate_xsr(mpuenb)
2776 gen_translate_xsr(ps)
2777 gen_translate_xsr(rasid)
2778 gen_translate_xsr(sar)
2779 gen_translate_xsr(windowbase)
2780 gen_translate_xsr(windowstart)
2781
2782 #undef gen_translate_xsr
2783
2784 static const XtensaOpcodeOps core_ops[] = {
2785 {
2786 .name = "abs",
2787 .translate = translate_abs,
2788 }, {
2789 .name = (const char * const[]) {
2790 "add", "add.n", NULL,
2791 },
2792 .translate = translate_add,
2793 .op_flags = XTENSA_OP_NAME_ARRAY,
2794 }, {
2795 .name = (const char * const[]) {
2796 "addi", "addi.n", NULL,
2797 },
2798 .translate = translate_addi,
2799 .op_flags = XTENSA_OP_NAME_ARRAY,
2800 }, {
2801 .name = "addmi",
2802 .translate = translate_addi,
2803 }, {
2804 .name = "addx2",
2805 .translate = translate_addx,
2806 .par = (const uint32_t[]){1},
2807 }, {
2808 .name = "addx4",
2809 .translate = translate_addx,
2810 .par = (const uint32_t[]){2},
2811 }, {
2812 .name = "addx8",
2813 .translate = translate_addx,
2814 .par = (const uint32_t[]){3},
2815 }, {
2816 .name = "all4",
2817 .translate = translate_all,
2818 .par = (const uint32_t[]){true, 4},
2819 }, {
2820 .name = "all8",
2821 .translate = translate_all,
2822 .par = (const uint32_t[]){true, 8},
2823 }, {
2824 .name = "and",
2825 .translate = translate_and,
2826 }, {
2827 .name = "andb",
2828 .translate = translate_boolean,
2829 .par = (const uint32_t[]){BOOLEAN_AND},
2830 }, {
2831 .name = "andbc",
2832 .translate = translate_boolean,
2833 .par = (const uint32_t[]){BOOLEAN_ANDC},
2834 }, {
2835 .name = "any4",
2836 .translate = translate_all,
2837 .par = (const uint32_t[]){false, 4},
2838 }, {
2839 .name = "any8",
2840 .translate = translate_all,
2841 .par = (const uint32_t[]){false, 8},
2842 }, {
2843 .name = (const char * const[]) {
2844 "ball", "ball.w15", "ball.w18", NULL,
2845 },
2846 .translate = translate_ball,
2847 .par = (const uint32_t[]){TCG_COND_EQ},
2848 .op_flags = XTENSA_OP_NAME_ARRAY,
2849 }, {
2850 .name = (const char * const[]) {
2851 "bany", "bany.w15", "bany.w18", NULL,
2852 },
2853 .translate = translate_bany,
2854 .par = (const uint32_t[]){TCG_COND_NE},
2855 .op_flags = XTENSA_OP_NAME_ARRAY,
2856 }, {
2857 .name = (const char * const[]) {
2858 "bbc", "bbc.w15", "bbc.w18", NULL,
2859 },
2860 .translate = translate_bb,
2861 .par = (const uint32_t[]){TCG_COND_EQ},
2862 .op_flags = XTENSA_OP_NAME_ARRAY,
2863 }, {
2864 .name = (const char * const[]) {
2865 "bbci", "bbci.w15", "bbci.w18", NULL,
2866 },
2867 .translate = translate_bbi,
2868 .par = (const uint32_t[]){TCG_COND_EQ},
2869 .op_flags = XTENSA_OP_NAME_ARRAY,
2870 }, {
2871 .name = (const char * const[]) {
2872 "bbs", "bbs.w15", "bbs.w18", NULL,
2873 },
2874 .translate = translate_bb,
2875 .par = (const uint32_t[]){TCG_COND_NE},
2876 .op_flags = XTENSA_OP_NAME_ARRAY,
2877 }, {
2878 .name = (const char * const[]) {
2879 "bbsi", "bbsi.w15", "bbsi.w18", NULL,
2880 },
2881 .translate = translate_bbi,
2882 .par = (const uint32_t[]){TCG_COND_NE},
2883 .op_flags = XTENSA_OP_NAME_ARRAY,
2884 }, {
2885 .name = (const char * const[]) {
2886 "beq", "beq.w15", "beq.w18", NULL,
2887 },
2888 .translate = translate_b,
2889 .par = (const uint32_t[]){TCG_COND_EQ},
2890 .op_flags = XTENSA_OP_NAME_ARRAY,
2891 }, {
2892 .name = (const char * const[]) {
2893 "beqi", "beqi.w15", "beqi.w18", NULL,
2894 },
2895 .translate = translate_bi,
2896 .par = (const uint32_t[]){TCG_COND_EQ},
2897 .op_flags = XTENSA_OP_NAME_ARRAY,
2898 }, {
2899 .name = (const char * const[]) {
2900 "beqz", "beqz.n", "beqz.w15", "beqz.w18", NULL,
2901 },
2902 .translate = translate_bz,
2903 .par = (const uint32_t[]){TCG_COND_EQ},
2904 .op_flags = XTENSA_OP_NAME_ARRAY,
2905 }, {
2906 .name = "bf",
2907 .translate = translate_bp,
2908 .par = (const uint32_t[]){TCG_COND_EQ},
2909 }, {
2910 .name = (const char * const[]) {
2911 "bge", "bge.w15", "bge.w18", NULL,
2912 },
2913 .translate = translate_b,
2914 .par = (const uint32_t[]){TCG_COND_GE},
2915 .op_flags = XTENSA_OP_NAME_ARRAY,
2916 }, {
2917 .name = (const char * const[]) {
2918 "bgei", "bgei.w15", "bgei.w18", NULL,
2919 },
2920 .translate = translate_bi,
2921 .par = (const uint32_t[]){TCG_COND_GE},
2922 .op_flags = XTENSA_OP_NAME_ARRAY,
2923 }, {
2924 .name = (const char * const[]) {
2925 "bgeu", "bgeu.w15", "bgeu.w18", NULL,
2926 },
2927 .translate = translate_b,
2928 .par = (const uint32_t[]){TCG_COND_GEU},
2929 .op_flags = XTENSA_OP_NAME_ARRAY,
2930 }, {
2931 .name = (const char * const[]) {
2932 "bgeui", "bgeui.w15", "bgeui.w18", NULL,
2933 },
2934 .translate = translate_bi,
2935 .par = (const uint32_t[]){TCG_COND_GEU},
2936 .op_flags = XTENSA_OP_NAME_ARRAY,
2937 }, {
2938 .name = (const char * const[]) {
2939 "bgez", "bgez.w15", "bgez.w18", NULL,
2940 },
2941 .translate = translate_bz,
2942 .par = (const uint32_t[]){TCG_COND_GE},
2943 .op_flags = XTENSA_OP_NAME_ARRAY,
2944 }, {
2945 .name = (const char * const[]) {
2946 "blt", "blt.w15", "blt.w18", NULL,
2947 },
2948 .translate = translate_b,
2949 .par = (const uint32_t[]){TCG_COND_LT},
2950 .op_flags = XTENSA_OP_NAME_ARRAY,
2951 }, {
2952 .name = (const char * const[]) {
2953 "blti", "blti.w15", "blti.w18", NULL,
2954 },
2955 .translate = translate_bi,
2956 .par = (const uint32_t[]){TCG_COND_LT},
2957 .op_flags = XTENSA_OP_NAME_ARRAY,
2958 }, {
2959 .name = (const char * const[]) {
2960 "bltu", "bltu.w15", "bltu.w18", NULL,
2961 },
2962 .translate = translate_b,
2963 .par = (const uint32_t[]){TCG_COND_LTU},
2964 .op_flags = XTENSA_OP_NAME_ARRAY,
2965 }, {
2966 .name = (const char * const[]) {
2967 "bltui", "bltui.w15", "bltui.w18", NULL,
2968 },
2969 .translate = translate_bi,
2970 .par = (const uint32_t[]){TCG_COND_LTU},
2971 .op_flags = XTENSA_OP_NAME_ARRAY,
2972 }, {
2973 .name = (const char * const[]) {
2974 "bltz", "bltz.w15", "bltz.w18", NULL,
2975 },
2976 .translate = translate_bz,
2977 .par = (const uint32_t[]){TCG_COND_LT},
2978 .op_flags = XTENSA_OP_NAME_ARRAY,
2979 }, {
2980 .name = (const char * const[]) {
2981 "bnall", "bnall.w15", "bnall.w18", NULL,
2982 },
2983 .translate = translate_ball,
2984 .par = (const uint32_t[]){TCG_COND_NE},
2985 .op_flags = XTENSA_OP_NAME_ARRAY,
2986 }, {
2987 .name = (const char * const[]) {
2988 "bne", "bne.w15", "bne.w18", NULL,
2989 },
2990 .translate = translate_b,
2991 .par = (const uint32_t[]){TCG_COND_NE},
2992 .op_flags = XTENSA_OP_NAME_ARRAY,
2993 }, {
2994 .name = (const char * const[]) {
2995 "bnei", "bnei.w15", "bnei.w18", NULL,
2996 },
2997 .translate = translate_bi,
2998 .par = (const uint32_t[]){TCG_COND_NE},
2999 .op_flags = XTENSA_OP_NAME_ARRAY,
3000 }, {
3001 .name = (const char * const[]) {
3002 "bnez", "bnez.n", "bnez.w15", "bnez.w18", NULL,
3003 },
3004 .translate = translate_bz,
3005 .par = (const uint32_t[]){TCG_COND_NE},
3006 .op_flags = XTENSA_OP_NAME_ARRAY,
3007 }, {
3008 .name = (const char * const[]) {
3009 "bnone", "bnone.w15", "bnone.w18", NULL,
3010 },
3011 .translate = translate_bany,
3012 .par = (const uint32_t[]){TCG_COND_EQ},
3013 .op_flags = XTENSA_OP_NAME_ARRAY,
3014 }, {
3015 .name = "break",
3016 .translate = translate_nop,
3017 .par = (const uint32_t[]){DEBUGCAUSE_BI},
3018 .op_flags = XTENSA_OP_DEBUG_BREAK,
3019 }, {
3020 .name = "break.n",
3021 .translate = translate_nop,
3022 .par = (const uint32_t[]){DEBUGCAUSE_BN},
3023 .op_flags = XTENSA_OP_DEBUG_BREAK,
3024 }, {
3025 .name = "bt",
3026 .translate = translate_bp,
3027 .par = (const uint32_t[]){TCG_COND_NE},
3028 }, {
3029 .name = "call0",
3030 .translate = translate_call0,
3031 }, {
3032 .name = "call12",
3033 .translate = translate_callw,
3034 .par = (const uint32_t[]){3},
3035 }, {
3036 .name = "call4",
3037 .translate = translate_callw,
3038 .par = (const uint32_t[]){1},
3039 }, {
3040 .name = "call8",
3041 .translate = translate_callw,
3042 .par = (const uint32_t[]){2},
3043 }, {
3044 .name = "callx0",
3045 .translate = translate_callx0,
3046 }, {
3047 .name = "callx12",
3048 .translate = translate_callxw,
3049 .par = (const uint32_t[]){3},
3050 }, {
3051 .name = "callx4",
3052 .translate = translate_callxw,
3053 .par = (const uint32_t[]){1},
3054 }, {
3055 .name = "callx8",
3056 .translate = translate_callxw,
3057 .par = (const uint32_t[]){2},
3058 }, {
3059 .name = "clamps",
3060 .translate = translate_clamps,
3061 }, {
3062 .name = "clrb_expstate",
3063 .translate = translate_clrb_expstate,
3064 }, {
3065 .name = "const16",
3066 .translate = translate_const16,
3067 }, {
3068 .name = "depbits",
3069 .translate = translate_depbits,
3070 }, {
3071 .name = "dhi",
3072 .translate = translate_dcache,
3073 .op_flags = XTENSA_OP_PRIVILEGED,
3074 }, {
3075 .name = "dhu",
3076 .translate = translate_dcache,
3077 .op_flags = XTENSA_OP_PRIVILEGED,
3078 }, {
3079 .name = "dhwb",
3080 .translate = translate_dcache,
3081 }, {
3082 .name = "dhwbi",
3083 .translate = translate_dcache,
3084 }, {
3085 .name = "dii",
3086 .translate = translate_nop,
3087 .op_flags = XTENSA_OP_PRIVILEGED,
3088 }, {
3089 .name = "diu",
3090 .translate = translate_nop,
3091 .op_flags = XTENSA_OP_PRIVILEGED,
3092 }, {
3093 .name = "diwb",
3094 .translate = translate_nop,
3095 .op_flags = XTENSA_OP_PRIVILEGED,
3096 }, {
3097 .name = "diwbi",
3098 .translate = translate_nop,
3099 .op_flags = XTENSA_OP_PRIVILEGED,
3100 }, {
3101 .name = "dpfl",
3102 .translate = translate_dcache,
3103 .op_flags = XTENSA_OP_PRIVILEGED,
3104 }, {
3105 .name = "dpfr",
3106 .translate = translate_nop,
3107 }, {
3108 .name = "dpfro",
3109 .translate = translate_nop,
3110 }, {
3111 .name = "dpfw",
3112 .translate = translate_nop,
3113 }, {
3114 .name = "dpfwo",
3115 .translate = translate_nop,
3116 }, {
3117 .name = "dsync",
3118 .translate = translate_nop,
3119 }, {
3120 .name = "entry",
3121 .translate = translate_entry,
3122 .test_ill = test_ill_entry,
3123 .test_overflow = test_overflow_entry,
3124 .op_flags = XTENSA_OP_EXIT_TB_M1 |
3125 XTENSA_OP_SYNC_REGISTER_WINDOW,
3126 }, {
3127 .name = "esync",
3128 .translate = translate_nop,
3129 }, {
3130 .name = "excw",
3131 .translate = translate_nop,
3132 }, {
3133 .name = "extui",
3134 .translate = translate_extui,
3135 }, {
3136 .name = "extw",
3137 .translate = translate_memw,
3138 }, {
3139 .name = "hwwdtlba",
3140 .op_flags = XTENSA_OP_ILL,
3141 }, {
3142 .name = "hwwitlba",
3143 .op_flags = XTENSA_OP_ILL,
3144 }, {
3145 .name = "idtlb",
3146 .translate = translate_itlb,
3147 .par = (const uint32_t[]){true},
3148 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
3149 }, {
3150 .name = "ihi",
3151 .translate = translate_icache,
3152 }, {
3153 .name = "ihu",
3154 .translate = translate_icache,
3155 .op_flags = XTENSA_OP_PRIVILEGED,
3156 }, {
3157 .name = "iii",
3158 .translate = translate_nop,
3159 .op_flags = XTENSA_OP_PRIVILEGED,
3160 }, {
3161 .name = "iitlb",
3162 .translate = translate_itlb,
3163 .par = (const uint32_t[]){false},
3164 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
3165 }, {
3166 .name = "iiu",
3167 .translate = translate_nop,
3168 .op_flags = XTENSA_OP_PRIVILEGED,
3169 }, {
3170 .name = (const char * const[]) {
3171 "ill", "ill.n", NULL,
3172 },
3173 .op_flags = XTENSA_OP_ILL | XTENSA_OP_NAME_ARRAY,
3174 }, {
3175 .name = "ipf",
3176 .translate = translate_nop,
3177 }, {
3178 .name = "ipfl",
3179 .translate = translate_icache,
3180 .op_flags = XTENSA_OP_PRIVILEGED,
3181 }, {
3182 .name = "isync",
3183 .translate = translate_nop,
3184 }, {
3185 .name = "j",
3186 .translate = translate_j,
3187 }, {
3188 .name = "jx",
3189 .translate = translate_jx,
3190 }, {
3191 .name = "l16si",
3192 .translate = translate_ldst,
3193 .par = (const uint32_t[]){MO_TESW, false, false},
3194 .op_flags = XTENSA_OP_LOAD,
3195 }, {
3196 .name = "l16ui",
3197 .translate = translate_ldst,
3198 .par = (const uint32_t[]){MO_TEUW, false, false},
3199 .op_flags = XTENSA_OP_LOAD,
3200 }, {
3201 .name = "l32ai",
3202 .translate = translate_ldst,
3203 .par = (const uint32_t[]){MO_TEUL, true, false},
3204 .op_flags = XTENSA_OP_LOAD,
3205 }, {
3206 .name = "l32e",
3207 .translate = translate_l32e,
3208 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_LOAD,
3209 }, {
3210 .name = (const char * const[]) {
3211 "l32i", "l32i.n", NULL,
3212 },
3213 .translate = translate_ldst,
3214 .par = (const uint32_t[]){MO_TEUL, false, false},
3215 .op_flags = XTENSA_OP_NAME_ARRAY | XTENSA_OP_LOAD,
3216 }, {
3217 .name = "l32r",
3218 .translate = translate_l32r,
3219 .op_flags = XTENSA_OP_LOAD,
3220 }, {
3221 .name = "l8ui",
3222 .translate = translate_ldst,
3223 .par = (const uint32_t[]){MO_UB, false, false},
3224 .op_flags = XTENSA_OP_LOAD,
3225 }, {
3226 .name = "lddec",
3227 .translate = translate_mac16,
3228 .par = (const uint32_t[]){MAC16_NONE, 0, -4},
3229 .op_flags = XTENSA_OP_LOAD,
3230 }, {
3231 .name = "ldinc",
3232 .translate = translate_mac16,
3233 .par = (const uint32_t[]){MAC16_NONE, 0, 4},
3234 .op_flags = XTENSA_OP_LOAD,
3235 }, {
3236 .name = "ldpte",
3237 .op_flags = XTENSA_OP_ILL,
3238 }, {
3239 .name = (const char * const[]) {
3240 "loop", "loop.w15", NULL,
3241 },
3242 .translate = translate_loop,
3243 .par = (const uint32_t[]){TCG_COND_NEVER},
3244 .op_flags = XTENSA_OP_NAME_ARRAY,
3245 }, {
3246 .name = (const char * const[]) {
3247 "loopgtz", "loopgtz.w15", NULL,
3248 },
3249 .translate = translate_loop,
3250 .par = (const uint32_t[]){TCG_COND_GT},
3251 .op_flags = XTENSA_OP_NAME_ARRAY,
3252 }, {
3253 .name = (const char * const[]) {
3254 "loopnez", "loopnez.w15", NULL,
3255 },
3256 .translate = translate_loop,
3257 .par = (const uint32_t[]){TCG_COND_NE},
3258 .op_flags = XTENSA_OP_NAME_ARRAY,
3259 }, {
3260 .name = "max",
3261 .translate = translate_smax,
3262 }, {
3263 .name = "maxu",
3264 .translate = translate_umax,
3265 }, {
3266 .name = "memw",
3267 .translate = translate_memw,
3268 }, {
3269 .name = "min",
3270 .translate = translate_smin,
3271 }, {
3272 .name = "minu",
3273 .translate = translate_umin,
3274 }, {
3275 .name = (const char * const[]) {
3276 "mov", "mov.n", NULL,
3277 },
3278 .translate = translate_mov,
3279 .op_flags = XTENSA_OP_NAME_ARRAY,
3280 }, {
3281 .name = "moveqz",
3282 .translate = translate_movcond,
3283 .par = (const uint32_t[]){TCG_COND_EQ},
3284 }, {
3285 .name = "movf",
3286 .translate = translate_movp,
3287 .par = (const uint32_t[]){TCG_COND_EQ},
3288 }, {
3289 .name = "movgez",
3290 .translate = translate_movcond,
3291 .par = (const uint32_t[]){TCG_COND_GE},
3292 }, {
3293 .name = "movi",
3294 .translate = translate_movi,
3295 }, {
3296 .name = "movi.n",
3297 .translate = translate_movi,
3298 }, {
3299 .name = "movltz",
3300 .translate = translate_movcond,
3301 .par = (const uint32_t[]){TCG_COND_LT},
3302 }, {
3303 .name = "movnez",
3304 .translate = translate_movcond,
3305 .par = (const uint32_t[]){TCG_COND_NE},
3306 }, {
3307 .name = "movsp",
3308 .translate = translate_movsp,
3309 .op_flags = XTENSA_OP_ALLOCA,
3310 }, {
3311 .name = "movt",
3312 .translate = translate_movp,
3313 .par = (const uint32_t[]){TCG_COND_NE},
3314 }, {
3315 .name = "mul.aa.hh",
3316 .translate = translate_mac16,
3317 .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0},
3318 }, {
3319 .name = "mul.aa.hl",
3320 .translate = translate_mac16,
3321 .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0},
3322 }, {
3323 .name = "mul.aa.lh",
3324 .translate = translate_mac16,
3325 .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0},
3326 }, {
3327 .name = "mul.aa.ll",
3328 .translate = translate_mac16,
3329 .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0},
3330 }, {
3331 .name = "mul.ad.hh",
3332 .translate = translate_mac16,
3333 .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0},
3334 }, {
3335 .name = "mul.ad.hl",
3336 .translate = translate_mac16,
3337 .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0},
3338 }, {
3339 .name = "mul.ad.lh",
3340 .translate = translate_mac16,
3341 .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0},
3342 }, {
3343 .name = "mul.ad.ll",
3344 .translate = translate_mac16,
3345 .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0},
3346 }, {
3347 .name = "mul.da.hh",
3348 .translate = translate_mac16,
3349 .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0},
3350 }, {
3351 .name = "mul.da.hl",
3352 .translate = translate_mac16,
3353 .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0},
3354 }, {
3355 .name = "mul.da.lh",
3356 .translate = translate_mac16,
3357 .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0},
3358 }, {
3359 .name = "mul.da.ll",
3360 .translate = translate_mac16,
3361 .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0},
3362 }, {
3363 .name = "mul.dd.hh",
3364 .translate = translate_mac16,
3365 .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0},
3366 }, {
3367 .name = "mul.dd.hl",
3368 .translate = translate_mac16,
3369 .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0},
3370 }, {
3371 .name = "mul.dd.lh",
3372 .translate = translate_mac16,
3373 .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0},
3374 }, {
3375 .name = "mul.dd.ll",
3376 .translate = translate_mac16,
3377 .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0},
3378 }, {
3379 .name = "mul16s",
3380 .translate = translate_mul16,
3381 .par = (const uint32_t[]){true},
3382 }, {
3383 .name = "mul16u",
3384 .translate = translate_mul16,
3385 .par = (const uint32_t[]){false},
3386 }, {
3387 .name = "mula.aa.hh",
3388 .translate = translate_mac16,
3389 .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0},
3390 }, {
3391 .name = "mula.aa.hl",
3392 .translate = translate_mac16,
3393 .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0},
3394 }, {
3395 .name = "mula.aa.lh",
3396 .translate = translate_mac16,
3397 .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0},
3398 }, {
3399 .name = "mula.aa.ll",
3400 .translate = translate_mac16,
3401 .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0},
3402 }, {
3403 .name = "mula.ad.hh",
3404 .translate = translate_mac16,
3405 .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0},
3406 }, {
3407 .name = "mula.ad.hl",
3408 .translate = translate_mac16,
3409 .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0},
3410 }, {
3411 .name = "mula.ad.lh",
3412 .translate = translate_mac16,
3413 .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0},
3414 }, {
3415 .name = "mula.ad.ll",
3416 .translate = translate_mac16,
3417 .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0},
3418 }, {
3419 .name = "mula.da.hh",
3420 .translate = translate_mac16,
3421 .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0},
3422 }, {
3423 .name = "mula.da.hh.lddec",
3424 .translate = translate_mac16,
3425 .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, -4},
3426 }, {
3427 .name = "mula.da.hh.ldinc",
3428 .translate = translate_mac16,
3429 .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 4},
3430 }, {
3431 .name = "mula.da.hl",
3432 .translate = translate_mac16,
3433 .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0},
3434 }, {
3435 .name = "mula.da.hl.lddec",
3436 .translate = translate_mac16,
3437 .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, -4},
3438 }, {
3439 .name = "mula.da.hl.ldinc",
3440 .translate = translate_mac16,
3441 .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 4},
3442 }, {
3443 .name = "mula.da.lh",
3444 .translate = translate_mac16,
3445 .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0},
3446 }, {
3447 .name = "mula.da.lh.lddec",
3448 .translate = translate_mac16,
3449 .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, -4},
3450 }, {
3451 .name = "mula.da.lh.ldinc",
3452 .translate = translate_mac16,
3453 .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 4},
3454 }, {
3455 .name = "mula.da.ll",
3456 .translate = translate_mac16,
3457 .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0},
3458 }, {
3459 .name = "mula.da.ll.lddec",
3460 .translate = translate_mac16,
3461 .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, -4},
3462 }, {
3463 .name = "mula.da.ll.ldinc",
3464 .translate = translate_mac16,
3465 .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 4},
3466 }, {
3467 .name = "mula.dd.hh",
3468 .translate = translate_mac16,
3469 .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0},
3470 }, {
3471 .name = "mula.dd.hh.lddec",
3472 .translate = translate_mac16,
3473 .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, -4},
3474 }, {
3475 .name = "mula.dd.hh.ldinc",
3476 .translate = translate_mac16,
3477 .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 4},
3478 }, {
3479 .name = "mula.dd.hl",
3480 .translate = translate_mac16,
3481 .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0},
3482 }, {
3483 .name = "mula.dd.hl.lddec",
3484 .translate = translate_mac16,
3485 .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, -4},
3486 }, {
3487 .name = "mula.dd.hl.ldinc",
3488 .translate = translate_mac16,
3489 .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 4},
3490 }, {
3491 .name = "mula.dd.lh",
3492 .translate = translate_mac16,
3493 .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0},
3494 }, {
3495 .name = "mula.dd.lh.lddec",
3496 .translate = translate_mac16,
3497 .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, -4},
3498 }, {
3499 .name = "mula.dd.lh.ldinc",
3500 .translate = translate_mac16,
3501 .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 4},
3502 }, {
3503 .name = "mula.dd.ll",
3504 .translate = translate_mac16,
3505 .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0},
3506 }, {
3507 .name = "mula.dd.ll.lddec",
3508 .translate = translate_mac16,
3509 .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, -4},
3510 }, {
3511 .name = "mula.dd.ll.ldinc",
3512 .translate = translate_mac16,
3513 .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 4},
3514 }, {
3515 .name = "mull",
3516 .translate = translate_mull,
3517 }, {
3518 .name = "muls.aa.hh",
3519 .translate = translate_mac16,
3520 .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0},
3521 }, {
3522 .name = "muls.aa.hl",
3523 .translate = translate_mac16,
3524 .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0},
3525 }, {
3526 .name = "muls.aa.lh",
3527 .translate = translate_mac16,
3528 .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0},
3529 }, {
3530 .name = "muls.aa.ll",
3531 .translate = translate_mac16,
3532 .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0},
3533 }, {
3534 .name = "muls.ad.hh",
3535 .translate = translate_mac16,
3536 .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0},
3537 }, {
3538 .name = "muls.ad.hl",
3539 .translate = translate_mac16,
3540 .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0},
3541 }, {
3542 .name = "muls.ad.lh",
3543 .translate = translate_mac16,
3544 .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0},
3545 }, {
3546 .name = "muls.ad.ll",
3547 .translate = translate_mac16,
3548 .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0},
3549 }, {
3550 .name = "muls.da.hh",
3551 .translate = translate_mac16,
3552 .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0},
3553 }, {
3554 .name = "muls.da.hl",
3555 .translate = translate_mac16,
3556 .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0},
3557 }, {
3558 .name = "muls.da.lh",
3559 .translate = translate_mac16,
3560 .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0},
3561 }, {
3562 .name = "muls.da.ll",
3563 .translate = translate_mac16,
3564 .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0},
3565 }, {
3566 .name = "muls.dd.hh",
3567 .translate = translate_mac16,
3568 .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0},
3569 }, {
3570 .name = "muls.dd.hl",
3571 .translate = translate_mac16,
3572 .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0},
3573 }, {
3574 .name = "muls.dd.lh",
3575 .translate = translate_mac16,
3576 .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0},
3577 }, {
3578 .name = "muls.dd.ll",
3579 .translate = translate_mac16,
3580 .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0},
3581 }, {
3582 .name = "mulsh",
3583 .translate = translate_mulh,
3584 .par = (const uint32_t[]){true},
3585 }, {
3586 .name = "muluh",
3587 .translate = translate_mulh,
3588 .par = (const uint32_t[]){false},
3589 }, {
3590 .name = "neg",
3591 .translate = translate_neg,
3592 }, {
3593 .name = (const char * const[]) {
3594 "nop", "nop.n", NULL,
3595 },
3596 .translate = translate_nop,
3597 .op_flags = XTENSA_OP_NAME_ARRAY,
3598 }, {
3599 .name = "nsa",
3600 .translate = translate_nsa,
3601 }, {
3602 .name = "nsau",
3603 .translate = translate_nsau,
3604 }, {
3605 .name = "or",
3606 .translate = translate_or,
3607 }, {
3608 .name = "orb",
3609 .translate = translate_boolean,
3610 .par = (const uint32_t[]){BOOLEAN_OR},
3611 }, {
3612 .name = "orbc",
3613 .translate = translate_boolean,
3614 .par = (const uint32_t[]){BOOLEAN_ORC},
3615 }, {
3616 .name = "pdtlb",
3617 .translate = translate_ptlb,
3618 .par = (const uint32_t[]){true},
3619 .op_flags = XTENSA_OP_PRIVILEGED,
3620 }, {
3621 .name = "pitlb",
3622 .translate = translate_ptlb,
3623 .par = (const uint32_t[]){false},
3624 .op_flags = XTENSA_OP_PRIVILEGED,
3625 }, {
3626 .name = "pptlb",
3627 .translate = translate_pptlb,
3628 .op_flags = XTENSA_OP_PRIVILEGED,
3629 }, {
3630 .name = "quos",
3631 .translate = translate_quos,
3632 .par = (const uint32_t[]){true},
3633 .op_flags = XTENSA_OP_DIVIDE_BY_ZERO,
3634 }, {
3635 .name = "quou",
3636 .translate = translate_quou,
3637 .op_flags = XTENSA_OP_DIVIDE_BY_ZERO,
3638 }, {
3639 .name = "rdtlb0",
3640 .translate = translate_rtlb,
3641 .par = (const uint32_t[]){true, 0},
3642 .op_flags = XTENSA_OP_PRIVILEGED,
3643 }, {
3644 .name = "rdtlb1",
3645 .translate = translate_rtlb,
3646 .par = (const uint32_t[]){true, 1},
3647 .op_flags = XTENSA_OP_PRIVILEGED,
3648 }, {
3649 .name = "read_impwire",
3650 .translate = translate_read_impwire,
3651 }, {
3652 .name = "rems",
3653 .translate = translate_quos,
3654 .par = (const uint32_t[]){false},
3655 .op_flags = XTENSA_OP_DIVIDE_BY_ZERO,
3656 }, {
3657 .name = "remu",
3658 .translate = translate_remu,
3659 .op_flags = XTENSA_OP_DIVIDE_BY_ZERO,
3660 }, {
3661 .name = "rer",
3662 .translate = translate_rer,
3663 .op_flags = XTENSA_OP_PRIVILEGED,
3664 }, {
3665 .name = (const char * const[]) {
3666 "ret", "ret.n", NULL,
3667 },
3668 .translate = translate_ret,
3669 .op_flags = XTENSA_OP_NAME_ARRAY,
3670 }, {
3671 .name = (const char * const[]) {
3672 "retw", "retw.n", NULL,
3673 },
3674 .translate = translate_retw,
3675 .test_ill = test_ill_retw,
3676 .op_flags = XTENSA_OP_UNDERFLOW | XTENSA_OP_NAME_ARRAY,
3677 }, {
3678 .name = "rfdd",
3679 .op_flags = XTENSA_OP_ILL,
3680 }, {
3681 .name = "rfde",
3682 .translate = translate_rfde,
3683 .op_flags = XTENSA_OP_PRIVILEGED,
3684 }, {
3685 .name = "rfdo",
3686 .op_flags = XTENSA_OP_ILL,
3687 }, {
3688 .name = "rfe",
3689 .translate = translate_rfe,
3690 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,
3691 }, {
3692 .name = "rfi",
3693 .translate = translate_rfi,
3694 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,
3695 }, {
3696 .name = "rfwo",
3697 .translate = translate_rfw,
3698 .par = (const uint32_t[]){true},
3699 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,
3700 }, {
3701 .name = "rfwu",
3702 .translate = translate_rfw,
3703 .par = (const uint32_t[]){false},
3704 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,
3705 }, {
3706 .name = "ritlb0",
3707 .translate = translate_rtlb,
3708 .par = (const uint32_t[]){false, 0},
3709 .op_flags = XTENSA_OP_PRIVILEGED,
3710 }, {
3711 .name = "ritlb1",
3712 .translate = translate_rtlb,
3713 .par = (const uint32_t[]){false, 1},
3714 .op_flags = XTENSA_OP_PRIVILEGED,
3715 }, {
3716 .name = "rptlb0",
3717 .translate = translate_rptlb0,
3718 .op_flags = XTENSA_OP_PRIVILEGED,
3719 }, {
3720 .name = "rptlb1",
3721 .translate = translate_rptlb1,
3722 .op_flags = XTENSA_OP_PRIVILEGED,
3723 }, {
3724 .name = "rotw",
3725 .translate = translate_rotw,
3726 .op_flags = XTENSA_OP_PRIVILEGED |
3727 XTENSA_OP_EXIT_TB_M1 |
3728 XTENSA_OP_SYNC_REGISTER_WINDOW,
3729 }, {
3730 .name = "rsil",
3731 .translate = translate_rsil,
3732 .op_flags =
3733 XTENSA_OP_PRIVILEGED |
3734 XTENSA_OP_EXIT_TB_0 |
3735 XTENSA_OP_CHECK_INTERRUPTS,
3736 }, {
3737 .name = "rsr.176",
3738 .translate = translate_rsr,
3739 .par = (const uint32_t[]){176},
3740 .op_flags = XTENSA_OP_PRIVILEGED,
3741 }, {
3742 .name = "rsr.208",
3743 .translate = translate_rsr,
3744 .par = (const uint32_t[]){208},
3745 .op_flags = XTENSA_OP_PRIVILEGED,
3746 }, {
3747 .name = "rsr.acchi",
3748 .translate = translate_rsr,
3749 .test_ill = test_ill_sr,
3750 .par = (const uint32_t[]){
3751 ACCHI,
3752 XTENSA_OPTION_MAC16,
3753 },
3754 }, {
3755 .name = "rsr.acclo",
3756 .translate = translate_rsr,
3757 .test_ill = test_ill_sr,
3758 .par = (const uint32_t[]){
3759 ACCLO,
3760 XTENSA_OPTION_MAC16,
3761 },
3762 }, {
3763 .name = "rsr.atomctl",
3764 .translate = translate_rsr,
3765 .test_ill = test_ill_sr,
3766 .par = (const uint32_t[]){
3767 ATOMCTL,
3768 XTENSA_OPTION_ATOMCTL,
3769 },
3770 .op_flags = XTENSA_OP_PRIVILEGED,
3771 }, {
3772 .name = "rsr.br",
3773 .translate = translate_rsr,
3774 .test_ill = test_ill_sr,
3775 .par = (const uint32_t[]){
3776 BR,
3777 XTENSA_OPTION_BOOLEAN,
3778 },
3779 }, {
3780 .name = "rsr.cacheadrdis",
3781 .translate = translate_rsr,
3782 .test_ill = test_ill_sr,
3783 .par = (const uint32_t[]){
3784 CACHEADRDIS,
3785 XTENSA_OPTION_MPU,
3786 },
3787 .op_flags = XTENSA_OP_PRIVILEGED,
3788 }, {
3789 .name = "rsr.cacheattr",
3790 .translate = translate_rsr,
3791 .test_ill = test_ill_sr,
3792 .par = (const uint32_t[]){
3793 CACHEATTR,
3794 XTENSA_OPTION_CACHEATTR,
3795 },
3796 .op_flags = XTENSA_OP_PRIVILEGED,
3797 }, {
3798 .name = "rsr.ccompare0",
3799 .translate = translate_rsr,
3800 .test_ill = test_ill_ccompare,
3801 .par = (const uint32_t[]){
3802 CCOMPARE,
3803 XTENSA_OPTION_TIMER_INTERRUPT,
3804 },
3805 .op_flags = XTENSA_OP_PRIVILEGED,
3806 }, {
3807 .name = "rsr.ccompare1",
3808 .translate = translate_rsr,
3809 .test_ill = test_ill_ccompare,
3810 .par = (const uint32_t[]){
3811 CCOMPARE + 1,
3812 XTENSA_OPTION_TIMER_INTERRUPT,
3813 },
3814 .op_flags = XTENSA_OP_PRIVILEGED,
3815 }, {
3816 .name = "rsr.ccompare2",
3817 .translate = translate_rsr,
3818 .test_ill = test_ill_ccompare,
3819 .par = (const uint32_t[]){
3820 CCOMPARE + 2,
3821 XTENSA_OPTION_TIMER_INTERRUPT,
3822 },
3823 .op_flags = XTENSA_OP_PRIVILEGED,
3824 }, {
3825 .name = "rsr.ccount",
3826 .translate = translate_rsr_ccount,
3827 .test_ill = test_ill_sr,
3828 .par = (const uint32_t[]){
3829 CCOUNT,
3830 XTENSA_OPTION_TIMER_INTERRUPT,
3831 },
3832 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
3833 }, {
3834 .name = "rsr.configid0",
3835 .translate = translate_rsr,
3836 .par = (const uint32_t[]){CONFIGID0},
3837 .op_flags = XTENSA_OP_PRIVILEGED,
3838 }, {
3839 .name = "rsr.configid1",
3840 .translate = translate_rsr,
3841 .par = (const uint32_t[]){CONFIGID1},
3842 .op_flags = XTENSA_OP_PRIVILEGED,
3843 }, {
3844 .name = "rsr.cpenable",
3845 .translate = translate_rsr,
3846 .test_ill = test_ill_sr,
3847 .par = (const uint32_t[]){
3848 CPENABLE,
3849 XTENSA_OPTION_COPROCESSOR,
3850 },
3851 .op_flags = XTENSA_OP_PRIVILEGED,
3852 }, {
3853 .name = "rsr.dbreaka0",
3854 .translate = translate_rsr,
3855 .test_ill = test_ill_dbreak,
3856 .par = (const uint32_t[]){
3857 DBREAKA,
3858 XTENSA_OPTION_DEBUG,
3859 },
3860 .op_flags = XTENSA_OP_PRIVILEGED,
3861 }, {
3862 .name = "rsr.dbreaka1",
3863 .translate = translate_rsr,
3864 .test_ill = test_ill_dbreak,
3865 .par = (const uint32_t[]){
3866 DBREAKA + 1,
3867 XTENSA_OPTION_DEBUG,
3868 },
3869 .op_flags = XTENSA_OP_PRIVILEGED,
3870 }, {
3871 .name = "rsr.dbreakc0",
3872 .translate = translate_rsr,
3873 .test_ill = test_ill_dbreak,
3874 .par = (const uint32_t[]){
3875 DBREAKC,
3876 XTENSA_OPTION_DEBUG,
3877 },
3878 .op_flags = XTENSA_OP_PRIVILEGED,
3879 }, {
3880 .name = "rsr.dbreakc1",
3881 .translate = translate_rsr,
3882 .test_ill = test_ill_dbreak,
3883 .par = (const uint32_t[]){
3884 DBREAKC + 1,
3885 XTENSA_OPTION_DEBUG,
3886 },
3887 .op_flags = XTENSA_OP_PRIVILEGED,
3888 }, {
3889 .name = "rsr.ddr",
3890 .translate = translate_rsr,
3891 .test_ill = test_ill_sr,
3892 .par = (const uint32_t[]){
3893 DDR,
3894 XTENSA_OPTION_DEBUG,
3895 },
3896 .op_flags = XTENSA_OP_PRIVILEGED,
3897 }, {
3898 .name = "rsr.debugcause",
3899 .translate = translate_rsr,
3900 .test_ill = test_ill_sr,
3901 .par = (const uint32_t[]){
3902 DEBUGCAUSE,
3903 XTENSA_OPTION_DEBUG,
3904 },
3905 .op_flags = XTENSA_OP_PRIVILEGED,
3906 }, {
3907 .name = "rsr.depc",
3908 .translate = translate_rsr,
3909 .test_ill = test_ill_sr,
3910 .par = (const uint32_t[]){
3911 DEPC,
3912 XTENSA_OPTION_EXCEPTION,
3913 },
3914 .op_flags = XTENSA_OP_PRIVILEGED,
3915 }, {
3916 .name = "rsr.dtlbcfg",
3917 .translate = translate_rsr,
3918 .test_ill = test_ill_sr,
3919 .par = (const uint32_t[]){
3920 DTLBCFG,
3921 XTENSA_OPTION_MMU,
3922 },
3923 .op_flags = XTENSA_OP_PRIVILEGED,
3924 }, {
3925 .name = "rsr.epc1",
3926 .translate = translate_rsr,
3927 .test_ill = test_ill_sr,
3928 .par = (const uint32_t[]){
3929 EPC1,
3930 XTENSA_OPTION_EXCEPTION,
3931 },
3932 .op_flags = XTENSA_OP_PRIVILEGED,
3933 }, {
3934 .name = "rsr.epc2",
3935 .translate = translate_rsr,
3936 .test_ill = test_ill_hpi,
3937 .par = (const uint32_t[]){
3938 EPC1 + 1,
3939 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
3940 },
3941 .op_flags = XTENSA_OP_PRIVILEGED,
3942 }, {
3943 .name = "rsr.epc3",
3944 .translate = translate_rsr,
3945 .test_ill = test_ill_hpi,
3946 .par = (const uint32_t[]){
3947 EPC1 + 2,
3948 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
3949 },
3950 .op_flags = XTENSA_OP_PRIVILEGED,
3951 }, {
3952 .name = "rsr.epc4",
3953 .translate = translate_rsr,
3954 .test_ill = test_ill_hpi,
3955 .par = (const uint32_t[]){
3956 EPC1 + 3,
3957 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
3958 },
3959 .op_flags = XTENSA_OP_PRIVILEGED,
3960 }, {
3961 .name = "rsr.epc5",
3962 .translate = translate_rsr,
3963 .test_ill = test_ill_hpi,
3964 .par = (const uint32_t[]){
3965 EPC1 + 4,
3966 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
3967 },
3968 .op_flags = XTENSA_OP_PRIVILEGED,
3969 }, {
3970 .name = "rsr.epc6",
3971 .translate = translate_rsr,
3972 .test_ill = test_ill_hpi,
3973 .par = (const uint32_t[]){
3974 EPC1 + 5,
3975 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
3976 },
3977 .op_flags = XTENSA_OP_PRIVILEGED,
3978 }, {
3979 .name = "rsr.epc7",
3980 .translate = translate_rsr,
3981 .test_ill = test_ill_hpi,
3982 .par = (const uint32_t[]){
3983 EPC1 + 6,
3984 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
3985 },
3986 .op_flags = XTENSA_OP_PRIVILEGED,
3987 }, {
3988 .name = "rsr.eps2",
3989 .translate = translate_rsr,
3990 .test_ill = test_ill_hpi,
3991 .par = (const uint32_t[]){
3992 EPS2,
3993 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
3994 },
3995 .op_flags = XTENSA_OP_PRIVILEGED,
3996 }, {
3997 .name = "rsr.eps3",
3998 .translate = translate_rsr,
3999 .test_ill = test_ill_hpi,
4000 .par = (const uint32_t[]){
4001 EPS2 + 1,
4002 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4003 },
4004 .op_flags = XTENSA_OP_PRIVILEGED,
4005 }, {
4006 .name = "rsr.eps4",
4007 .translate = translate_rsr,
4008 .test_ill = test_ill_hpi,
4009 .par = (const uint32_t[]){
4010 EPS2 + 2,
4011 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4012 },
4013 .op_flags = XTENSA_OP_PRIVILEGED,
4014 }, {
4015 .name = "rsr.eps5",
4016 .translate = translate_rsr,
4017 .test_ill = test_ill_hpi,
4018 .par = (const uint32_t[]){
4019 EPS2 + 3,
4020 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4021 },
4022 .op_flags = XTENSA_OP_PRIVILEGED,
4023 }, {
4024 .name = "rsr.eps6",
4025 .translate = translate_rsr,
4026 .test_ill = test_ill_hpi,
4027 .par = (const uint32_t[]){
4028 EPS2 + 4,
4029 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4030 },
4031 .op_flags = XTENSA_OP_PRIVILEGED,
4032 }, {
4033 .name = "rsr.eps7",
4034 .translate = translate_rsr,
4035 .test_ill = test_ill_hpi,
4036 .par = (const uint32_t[]){
4037 EPS2 + 5,
4038 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4039 },
4040 .op_flags = XTENSA_OP_PRIVILEGED,
4041 }, {
4042 .name = "rsr.eraccess",
4043 .translate = translate_rsr,
4044 .par = (const uint32_t[]){ERACCESS},
4045 .op_flags = XTENSA_OP_PRIVILEGED,
4046 }, {
4047 .name = "rsr.exccause",
4048 .translate = translate_rsr,
4049 .test_ill = test_ill_sr,
4050 .par = (const uint32_t[]){
4051 EXCCAUSE,
4052 XTENSA_OPTION_EXCEPTION,
4053 },
4054 .op_flags = XTENSA_OP_PRIVILEGED,
4055 }, {
4056 .name = "rsr.excsave1",
4057 .translate = translate_rsr,
4058 .test_ill = test_ill_sr,
4059 .par = (const uint32_t[]){
4060 EXCSAVE1,
4061 XTENSA_OPTION_EXCEPTION,
4062 },
4063 .op_flags = XTENSA_OP_PRIVILEGED,
4064 }, {
4065 .name = "rsr.excsave2",
4066 .translate = translate_rsr,
4067 .test_ill = test_ill_hpi,
4068 .par = (const uint32_t[]){
4069 EXCSAVE1 + 1,
4070 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4071 },
4072 .op_flags = XTENSA_OP_PRIVILEGED,
4073 }, {
4074 .name = "rsr.excsave3",
4075 .translate = translate_rsr,
4076 .test_ill = test_ill_hpi,
4077 .par = (const uint32_t[]){
4078 EXCSAVE1 + 2,
4079 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4080 },
4081 .op_flags = XTENSA_OP_PRIVILEGED,
4082 }, {
4083 .name = "rsr.excsave4",
4084 .translate = translate_rsr,
4085 .test_ill = test_ill_hpi,
4086 .par = (const uint32_t[]){
4087 EXCSAVE1 + 3,
4088 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4089 },
4090 .op_flags = XTENSA_OP_PRIVILEGED,
4091 }, {
4092 .name = "rsr.excsave5",
4093 .translate = translate_rsr,
4094 .test_ill = test_ill_hpi,
4095 .par = (const uint32_t[]){
4096 EXCSAVE1 + 4,
4097 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4098 },
4099 .op_flags = XTENSA_OP_PRIVILEGED,
4100 }, {
4101 .name = "rsr.excsave6",
4102 .translate = translate_rsr,
4103 .test_ill = test_ill_hpi,
4104 .par = (const uint32_t[]){
4105 EXCSAVE1 + 5,
4106 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4107 },
4108 .op_flags = XTENSA_OP_PRIVILEGED,
4109 }, {
4110 .name = "rsr.excsave7",
4111 .translate = translate_rsr,
4112 .test_ill = test_ill_hpi,
4113 .par = (const uint32_t[]){
4114 EXCSAVE1 + 6,
4115 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4116 },
4117 .op_flags = XTENSA_OP_PRIVILEGED,
4118 }, {
4119 .name = "rsr.excvaddr",
4120 .translate = translate_rsr,
4121 .test_ill = test_ill_sr,
4122 .par = (const uint32_t[]){
4123 EXCVADDR,
4124 XTENSA_OPTION_EXCEPTION,
4125 },
4126 .op_flags = XTENSA_OP_PRIVILEGED,
4127 }, {
4128 .name = "rsr.ibreaka0",
4129 .translate = translate_rsr,
4130 .test_ill = test_ill_ibreak,
4131 .par = (const uint32_t[]){
4132 IBREAKA,
4133 XTENSA_OPTION_DEBUG,
4134 },
4135 .op_flags = XTENSA_OP_PRIVILEGED,
4136 }, {
4137 .name = "rsr.ibreaka1",
4138 .translate = translate_rsr,
4139 .test_ill = test_ill_ibreak,
4140 .par = (const uint32_t[]){
4141 IBREAKA + 1,
4142 XTENSA_OPTION_DEBUG,
4143 },
4144 .op_flags = XTENSA_OP_PRIVILEGED,
4145 }, {
4146 .name = "rsr.ibreakenable",
4147 .translate = translate_rsr,
4148 .test_ill = test_ill_sr,
4149 .par = (const uint32_t[]){
4150 IBREAKENABLE,
4151 XTENSA_OPTION_DEBUG,
4152 },
4153 .op_flags = XTENSA_OP_PRIVILEGED,
4154 }, {
4155 .name = "rsr.icount",
4156 .translate = translate_rsr,
4157 .test_ill = test_ill_sr,
4158 .par = (const uint32_t[]){
4159 ICOUNT,
4160 XTENSA_OPTION_DEBUG,
4161 },
4162 .op_flags = XTENSA_OP_PRIVILEGED,
4163 }, {
4164 .name = "rsr.icountlevel",
4165 .translate = translate_rsr,
4166 .test_ill = test_ill_sr,
4167 .par = (const uint32_t[]){
4168 ICOUNTLEVEL,
4169 XTENSA_OPTION_DEBUG,
4170 },
4171 .op_flags = XTENSA_OP_PRIVILEGED,
4172 }, {
4173 .name = "rsr.intclear",
4174 .translate = translate_rsr,
4175 .test_ill = test_ill_sr,
4176 .par = (const uint32_t[]){
4177 INTCLEAR,
4178 XTENSA_OPTION_INTERRUPT,
4179 },
4180 .op_flags = XTENSA_OP_PRIVILEGED,
4181 }, {
4182 .name = "rsr.intenable",
4183 .translate = translate_rsr,
4184 .test_ill = test_ill_sr,
4185 .par = (const uint32_t[]){
4186 INTENABLE,
4187 XTENSA_OPTION_INTERRUPT,
4188 },
4189 .op_flags = XTENSA_OP_PRIVILEGED,
4190 }, {
4191 .name = "rsr.interrupt",
4192 .translate = translate_rsr_ccount,
4193 .test_ill = test_ill_sr,
4194 .par = (const uint32_t[]){
4195 INTSET,
4196 XTENSA_OPTION_INTERRUPT,
4197 },
4198 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4199 }, {
4200 .name = "rsr.intset",
4201 .translate = translate_rsr_ccount,
4202 .test_ill = test_ill_sr,
4203 .par = (const uint32_t[]){
4204 INTSET,
4205 XTENSA_OPTION_INTERRUPT,
4206 },
4207 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4208 }, {
4209 .name = "rsr.itlbcfg",
4210 .translate = translate_rsr,
4211 .test_ill = test_ill_sr,
4212 .par = (const uint32_t[]){
4213 ITLBCFG,
4214 XTENSA_OPTION_MMU,
4215 },
4216 .op_flags = XTENSA_OP_PRIVILEGED,
4217 }, {
4218 .name = "rsr.lbeg",
4219 .translate = translate_rsr,
4220 .test_ill = test_ill_sr,
4221 .par = (const uint32_t[]){
4222 LBEG,
4223 XTENSA_OPTION_LOOP,
4224 },
4225 }, {
4226 .name = "rsr.lcount",
4227 .translate = translate_rsr,
4228 .test_ill = test_ill_sr,
4229 .par = (const uint32_t[]){
4230 LCOUNT,
4231 XTENSA_OPTION_LOOP,
4232 },
4233 }, {
4234 .name = "rsr.lend",
4235 .translate = translate_rsr,
4236 .test_ill = test_ill_sr,
4237 .par = (const uint32_t[]){
4238 LEND,
4239 XTENSA_OPTION_LOOP,
4240 },
4241 }, {
4242 .name = "rsr.litbase",
4243 .translate = translate_rsr,
4244 .test_ill = test_ill_sr,
4245 .par = (const uint32_t[]){
4246 LITBASE,
4247 XTENSA_OPTION_EXTENDED_L32R,
4248 },
4249 }, {
4250 .name = "rsr.m0",
4251 .translate = translate_rsr,
4252 .test_ill = test_ill_sr,
4253 .par = (const uint32_t[]){
4254 MR,
4255 XTENSA_OPTION_MAC16,
4256 },
4257 }, {
4258 .name = "rsr.m1",
4259 .translate = translate_rsr,
4260 .test_ill = test_ill_sr,
4261 .par = (const uint32_t[]){
4262 MR + 1,
4263 XTENSA_OPTION_MAC16,
4264 },
4265 }, {
4266 .name = "rsr.m2",
4267 .translate = translate_rsr,
4268 .test_ill = test_ill_sr,
4269 .par = (const uint32_t[]){
4270 MR + 2,
4271 XTENSA_OPTION_MAC16,
4272 },
4273 }, {
4274 .name = "rsr.m3",
4275 .translate = translate_rsr,
4276 .test_ill = test_ill_sr,
4277 .par = (const uint32_t[]){
4278 MR + 3,
4279 XTENSA_OPTION_MAC16,
4280 },
4281 }, {
4282 .name = "rsr.memctl",
4283 .translate = translate_rsr,
4284 .par = (const uint32_t[]){MEMCTL},
4285 .op_flags = XTENSA_OP_PRIVILEGED,
4286 }, {
4287 .name = "rsr.mecr",
4288 .translate = translate_rsr,
4289 .test_ill = test_ill_sr,
4290 .par = (const uint32_t[]){
4291 MECR,
4292 XTENSA_OPTION_MEMORY_ECC_PARITY,
4293 },
4294 .op_flags = XTENSA_OP_PRIVILEGED,
4295 }, {
4296 .name = "rsr.mepc",
4297 .translate = translate_rsr,
4298 .test_ill = test_ill_sr,
4299 .par = (const uint32_t[]){
4300 MEPC,
4301 XTENSA_OPTION_MEMORY_ECC_PARITY,
4302 },
4303 .op_flags = XTENSA_OP_PRIVILEGED,
4304 }, {
4305 .name = "rsr.meps",
4306 .translate = translate_rsr,
4307 .test_ill = test_ill_sr,
4308 .par = (const uint32_t[]){
4309 MEPS,
4310 XTENSA_OPTION_MEMORY_ECC_PARITY,
4311 },
4312 .op_flags = XTENSA_OP_PRIVILEGED,
4313 }, {
4314 .name = "rsr.mesave",
4315 .translate = translate_rsr,
4316 .test_ill = test_ill_sr,
4317 .par = (const uint32_t[]){
4318 MESAVE,
4319 XTENSA_OPTION_MEMORY_ECC_PARITY,
4320 },
4321 .op_flags = XTENSA_OP_PRIVILEGED,
4322 }, {
4323 .name = "rsr.mesr",
4324 .translate = translate_rsr,
4325 .test_ill = test_ill_sr,
4326 .par = (const uint32_t[]){
4327 MESR,
4328 XTENSA_OPTION_MEMORY_ECC_PARITY,
4329 },
4330 .op_flags = XTENSA_OP_PRIVILEGED,
4331 }, {
4332 .name = "rsr.mevaddr",
4333 .translate = translate_rsr,
4334 .test_ill = test_ill_sr,
4335 .par = (const uint32_t[]){
4336 MESR,
4337 XTENSA_OPTION_MEMORY_ECC_PARITY,
4338 },
4339 .op_flags = XTENSA_OP_PRIVILEGED,
4340 }, {
4341 .name = "rsr.misc0",
4342 .translate = translate_rsr,
4343 .test_ill = test_ill_sr,
4344 .par = (const uint32_t[]){
4345 MISC,
4346 XTENSA_OPTION_MISC_SR,
4347 },
4348 .op_flags = XTENSA_OP_PRIVILEGED,
4349 }, {
4350 .name = "rsr.misc1",
4351 .translate = translate_rsr,
4352 .test_ill = test_ill_sr,
4353 .par = (const uint32_t[]){
4354 MISC + 1,
4355 XTENSA_OPTION_MISC_SR,
4356 },
4357 .op_flags = XTENSA_OP_PRIVILEGED,
4358 }, {
4359 .name = "rsr.misc2",
4360 .translate = translate_rsr,
4361 .test_ill = test_ill_sr,
4362 .par = (const uint32_t[]){
4363 MISC + 2,
4364 XTENSA_OPTION_MISC_SR,
4365 },
4366 .op_flags = XTENSA_OP_PRIVILEGED,
4367 }, {
4368 .name = "rsr.misc3",
4369 .translate = translate_rsr,
4370 .test_ill = test_ill_sr,
4371 .par = (const uint32_t[]){
4372 MISC + 3,
4373 XTENSA_OPTION_MISC_SR,
4374 },
4375 .op_flags = XTENSA_OP_PRIVILEGED,
4376 }, {
4377 .name = "rsr.mpucfg",
4378 .translate = translate_rsr,
4379 .test_ill = test_ill_sr,
4380 .par = (const uint32_t[]){
4381 MPUCFG,
4382 XTENSA_OPTION_MPU,
4383 },
4384 .op_flags = XTENSA_OP_PRIVILEGED,
4385 }, {
4386 .name = "rsr.mpuenb",
4387 .translate = translate_rsr,
4388 .test_ill = test_ill_sr,
4389 .par = (const uint32_t[]){
4390 MPUENB,
4391 XTENSA_OPTION_MPU,
4392 },
4393 .op_flags = XTENSA_OP_PRIVILEGED,
4394 }, {
4395 .name = "rsr.prefctl",
4396 .translate = translate_rsr,
4397 .par = (const uint32_t[]){PREFCTL},
4398 }, {
4399 .name = "rsr.prid",
4400 .translate = translate_rsr,
4401 .test_ill = test_ill_sr,
4402 .par = (const uint32_t[]){
4403 PRID,
4404 XTENSA_OPTION_PROCESSOR_ID,
4405 },
4406 .op_flags = XTENSA_OP_PRIVILEGED,
4407 }, {
4408 .name = "rsr.ps",
4409 .translate = translate_rsr,
4410 .test_ill = test_ill_sr,
4411 .par = (const uint32_t[]){
4412 PS,
4413 XTENSA_OPTION_EXCEPTION,
4414 },
4415 .op_flags = XTENSA_OP_PRIVILEGED,
4416 }, {
4417 .name = "rsr.ptevaddr",
4418 .translate = translate_rsr_ptevaddr,
4419 .test_ill = test_ill_sr,
4420 .par = (const uint32_t[]){
4421 PTEVADDR,
4422 XTENSA_OPTION_MMU,
4423 },
4424 .op_flags = XTENSA_OP_PRIVILEGED,
4425 }, {
4426 .name = "rsr.rasid",
4427 .translate = translate_rsr,
4428 .test_ill = test_ill_sr,
4429 .par = (const uint32_t[]){
4430 RASID,
4431 XTENSA_OPTION_MMU,
4432 },
4433 .op_flags = XTENSA_OP_PRIVILEGED,
4434 }, {
4435 .name = "rsr.sar",
4436 .translate = translate_rsr,
4437 .par = (const uint32_t[]){SAR},
4438 }, {
4439 .name = "rsr.scompare1",
4440 .translate = translate_rsr,
4441 .test_ill = test_ill_sr,
4442 .par = (const uint32_t[]){
4443 SCOMPARE1,
4444 XTENSA_OPTION_CONDITIONAL_STORE,
4445 },
4446 }, {
4447 .name = "rsr.vecbase",
4448 .translate = translate_rsr,
4449 .test_ill = test_ill_sr,
4450 .par = (const uint32_t[]){
4451 VECBASE,
4452 XTENSA_OPTION_RELOCATABLE_VECTOR,
4453 },
4454 .op_flags = XTENSA_OP_PRIVILEGED,
4455 }, {
4456 .name = "rsr.windowbase",
4457 .translate = translate_rsr,
4458 .test_ill = test_ill_sr,
4459 .par = (const uint32_t[]){
4460 WINDOW_BASE,
4461 XTENSA_OPTION_WINDOWED_REGISTER,
4462 },
4463 .op_flags = XTENSA_OP_PRIVILEGED,
4464 }, {
4465 .name = "rsr.windowstart",
4466 .translate = translate_rsr,
4467 .test_ill = test_ill_sr,
4468 .par = (const uint32_t[]){
4469 WINDOW_START,
4470 XTENSA_OPTION_WINDOWED_REGISTER,
4471 },
4472 .op_flags = XTENSA_OP_PRIVILEGED,
4473 }, {
4474 .name = "rsync",
4475 .translate = translate_nop,
4476 }, {
4477 .name = "rur.expstate",
4478 .translate = translate_rur,
4479 .par = (const uint32_t[]){EXPSTATE},
4480 }, {
4481 .name = "rur.fcr",
4482 .translate = translate_rur,
4483 .par = (const uint32_t[]){FCR},
4484 .coprocessor = 0x1,
4485 }, {
4486 .name = "rur.fsr",
4487 .translate = translate_rur,
4488 .par = (const uint32_t[]){FSR},
4489 .coprocessor = 0x1,
4490 }, {
4491 .name = "rur.threadptr",
4492 .translate = translate_rur,
4493 .par = (const uint32_t[]){THREADPTR},
4494 }, {
4495 .name = "s16i",
4496 .translate = translate_ldst,
4497 .par = (const uint32_t[]){MO_TEUW, false, true},
4498 .op_flags = XTENSA_OP_STORE,
4499 }, {
4500 .name = "s32c1i",
4501 .translate = translate_s32c1i,
4502 .op_flags = XTENSA_OP_LOAD | XTENSA_OP_STORE,
4503 }, {
4504 .name = "s32e",
4505 .translate = translate_s32e,
4506 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_STORE,
4507 }, {
4508 .name = (const char * const[]) {
4509 "s32i", "s32i.n", "s32nb", NULL,
4510 },
4511 .translate = translate_ldst,
4512 .par = (const uint32_t[]){MO_TEUL, false, true},
4513 .op_flags = XTENSA_OP_NAME_ARRAY | XTENSA_OP_STORE,
4514 }, {
4515 .name = "s32ri",
4516 .translate = translate_ldst,
4517 .par = (const uint32_t[]){MO_TEUL, true, true},
4518 .op_flags = XTENSA_OP_STORE,
4519 }, {
4520 .name = "s8i",
4521 .translate = translate_ldst,
4522 .par = (const uint32_t[]){MO_UB, false, true},
4523 .op_flags = XTENSA_OP_STORE,
4524 }, {
4525 .name = "salt",
4526 .translate = translate_salt,
4527 .par = (const uint32_t[]){TCG_COND_LT},
4528 }, {
4529 .name = "saltu",
4530 .translate = translate_salt,
4531 .par = (const uint32_t[]){TCG_COND_LTU},
4532 }, {
4533 .name = "setb_expstate",
4534 .translate = translate_setb_expstate,
4535 }, {
4536 .name = "sext",
4537 .translate = translate_sext,
4538 }, {
4539 .name = "simcall",
4540 .translate = translate_simcall,
4541 .test_ill = test_ill_simcall,
4542 .op_flags = XTENSA_OP_PRIVILEGED,
4543 }, {
4544 .name = "sll",
4545 .translate = translate_sll,
4546 }, {
4547 .name = "slli",
4548 .translate = translate_slli,
4549 }, {
4550 .name = "sra",
4551 .translate = translate_sra,
4552 }, {
4553 .name = "srai",
4554 .translate = translate_srai,
4555 }, {
4556 .name = "src",
4557 .translate = translate_src,
4558 }, {
4559 .name = "srl",
4560 .translate = translate_srl,
4561 }, {
4562 .name = "srli",
4563 .translate = translate_srli,
4564 }, {
4565 .name = "ssa8b",
4566 .translate = translate_ssa8b,
4567 }, {
4568 .name = "ssa8l",
4569 .translate = translate_ssa8l,
4570 }, {
4571 .name = "ssai",
4572 .translate = translate_ssai,
4573 }, {
4574 .name = "ssl",
4575 .translate = translate_ssl,
4576 }, {
4577 .name = "ssr",
4578 .translate = translate_ssr,
4579 }, {
4580 .name = "sub",
4581 .translate = translate_sub,
4582 }, {
4583 .name = "subx2",
4584 .translate = translate_subx,
4585 .par = (const uint32_t[]){1},
4586 }, {
4587 .name = "subx4",
4588 .translate = translate_subx,
4589 .par = (const uint32_t[]){2},
4590 }, {
4591 .name = "subx8",
4592 .translate = translate_subx,
4593 .par = (const uint32_t[]){3},
4594 }, {
4595 .name = "syscall",
4596 .op_flags = XTENSA_OP_SYSCALL,
4597 }, {
4598 .name = "umul.aa.hh",
4599 .translate = translate_mac16,
4600 .par = (const uint32_t[]){MAC16_UMUL, MAC16_HH, 0},
4601 }, {
4602 .name = "umul.aa.hl",
4603 .translate = translate_mac16,
4604 .par = (const uint32_t[]){MAC16_UMUL, MAC16_HL, 0},
4605 }, {
4606 .name = "umul.aa.lh",
4607 .translate = translate_mac16,
4608 .par = (const uint32_t[]){MAC16_UMUL, MAC16_LH, 0},
4609 }, {
4610 .name = "umul.aa.ll",
4611 .translate = translate_mac16,
4612 .par = (const uint32_t[]){MAC16_UMUL, MAC16_LL, 0},
4613 }, {
4614 .name = "waiti",
4615 .translate = translate_waiti,
4616 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4617 }, {
4618 .name = "wdtlb",
4619 .translate = translate_wtlb,
4620 .par = (const uint32_t[]){true},
4621 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
4622 }, {
4623 .name = "wer",
4624 .translate = translate_wer,
4625 .op_flags = XTENSA_OP_PRIVILEGED,
4626 }, {
4627 .name = "witlb",
4628 .translate = translate_wtlb,
4629 .par = (const uint32_t[]){false},
4630 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
4631 }, {
4632 .name = "wptlb",
4633 .translate = translate_wptlb,
4634 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
4635 }, {
4636 .name = "wrmsk_expstate",
4637 .translate = translate_wrmsk_expstate,
4638 }, {
4639 .name = "wsr.176",
4640 .op_flags = XTENSA_OP_ILL,
4641 }, {
4642 .name = "wsr.208",
4643 .op_flags = XTENSA_OP_ILL,
4644 }, {
4645 .name = "wsr.acchi",
4646 .translate = translate_wsr_acchi,
4647 .test_ill = test_ill_sr,
4648 .par = (const uint32_t[]){
4649 ACCHI,
4650 XTENSA_OPTION_MAC16,
4651 },
4652 }, {
4653 .name = "wsr.acclo",
4654 .translate = translate_wsr,
4655 .test_ill = test_ill_sr,
4656 .par = (const uint32_t[]){
4657 ACCLO,
4658 XTENSA_OPTION_MAC16,
4659 },
4660 }, {
4661 .name = "wsr.atomctl",
4662 .translate = translate_wsr_mask,
4663 .test_ill = test_ill_sr,
4664 .par = (const uint32_t[]){
4665 ATOMCTL,
4666 XTENSA_OPTION_ATOMCTL,
4667 0x3f,
4668 },
4669 .op_flags = XTENSA_OP_PRIVILEGED,
4670 }, {
4671 .name = "wsr.br",
4672 .translate = translate_wsr_mask,
4673 .test_ill = test_ill_sr,
4674 .par = (const uint32_t[]){
4675 BR,
4676 XTENSA_OPTION_BOOLEAN,
4677 0xffff,
4678 },
4679 }, {
4680 .name = "wsr.cacheadrdis",
4681 .translate = translate_wsr_mask,
4682 .test_ill = test_ill_sr,
4683 .par = (const uint32_t[]){
4684 CACHEADRDIS,
4685 XTENSA_OPTION_MPU,
4686 0xff,
4687 },
4688 .op_flags = XTENSA_OP_PRIVILEGED,
4689 }, {
4690 .name = "wsr.cacheattr",
4691 .translate = translate_wsr,
4692 .test_ill = test_ill_sr,
4693 .par = (const uint32_t[]){
4694 CACHEATTR,
4695 XTENSA_OPTION_CACHEATTR,
4696 },
4697 .op_flags = XTENSA_OP_PRIVILEGED,
4698 }, {
4699 .name = "wsr.ccompare0",
4700 .translate = translate_wsr_ccompare,
4701 .test_ill = test_ill_ccompare,
4702 .par = (const uint32_t[]){
4703 CCOMPARE,
4704 XTENSA_OPTION_TIMER_INTERRUPT,
4705 },
4706 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4707 }, {
4708 .name = "wsr.ccompare1",
4709 .translate = translate_wsr_ccompare,
4710 .test_ill = test_ill_ccompare,
4711 .par = (const uint32_t[]){
4712 CCOMPARE + 1,
4713 XTENSA_OPTION_TIMER_INTERRUPT,
4714 },
4715 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4716 }, {
4717 .name = "wsr.ccompare2",
4718 .translate = translate_wsr_ccompare,
4719 .test_ill = test_ill_ccompare,
4720 .par = (const uint32_t[]){
4721 CCOMPARE + 2,
4722 XTENSA_OPTION_TIMER_INTERRUPT,
4723 },
4724 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4725 }, {
4726 .name = "wsr.ccount",
4727 .translate = translate_wsr_ccount,
4728 .test_ill = test_ill_sr,
4729 .par = (const uint32_t[]){
4730 CCOUNT,
4731 XTENSA_OPTION_TIMER_INTERRUPT,
4732 },
4733 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4734 }, {
4735 .name = "wsr.configid0",
4736 .op_flags = XTENSA_OP_ILL,
4737 }, {
4738 .name = "wsr.configid1",
4739 .op_flags = XTENSA_OP_ILL,
4740 }, {
4741 .name = "wsr.cpenable",
4742 .translate = translate_wsr_mask,
4743 .test_ill = test_ill_sr,
4744 .par = (const uint32_t[]){
4745 CPENABLE,
4746 XTENSA_OPTION_COPROCESSOR,
4747 0xff,
4748 },
4749 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
4750 }, {
4751 .name = "wsr.dbreaka0",
4752 .translate = translate_wsr_dbreaka,
4753 .test_ill = test_ill_dbreak,
4754 .par = (const uint32_t[]){
4755 DBREAKA,
4756 XTENSA_OPTION_DEBUG,
4757 },
4758 .op_flags = XTENSA_OP_PRIVILEGED,
4759 }, {
4760 .name = "wsr.dbreaka1",
4761 .translate = translate_wsr_dbreaka,
4762 .test_ill = test_ill_dbreak,
4763 .par = (const uint32_t[]){
4764 DBREAKA + 1,
4765 XTENSA_OPTION_DEBUG,
4766 },
4767 .op_flags = XTENSA_OP_PRIVILEGED,
4768 }, {
4769 .name = "wsr.dbreakc0",
4770 .translate = translate_wsr_dbreakc,
4771 .test_ill = test_ill_dbreak,
4772 .par = (const uint32_t[]){
4773 DBREAKC,
4774 XTENSA_OPTION_DEBUG,
4775 },
4776 .op_flags = XTENSA_OP_PRIVILEGED,
4777 }, {
4778 .name = "wsr.dbreakc1",
4779 .translate = translate_wsr_dbreakc,
4780 .test_ill = test_ill_dbreak,
4781 .par = (const uint32_t[]){
4782 DBREAKC + 1,
4783 XTENSA_OPTION_DEBUG,
4784 },
4785 .op_flags = XTENSA_OP_PRIVILEGED,
4786 }, {
4787 .name = "wsr.ddr",
4788 .translate = translate_wsr,
4789 .test_ill = test_ill_sr,
4790 .par = (const uint32_t[]){
4791 DDR,
4792 XTENSA_OPTION_DEBUG,
4793 },
4794 .op_flags = XTENSA_OP_PRIVILEGED,
4795 }, {
4796 .name = "wsr.debugcause",
4797 .op_flags = XTENSA_OP_ILL,
4798 }, {
4799 .name = "wsr.depc",
4800 .translate = translate_wsr,
4801 .test_ill = test_ill_sr,
4802 .par = (const uint32_t[]){
4803 DEPC,
4804 XTENSA_OPTION_EXCEPTION,
4805 },
4806 .op_flags = XTENSA_OP_PRIVILEGED,
4807 }, {
4808 .name = "wsr.dtlbcfg",
4809 .translate = translate_wsr_mask,
4810 .test_ill = test_ill_sr,
4811 .par = (const uint32_t[]){
4812 DTLBCFG,
4813 XTENSA_OPTION_MMU,
4814 0x01130000,
4815 },
4816 .op_flags = XTENSA_OP_PRIVILEGED,
4817 }, {
4818 .name = "wsr.epc1",
4819 .translate = translate_wsr,
4820 .test_ill = test_ill_sr,
4821 .par = (const uint32_t[]){
4822 EPC1,
4823 XTENSA_OPTION_EXCEPTION,
4824 },
4825 .op_flags = XTENSA_OP_PRIVILEGED,
4826 }, {
4827 .name = "wsr.epc2",
4828 .translate = translate_wsr,
4829 .test_ill = test_ill_hpi,
4830 .par = (const uint32_t[]){
4831 EPC1 + 1,
4832 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4833 },
4834 .op_flags = XTENSA_OP_PRIVILEGED,
4835 }, {
4836 .name = "wsr.epc3",
4837 .translate = translate_wsr,
4838 .test_ill = test_ill_hpi,
4839 .par = (const uint32_t[]){
4840 EPC1 + 2,
4841 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4842 },
4843 .op_flags = XTENSA_OP_PRIVILEGED,
4844 }, {
4845 .name = "wsr.epc4",
4846 .translate = translate_wsr,
4847 .test_ill = test_ill_hpi,
4848 .par = (const uint32_t[]){
4849 EPC1 + 3,
4850 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4851 },
4852 .op_flags = XTENSA_OP_PRIVILEGED,
4853 }, {
4854 .name = "wsr.epc5",
4855 .translate = translate_wsr,
4856 .test_ill = test_ill_hpi,
4857 .par = (const uint32_t[]){
4858 EPC1 + 4,
4859 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4860 },
4861 .op_flags = XTENSA_OP_PRIVILEGED,
4862 }, {
4863 .name = "wsr.epc6",
4864 .translate = translate_wsr,
4865 .test_ill = test_ill_hpi,
4866 .par = (const uint32_t[]){
4867 EPC1 + 5,
4868 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4869 },
4870 .op_flags = XTENSA_OP_PRIVILEGED,
4871 }, {
4872 .name = "wsr.epc7",
4873 .translate = translate_wsr,
4874 .test_ill = test_ill_hpi,
4875 .par = (const uint32_t[]){
4876 EPC1 + 6,
4877 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4878 },
4879 .op_flags = XTENSA_OP_PRIVILEGED,
4880 }, {
4881 .name = "wsr.eps2",
4882 .translate = translate_wsr,
4883 .test_ill = test_ill_hpi,
4884 .par = (const uint32_t[]){
4885 EPS2,
4886 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4887 },
4888 .op_flags = XTENSA_OP_PRIVILEGED,
4889 }, {
4890 .name = "wsr.eps3",
4891 .translate = translate_wsr,
4892 .test_ill = test_ill_hpi,
4893 .par = (const uint32_t[]){
4894 EPS2 + 1,
4895 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4896 },
4897 .op_flags = XTENSA_OP_PRIVILEGED,
4898 }, {
4899 .name = "wsr.eps4",
4900 .translate = translate_wsr,
4901 .test_ill = test_ill_hpi,
4902 .par = (const uint32_t[]){
4903 EPS2 + 2,
4904 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4905 },
4906 .op_flags = XTENSA_OP_PRIVILEGED,
4907 }, {
4908 .name = "wsr.eps5",
4909 .translate = translate_wsr,
4910 .test_ill = test_ill_hpi,
4911 .par = (const uint32_t[]){
4912 EPS2 + 3,
4913 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4914 },
4915 .op_flags = XTENSA_OP_PRIVILEGED,
4916 }, {
4917 .name = "wsr.eps6",
4918 .translate = translate_wsr,
4919 .test_ill = test_ill_hpi,
4920 .par = (const uint32_t[]){
4921 EPS2 + 4,
4922 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4923 },
4924 .op_flags = XTENSA_OP_PRIVILEGED,
4925 }, {
4926 .name = "wsr.eps7",
4927 .translate = translate_wsr,
4928 .test_ill = test_ill_hpi,
4929 .par = (const uint32_t[]){
4930 EPS2 + 5,
4931 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4932 },
4933 .op_flags = XTENSA_OP_PRIVILEGED,
4934 }, {
4935 .name = "wsr.eraccess",
4936 .translate = translate_wsr_mask,
4937 .par = (const uint32_t[]){
4938 ERACCESS,
4939 0,
4940 0xffff,
4941 },
4942 .op_flags = XTENSA_OP_PRIVILEGED,
4943 }, {
4944 .name = "wsr.exccause",
4945 .translate = translate_wsr,
4946 .test_ill = test_ill_sr,
4947 .par = (const uint32_t[]){
4948 EXCCAUSE,
4949 XTENSA_OPTION_EXCEPTION,
4950 },
4951 .op_flags = XTENSA_OP_PRIVILEGED,
4952 }, {
4953 .name = "wsr.excsave1",
4954 .translate = translate_wsr,
4955 .test_ill = test_ill_sr,
4956 .par = (const uint32_t[]){
4957 EXCSAVE1,
4958 XTENSA_OPTION_EXCEPTION,
4959 },
4960 .op_flags = XTENSA_OP_PRIVILEGED,
4961 }, {
4962 .name = "wsr.excsave2",
4963 .translate = translate_wsr,
4964 .test_ill = test_ill_hpi,
4965 .par = (const uint32_t[]){
4966 EXCSAVE1 + 1,
4967 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4968 },
4969 .op_flags = XTENSA_OP_PRIVILEGED,
4970 }, {
4971 .name = "wsr.excsave3",
4972 .translate = translate_wsr,
4973 .test_ill = test_ill_hpi,
4974 .par = (const uint32_t[]){
4975 EXCSAVE1 + 2,
4976 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4977 },
4978 .op_flags = XTENSA_OP_PRIVILEGED,
4979 }, {
4980 .name = "wsr.excsave4",
4981 .translate = translate_wsr,
4982 .test_ill = test_ill_hpi,
4983 .par = (const uint32_t[]){
4984 EXCSAVE1 + 3,
4985 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4986 },
4987 .op_flags = XTENSA_OP_PRIVILEGED,
4988 }, {
4989 .name = "wsr.excsave5",
4990 .translate = translate_wsr,
4991 .test_ill = test_ill_hpi,
4992 .par = (const uint32_t[]){
4993 EXCSAVE1 + 4,
4994 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4995 },
4996 .op_flags = XTENSA_OP_PRIVILEGED,
4997 }, {
4998 .name = "wsr.excsave6",
4999 .translate = translate_wsr,
5000 .test_ill = test_ill_hpi,
5001 .par = (const uint32_t[]){
5002 EXCSAVE1 + 5,
5003 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5004 },
5005 .op_flags = XTENSA_OP_PRIVILEGED,
5006 }, {
5007 .name = "wsr.excsave7",
5008 .translate = translate_wsr,
5009 .test_ill = test_ill_hpi,
5010 .par = (const uint32_t[]){
5011 EXCSAVE1 + 6,
5012 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5013 },
5014 .op_flags = XTENSA_OP_PRIVILEGED,
5015 }, {
5016 .name = "wsr.excvaddr",
5017 .translate = translate_wsr,
5018 .test_ill = test_ill_sr,
5019 .par = (const uint32_t[]){
5020 EXCVADDR,
5021 XTENSA_OPTION_EXCEPTION,
5022 },
5023 .op_flags = XTENSA_OP_PRIVILEGED,
5024 }, {
5025 .name = "wsr.ibreaka0",
5026 .translate = translate_wsr_ibreaka,
5027 .test_ill = test_ill_ibreak,
5028 .par = (const uint32_t[]){
5029 IBREAKA,
5030 XTENSA_OPTION_DEBUG,
5031 },
5032 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5033 }, {
5034 .name = "wsr.ibreaka1",
5035 .translate = translate_wsr_ibreaka,
5036 .test_ill = test_ill_ibreak,
5037 .par = (const uint32_t[]){
5038 IBREAKA + 1,
5039 XTENSA_OPTION_DEBUG,
5040 },
5041 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5042 }, {
5043 .name = "wsr.ibreakenable",
5044 .translate = translate_wsr_ibreakenable,
5045 .test_ill = test_ill_sr,
5046 .par = (const uint32_t[]){
5047 IBREAKENABLE,
5048 XTENSA_OPTION_DEBUG,
5049 },
5050 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5051 }, {
5052 .name = "wsr.icount",
5053 .translate = translate_wsr_icount,
5054 .test_ill = test_ill_sr,
5055 .par = (const uint32_t[]){
5056 ICOUNT,
5057 XTENSA_OPTION_DEBUG,
5058 },
5059 .op_flags = XTENSA_OP_PRIVILEGED,
5060 }, {
5061 .name = "wsr.icountlevel",
5062 .translate = translate_wsr_mask,
5063 .test_ill = test_ill_sr,
5064 .par = (const uint32_t[]){
5065 ICOUNTLEVEL,
5066 XTENSA_OPTION_DEBUG,
5067 0xf,
5068 },
5069 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
5070 }, {
5071 .name = "wsr.intclear",
5072 .translate = translate_wsr_intclear,
5073 .test_ill = test_ill_sr,
5074 .par = (const uint32_t[]){
5075 INTCLEAR,
5076 XTENSA_OPTION_INTERRUPT,
5077 },
5078 .op_flags =
5079 XTENSA_OP_PRIVILEGED |
5080 XTENSA_OP_EXIT_TB_0 |
5081 XTENSA_OP_CHECK_INTERRUPTS,
5082 }, {
5083 .name = "wsr.intenable",
5084 .translate = translate_wsr,
5085 .test_ill = test_ill_sr,
5086 .par = (const uint32_t[]){
5087 INTENABLE,
5088 XTENSA_OPTION_INTERRUPT,
5089 },
5090 .op_flags =
5091 XTENSA_OP_PRIVILEGED |
5092 XTENSA_OP_EXIT_TB_0 |
5093 XTENSA_OP_CHECK_INTERRUPTS,
5094 }, {
5095 .name = "wsr.interrupt",
5096 .translate = translate_wsr,
5097 .test_ill = test_ill_sr,
5098 .par = (const uint32_t[]){
5099 INTSET,
5100 XTENSA_OPTION_INTERRUPT,
5101 },
5102 .op_flags =
5103 XTENSA_OP_PRIVILEGED |
5104 XTENSA_OP_EXIT_TB_0 |
5105 XTENSA_OP_CHECK_INTERRUPTS,
5106 }, {
5107 .name = "wsr.intset",
5108 .translate = translate_wsr_intset,
5109 .test_ill = test_ill_sr,
5110 .par = (const uint32_t[]){
5111 INTSET,
5112 XTENSA_OPTION_INTERRUPT,
5113 },
5114 .op_flags =
5115 XTENSA_OP_PRIVILEGED |
5116 XTENSA_OP_EXIT_TB_0 |
5117 XTENSA_OP_CHECK_INTERRUPTS,
5118 }, {
5119 .name = "wsr.itlbcfg",
5120 .translate = translate_wsr_mask,
5121 .test_ill = test_ill_sr,
5122 .par = (const uint32_t[]){
5123 ITLBCFG,
5124 XTENSA_OPTION_MMU,
5125 0x01130000,
5126 },
5127 .op_flags = XTENSA_OP_PRIVILEGED,
5128 }, {
5129 .name = "wsr.lbeg",
5130 .translate = translate_wsr,
5131 .test_ill = test_ill_sr,
5132 .par = (const uint32_t[]){
5133 LBEG,
5134 XTENSA_OPTION_LOOP,
5135 },
5136 .op_flags = XTENSA_OP_EXIT_TB_M1,
5137 }, {
5138 .name = "wsr.lcount",
5139 .translate = translate_wsr,
5140 .test_ill = test_ill_sr,
5141 .par = (const uint32_t[]){
5142 LCOUNT,
5143 XTENSA_OPTION_LOOP,
5144 },
5145 }, {
5146 .name = "wsr.lend",
5147 .translate = translate_wsr,
5148 .test_ill = test_ill_sr,
5149 .par = (const uint32_t[]){
5150 LEND,
5151 XTENSA_OPTION_LOOP,
5152 },
5153 .op_flags = XTENSA_OP_EXIT_TB_M1,
5154 }, {
5155 .name = "wsr.litbase",
5156 .translate = translate_wsr_mask,
5157 .test_ill = test_ill_sr,
5158 .par = (const uint32_t[]){
5159 LITBASE,
5160 XTENSA_OPTION_EXTENDED_L32R,
5161 0xfffff001,
5162 },
5163 .op_flags = XTENSA_OP_EXIT_TB_M1,
5164 }, {
5165 .name = "wsr.m0",
5166 .translate = translate_wsr,
5167 .test_ill = test_ill_sr,
5168 .par = (const uint32_t[]){
5169 MR,
5170 XTENSA_OPTION_MAC16,
5171 },
5172 }, {
5173 .name = "wsr.m1",
5174 .translate = translate_wsr,
5175 .test_ill = test_ill_sr,
5176 .par = (const uint32_t[]){
5177 MR + 1,
5178 XTENSA_OPTION_MAC16,
5179 },
5180 }, {
5181 .name = "wsr.m2",
5182 .translate = translate_wsr,
5183 .test_ill = test_ill_sr,
5184 .par = (const uint32_t[]){
5185 MR + 2,
5186 XTENSA_OPTION_MAC16,
5187 },
5188 }, {
5189 .name = "wsr.m3",
5190 .translate = translate_wsr,
5191 .test_ill = test_ill_sr,
5192 .par = (const uint32_t[]){
5193 MR + 3,
5194 XTENSA_OPTION_MAC16,
5195 },
5196 }, {
5197 .name = "wsr.memctl",
5198 .translate = translate_wsr_memctl,
5199 .par = (const uint32_t[]){MEMCTL},
5200 .op_flags = XTENSA_OP_PRIVILEGED,
5201 }, {
5202 .name = "wsr.mecr",
5203 .translate = translate_wsr,
5204 .test_ill = test_ill_sr,
5205 .par = (const uint32_t[]){
5206 MECR,
5207 XTENSA_OPTION_MEMORY_ECC_PARITY,
5208 },
5209 .op_flags = XTENSA_OP_PRIVILEGED,
5210 }, {
5211 .name = "wsr.mepc",
5212 .translate = translate_wsr,
5213 .test_ill = test_ill_sr,
5214 .par = (const uint32_t[]){
5215 MEPC,
5216 XTENSA_OPTION_MEMORY_ECC_PARITY,
5217 },
5218 .op_flags = XTENSA_OP_PRIVILEGED,
5219 }, {
5220 .name = "wsr.meps",
5221 .translate = translate_wsr,
5222 .test_ill = test_ill_sr,
5223 .par = (const uint32_t[]){
5224 MEPS,
5225 XTENSA_OPTION_MEMORY_ECC_PARITY,
5226 },
5227 .op_flags = XTENSA_OP_PRIVILEGED,
5228 }, {
5229 .name = "wsr.mesave",
5230 .translate = translate_wsr,
5231 .test_ill = test_ill_sr,
5232 .par = (const uint32_t[]){
5233 MESAVE,
5234 XTENSA_OPTION_MEMORY_ECC_PARITY,
5235 },
5236 .op_flags = XTENSA_OP_PRIVILEGED,
5237 }, {
5238 .name = "wsr.mesr",
5239 .translate = translate_wsr,
5240 .test_ill = test_ill_sr,
5241 .par = (const uint32_t[]){
5242 MESR,
5243 XTENSA_OPTION_MEMORY_ECC_PARITY,
5244 },
5245 .op_flags = XTENSA_OP_PRIVILEGED,
5246 }, {
5247 .name = "wsr.mevaddr",
5248 .translate = translate_wsr,
5249 .test_ill = test_ill_sr,
5250 .par = (const uint32_t[]){
5251 MESR,
5252 XTENSA_OPTION_MEMORY_ECC_PARITY,
5253 },
5254 .op_flags = XTENSA_OP_PRIVILEGED,
5255 }, {
5256 .name = "wsr.misc0",
5257 .translate = translate_wsr,
5258 .test_ill = test_ill_sr,
5259 .par = (const uint32_t[]){
5260 MISC,
5261 XTENSA_OPTION_MISC_SR,
5262 },
5263 .op_flags = XTENSA_OP_PRIVILEGED,
5264 }, {
5265 .name = "wsr.misc1",
5266 .translate = translate_wsr,
5267 .test_ill = test_ill_sr,
5268 .par = (const uint32_t[]){
5269 MISC + 1,
5270 XTENSA_OPTION_MISC_SR,
5271 },
5272 .op_flags = XTENSA_OP_PRIVILEGED,
5273 }, {
5274 .name = "wsr.misc2",
5275 .translate = translate_wsr,
5276 .test_ill = test_ill_sr,
5277 .par = (const uint32_t[]){
5278 MISC + 2,
5279 XTENSA_OPTION_MISC_SR,
5280 },
5281 .op_flags = XTENSA_OP_PRIVILEGED,
5282 }, {
5283 .name = "wsr.misc3",
5284 .translate = translate_wsr,
5285 .test_ill = test_ill_sr,
5286 .par = (const uint32_t[]){
5287 MISC + 3,
5288 XTENSA_OPTION_MISC_SR,
5289 },
5290 .op_flags = XTENSA_OP_PRIVILEGED,
5291 }, {
5292 .name = "wsr.mmid",
5293 .translate = translate_wsr,
5294 .test_ill = test_ill_sr,
5295 .par = (const uint32_t[]){
5296 MMID,
5297 XTENSA_OPTION_TRACE_PORT,
5298 },
5299 .op_flags = XTENSA_OP_PRIVILEGED,
5300 }, {
5301 .name = "wsr.mpuenb",
5302 .translate = translate_wsr_mpuenb,
5303 .test_ill = test_ill_sr,
5304 .par = (const uint32_t[]){
5305 MPUENB,
5306 XTENSA_OPTION_MPU,
5307 },
5308 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
5309 }, {
5310 .name = "wsr.prefctl",
5311 .translate = translate_wsr,
5312 .par = (const uint32_t[]){PREFCTL},
5313 }, {
5314 .name = "wsr.prid",
5315 .op_flags = XTENSA_OP_ILL,
5316 }, {
5317 .name = "wsr.ps",
5318 .translate = translate_wsr_ps,
5319 .test_ill = test_ill_sr,
5320 .par = (const uint32_t[]){
5321 PS,
5322 XTENSA_OPTION_EXCEPTION,
5323 },
5324 .op_flags =
5325 XTENSA_OP_PRIVILEGED |
5326 XTENSA_OP_EXIT_TB_M1 |
5327 XTENSA_OP_CHECK_INTERRUPTS,
5328 }, {
5329 .name = "wsr.ptevaddr",
5330 .translate = translate_wsr_mask,
5331 .test_ill = test_ill_sr,
5332 .par = (const uint32_t[]){
5333 PTEVADDR,
5334 XTENSA_OPTION_MMU,
5335 0xffc00000,
5336 },
5337 .op_flags = XTENSA_OP_PRIVILEGED,
5338 }, {
5339 .name = "wsr.rasid",
5340 .translate = translate_wsr_rasid,
5341 .test_ill = test_ill_sr,
5342 .par = (const uint32_t[]){
5343 RASID,
5344 XTENSA_OPTION_MMU,
5345 },
5346 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
5347 }, {
5348 .name = "wsr.sar",
5349 .translate = translate_wsr_sar,
5350 .par = (const uint32_t[]){SAR},
5351 }, {
5352 .name = "wsr.scompare1",
5353 .translate = translate_wsr,
5354 .test_ill = test_ill_sr,
5355 .par = (const uint32_t[]){
5356 SCOMPARE1,
5357 XTENSA_OPTION_CONDITIONAL_STORE,
5358 },
5359 }, {
5360 .name = "wsr.vecbase",
5361 .translate = translate_wsr,
5362 .test_ill = test_ill_sr,
5363 .par = (const uint32_t[]){
5364 VECBASE,
5365 XTENSA_OPTION_RELOCATABLE_VECTOR,
5366 },
5367 .op_flags = XTENSA_OP_PRIVILEGED,
5368 }, {
5369 .name = "wsr.windowbase",
5370 .translate = translate_wsr_windowbase,
5371 .test_ill = test_ill_sr,
5372 .par = (const uint32_t[]){
5373 WINDOW_BASE,
5374 XTENSA_OPTION_WINDOWED_REGISTER,
5375 },
5376 .op_flags = XTENSA_OP_PRIVILEGED |
5377 XTENSA_OP_EXIT_TB_M1 |
5378 XTENSA_OP_SYNC_REGISTER_WINDOW,
5379 }, {
5380 .name = "wsr.windowstart",
5381 .translate = translate_wsr_windowstart,
5382 .test_ill = test_ill_sr,
5383 .par = (const uint32_t[]){
5384 WINDOW_START,
5385 XTENSA_OPTION_WINDOWED_REGISTER,
5386 },
5387 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
5388 }, {
5389 .name = "wur.expstate",
5390 .translate = translate_wur,
5391 .par = (const uint32_t[]){EXPSTATE},
5392 }, {
5393 .name = "wur.fcr",
5394 .translate = translate_wur_fcr,
5395 .par = (const uint32_t[]){FCR},
5396 .coprocessor = 0x1,
5397 }, {
5398 .name = "wur.fsr",
5399 .translate = translate_wur_fsr,
5400 .par = (const uint32_t[]){FSR},
5401 .coprocessor = 0x1,
5402 }, {
5403 .name = "wur.threadptr",
5404 .translate = translate_wur,
5405 .par = (const uint32_t[]){THREADPTR},
5406 }, {
5407 .name = "xor",
5408 .translate = translate_xor,
5409 }, {
5410 .name = "xorb",
5411 .translate = translate_boolean,
5412 .par = (const uint32_t[]){BOOLEAN_XOR},
5413 }, {
5414 .name = "xsr.176",
5415 .op_flags = XTENSA_OP_ILL,
5416 }, {
5417 .name = "xsr.208",
5418 .op_flags = XTENSA_OP_ILL,
5419 }, {
5420 .name = "xsr.acchi",
5421 .translate = translate_xsr_acchi,
5422 .test_ill = test_ill_sr,
5423 .par = (const uint32_t[]){
5424 ACCHI,
5425 XTENSA_OPTION_MAC16,
5426 },
5427 }, {
5428 .name = "xsr.acclo",
5429 .translate = translate_xsr,
5430 .test_ill = test_ill_sr,
5431 .par = (const uint32_t[]){
5432 ACCLO,
5433 XTENSA_OPTION_MAC16,
5434 },
5435 }, {
5436 .name = "xsr.atomctl",
5437 .translate = translate_xsr_mask,
5438 .test_ill = test_ill_sr,
5439 .par = (const uint32_t[]){
5440 ATOMCTL,
5441 XTENSA_OPTION_ATOMCTL,
5442 0x3f,
5443 },
5444 .op_flags = XTENSA_OP_PRIVILEGED,
5445 }, {
5446 .name = "xsr.br",
5447 .translate = translate_xsr_mask,
5448 .test_ill = test_ill_sr,
5449 .par = (const uint32_t[]){
5450 BR,
5451 XTENSA_OPTION_BOOLEAN,
5452 0xffff,
5453 },
5454 }, {
5455 .name = "xsr.cacheadrdis",
5456 .translate = translate_xsr_mask,
5457 .test_ill = test_ill_sr,
5458 .par = (const uint32_t[]){
5459 CACHEADRDIS,
5460 XTENSA_OPTION_MPU,
5461 0xff,
5462 },
5463 .op_flags = XTENSA_OP_PRIVILEGED,
5464 }, {
5465 .name = "xsr.cacheattr",
5466 .translate = translate_xsr,
5467 .test_ill = test_ill_sr,
5468 .par = (const uint32_t[]){
5469 CACHEATTR,
5470 XTENSA_OPTION_CACHEATTR,
5471 },
5472 .op_flags = XTENSA_OP_PRIVILEGED,
5473 }, {
5474 .name = "xsr.ccompare0",
5475 .translate = translate_xsr_ccompare,
5476 .test_ill = test_ill_ccompare,
5477 .par = (const uint32_t[]){
5478 CCOMPARE,
5479 XTENSA_OPTION_TIMER_INTERRUPT,
5480 },
5481 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5482 }, {
5483 .name = "xsr.ccompare1",
5484 .translate = translate_xsr_ccompare,
5485 .test_ill = test_ill_ccompare,
5486 .par = (const uint32_t[]){
5487 CCOMPARE + 1,
5488 XTENSA_OPTION_TIMER_INTERRUPT,
5489 },
5490 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5491 }, {
5492 .name = "xsr.ccompare2",
5493 .translate = translate_xsr_ccompare,
5494 .test_ill = test_ill_ccompare,
5495 .par = (const uint32_t[]){
5496 CCOMPARE + 2,
5497 XTENSA_OPTION_TIMER_INTERRUPT,
5498 },
5499 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5500 }, {
5501 .name = "xsr.ccount",
5502 .translate = translate_xsr_ccount,
5503 .test_ill = test_ill_sr,
5504 .par = (const uint32_t[]){
5505 CCOUNT,
5506 XTENSA_OPTION_TIMER_INTERRUPT,
5507 },
5508 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5509 }, {
5510 .name = "xsr.configid0",
5511 .op_flags = XTENSA_OP_ILL,
5512 }, {
5513 .name = "xsr.configid1",
5514 .op_flags = XTENSA_OP_ILL,
5515 }, {
5516 .name = "xsr.cpenable",
5517 .translate = translate_xsr_mask,
5518 .test_ill = test_ill_sr,
5519 .par = (const uint32_t[]){
5520 CPENABLE,
5521 XTENSA_OPTION_COPROCESSOR,
5522 0xff,
5523 },
5524 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
5525 }, {
5526 .name = "xsr.dbreaka0",
5527 .translate = translate_xsr_dbreaka,
5528 .test_ill = test_ill_dbreak,
5529 .par = (const uint32_t[]){
5530 DBREAKA,
5531 XTENSA_OPTION_DEBUG,
5532 },
5533 .op_flags = XTENSA_OP_PRIVILEGED,
5534 }, {
5535 .name = "xsr.dbreaka1",
5536 .translate = translate_xsr_dbreaka,
5537 .test_ill = test_ill_dbreak,
5538 .par = (const uint32_t[]){
5539 DBREAKA + 1,
5540 XTENSA_OPTION_DEBUG,
5541 },
5542 .op_flags = XTENSA_OP_PRIVILEGED,
5543 }, {
5544 .name = "xsr.dbreakc0",
5545 .translate = translate_xsr_dbreakc,
5546 .test_ill = test_ill_dbreak,
5547 .par = (const uint32_t[]){
5548 DBREAKC,
5549 XTENSA_OPTION_DEBUG,
5550 },
5551 .op_flags = XTENSA_OP_PRIVILEGED,
5552 }, {
5553 .name = "xsr.dbreakc1",
5554 .translate = translate_xsr_dbreakc,
5555 .test_ill = test_ill_dbreak,
5556 .par = (const uint32_t[]){
5557 DBREAKC + 1,
5558 XTENSA_OPTION_DEBUG,
5559 },
5560 .op_flags = XTENSA_OP_PRIVILEGED,
5561 }, {
5562 .name = "xsr.ddr",
5563 .translate = translate_xsr,
5564 .test_ill = test_ill_sr,
5565 .par = (const uint32_t[]){
5566 DDR,
5567 XTENSA_OPTION_DEBUG,
5568 },
5569 .op_flags = XTENSA_OP_PRIVILEGED,
5570 }, {
5571 .name = "xsr.debugcause",
5572 .op_flags = XTENSA_OP_ILL,
5573 }, {
5574 .name = "xsr.depc",
5575 .translate = translate_xsr,
5576 .test_ill = test_ill_sr,
5577 .par = (const uint32_t[]){
5578 DEPC,
5579 XTENSA_OPTION_EXCEPTION,
5580 },
5581 .op_flags = XTENSA_OP_PRIVILEGED,
5582 }, {
5583 .name = "xsr.dtlbcfg",
5584 .translate = translate_xsr_mask,
5585 .test_ill = test_ill_sr,
5586 .par = (const uint32_t[]){
5587 DTLBCFG,
5588 XTENSA_OPTION_MMU,
5589 0x01130000,
5590 },
5591 .op_flags = XTENSA_OP_PRIVILEGED,
5592 }, {
5593 .name = "xsr.epc1",
5594 .translate = translate_xsr,
5595 .test_ill = test_ill_sr,
5596 .par = (const uint32_t[]){
5597 EPC1,
5598 XTENSA_OPTION_EXCEPTION,
5599 },
5600 .op_flags = XTENSA_OP_PRIVILEGED,
5601 }, {
5602 .name = "xsr.epc2",
5603 .translate = translate_xsr,
5604 .test_ill = test_ill_hpi,
5605 .par = (const uint32_t[]){
5606 EPC1 + 1,
5607 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5608 },
5609 .op_flags = XTENSA_OP_PRIVILEGED,
5610 }, {
5611 .name = "xsr.epc3",
5612 .translate = translate_xsr,
5613 .test_ill = test_ill_hpi,
5614 .par = (const uint32_t[]){
5615 EPC1 + 2,
5616 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5617 },
5618 .op_flags = XTENSA_OP_PRIVILEGED,
5619 }, {
5620 .name = "xsr.epc4",
5621 .translate = translate_xsr,
5622 .test_ill = test_ill_hpi,
5623 .par = (const uint32_t[]){
5624 EPC1 + 3,
5625 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5626 },
5627 .op_flags = XTENSA_OP_PRIVILEGED,
5628 }, {
5629 .name = "xsr.epc5",
5630 .translate = translate_xsr,
5631 .test_ill = test_ill_hpi,
5632 .par = (const uint32_t[]){
5633 EPC1 + 4,
5634 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5635 },
5636 .op_flags = XTENSA_OP_PRIVILEGED,
5637 }, {
5638 .name = "xsr.epc6",
5639 .translate = translate_xsr,
5640 .test_ill = test_ill_hpi,
5641 .par = (const uint32_t[]){
5642 EPC1 + 5,
5643 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5644 },
5645 .op_flags = XTENSA_OP_PRIVILEGED,
5646 }, {
5647 .name = "xsr.epc7",
5648 .translate = translate_xsr,
5649 .test_ill = test_ill_hpi,
5650 .par = (const uint32_t[]){
5651 EPC1 + 6,
5652 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5653 },
5654 .op_flags = XTENSA_OP_PRIVILEGED,
5655 }, {
5656 .name = "xsr.eps2",
5657 .translate = translate_xsr,
5658 .test_ill = test_ill_hpi,
5659 .par = (const uint32_t[]){
5660 EPS2,
5661 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5662 },
5663 .op_flags = XTENSA_OP_PRIVILEGED,
5664 }, {
5665 .name = "xsr.eps3",
5666 .translate = translate_xsr,
5667 .test_ill = test_ill_hpi,
5668 .par = (const uint32_t[]){
5669 EPS2 + 1,
5670 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5671 },
5672 .op_flags = XTENSA_OP_PRIVILEGED,
5673 }, {
5674 .name = "xsr.eps4",
5675 .translate = translate_xsr,
5676 .test_ill = test_ill_hpi,
5677 .par = (const uint32_t[]){
5678 EPS2 + 2,
5679 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5680 },
5681 .op_flags = XTENSA_OP_PRIVILEGED,
5682 }, {
5683 .name = "xsr.eps5",
5684 .translate = translate_xsr,
5685 .test_ill = test_ill_hpi,
5686 .par = (const uint32_t[]){
5687 EPS2 + 3,
5688 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5689 },
5690 .op_flags = XTENSA_OP_PRIVILEGED,
5691 }, {
5692 .name = "xsr.eps6",
5693 .translate = translate_xsr,
5694 .test_ill = test_ill_hpi,
5695 .par = (const uint32_t[]){
5696 EPS2 + 4,
5697 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5698 },
5699 .op_flags = XTENSA_OP_PRIVILEGED,
5700 }, {
5701 .name = "xsr.eps7",
5702 .translate = translate_xsr,
5703 .test_ill = test_ill_hpi,
5704 .par = (const uint32_t[]){
5705 EPS2 + 5,
5706 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5707 },
5708 .op_flags = XTENSA_OP_PRIVILEGED,
5709 }, {
5710 .name = "xsr.eraccess",
5711 .translate = translate_xsr_mask,
5712 .par = (const uint32_t[]){
5713 ERACCESS,
5714 0,
5715 0xffff,
5716 },
5717 .op_flags = XTENSA_OP_PRIVILEGED,
5718 }, {
5719 .name = "xsr.exccause",
5720 .translate = translate_xsr,
5721 .test_ill = test_ill_sr,
5722 .par = (const uint32_t[]){
5723 EXCCAUSE,
5724 XTENSA_OPTION_EXCEPTION,
5725 },
5726 .op_flags = XTENSA_OP_PRIVILEGED,
5727 }, {
5728 .name = "xsr.excsave1",
5729 .translate = translate_xsr,
5730 .test_ill = test_ill_sr,
5731 .par = (const uint32_t[]){
5732 EXCSAVE1,
5733 XTENSA_OPTION_EXCEPTION,
5734 },
5735 .op_flags = XTENSA_OP_PRIVILEGED,
5736 }, {
5737 .name = "xsr.excsave2",
5738 .translate = translate_xsr,
5739 .test_ill = test_ill_hpi,
5740 .par = (const uint32_t[]){
5741 EXCSAVE1 + 1,
5742 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5743 },
5744 .op_flags = XTENSA_OP_PRIVILEGED,
5745 }, {
5746 .name = "xsr.excsave3",
5747 .translate = translate_xsr,
5748 .test_ill = test_ill_hpi,
5749 .par = (const uint32_t[]){
5750 EXCSAVE1 + 2,
5751 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5752 },
5753 .op_flags = XTENSA_OP_PRIVILEGED,
5754 }, {
5755 .name = "xsr.excsave4",
5756 .translate = translate_xsr,
5757 .test_ill = test_ill_hpi,
5758 .par = (const uint32_t[]){
5759 EXCSAVE1 + 3,
5760 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5761 },
5762 .op_flags = XTENSA_OP_PRIVILEGED,
5763 }, {
5764 .name = "xsr.excsave5",
5765 .translate = translate_xsr,
5766 .test_ill = test_ill_hpi,
5767 .par = (const uint32_t[]){
5768 EXCSAVE1 + 4,
5769 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5770 },
5771 .op_flags = XTENSA_OP_PRIVILEGED,
5772 }, {
5773 .name = "xsr.excsave6",
5774 .translate = translate_xsr,
5775 .test_ill = test_ill_hpi,
5776 .par = (const uint32_t[]){
5777 EXCSAVE1 + 5,
5778 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5779 },
5780 .op_flags = XTENSA_OP_PRIVILEGED,
5781 }, {
5782 .name = "xsr.excsave7",
5783 .translate = translate_xsr,
5784 .test_ill = test_ill_hpi,
5785 .par = (const uint32_t[]){
5786 EXCSAVE1 + 6,
5787 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5788 },
5789 .op_flags = XTENSA_OP_PRIVILEGED,
5790 }, {
5791 .name = "xsr.excvaddr",
5792 .translate = translate_xsr,
5793 .test_ill = test_ill_sr,
5794 .par = (const uint32_t[]){
5795 EXCVADDR,
5796 XTENSA_OPTION_EXCEPTION,
5797 },
5798 .op_flags = XTENSA_OP_PRIVILEGED,
5799 }, {
5800 .name = "xsr.ibreaka0",
5801 .translate = translate_xsr_ibreaka,
5802 .test_ill = test_ill_ibreak,
5803 .par = (const uint32_t[]){
5804 IBREAKA,
5805 XTENSA_OPTION_DEBUG,
5806 },
5807 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5808 }, {
5809 .name = "xsr.ibreaka1",
5810 .translate = translate_xsr_ibreaka,
5811 .test_ill = test_ill_ibreak,
5812 .par = (const uint32_t[]){
5813 IBREAKA + 1,
5814 XTENSA_OPTION_DEBUG,
5815 },
5816 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5817 }, {
5818 .name = "xsr.ibreakenable",
5819 .translate = translate_xsr_ibreakenable,
5820 .test_ill = test_ill_sr,
5821 .par = (const uint32_t[]){
5822 IBREAKENABLE,
5823 XTENSA_OPTION_DEBUG,
5824 },
5825 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5826 }, {
5827 .name = "xsr.icount",
5828 .translate = translate_xsr_icount,
5829 .test_ill = test_ill_sr,
5830 .par = (const uint32_t[]){
5831 ICOUNT,
5832 XTENSA_OPTION_DEBUG,
5833 },
5834 .op_flags = XTENSA_OP_PRIVILEGED,
5835 }, {
5836 .name = "xsr.icountlevel",
5837 .translate = translate_xsr_mask,
5838 .test_ill = test_ill_sr,
5839 .par = (const uint32_t[]){
5840 ICOUNTLEVEL,
5841 XTENSA_OPTION_DEBUG,
5842 0xf,
5843 },
5844 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
5845 }, {
5846 .name = "xsr.intclear",
5847 .op_flags = XTENSA_OP_ILL,
5848 }, {
5849 .name = "xsr.intenable",
5850 .translate = translate_xsr,
5851 .test_ill = test_ill_sr,
5852 .par = (const uint32_t[]){
5853 INTENABLE,
5854 XTENSA_OPTION_INTERRUPT,
5855 },
5856 .op_flags =
5857 XTENSA_OP_PRIVILEGED |
5858 XTENSA_OP_EXIT_TB_0 |
5859 XTENSA_OP_CHECK_INTERRUPTS,
5860 }, {
5861 .name = "xsr.interrupt",
5862 .op_flags = XTENSA_OP_ILL,
5863 }, {
5864 .name = "xsr.intset",
5865 .op_flags = XTENSA_OP_ILL,
5866 }, {
5867 .name = "xsr.itlbcfg",
5868 .translate = translate_xsr_mask,
5869 .test_ill = test_ill_sr,
5870 .par = (const uint32_t[]){
5871 ITLBCFG,
5872 XTENSA_OPTION_MMU,
5873 0x01130000,
5874 },
5875 .op_flags = XTENSA_OP_PRIVILEGED,
5876 }, {
5877 .name = "xsr.lbeg",
5878 .translate = translate_xsr,
5879 .test_ill = test_ill_sr,
5880 .par = (const uint32_t[]){
5881 LBEG,
5882 XTENSA_OPTION_LOOP,
5883 },
5884 .op_flags = XTENSA_OP_EXIT_TB_M1,
5885 }, {
5886 .name = "xsr.lcount",
5887 .translate = translate_xsr,
5888 .test_ill = test_ill_sr,
5889 .par = (const uint32_t[]){
5890 LCOUNT,
5891 XTENSA_OPTION_LOOP,
5892 },
5893 }, {
5894 .name = "xsr.lend",
5895 .translate = translate_xsr,
5896 .test_ill = test_ill_sr,
5897 .par = (const uint32_t[]){
5898 LEND,
5899 XTENSA_OPTION_LOOP,
5900 },
5901 .op_flags = XTENSA_OP_EXIT_TB_M1,
5902 }, {
5903 .name = "xsr.litbase",
5904 .translate = translate_xsr_mask,
5905 .test_ill = test_ill_sr,
5906 .par = (const uint32_t[]){
5907 LITBASE,
5908 XTENSA_OPTION_EXTENDED_L32R,
5909 0xfffff001,
5910 },
5911 .op_flags = XTENSA_OP_EXIT_TB_M1,
5912 }, {
5913 .name = "xsr.m0",
5914 .translate = translate_xsr,
5915 .test_ill = test_ill_sr,
5916 .par = (const uint32_t[]){
5917 MR,
5918 XTENSA_OPTION_MAC16,
5919 },
5920 }, {
5921 .name = "xsr.m1",
5922 .translate = translate_xsr,
5923 .test_ill = test_ill_sr,
5924 .par = (const uint32_t[]){
5925 MR + 1,
5926 XTENSA_OPTION_MAC16,
5927 },
5928 }, {
5929 .name = "xsr.m2",
5930 .translate = translate_xsr,
5931 .test_ill = test_ill_sr,
5932 .par = (const uint32_t[]){
5933 MR + 2,
5934 XTENSA_OPTION_MAC16,
5935 },
5936 }, {
5937 .name = "xsr.m3",
5938 .translate = translate_xsr,
5939 .test_ill = test_ill_sr,
5940 .par = (const uint32_t[]){
5941 MR + 3,
5942 XTENSA_OPTION_MAC16,
5943 },
5944 }, {
5945 .name = "xsr.memctl",
5946 .translate = translate_xsr_memctl,
5947 .par = (const uint32_t[]){MEMCTL},
5948 .op_flags = XTENSA_OP_PRIVILEGED,
5949 }, {
5950 .name = "xsr.mecr",
5951 .translate = translate_xsr,
5952 .test_ill = test_ill_sr,
5953 .par = (const uint32_t[]){
5954 MECR,
5955 XTENSA_OPTION_MEMORY_ECC_PARITY,
5956 },
5957 .op_flags = XTENSA_OP_PRIVILEGED,
5958 }, {
5959 .name = "xsr.mepc",
5960 .translate = translate_xsr,
5961 .test_ill = test_ill_sr,
5962 .par = (const uint32_t[]){
5963 MEPC,
5964 XTENSA_OPTION_MEMORY_ECC_PARITY,
5965 },
5966 .op_flags = XTENSA_OP_PRIVILEGED,
5967 }, {
5968 .name = "xsr.meps",
5969 .translate = translate_xsr,
5970 .test_ill = test_ill_sr,
5971 .par = (const uint32_t[]){
5972 MEPS,
5973 XTENSA_OPTION_MEMORY_ECC_PARITY,
5974 },
5975 .op_flags = XTENSA_OP_PRIVILEGED,
5976 }, {
5977 .name = "xsr.mesave",
5978 .translate = translate_xsr,
5979 .test_ill = test_ill_sr,
5980 .par = (const uint32_t[]){
5981 MESAVE,
5982 XTENSA_OPTION_MEMORY_ECC_PARITY,
5983 },
5984 .op_flags = XTENSA_OP_PRIVILEGED,
5985 }, {
5986 .name = "xsr.mesr",
5987 .translate = translate_xsr,
5988 .test_ill = test_ill_sr,
5989 .par = (const uint32_t[]){
5990 MESR,
5991 XTENSA_OPTION_MEMORY_ECC_PARITY,
5992 },
5993 .op_flags = XTENSA_OP_PRIVILEGED,
5994 }, {
5995 .name = "xsr.mevaddr",
5996 .translate = translate_xsr,
5997 .test_ill = test_ill_sr,
5998 .par = (const uint32_t[]){
5999 MESR,
6000 XTENSA_OPTION_MEMORY_ECC_PARITY,
6001 },
6002 .op_flags = XTENSA_OP_PRIVILEGED,
6003 }, {
6004 .name = "xsr.misc0",
6005 .translate = translate_xsr,
6006 .test_ill = test_ill_sr,
6007 .par = (const uint32_t[]){
6008 MISC,
6009 XTENSA_OPTION_MISC_SR,
6010 },
6011 .op_flags = XTENSA_OP_PRIVILEGED,
6012 }, {
6013 .name = "xsr.misc1",
6014 .translate = translate_xsr,
6015 .test_ill = test_ill_sr,
6016 .par = (const uint32_t[]){
6017 MISC + 1,
6018 XTENSA_OPTION_MISC_SR,
6019 },
6020 .op_flags = XTENSA_OP_PRIVILEGED,
6021 }, {
6022 .name = "xsr.misc2",
6023 .translate = translate_xsr,
6024 .test_ill = test_ill_sr,
6025 .par = (const uint32_t[]){
6026 MISC + 2,
6027 XTENSA_OPTION_MISC_SR,
6028 },
6029 .op_flags = XTENSA_OP_PRIVILEGED,
6030 }, {
6031 .name = "xsr.misc3",
6032 .translate = translate_xsr,
6033 .test_ill = test_ill_sr,
6034 .par = (const uint32_t[]){
6035 MISC + 3,
6036 XTENSA_OPTION_MISC_SR,
6037 },
6038 .op_flags = XTENSA_OP_PRIVILEGED,
6039 }, {
6040 .name = "xsr.mpuenb",
6041 .translate = translate_xsr_mpuenb,
6042 .test_ill = test_ill_sr,
6043 .par = (const uint32_t[]){
6044 MPUENB,
6045 XTENSA_OPTION_MPU,
6046 },
6047 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
6048 }, {
6049 .name = "xsr.prefctl",
6050 .translate = translate_xsr,
6051 .par = (const uint32_t[]){PREFCTL},
6052 }, {
6053 .name = "xsr.prid",
6054 .op_flags = XTENSA_OP_ILL,
6055 }, {
6056 .name = "xsr.ps",
6057 .translate = translate_xsr_ps,
6058 .test_ill = test_ill_sr,
6059 .par = (const uint32_t[]){
6060 PS,
6061 XTENSA_OPTION_EXCEPTION,
6062 },
6063 .op_flags =
6064 XTENSA_OP_PRIVILEGED |
6065 XTENSA_OP_EXIT_TB_M1 |
6066 XTENSA_OP_CHECK_INTERRUPTS,
6067 }, {
6068 .name = "xsr.ptevaddr",
6069 .translate = translate_xsr_mask,
6070 .test_ill = test_ill_sr,
6071 .par = (const uint32_t[]){
6072 PTEVADDR,
6073 XTENSA_OPTION_MMU,
6074 0xffc00000,
6075 },
6076 .op_flags = XTENSA_OP_PRIVILEGED,
6077 }, {
6078 .name = "xsr.rasid",
6079 .translate = translate_xsr_rasid,
6080 .test_ill = test_ill_sr,
6081 .par = (const uint32_t[]){
6082 RASID,
6083 XTENSA_OPTION_MMU,
6084 },
6085 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
6086 }, {
6087 .name = "xsr.sar",
6088 .translate = translate_xsr_sar,
6089 .par = (const uint32_t[]){SAR},
6090 }, {
6091 .name = "xsr.scompare1",
6092 .translate = translate_xsr,
6093 .test_ill = test_ill_sr,
6094 .par = (const uint32_t[]){
6095 SCOMPARE1,
6096 XTENSA_OPTION_CONDITIONAL_STORE,
6097 },
6098 }, {
6099 .name = "xsr.vecbase",
6100 .translate = translate_xsr,
6101 .test_ill = test_ill_sr,
6102 .par = (const uint32_t[]){
6103 VECBASE,
6104 XTENSA_OPTION_RELOCATABLE_VECTOR,
6105 },
6106 .op_flags = XTENSA_OP_PRIVILEGED,
6107 }, {
6108 .name = "xsr.windowbase",
6109 .translate = translate_xsr_windowbase,
6110 .test_ill = test_ill_sr,
6111 .par = (const uint32_t[]){
6112 WINDOW_BASE,
6113 XTENSA_OPTION_WINDOWED_REGISTER,
6114 },
6115 .op_flags = XTENSA_OP_PRIVILEGED |
6116 XTENSA_OP_EXIT_TB_M1 |
6117 XTENSA_OP_SYNC_REGISTER_WINDOW,
6118 }, {
6119 .name = "xsr.windowstart",
6120 .translate = translate_xsr_windowstart,
6121 .test_ill = test_ill_sr,
6122 .par = (const uint32_t[]){
6123 WINDOW_START,
6124 XTENSA_OPTION_WINDOWED_REGISTER,
6125 },
6126 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
6127 },
6128 };
6129
6130 const XtensaOpcodeTranslators xtensa_core_opcodes = {
6131 .num_opcodes = ARRAY_SIZE(core_ops),
6132 .opcode = core_ops,
6133 };
6134
6135
6136 static void translate_abs_s(DisasContext *dc, const OpcodeArg arg[],
6137 const uint32_t par[])
6138 {
6139 gen_helper_abs_s(arg[0].out, arg[1].in);
6140 }
6141
6142 static void translate_add_s(DisasContext *dc, const OpcodeArg arg[],
6143 const uint32_t par[])
6144 {
6145 gen_helper_add_s(arg[0].out, cpu_env,
6146 arg[1].in, arg[2].in);
6147 }
6148
6149 enum {
6150 COMPARE_UN,
6151 COMPARE_OEQ,
6152 COMPARE_UEQ,
6153 COMPARE_OLT,
6154 COMPARE_ULT,
6155 COMPARE_OLE,
6156 COMPARE_ULE,
6157 };
6158
6159 static void translate_compare_s(DisasContext *dc, const OpcodeArg arg[],
6160 const uint32_t par[])
6161 {
6162 static void (* const helper[])(TCGv_env env, TCGv_i32 bit,
6163 TCGv_i32 s, TCGv_i32 t) = {
6164 [COMPARE_UN] = gen_helper_un_s,
6165 [COMPARE_OEQ] = gen_helper_oeq_s,
6166 [COMPARE_UEQ] = gen_helper_ueq_s,
6167 [COMPARE_OLT] = gen_helper_olt_s,
6168 [COMPARE_ULT] = gen_helper_ult_s,
6169 [COMPARE_OLE] = gen_helper_ole_s,
6170 [COMPARE_ULE] = gen_helper_ule_s,
6171 };
6172 TCGv_i32 bit = tcg_const_i32(1 << arg[0].imm);
6173
6174 helper[par[0]](cpu_env, bit, arg[1].in, arg[2].in);
6175 tcg_temp_free(bit);
6176 }
6177
6178 static void translate_float_s(DisasContext *dc, const OpcodeArg arg[],
6179 const uint32_t par[])
6180 {
6181 TCGv_i32 scale = tcg_const_i32(-arg[2].imm);
6182
6183 if (par[0]) {
6184 gen_helper_uitof(arg[0].out, cpu_env, arg[1].in, scale);
6185 } else {
6186 gen_helper_itof(arg[0].out, cpu_env, arg[1].in, scale);
6187 }
6188 tcg_temp_free(scale);
6189 }
6190
6191 static void translate_ftoi_s(DisasContext *dc, const OpcodeArg arg[],
6192 const uint32_t par[])
6193 {
6194 TCGv_i32 rounding_mode = tcg_const_i32(par[0]);
6195 TCGv_i32 scale = tcg_const_i32(arg[2].imm);
6196
6197 if (par[1]) {
6198 gen_helper_ftoui(arg[0].out, arg[1].in,
6199 rounding_mode, scale);
6200 } else {
6201 gen_helper_ftoi(arg[0].out, arg[1].in,
6202 rounding_mode, scale);
6203 }
6204 tcg_temp_free(rounding_mode);
6205 tcg_temp_free(scale);
6206 }
6207
6208 static void translate_ldsti(DisasContext *dc, const OpcodeArg arg[],
6209 const uint32_t par[])
6210 {
6211 TCGv_i32 addr = tcg_temp_new_i32();
6212
6213 tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
6214 gen_load_store_alignment(dc, 2, addr, false);
6215 if (par[0]) {
6216 tcg_gen_qemu_st32(arg[0].in, addr, dc->cring);
6217 } else {
6218 tcg_gen_qemu_ld32u(arg[0].out, addr, dc->cring);
6219 }
6220 if (par[1]) {
6221 tcg_gen_mov_i32(arg[1].out, addr);
6222 }
6223 tcg_temp_free(addr);
6224 }
6225
6226 static void translate_ldstx(DisasContext *dc, const OpcodeArg arg[],
6227 const uint32_t par[])
6228 {
6229 TCGv_i32 addr = tcg_temp_new_i32();
6230
6231 tcg_gen_add_i32(addr, arg[1].in, arg[2].in);
6232 gen_load_store_alignment(dc, 2, addr, false);
6233 if (par[0]) {
6234 tcg_gen_qemu_st32(arg[0].in, addr, dc->cring);
6235 } else {
6236 tcg_gen_qemu_ld32u(arg[0].out, addr, dc->cring);
6237 }
6238 if (par[1]) {
6239 tcg_gen_mov_i32(arg[1].out, addr);
6240 }
6241 tcg_temp_free(addr);
6242 }
6243
6244 static void translate_madd_s(DisasContext *dc, const OpcodeArg arg[],
6245 const uint32_t par[])
6246 {
6247 gen_helper_madd_s(arg[0].out, cpu_env,
6248 arg[0].in, arg[1].in, arg[2].in);
6249 }
6250
6251 static void translate_mov_s(DisasContext *dc, const OpcodeArg arg[],
6252 const uint32_t par[])
6253 {
6254 tcg_gen_mov_i32(arg[0].out, arg[1].in);
6255 }
6256
6257 static void translate_movcond_s(DisasContext *dc, const OpcodeArg arg[],
6258 const uint32_t par[])
6259 {
6260 TCGv_i32 zero = tcg_const_i32(0);
6261
6262 tcg_gen_movcond_i32(par[0], arg[0].out,
6263 arg[2].in, zero,
6264 arg[1].in, arg[0].in);
6265 tcg_temp_free(zero);
6266 }
6267
6268 static void translate_movp_s(DisasContext *dc, const OpcodeArg arg[],
6269 const uint32_t par[])
6270 {
6271 TCGv_i32 zero = tcg_const_i32(0);
6272 TCGv_i32 tmp = tcg_temp_new_i32();
6273
6274 tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm);
6275 tcg_gen_movcond_i32(par[0],
6276 arg[0].out, tmp, zero,
6277 arg[1].in, arg[0].in);
6278 tcg_temp_free(tmp);
6279 tcg_temp_free(zero);
6280 }
6281
6282 static void translate_mul_s(DisasContext *dc, const OpcodeArg arg[],
6283 const uint32_t par[])
6284 {
6285 gen_helper_mul_s(arg[0].out, cpu_env,
6286 arg[1].in, arg[2].in);
6287 }
6288
6289 static void translate_msub_s(DisasContext *dc, const OpcodeArg arg[],
6290 const uint32_t par[])
6291 {
6292 gen_helper_msub_s(arg[0].out, cpu_env,
6293 arg[0].in, arg[1].in, arg[2].in);
6294 }
6295
6296 static void translate_neg_s(DisasContext *dc, const OpcodeArg arg[],
6297 const uint32_t par[])
6298 {
6299 gen_helper_neg_s(arg[0].out, arg[1].in);
6300 }
6301
6302 static void translate_rfr_s(DisasContext *dc, const OpcodeArg arg[],
6303 const uint32_t par[])
6304 {
6305 tcg_gen_mov_i32(arg[0].out, arg[1].in);
6306 }
6307
6308 static void translate_sub_s(DisasContext *dc, const OpcodeArg arg[],
6309 const uint32_t par[])
6310 {
6311 gen_helper_sub_s(arg[0].out, cpu_env,
6312 arg[1].in, arg[2].in);
6313 }
6314
6315 static void translate_wfr_s(DisasContext *dc, const OpcodeArg arg[],
6316 const uint32_t par[])
6317 {
6318 tcg_gen_mov_i32(arg[0].out, arg[1].in);
6319 }
6320
6321 static const XtensaOpcodeOps fpu2000_ops[] = {
6322 {
6323 .name = "abs.s",
6324 .translate = translate_abs_s,
6325 .coprocessor = 0x1,
6326 }, {
6327 .name = "add.s",
6328 .translate = translate_add_s,
6329 .coprocessor = 0x1,
6330 }, {
6331 .name = "ceil.s",
6332 .translate = translate_ftoi_s,
6333 .par = (const uint32_t[]){float_round_up, false},
6334 .coprocessor = 0x1,
6335 }, {
6336 .name = "float.s",
6337 .translate = translate_float_s,
6338 .par = (const uint32_t[]){false},
6339 .coprocessor = 0x1,
6340 }, {
6341 .name = "floor.s",
6342 .translate = translate_ftoi_s,
6343 .par = (const uint32_t[]){float_round_down, false},
6344 .coprocessor = 0x1,
6345 }, {
6346 .name = "lsi",
6347 .translate = translate_ldsti,
6348 .par = (const uint32_t[]){false, false},
6349 .op_flags = XTENSA_OP_LOAD,
6350 .coprocessor = 0x1,
6351 }, {
6352 .name = "lsiu",
6353 .translate = translate_ldsti,
6354 .par = (const uint32_t[]){false, true},
6355 .op_flags = XTENSA_OP_LOAD,
6356 .coprocessor = 0x1,
6357 }, {
6358 .name = "lsx",
6359 .translate = translate_ldstx,
6360 .par = (const uint32_t[]){false, false},
6361 .op_flags = XTENSA_OP_LOAD,
6362 .coprocessor = 0x1,
6363 }, {
6364 .name = "lsxu",
6365 .translate = translate_ldstx,
6366 .par = (const uint32_t[]){false, true},
6367 .op_flags = XTENSA_OP_LOAD,
6368 .coprocessor = 0x1,
6369 }, {
6370 .name = "madd.s",
6371 .translate = translate_madd_s,
6372 .coprocessor = 0x1,
6373 }, {
6374 .name = "mov.s",
6375 .translate = translate_mov_s,
6376 .coprocessor = 0x1,
6377 }, {
6378 .name = "moveqz.s",
6379 .translate = translate_movcond_s,
6380 .par = (const uint32_t[]){TCG_COND_EQ},
6381 .coprocessor = 0x1,
6382 }, {
6383 .name = "movf.s",
6384 .translate = translate_movp_s,
6385 .par = (const uint32_t[]){TCG_COND_EQ},
6386 .coprocessor = 0x1,
6387 }, {
6388 .name = "movgez.s",
6389 .translate = translate_movcond_s,
6390 .par = (const uint32_t[]){TCG_COND_GE},
6391 .coprocessor = 0x1,
6392 }, {
6393 .name = "movltz.s",
6394 .translate = translate_movcond_s,
6395 .par = (const uint32_t[]){TCG_COND_LT},
6396 .coprocessor = 0x1,
6397 }, {
6398 .name = "movnez.s",
6399 .translate = translate_movcond_s,
6400 .par = (const uint32_t[]){TCG_COND_NE},
6401 .coprocessor = 0x1,
6402 }, {
6403 .name = "movt.s",
6404 .translate = translate_movp_s,
6405 .par = (const uint32_t[]){TCG_COND_NE},
6406 .coprocessor = 0x1,
6407 }, {
6408 .name = "msub.s",
6409 .translate = translate_msub_s,
6410 .coprocessor = 0x1,
6411 }, {
6412 .name = "mul.s",
6413 .translate = translate_mul_s,
6414 .coprocessor = 0x1,
6415 }, {
6416 .name = "neg.s",
6417 .translate = translate_neg_s,
6418 .coprocessor = 0x1,
6419 }, {
6420 .name = "oeq.s",
6421 .translate = translate_compare_s,
6422 .par = (const uint32_t[]){COMPARE_OEQ},
6423 .coprocessor = 0x1,
6424 }, {
6425 .name = "ole.s",
6426 .translate = translate_compare_s,
6427 .par = (const uint32_t[]){COMPARE_OLE},
6428 .coprocessor = 0x1,
6429 }, {
6430 .name = "olt.s",
6431 .translate = translate_compare_s,
6432 .par = (const uint32_t[]){COMPARE_OLT},
6433 .coprocessor = 0x1,
6434 }, {
6435 .name = "rfr",
6436 .translate = translate_rfr_s,
6437 .coprocessor = 0x1,
6438 }, {
6439 .name = "round.s",
6440 .translate = translate_ftoi_s,
6441 .par = (const uint32_t[]){float_round_nearest_even, false},
6442 .coprocessor = 0x1,
6443 }, {
6444 .name = "ssi",
6445 .translate = translate_ldsti,
6446 .par = (const uint32_t[]){true, false},
6447 .op_flags = XTENSA_OP_STORE,
6448 .coprocessor = 0x1,
6449 }, {
6450 .name = "ssiu",
6451 .translate = translate_ldsti,
6452 .par = (const uint32_t[]){true, true},
6453 .op_flags = XTENSA_OP_STORE,
6454 .coprocessor = 0x1,
6455 }, {
6456 .name = "ssx",
6457 .translate = translate_ldstx,
6458 .par = (const uint32_t[]){true, false},
6459 .op_flags = XTENSA_OP_STORE,
6460 .coprocessor = 0x1,
6461 }, {
6462 .name = "ssxu",
6463 .translate = translate_ldstx,
6464 .par = (const uint32_t[]){true, true},
6465 .op_flags = XTENSA_OP_STORE,
6466 .coprocessor = 0x1,
6467 }, {
6468 .name = "sub.s",
6469 .translate = translate_sub_s,
6470 .coprocessor = 0x1,
6471 }, {
6472 .name = "trunc.s",
6473 .translate = translate_ftoi_s,
6474 .par = (const uint32_t[]){float_round_to_zero, false},
6475 .coprocessor = 0x1,
6476 }, {
6477 .name = "ueq.s",
6478 .translate = translate_compare_s,
6479 .par = (const uint32_t[]){COMPARE_UEQ},
6480 .coprocessor = 0x1,
6481 }, {
6482 .name = "ufloat.s",
6483 .translate = translate_float_s,
6484 .par = (const uint32_t[]){true},
6485 .coprocessor = 0x1,
6486 }, {
6487 .name = "ule.s",
6488 .translate = translate_compare_s,
6489 .par = (const uint32_t[]){COMPARE_ULE},
6490 .coprocessor = 0x1,
6491 }, {
6492 .name = "ult.s",
6493 .translate = translate_compare_s,
6494 .par = (const uint32_t[]){COMPARE_ULT},
6495 .coprocessor = 0x1,
6496 }, {
6497 .name = "un.s",
6498 .translate = translate_compare_s,
6499 .par = (const uint32_t[]){COMPARE_UN},
6500 .coprocessor = 0x1,
6501 }, {
6502 .name = "utrunc.s",
6503 .translate = translate_ftoi_s,
6504 .par = (const uint32_t[]){float_round_to_zero, true},
6505 .coprocessor = 0x1,
6506 }, {
6507 .name = "wfr",
6508 .translate = translate_wfr_s,
6509 .coprocessor = 0x1,
6510 },
6511 };
6512
6513 const XtensaOpcodeTranslators xtensa_fpu2000_opcodes = {
6514 .num_opcodes = ARRAY_SIZE(fpu2000_ops),
6515 .opcode = fpu2000_ops,
6516 };
AR7 emulation for QEMU