target/xtensa/cpu.h

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #ifndef XTENSA_CPU_H
  29 #define XTENSA_CPU_H
  30
  31 #define ALIGNED_ONLY
  32 #define TARGET_LONG_BITS 32
  33
  34 /* Xtensa processors have a weak memory model */
  35 #define TCG_GUEST_DEFAULT_MO      (0)
  36
  37 #define CPUArchState struct CPUXtensaState
  38
  39 #include "qemu-common.h"
  40 #include "cpu-qom.h"
  41 #include "exec/cpu-defs.h"
  42 #include "xtensa-isa.h"
  43
  44 #define NB_MMU_MODES 4
  45
  46 #define TARGET_PHYS_ADDR_SPACE_BITS 32
  47 #ifdef CONFIG_USER_ONLY
  48 #define TARGET_VIRT_ADDR_SPACE_BITS 30
  49 #else
  50 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  51 #endif
  52 #define TARGET_PAGE_BITS 12
  53
  54 enum {
  55     /* Additional instructions */
  56     XTENSA_OPTION_CODE_DENSITY,
  57     XTENSA_OPTION_LOOP,
  58     XTENSA_OPTION_EXTENDED_L32R,
  59     XTENSA_OPTION_16_BIT_IMUL,
  60     XTENSA_OPTION_32_BIT_IMUL,
  61     XTENSA_OPTION_32_BIT_IMUL_HIGH,
  62     XTENSA_OPTION_32_BIT_IDIV,
  63     XTENSA_OPTION_MAC16,
  64     XTENSA_OPTION_MISC_OP_NSA,
  65     XTENSA_OPTION_MISC_OP_MINMAX,
  66     XTENSA_OPTION_MISC_OP_SEXT,
  67     XTENSA_OPTION_MISC_OP_CLAMPS,
  68     XTENSA_OPTION_COPROCESSOR,
  69     XTENSA_OPTION_BOOLEAN,
  70     XTENSA_OPTION_FP_COPROCESSOR,
  71     XTENSA_OPTION_MP_SYNCHRO,
  72     XTENSA_OPTION_CONDITIONAL_STORE,
  73     XTENSA_OPTION_ATOMCTL,
  74     XTENSA_OPTION_DEPBITS,
  75
  76     /* Interrupts and exceptions */
  77     XTENSA_OPTION_EXCEPTION,
  78     XTENSA_OPTION_RELOCATABLE_VECTOR,
  79     XTENSA_OPTION_UNALIGNED_EXCEPTION,
  80     XTENSA_OPTION_INTERRUPT,
  81     XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
  82     XTENSA_OPTION_TIMER_INTERRUPT,
  83
  84     /* Local memory */
  85     XTENSA_OPTION_ICACHE,
  86     XTENSA_OPTION_ICACHE_TEST,
  87     XTENSA_OPTION_ICACHE_INDEX_LOCK,
  88     XTENSA_OPTION_DCACHE,
  89     XTENSA_OPTION_DCACHE_TEST,
  90     XTENSA_OPTION_DCACHE_INDEX_LOCK,
  91     XTENSA_OPTION_IRAM,
  92     XTENSA_OPTION_IROM,
  93     XTENSA_OPTION_DRAM,
  94     XTENSA_OPTION_DROM,
  95     XTENSA_OPTION_XLMI,
  96     XTENSA_OPTION_HW_ALIGNMENT,
  97     XTENSA_OPTION_MEMORY_ECC_PARITY,
  98
  99     /* Memory protection and translation */
 100     XTENSA_OPTION_REGION_PROTECTION,
 101     XTENSA_OPTION_REGION_TRANSLATION,
 102     XTENSA_OPTION_MPU,
 103     XTENSA_OPTION_MMU,
 104     XTENSA_OPTION_CACHEATTR,
 105
 106     /* Other */
 107     XTENSA_OPTION_WINDOWED_REGISTER,
 108     XTENSA_OPTION_PROCESSOR_INTERFACE,
 109     XTENSA_OPTION_MISC_SR,
 110     XTENSA_OPTION_THREAD_POINTER,
 111     XTENSA_OPTION_PROCESSOR_ID,
 112     XTENSA_OPTION_DEBUG,
 113     XTENSA_OPTION_TRACE_PORT,
 114     XTENSA_OPTION_EXTERN_REGS,
 115 };
 116
 117 enum {
 118     EXPSTATE = 230,
 119     THREADPTR = 231,
 120     FCR = 232,
 121     FSR = 233,
 122 };
 123
 124 enum {
 125     LBEG = 0,
 126     LEND = 1,
 127     LCOUNT = 2,
 128     SAR = 3,
 129     BR = 4,
 130     LITBASE = 5,
 131     SCOMPARE1 = 12,
 132     ACCLO = 16,
 133     ACCHI = 17,
 134     MR = 32,
 135     PREFCTL = 40,
 136     WINDOW_BASE = 72,
 137     WINDOW_START = 73,
 138     PTEVADDR = 83,
 139     MMID = 89,
 140     RASID = 90,
 141     MPUENB = 90,
 142     ITLBCFG = 91,
 143     DTLBCFG = 92,
 144     MPUCFG = 92,
 145     ERACCESS = 95,
 146     IBREAKENABLE = 96,
 147     MEMCTL = 97,
 148     CACHEATTR = 98,
 149     CACHEADRDIS = 98,
 150     ATOMCTL = 99,
 151     DDR = 104,
 152     MEPC = 106,
 153     MEPS = 107,
 154     MESAVE = 108,
 155     MESR = 109,
 156     MECR = 110,
 157     MEVADDR = 111,
 158     IBREAKA = 128,
 159     DBREAKA = 144,
 160     DBREAKC = 160,
 161     CONFIGID0 = 176,
 162     EPC1 = 177,
 163     DEPC = 192,
 164     EPS2 = 194,
 165     CONFIGID1 = 208,
 166     EXCSAVE1 = 209,
 167     CPENABLE = 224,
 168     INTSET = 226,
 169     INTCLEAR = 227,
 170     INTENABLE = 228,
 171     PS = 230,
 172     VECBASE = 231,
 173     EXCCAUSE = 232,
 174     DEBUGCAUSE = 233,
 175     CCOUNT = 234,
 176     PRID = 235,
 177     ICOUNT = 236,
 178     ICOUNTLEVEL = 237,
 179     EXCVADDR = 238,
 180     CCOMPARE = 240,
 181     MISC = 244,
 182 };
 183
 184 #define PS_INTLEVEL 0xf
 185 #define PS_INTLEVEL_SHIFT 0
 186
 187 #define PS_EXCM 0x10
 188 #define PS_UM 0x20
 189
 190 #define PS_RING 0xc0
 191 #define PS_RING_SHIFT 6
 192
 193 #define PS_OWB 0xf00
 194 #define PS_OWB_SHIFT 8
 195 #define PS_OWB_LEN 4
 196
 197 #define PS_CALLINC 0x30000
 198 #define PS_CALLINC_SHIFT 16
 199 #define PS_CALLINC_LEN 2
 200
 201 #define PS_WOE 0x40000
 202
 203 #define DEBUGCAUSE_IC 0x1
 204 #define DEBUGCAUSE_IB 0x2
 205 #define DEBUGCAUSE_DB 0x4
 206 #define DEBUGCAUSE_BI 0x8
 207 #define DEBUGCAUSE_BN 0x10
 208 #define DEBUGCAUSE_DI 0x20
 209 #define DEBUGCAUSE_DBNUM 0xf00
 210 #define DEBUGCAUSE_DBNUM_SHIFT 8
 211
 212 #define DBREAKC_SB 0x80000000
 213 #define DBREAKC_LB 0x40000000
 214 #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
 215 #define DBREAKC_MASK 0x3f
 216
 217 #define MEMCTL_INIT 0x00800000
 218 #define MEMCTL_IUSEWAYS_SHIFT 18
 219 #define MEMCTL_IUSEWAYS_LEN 5
 220 #define MEMCTL_IUSEWAYS_MASK 0x007c0000
 221 #define MEMCTL_DALLOCWAYS_SHIFT 13
 222 #define MEMCTL_DALLOCWAYS_LEN 5
 223 #define MEMCTL_DALLOCWAYS_MASK 0x0003e000
 224 #define MEMCTL_DUSEWAYS_SHIFT 8
 225 #define MEMCTL_DUSEWAYS_LEN 5
 226 #define MEMCTL_DUSEWAYS_MASK 0x00001f00
 227 #define MEMCTL_ISNP 0x4
 228 #define MEMCTL_DSNP 0x2
 229 #define MEMCTL_IL0EN 0x1
 230
 231 #define MAX_INSN_LENGTH 64
 232 #define MAX_INSN_SLOTS 32
 233 #define MAX_OPCODE_ARGS 16
 234 #define MAX_NAREG 64
 235 #define MAX_NINTERRUPT 32
 236 #define MAX_NLEVEL 6
 237 #define MAX_NNMI 1
 238 #define MAX_NCCOMPARE 3
 239 #define MAX_TLB_WAY_SIZE 8
 240 #define MAX_NDBREAK 2
 241 #define MAX_NMEMORY 4
 242 #define MAX_MPU_FOREGROUND_SEGMENTS 32
 243
 244 #define REGION_PAGE_MASK 0xe0000000
 245
 246 #define PAGE_CACHE_MASK    0x700
 247 #define PAGE_CACHE_SHIFT   8
 248 #define PAGE_CACHE_INVALID 0x000
 249 #define PAGE_CACHE_BYPASS  0x100
 250 #define PAGE_CACHE_WT      0x200
 251 #define PAGE_CACHE_WB      0x400
 252 #define PAGE_CACHE_ISOLATE 0x600
 253
 254 enum {
 255     /* Static vectors */
 256     EXC_RESET0,
 257     EXC_RESET1,
 258     EXC_MEMORY_ERROR,
 259
 260     /* Dynamic vectors */
 261     EXC_WINDOW_OVERFLOW4,
 262     EXC_WINDOW_UNDERFLOW4,
 263     EXC_WINDOW_OVERFLOW8,
 264     EXC_WINDOW_UNDERFLOW8,
 265     EXC_WINDOW_OVERFLOW12,
 266     EXC_WINDOW_UNDERFLOW12,
 267     EXC_IRQ,
 268     EXC_KERNEL,
 269     EXC_USER,
 270     EXC_DOUBLE,
 271     EXC_DEBUG,
 272     EXC_MAX
 273 };
 274
 275 enum {
 276     ILLEGAL_INSTRUCTION_CAUSE = 0,
 277     SYSCALL_CAUSE,
 278     INSTRUCTION_FETCH_ERROR_CAUSE,
 279     LOAD_STORE_ERROR_CAUSE,
 280     LEVEL1_INTERRUPT_CAUSE,
 281     ALLOCA_CAUSE,
 282     INTEGER_DIVIDE_BY_ZERO_CAUSE,
 283     PRIVILEGED_CAUSE = 8,
 284     LOAD_STORE_ALIGNMENT_CAUSE,
 285
 286     INSTR_PIF_DATA_ERROR_CAUSE = 12,
 287     LOAD_STORE_PIF_DATA_ERROR_CAUSE,
 288     INSTR_PIF_ADDR_ERROR_CAUSE,
 289     LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
 290
 291     INST_TLB_MISS_CAUSE,
 292     INST_TLB_MULTI_HIT_CAUSE,
 293     INST_FETCH_PRIVILEGE_CAUSE,
 294     INST_FETCH_PROHIBITED_CAUSE = 20,
 295     LOAD_STORE_TLB_MISS_CAUSE = 24,
 296     LOAD_STORE_TLB_MULTI_HIT_CAUSE,
 297     LOAD_STORE_PRIVILEGE_CAUSE,
 298     LOAD_PROHIBITED_CAUSE = 28,
 299     STORE_PROHIBITED_CAUSE,
 300
 301     COPROCESSOR0_DISABLED = 32,
 302 };
 303
 304 typedef enum {
 305     INTTYPE_LEVEL,
 306     INTTYPE_EDGE,
 307     INTTYPE_NMI,
 308     INTTYPE_SOFTWARE,
 309     INTTYPE_TIMER,
 310     INTTYPE_DEBUG,
 311     INTTYPE_WRITE_ERR,
 312     INTTYPE_PROFILING,
 313     INTTYPE_IDMA_DONE,
 314     INTTYPE_IDMA_ERR,
 315     INTTYPE_GS_ERR,
 316     INTTYPE_MAX
 317 } interrupt_type;
 318
 319 struct CPUXtensaState;
 320
 321 typedef struct xtensa_tlb_entry {
 322     uint32_t vaddr;
 323     uint32_t paddr;
 324     uint8_t asid;
 325     uint8_t attr;
 326     bool variable;
 327 } xtensa_tlb_entry;
 328
 329 typedef struct xtensa_tlb {
 330     unsigned nways;
 331     const unsigned way_size[10];
 332     bool varway56;
 333     unsigned nrefillentries;
 334 } xtensa_tlb;
 335
 336 typedef struct xtensa_mpu_entry {
 337     uint32_t vaddr;
 338     uint32_t attr;
 339 } xtensa_mpu_entry;
 340
 341 typedef struct XtensaGdbReg {
 342     int targno;
 343     unsigned flags;
 344     int type;
 345     int group;
 346     unsigned size;
 347 } XtensaGdbReg;
 348
 349 typedef struct XtensaGdbRegmap {
 350     int num_regs;
 351     int num_core_regs;
 352     /* PC + a + ar + sr + ur */
 353     XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
 354 } XtensaGdbRegmap;
 355
 356 typedef struct XtensaCcompareTimer {
 357     struct CPUXtensaState *env;
 358     QEMUTimer *timer;
 359 } XtensaCcompareTimer;
 360
 361 typedef struct XtensaMemory {
 362     unsigned num;
 363     struct XtensaMemoryRegion {
 364         uint32_t addr;
 365         uint32_t size;
 366     } location[MAX_NMEMORY];
 367 } XtensaMemory;
 368
 369 typedef struct opcode_arg {
 370     uint32_t imm;
 371     uint32_t raw_imm;
 372     void *in;
 373     void *out;
 374 } OpcodeArg;
 375
 376 typedef struct DisasContext DisasContext;
 377 typedef void (*XtensaOpcodeOp)(DisasContext *dc, const OpcodeArg arg[],
 378                                const uint32_t par[]);
 379 typedef bool (*XtensaOpcodeBoolTest)(DisasContext *dc,
 380                                      const OpcodeArg arg[],
 381                                      const uint32_t par[]);
 382 typedef uint32_t (*XtensaOpcodeUintTest)(DisasContext *dc,
 383                                          const OpcodeArg arg[],
 384                                          const uint32_t par[]);
 385
 386 enum {
 387     XTENSA_OP_ILL = 0x1,
 388     XTENSA_OP_PRIVILEGED = 0x2,
 389     XTENSA_OP_SYSCALL = 0x4,
 390     XTENSA_OP_DEBUG_BREAK = 0x8,
 391
 392     XTENSA_OP_OVERFLOW = 0x10,
 393     XTENSA_OP_UNDERFLOW = 0x20,
 394     XTENSA_OP_ALLOCA = 0x40,
 395     XTENSA_OP_COPROCESSOR = 0x80,
 396
 397     XTENSA_OP_DIVIDE_BY_ZERO = 0x100,
 398
 399     /* Postprocessing flags */
 400     XTENSA_OP_CHECK_INTERRUPTS = 0x200,
 401     XTENSA_OP_EXIT_TB_M1 = 0x400,
 402     XTENSA_OP_EXIT_TB_0 = 0x800,
 403     XTENSA_OP_SYNC_REGISTER_WINDOW = 0x1000,
 404
 405     XTENSA_OP_POSTPROCESS =
 406         XTENSA_OP_CHECK_INTERRUPTS |
 407         XTENSA_OP_EXIT_TB_M1 |
 408         XTENSA_OP_EXIT_TB_0 |
 409         XTENSA_OP_SYNC_REGISTER_WINDOW,
 410
 411     XTENSA_OP_NAME_ARRAY = 0x8000,
 412
 413     XTENSA_OP_CONTROL_FLOW = 0x10000,
 414     XTENSA_OP_STORE = 0x20000,
 415     XTENSA_OP_LOAD = 0x40000,
 416     XTENSA_OP_LOAD_STORE =
 417         XTENSA_OP_LOAD | XTENSA_OP_STORE,
 418 };
 419
 420 typedef struct XtensaOpcodeOps {
 421     const void *name;
 422     XtensaOpcodeOp translate;
 423     XtensaOpcodeBoolTest test_ill;
 424     XtensaOpcodeUintTest test_overflow;
 425     const uint32_t *par;
 426     uint32_t op_flags;
 427     uint32_t coprocessor;
 428 } XtensaOpcodeOps;
 429
 430 typedef struct XtensaOpcodeTranslators {
 431     unsigned num_opcodes;
 432     const XtensaOpcodeOps *opcode;
 433 } XtensaOpcodeTranslators;
 434
 435 extern const XtensaOpcodeTranslators xtensa_core_opcodes;
 436 extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes;
 437
 438 struct XtensaConfig {
 439     const char *name;
 440     uint64_t options;
 441     XtensaGdbRegmap gdb_regmap;
 442     unsigned nareg;
 443     int excm_level;
 444     int ndepc;
 445     unsigned inst_fetch_width;
 446     unsigned max_insn_size;
 447     uint32_t vecbase;
 448     uint32_t exception_vector[EXC_MAX];
 449     unsigned ninterrupt;
 450     unsigned nlevel;
 451     uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
 452     uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
 453     uint32_t inttype_mask[INTTYPE_MAX];
 454     struct {
 455         uint32_t level;
 456         interrupt_type inttype;
 457     } interrupt[MAX_NINTERRUPT];
 458     unsigned nccompare;
 459     uint32_t timerint[MAX_NCCOMPARE];
 460     unsigned nextint;
 461     unsigned extint[MAX_NINTERRUPT];
 462
 463     unsigned debug_level;
 464     unsigned nibreak;
 465     unsigned ndbreak;
 466
 467     unsigned icache_ways;
 468     unsigned dcache_ways;
 469     uint32_t memctl_mask;
 470
 471     XtensaMemory instrom;
 472     XtensaMemory instram;
 473     XtensaMemory datarom;
 474     XtensaMemory dataram;
 475     XtensaMemory sysrom;
 476     XtensaMemory sysram;
 477
 478     uint32_t configid[2];
 479
 480     void *isa_internal;
 481     xtensa_isa isa;
 482     XtensaOpcodeOps **opcode_ops;
 483     const XtensaOpcodeTranslators **opcode_translators;
 484     xtensa_regfile a_regfile;
 485     void ***regfile;
 486
 487     uint32_t clock_freq_khz;
 488
 489     xtensa_tlb itlb;
 490     xtensa_tlb dtlb;
 491
 492     uint32_t mpu_align;
 493     unsigned n_mpu_fg_segments;
 494     unsigned n_mpu_bg_segments;
 495     const xtensa_mpu_entry *mpu_bg;
 496 };
 497
 498 typedef struct XtensaConfigList {
 499     const XtensaConfig *config;
 500     struct XtensaConfigList *next;
 501 } XtensaConfigList;
 502
 503 #ifdef HOST_WORDS_BIGENDIAN
 504 enum {
 505     FP_F32_HIGH,
 506     FP_F32_LOW,
 507 };
 508 #else
 509 enum {
 510     FP_F32_LOW,
 511     FP_F32_HIGH,
 512 };
 513 #endif
 514
 515 typedef struct CPUXtensaState {
 516     const XtensaConfig *config;
 517     uint32_t regs[16];
 518     uint32_t pc;
 519     uint32_t sregs[256];
 520     uint32_t uregs[256];
 521     uint32_t phys_regs[MAX_NAREG];
 522     union {
 523         float32 f32[2];
 524         float64 f64;
 525     } fregs[16];
 526     float_status fp_status;
 527     uint32_t windowbase_next;
 528
 529 #ifndef CONFIG_USER_ONLY
 530     xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
 531     xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
 532     xtensa_mpu_entry mpu_fg[MAX_MPU_FOREGROUND_SEGMENTS];
 533     unsigned autorefill_idx;
 534     bool runstall;
 535     AddressSpace *address_space_er;
 536     MemoryRegion *system_er;
 537     int pending_irq_level; /* level of last raised IRQ */
 538     qemu_irq *irq_inputs;
 539     qemu_irq ext_irq_inputs[MAX_NINTERRUPT];
 540     qemu_irq runstall_irq;
 541     XtensaCcompareTimer ccompare[MAX_NCCOMPARE];
 542     uint64_t time_base;
 543     uint64_t ccount_time;
 544     uint32_t ccount_base;
 545 #endif
 546
 547     int exception_taken;
 548     int yield_needed;
 549     unsigned static_vectors;
 550
 551     /* Watchpoints for DBREAK registers */
 552     struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
 553
 554     CPU_COMMON
 555 } CPUXtensaState;
 556
 557 /**
 558  * XtensaCPU:
 559  * @env: #CPUXtensaState
 560  *
 561  * An Xtensa CPU.
 562  */
 563 struct XtensaCPU {
 564     /*< private >*/
 565     CPUState parent_obj;
 566     /*< public >*/
 567
 568     CPUXtensaState env;
 569 };
 570
 571 static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env)
 572 {
 573     return container_of(env, XtensaCPU, env);
 574 }
 575
 576 #define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e))
 577
 578 #define ENV_OFFSET offsetof(XtensaCPU, env)
 579
 580
 581 int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int size,
 582                                 int mmu_idx);
 583 void xtensa_cpu_do_interrupt(CPUState *cpu);
 584 bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
 585 void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
 586                                       unsigned size, MMUAccessType access_type,
 587                                       int mmu_idx, MemTxAttrs attrs,
 588                                       MemTxResult response, uintptr_t retaddr);
 589 void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
 590 hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 591 void xtensa_count_regs(const XtensaConfig *config,
 592                        unsigned *n_regs, unsigned *n_core_regs);
 593 int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 594 int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 595 void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
 596                                     MMUAccessType access_type,
 597                                     int mmu_idx, uintptr_t retaddr);
 598
 599 #define cpu_signal_handler cpu_xtensa_signal_handler
 600 #define cpu_list xtensa_cpu_list
 601
 602 #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU
 603 #define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX
 604 #define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU
 605
 606 #ifdef TARGET_WORDS_BIGENDIAN
 607 #define XTENSA_DEFAULT_CPU_MODEL "fsf"
 608 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "fsf"
 609 #else
 610 #define XTENSA_DEFAULT_CPU_MODEL "dc232b"
 611 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "de212"
 612 #endif
 613 #define XTENSA_DEFAULT_CPU_TYPE \
 614     XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_MODEL)
 615 #define XTENSA_DEFAULT_CPU_NOMMU_TYPE \
 616     XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL)
 617
 618 void xtensa_collect_sr_names(const XtensaConfig *config);
 619 void xtensa_translate_init(void);
 620 void **xtensa_get_regfile_by_name(const char *name);
 621 void xtensa_breakpoint_handler(CPUState *cs);
 622 void xtensa_register_core(XtensaConfigList *node);
 623 void xtensa_sim_open_console(Chardev *chr);
 624 void check_interrupts(CPUXtensaState *s);
 625 void xtensa_irq_init(CPUXtensaState *env);
 626 qemu_irq *xtensa_get_extints(CPUXtensaState *env);
 627 qemu_irq xtensa_get_runstall(CPUXtensaState *env);
 628 int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
 629 void xtensa_cpu_list(void);
 630 void xtensa_sync_window_from_phys(CPUXtensaState *env);
 631 void xtensa_sync_phys_from_window(CPUXtensaState *env);
 632 void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta);
 633 void xtensa_restore_owb(CPUXtensaState *env);
 634 void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
 635
 636 static inline void xtensa_select_static_vectors(CPUXtensaState *env,
 637                                                 unsigned n)
 638 {
 639     assert(n < 2);
 640     env->static_vectors = n;
 641 }
 642 void xtensa_runstall(CPUXtensaState *env, bool runstall);
 643
 644 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
 645 #define XTENSA_OPTION_ALL (~(uint64_t)0)
 646
 647 static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
 648         uint64_t opt)
 649 {
 650     return (config->options & opt) != 0;
 651 }
 652
 653 static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
 654 {
 655     return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
 656 }
 657
 658 static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
 659 {
 660     int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
 661     if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
 662         level = env->config->excm_level;
 663     }
 664     return level;
 665 }
 666
 667 static inline int xtensa_get_ring(const CPUXtensaState *env)
 668 {
 669     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 670         return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
 671     } else {
 672         return 0;
 673     }
 674 }
 675
 676 static inline int xtensa_get_cring(const CPUXtensaState *env)
 677 {
 678     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
 679             (env->sregs[PS] & PS_EXCM) == 0) {
 680         return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
 681     } else {
 682         return 0;
 683     }
 684 }
 685
 686 #ifndef CONFIG_USER_ONLY
 687 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
 688         uint32_t vaddr, int is_write, int mmu_idx,
 689         uint32_t *paddr, uint32_t *page_size, unsigned *access);
 690 void reset_mmu(CPUXtensaState *env);
 691 void dump_mmu(CPUXtensaState *env);
 692
 693 static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env)
 694 {
 695     return env->system_er;
 696 }
 697 #endif
 698
 699 static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
 700 {
 701     return env->sregs[WINDOW_START] |
 702         (env->sregs[WINDOW_START] << env->config->nareg / 4);
 703 }
 704
 705 /* MMU modes definitions */
 706 #define MMU_MODE0_SUFFIX _ring0
 707 #define MMU_MODE1_SUFFIX _ring1
 708 #define MMU_MODE2_SUFFIX _ring2
 709 #define MMU_MODE3_SUFFIX _ring3
 710 #define MMU_USER_IDX 3
 711
 712 static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
 713 {
 714     return xtensa_get_cring(env);
 715 }
 716
 717 #define XTENSA_TBFLAG_RING_MASK 0x3
 718 #define XTENSA_TBFLAG_EXCM 0x4
 719 #define XTENSA_TBFLAG_LITBASE 0x8
 720 #define XTENSA_TBFLAG_DEBUG 0x10
 721 #define XTENSA_TBFLAG_ICOUNT 0x20
 722 #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
 723 #define XTENSA_TBFLAG_CPENABLE_SHIFT 6
 724 #define XTENSA_TBFLAG_EXCEPTION 0x4000
 725 #define XTENSA_TBFLAG_WINDOW_MASK 0x18000
 726 #define XTENSA_TBFLAG_WINDOW_SHIFT 15
 727 #define XTENSA_TBFLAG_YIELD 0x20000
 728 #define XTENSA_TBFLAG_CWOE 0x40000
 729 #define XTENSA_TBFLAG_CALLINC_MASK 0x180000
 730 #define XTENSA_TBFLAG_CALLINC_SHIFT 19
 731
 732 #define XTENSA_CSBASE_LEND_MASK 0x0000ffff
 733 #define XTENSA_CSBASE_LEND_SHIFT 0
 734 #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000
 735 #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16
 736
 737 static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
 738         target_ulong *cs_base, uint32_t *flags)
 739 {
 740     CPUState *cs = CPU(xtensa_env_get_cpu(env));
 741
 742     *pc = env->pc;
 743     *cs_base = 0;
 744     *flags = 0;
 745     *flags |= xtensa_get_ring(env);
 746     if (env->sregs[PS] & PS_EXCM) {
 747         *flags |= XTENSA_TBFLAG_EXCM;
 748     } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) {
 749         target_ulong lend_dist =
 750             env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS));
 751
 752         /*
 753          * 0 in the csbase_lend field means that there may not be a loopback
 754          * for any instruction that starts inside this page. Any other value
 755          * means that an instruction that ends at this offset from the page
 756          * start may loop back and will need loopback code to be generated.
 757          *
 758          * lend_dist is 0 when LEND points to the start of the page, but
 759          * no instruction that starts inside this page may end at offset 0,
 760          * so it's still correct.
 761          *
 762          * When an instruction ends at a page boundary it may only start in
 763          * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE
 764          * for the TB that contains this instruction.
 765          */
 766         if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) {
 767             target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG];
 768
 769             *cs_base = lend_dist;
 770             if (lbeg_off < 256) {
 771                 *cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT;
 772             }
 773         }
 774     }
 775     if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
 776             (env->sregs[LITBASE] & 1)) {
 777         *flags |= XTENSA_TBFLAG_LITBASE;
 778     }
 779     if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
 780         if (xtensa_get_cintlevel(env) < env->config->debug_level) {
 781             *flags |= XTENSA_TBFLAG_DEBUG;
 782         }
 783         if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
 784             *flags |= XTENSA_TBFLAG_ICOUNT;
 785         }
 786     }
 787     if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
 788         *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
 789     }
 790     if (cs->singlestep_enabled && env->exception_taken) {
 791         *flags |= XTENSA_TBFLAG_EXCEPTION;
 792     }
 793     if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
 794         (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) {
 795         uint32_t windowstart = xtensa_replicate_windowstart(env) >>
 796             (env->sregs[WINDOW_BASE] + 1);
 797         uint32_t w = ctz32(windowstart | 0x8);
 798
 799         *flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE;
 800         *flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT,
 801                             PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT;
 802     } else {
 803         *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
 804     }
 805     if (env->yield_needed) {
 806         *flags |= XTENSA_TBFLAG_YIELD;
 807     }
 808 }
 809
 810 #include "exec/cpu-all.h"
 811
 812 #endif