hw/net/stellaris_enet.c

   1 /*
   2  * Luminary Micro Stellaris Ethernet Controller
   3  *
   4  * Copyright (c) 2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9 #include "qemu/osdep.h"
  10 #include "hw/sysbus.h"
  11 #include "net/net.h"
  12 #include "qemu/log.h"
  13 #include <zlib.h>
  14
  15 //#define DEBUG_STELLARIS_ENET 1
  16
  17 #ifdef DEBUG_STELLARIS_ENET
  18 #define DPRINTF(fmt, ...) \
  19 do { printf("stellaris_enet: " fmt , ## __VA_ARGS__); } while (0)
  20 #define BADF(fmt, ...) \
  21 do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
  22 #else
  23 #define DPRINTF(fmt, ...) do {} while(0)
  24 #define BADF(fmt, ...) \
  25 do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__);} while (0)
  26 #endif
  27
  28 #define SE_INT_RX       0x01
  29 #define SE_INT_TXER     0x02
  30 #define SE_INT_TXEMP    0x04
  31 #define SE_INT_FOV      0x08
  32 #define SE_INT_RXER     0x10
  33 #define SE_INT_MD       0x20
  34 #define SE_INT_PHY      0x40
  35
  36 #define SE_RCTL_RXEN    0x01
  37 #define SE_RCTL_AMUL    0x02
  38 #define SE_RCTL_PRMS    0x04
  39 #define SE_RCTL_BADCRC  0x08
  40 #define SE_RCTL_RSTFIFO 0x10
  41
  42 #define SE_TCTL_TXEN    0x01
  43 #define SE_TCTL_PADEN   0x02
  44 #define SE_TCTL_CRC     0x04
  45 #define SE_TCTL_DUPLEX  0x08
  46
  47 #define TYPE_STELLARIS_ENET "stellaris_enet"
  48 #define STELLARIS_ENET(obj) \
  49     OBJECT_CHECK(stellaris_enet_state, (obj), TYPE_STELLARIS_ENET)
  50
  51 typedef struct {
  52     uint8_t data[2048];
  53     uint32_t len;
  54 } StellarisEnetRxFrame;
  55
  56 typedef struct {
  57     SysBusDevice parent_obj;
  58
  59     uint32_t ris;
  60     uint32_t im;
  61     uint32_t rctl;
  62     uint32_t tctl;
  63     uint32_t thr;
  64     uint32_t mctl;
  65     uint32_t mdv;
  66     uint32_t mtxd;
  67     uint32_t mrxd;
  68     uint32_t np;
  69     uint32_t tx_fifo_len;
  70     uint8_t tx_fifo[2048];
  71     /* Real hardware has a 2k fifo, which works out to be at most 31 packets.
  72        We implement a full 31 packet fifo.  */
  73     StellarisEnetRxFrame rx[31];
  74     uint32_t rx_fifo_offset;
  75     uint32_t next_packet;
  76     NICState *nic;
  77     NICConf conf;
  78     qemu_irq irq;
  79     MemoryRegion mmio;
  80 } stellaris_enet_state;
  81
  82 static const VMStateDescription vmstate_rx_frame = {
  83     .name = "stellaris_enet/rx_frame",
  84     .version_id = 1,
  85     .minimum_version_id = 1,
  86     .fields = (VMStateField[]) {
  87         VMSTATE_UINT8_ARRAY(data, StellarisEnetRxFrame, 2048),
  88         VMSTATE_UINT32(len, StellarisEnetRxFrame),
  89         VMSTATE_END_OF_LIST()
  90     }
  91 };
  92
  93 static int stellaris_enet_post_load(void *opaque, int version_id)
  94 {
  95     stellaris_enet_state *s = opaque;
  96     int i;
  97
  98     /* Sanitize inbound state. Note that next_packet is an index but
  99      * np is a size; hence their valid upper bounds differ.
 100      */
 101     if (s->next_packet >= ARRAY_SIZE(s->rx)) {
 102         return -1;
 103     }
 104
 105     if (s->np > ARRAY_SIZE(s->rx)) {
 106         return -1;
 107     }
 108
 109     for (i = 0; i < ARRAY_SIZE(s->rx); i++) {
 110         if (s->rx[i].len > ARRAY_SIZE(s->rx[i].data)) {
 111             return -1;
 112         }
 113     }
 114
 115     if (s->rx_fifo_offset > ARRAY_SIZE(s->rx[0].data) - 4) {
 116         return -1;
 117     }
 118
 119     if (s->tx_fifo_len > ARRAY_SIZE(s->tx_fifo)) {
 120         return -1;
 121     }
 122
 123     return 0;
 124 }
 125
 126 static const VMStateDescription vmstate_stellaris_enet = {
 127     .name = "stellaris_enet",
 128     .version_id = 2,
 129     .minimum_version_id = 2,
 130     .post_load = stellaris_enet_post_load,
 131     .fields = (VMStateField[]) {
 132         VMSTATE_UINT32(ris, stellaris_enet_state),
 133         VMSTATE_UINT32(im, stellaris_enet_state),
 134         VMSTATE_UINT32(rctl, stellaris_enet_state),
 135         VMSTATE_UINT32(tctl, stellaris_enet_state),
 136         VMSTATE_UINT32(thr, stellaris_enet_state),
 137         VMSTATE_UINT32(mctl, stellaris_enet_state),
 138         VMSTATE_UINT32(mdv, stellaris_enet_state),
 139         VMSTATE_UINT32(mtxd, stellaris_enet_state),
 140         VMSTATE_UINT32(mrxd, stellaris_enet_state),
 141         VMSTATE_UINT32(np, stellaris_enet_state),
 142         VMSTATE_UINT32(tx_fifo_len, stellaris_enet_state),
 143         VMSTATE_UINT8_ARRAY(tx_fifo, stellaris_enet_state, 2048),
 144         VMSTATE_STRUCT_ARRAY(rx, stellaris_enet_state, 31, 1,
 145                              vmstate_rx_frame, StellarisEnetRxFrame),
 146         VMSTATE_UINT32(rx_fifo_offset, stellaris_enet_state),
 147         VMSTATE_UINT32(next_packet, stellaris_enet_state),
 148         VMSTATE_END_OF_LIST()
 149     }
 150 };
 151
 152 static void stellaris_enet_update(stellaris_enet_state *s)
 153 {
 154     qemu_set_irq(s->irq, (s->ris & s->im) != 0);
 155 }
 156
 157 /* Return the data length of the packet currently being assembled
 158  * in the TX fifo.
 159  */
 160 static inline int stellaris_txpacket_datalen(stellaris_enet_state *s)
 161 {
 162     return s->tx_fifo[0] | (s->tx_fifo[1] << 8);
 163 }
 164
 165 /* Return true if the packet currently in the TX FIFO is complete,
 166 * ie the FIFO holds enough bytes for the data length, ethernet header,
 167 * payload and optionally CRC.
 168 */
 169 static inline bool stellaris_txpacket_complete(stellaris_enet_state *s)
 170 {
 171     int framelen = stellaris_txpacket_datalen(s);
 172     framelen += 16;
 173     if (!(s->tctl & SE_TCTL_CRC)) {
 174         framelen += 4;
 175     }
 176     /* Cover the corner case of a 2032 byte payload with auto-CRC disabled:
 177      * this requires more bytes than will fit in the FIFO. It's not totally
 178      * clear how the h/w handles this, but if using threshold-based TX
 179      * it will definitely try to transmit something.
 180      */
 181     framelen = MIN(framelen, ARRAY_SIZE(s->tx_fifo));
 182     return s->tx_fifo_len >= framelen;
 183 }
 184
 185 /* Return true if the TX FIFO threshold is enabled and the FIFO
 186  * has filled enough to reach it.
 187  */
 188 static inline bool stellaris_tx_thr_reached(stellaris_enet_state *s)
 189 {
 190     return (s->thr < 0x3f &&
 191             (s->tx_fifo_len >= 4 * (s->thr * 8 + 1)));
 192 }
 193
 194 /* Send the packet currently in the TX FIFO */
 195 static void stellaris_enet_send(stellaris_enet_state *s)
 196 {
 197     int framelen = stellaris_txpacket_datalen(s);
 198
 199     /* Ethernet header is in the FIFO but not in the datacount.
 200      * We don't implement explicit CRC, so just ignore any
 201      * CRC value in the FIFO.
 202      */
 203     framelen += 14;
 204     if ((s->tctl & SE_TCTL_PADEN) && framelen < 60) {
 205         memset(&s->tx_fifo[framelen + 2], 0, 60 - framelen);
 206         framelen = 60;
 207     }
 208     /* This MIN will have no effect unless the FIFO data is corrupt
 209      * (eg bad data from an incoming migration); otherwise the check
 210      * on the datalen at the start of writing the data into the FIFO
 211      * will have caught this. Silently write a corrupt half-packet,
 212      * which is what the hardware does in FIFO underrun situations.
 213      */
 214     framelen = MIN(framelen, ARRAY_SIZE(s->tx_fifo) - 2);
 215     qemu_send_packet(qemu_get_queue(s->nic), s->tx_fifo + 2, framelen);
 216     s->tx_fifo_len = 0;
 217     s->ris |= SE_INT_TXEMP;
 218     stellaris_enet_update(s);
 219     DPRINTF("Done TX\n");
 220 }
 221
 222 /* TODO: Implement MAC address filtering.  */
 223 static ssize_t stellaris_enet_receive(NetClientState *nc, const uint8_t *buf, size_t size)
 224 {
 225     stellaris_enet_state *s = qemu_get_nic_opaque(nc);
 226     int n;
 227     uint8_t *p;
 228     uint32_t crc;
 229
 230     if ((s->rctl & SE_RCTL_RXEN) == 0)
 231         return -1;
 232     if (s->np >= 31) {
 233         return 0;
 234     }
 235
 236     DPRINTF("Received packet len=%zu\n", size);
 237     n = s->next_packet + s->np;
 238     if (n >= 31)
 239         n -= 31;
 240
 241     if (size >= sizeof(s->rx[n].data) - 6) {
 242         /* If the packet won't fit into the
 243          * emulated 2K RAM, this is reported
 244          * as a FIFO overrun error.
 245          */
 246         s->ris |= SE_INT_FOV;
 247         stellaris_enet_update(s);
 248         return -1;
 249     }
 250
 251     s->np++;
 252     s->rx[n].len = size + 6;
 253     p = s->rx[n].data;
 254     *(p++) = (size + 6);
 255     *(p++) = (size + 6) >> 8;
 256     memcpy (p, buf, size);
 257     p += size;
 258     crc = crc32(~0, buf, size);
 259     *(p++) = crc;
 260     *(p++) = crc >> 8;
 261     *(p++) = crc >> 16;
 262     *(p++) = crc >> 24;
 263     /* Clear the remaining bytes in the last word.  */
 264     if ((size & 3) != 2) {
 265         memset(p, 0, (6 - size) & 3);
 266     }
 267
 268     s->ris |= SE_INT_RX;
 269     stellaris_enet_update(s);
 270
 271     return size;
 272 }
 273
 274 static int stellaris_enet_can_receive(stellaris_enet_state *s)
 275 {
 276     return (s->np < 31);
 277 }
 278
 279 static uint64_t stellaris_enet_read(void *opaque, hwaddr offset,
 280                                     unsigned size)
 281 {
 282     stellaris_enet_state *s = (stellaris_enet_state *)opaque;
 283     uint32_t val;
 284
 285     switch (offset) {
 286     case 0x00: /* RIS */
 287         DPRINTF("IRQ status %02x\n", s->ris);
 288         return s->ris;
 289     case 0x04: /* IM */
 290         return s->im;
 291     case 0x08: /* RCTL */
 292         return s->rctl;
 293     case 0x0c: /* TCTL */
 294         return s->tctl;
 295     case 0x10: /* DATA */
 296     {
 297         uint8_t *rx_fifo;
 298
 299         if (s->np == 0) {
 300             BADF("RX underflow\n");
 301             return 0;
 302         }
 303
 304         rx_fifo = s->rx[s->next_packet].data + s->rx_fifo_offset;
 305
 306         val = rx_fifo[0] | (rx_fifo[1] << 8) | (rx_fifo[2] << 16)
 307               | (rx_fifo[3] << 24);
 308         s->rx_fifo_offset += 4;
 309         if (s->rx_fifo_offset >= s->rx[s->next_packet].len) {
 310             s->rx_fifo_offset = 0;
 311             s->next_packet++;
 312             if (s->next_packet >= 31)
 313                 s->next_packet = 0;
 314             s->np--;
 315             DPRINTF("RX done np=%d\n", s->np);
 316             if (!s->np && stellaris_enet_can_receive(s)) {
 317                 qemu_flush_queued_packets(qemu_get_queue(s->nic));
 318             }
 319         }
 320         return val;
 321     }
 322     case 0x14: /* IA0 */
 323         return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8)
 324             | (s->conf.macaddr.a[2] << 16)
 325             | ((uint32_t)s->conf.macaddr.a[3] << 24);
 326     case 0x18: /* IA1 */
 327         return s->conf.macaddr.a[4] | (s->conf.macaddr.a[5] << 8);
 328     case 0x1c: /* THR */
 329         return s->thr;
 330     case 0x20: /* MCTL */
 331         return s->mctl;
 332     case 0x24: /* MDV */
 333         return s->mdv;
 334     case 0x28: /* MADD */
 335         return 0;
 336     case 0x2c: /* MTXD */
 337         return s->mtxd;
 338     case 0x30: /* MRXD */
 339         return s->mrxd;
 340     case 0x34: /* NP */
 341         return s->np;
 342     case 0x38: /* TR */
 343         return 0;
 344     case 0x3c: /* Undocumented: Timestamp? */
 345         return 0;
 346     default:
 347         qemu_log_mask(LOG_GUEST_ERROR, "stellaris_enet_rd%d: Illegal register"
 348                                        " 0x02%" HWADDR_PRIx "\n",
 349                       size * 8, offset);
 350         return 0;
 351     }
 352 }
 353
 354 static void stellaris_enet_write(void *opaque, hwaddr offset,
 355                                  uint64_t value, unsigned size)
 356 {
 357     stellaris_enet_state *s = (stellaris_enet_state *)opaque;
 358
 359     switch (offset) {
 360     case 0x00: /* IACK */
 361         s->ris &= ~value;
 362         DPRINTF("IRQ ack %02" PRIx64 "/%02x\n", value, s->ris);
 363         stellaris_enet_update(s);
 364         /* Clearing TXER also resets the TX fifo.  */
 365         if (value & SE_INT_TXER) {
 366             s->tx_fifo_len = 0;
 367         }
 368         break;
 369     case 0x04: /* IM */
 370         DPRINTF("IRQ mask %02" PRIx64 "/%02x\n", value, s->ris);
 371         s->im = value;
 372         stellaris_enet_update(s);
 373         break;
 374     case 0x08: /* RCTL */
 375         s->rctl = value;
 376         if (value & SE_RCTL_RSTFIFO) {
 377             s->np = 0;
 378             s->rx_fifo_offset = 0;
 379             stellaris_enet_update(s);
 380         }
 381         break;
 382     case 0x0c: /* TCTL */
 383         s->tctl = value;
 384         break;
 385     case 0x10: /* DATA */
 386         if (s->tx_fifo_len == 0) {
 387             /* The first word is special, it contains the data length */
 388             int framelen = value & 0xffff;
 389             if (framelen > 2032) {
 390                 DPRINTF("TX frame too long (%d)\n", framelen);
 391                 s->ris |= SE_INT_TXER;
 392                 stellaris_enet_update(s);
 393                 break;
 394             }
 395         }
 396
 397         if (s->tx_fifo_len + 4 <= ARRAY_SIZE(s->tx_fifo)) {
 398             s->tx_fifo[s->tx_fifo_len++] = value;
 399             s->tx_fifo[s->tx_fifo_len++] = value >> 8;
 400             s->tx_fifo[s->tx_fifo_len++] = value >> 16;
 401             s->tx_fifo[s->tx_fifo_len++] = value >> 24;
 402         }
 403
 404         if (stellaris_tx_thr_reached(s) && stellaris_txpacket_complete(s)) {
 405             stellaris_enet_send(s);
 406         }
 407         break;
 408     case 0x14: /* IA0 */
 409         s->conf.macaddr.a[0] = value;
 410         s->conf.macaddr.a[1] = value >> 8;
 411         s->conf.macaddr.a[2] = value >> 16;
 412         s->conf.macaddr.a[3] = value >> 24;
 413         break;
 414     case 0x18: /* IA1 */
 415         s->conf.macaddr.a[4] = value;
 416         s->conf.macaddr.a[5] = value >> 8;
 417         break;
 418     case 0x1c: /* THR */
 419         s->thr = value;
 420         break;
 421     case 0x20: /* MCTL */
 422         /* TODO: MII registers aren't modelled.
 423          * Clear START, indicating that the operation completes immediately.
 424          */
 425         s->mctl = value & ~1;
 426         break;
 427     case 0x24: /* MDV */
 428         s->mdv = value;
 429         break;
 430     case 0x28: /* MADD */
 431         /* ignored.  */
 432         break;
 433     case 0x2c: /* MTXD */
 434         s->mtxd = value & 0xff;
 435         break;
 436     case 0x38: /* TR */
 437         if (value & 1) {
 438             stellaris_enet_send(s);
 439         }
 440         break;
 441     case 0x30: /* MRXD */
 442     case 0x34: /* NP */
 443         /* Ignored.  */
 444     case 0x3c: /* Undocuented: Timestamp? */
 445         /* Ignored.  */
 446         break;
 447     default:
 448         qemu_log_mask(LOG_GUEST_ERROR, "stellaris_enet_wr%d: Illegal register "
 449                                        "0x02%" HWADDR_PRIx " = 0x%" PRIx64 "\n",
 450                       size * 8, offset, value);
 451     }
 452 }
 453
 454 static const MemoryRegionOps stellaris_enet_ops = {
 455     .read = stellaris_enet_read,
 456     .write = stellaris_enet_write,
 457     .endianness = DEVICE_NATIVE_ENDIAN,
 458 };
 459
 460 static void stellaris_enet_reset(DeviceState *dev)
 461 {
 462     stellaris_enet_state *s =  STELLARIS_ENET(dev);
 463
 464     s->mdv = 0x80;
 465     s->rctl = SE_RCTL_BADCRC;
 466     s->im = SE_INT_PHY | SE_INT_MD | SE_INT_RXER | SE_INT_FOV | SE_INT_TXEMP
 467             | SE_INT_TXER | SE_INT_RX;
 468     s->thr = 0x3f;
 469     s->tx_fifo_len = 0;
 470 }
 471
 472 static NetClientInfo net_stellaris_enet_info = {
 473     .type = NET_CLIENT_DRIVER_NIC,
 474     .size = sizeof(NICState),
 475     .receive = stellaris_enet_receive,
 476 };
 477
 478 static void stellaris_enet_realize(DeviceState *dev, Error **errp)
 479 {
 480     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 481     stellaris_enet_state *s = STELLARIS_ENET(dev);
 482
 483     memory_region_init_io(&s->mmio, OBJECT(s), &stellaris_enet_ops, s,
 484                           "stellaris_enet", 0x1000);
 485     sysbus_init_mmio(sbd, &s->mmio);
 486     sysbus_init_irq(sbd, &s->irq);
 487     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 488
 489     s->nic = qemu_new_nic(&net_stellaris_enet_info, &s->conf,
 490                           object_get_typename(OBJECT(dev)), dev->id, s);
 491     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 492 }
 493
 494 static Property stellaris_enet_properties[] = {
 495     DEFINE_NIC_PROPERTIES(stellaris_enet_state, conf),
 496     DEFINE_PROP_END_OF_LIST(),
 497 };
 498
 499 static void stellaris_enet_class_init(ObjectClass *klass, void *data)
 500 {
 501     DeviceClass *dc = DEVICE_CLASS(klass);
 502
 503     dc->realize = stellaris_enet_realize;
 504     dc->reset = stellaris_enet_reset;
 505     dc->props = stellaris_enet_properties;
 506     dc->vmsd = &vmstate_stellaris_enet;
 507 }
 508
 509 static const TypeInfo stellaris_enet_info = {
 510     .name          = TYPE_STELLARIS_ENET,
 511     .parent        = TYPE_SYS_BUS_DEVICE,
 512     .instance_size = sizeof(stellaris_enet_state),
 513     .class_init    = stellaris_enet_class_init,
 514 };
 515
 516 static void stellaris_enet_register_types(void)
 517 {
 518     type_register_static(&stellaris_enet_info);
 519 }
 520
 521 type_init(stellaris_enet_register_types)