4 * Generate helpers used by TCG for qemu_ld/st ops and code load
7 * Included from target op helpers and exec.c.
9 * Copyright (c) 2003 Fabrice Bellard
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or (at your option) any later version.
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #include "qemu/timer.h"
25 #include "exec/address-spaces.h"
26 #include "exec/memory.h"
28 #define DATA_SIZE (1 << SHIFT)
33 #define SDATA_TYPE int64_t
34 #define DATA_TYPE uint64_t
38 #define SDATA_TYPE int32_t
39 #define DATA_TYPE uint32_t
43 #define SDATA_TYPE int16_t
44 #define DATA_TYPE uint16_t
48 #define SDATA_TYPE int8_t
49 #define DATA_TYPE uint8_t
51 #error unsupported data size
55 /* For the benefit of TCG generated code, we want to avoid the complication
56 of ABI-specific return type promotion and always return a value extended
57 to the register size of the host. This is tcg_target_long, except in the
58 case of a 32-bit host and 64-bit data, and for that we always have
59 uint64_t. Don't bother with this widened value for SOFTMMU_CODE_ACCESS. */
60 #if defined(SOFTMMU_CODE_ACCESS) || DATA_SIZE == 8
61 # define WORD_TYPE DATA_TYPE
62 # define USUFFIX SUFFIX
64 # define WORD_TYPE tcg_target_ulong
65 # define USUFFIX glue(u, SUFFIX)
66 # define SSUFFIX glue(s, SUFFIX)
69 #ifdef SOFTMMU_CODE_ACCESS
70 #define READ_ACCESS_TYPE MMU_INST_FETCH
71 #define ADDR_READ addr_code
73 #define READ_ACCESS_TYPE MMU_DATA_LOAD
74 #define ADDR_READ addr_read
78 # define BSWAP(X) bswap64(X)
80 # define BSWAP(X) bswap32(X)
82 # define BSWAP(X) bswap16(X)
87 #ifdef TARGET_WORDS_BIGENDIAN
88 # define TGT_BE(X) (X)
89 # define TGT_LE(X) BSWAP(X)
91 # define TGT_BE(X) BSWAP(X)
92 # define TGT_LE(X) (X)
96 # define helper_le_ld_name glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)
97 # define helper_be_ld_name helper_le_ld_name
98 # define helper_le_lds_name glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX)
99 # define helper_be_lds_name helper_le_lds_name
100 # define helper_le_st_name glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)
101 # define helper_be_st_name helper_le_st_name
103 # define helper_le_ld_name glue(glue(helper_le_ld, USUFFIX), MMUSUFFIX)
104 # define helper_be_ld_name glue(glue(helper_be_ld, USUFFIX), MMUSUFFIX)
105 # define helper_le_lds_name glue(glue(helper_le_ld, SSUFFIX), MMUSUFFIX)
106 # define helper_be_lds_name glue(glue(helper_be_ld, SSUFFIX), MMUSUFFIX)
107 # define helper_le_st_name glue(glue(helper_le_st, SUFFIX), MMUSUFFIX)
108 # define helper_be_st_name glue(glue(helper_be_st, SUFFIX), MMUSUFFIX)
111 #ifdef TARGET_WORDS_BIGENDIAN
112 # define helper_te_ld_name helper_be_ld_name
113 # define helper_te_st_name helper_be_st_name
115 # define helper_te_ld_name helper_le_ld_name
116 # define helper_te_st_name helper_le_st_name
119 /* macro to check the victim tlb */
120 #define VICTIM_TLB_HIT(ty) \
122 /* we are about to do a page table walk. our last hope is the \
123 * victim tlb. try to refill from the victim tlb before walking the \
127 CPUTLBEntry tmptlb; \
128 for (vidx = CPU_VTLB_SIZE-1; vidx >= 0; --vidx) { \
129 if (env->tlb_v_table[mmu_idx][vidx].ty == (addr & TARGET_PAGE_MASK)) {\
130 /* found entry in victim tlb, swap tlb and iotlb */ \
131 tmptlb = env->tlb_table[mmu_idx][index]; \
132 env->tlb_table[mmu_idx][index] = env->tlb_v_table[mmu_idx][vidx]; \
133 env->tlb_v_table[mmu_idx][vidx] = tmptlb; \
134 tmpiotlb = env->iotlb[mmu_idx][index]; \
135 env->iotlb[mmu_idx][index] = env->iotlb_v[mmu_idx][vidx]; \
136 env->iotlb_v[mmu_idx][vidx] = tmpiotlb; \
140 /* return true when there is a vtlb hit, i.e. vidx >=0 */ \
144 #ifndef SOFTMMU_CODE_ACCESS
145 static inline DATA_TYPE
glue(io_read
, SUFFIX
)(CPUArchState
*env
,
151 CPUState
*cpu
= ENV_GET_CPU(env
);
152 MemoryRegion
*mr
= iotlb_to_region(cpu
, physaddr
);
154 physaddr
= (physaddr
& TARGET_PAGE_MASK
) + addr
;
155 cpu
->mem_io_pc
= retaddr
;
156 if (mr
!= &io_mem_rom
&& mr
!= &io_mem_notdirty
&& !cpu_can_do_io(cpu
)) {
157 cpu_io_recompile(cpu
, retaddr
);
160 cpu
->mem_io_vaddr
= addr
;
161 io_mem_read(mr
, physaddr
, &val
, 1 << SHIFT
);
166 #ifdef SOFTMMU_CODE_ACCESS
167 static __attribute__((unused
))
169 WORD_TYPE
helper_le_ld_name(CPUArchState
*env
, target_ulong addr
, int mmu_idx
,
172 int index
= (addr
>> TARGET_PAGE_BITS
) & (CPU_TLB_SIZE
- 1);
173 target_ulong tlb_addr
= env
->tlb_table
[mmu_idx
][index
].ADDR_READ
;
177 /* Adjust the given return address. */
178 retaddr
-= GETPC_ADJ
;
180 /* If the TLB entry is for a different page, reload and try again. */
181 if ((addr
& TARGET_PAGE_MASK
)
182 != (tlb_addr
& (TARGET_PAGE_MASK
| TLB_INVALID_MASK
))) {
184 if ((addr
& (DATA_SIZE
- 1)) != 0) {
185 cpu_unaligned_access(ENV_GET_CPU(env
), addr
, READ_ACCESS_TYPE
,
189 if (!VICTIM_TLB_HIT(ADDR_READ
)) {
190 tlb_fill(ENV_GET_CPU(env
), addr
, READ_ACCESS_TYPE
,
193 tlb_addr
= env
->tlb_table
[mmu_idx
][index
].ADDR_READ
;
196 /* Handle an IO access. */
197 if (unlikely(tlb_addr
& ~TARGET_PAGE_MASK
)) {
199 if ((addr
& (DATA_SIZE
- 1)) != 0) {
200 goto do_unaligned_access
;
202 ioaddr
= env
->iotlb
[mmu_idx
][index
];
204 /* ??? Note that the io helpers always read data in the target
205 byte ordering. We should push the LE/BE request down into io. */
206 res
= glue(io_read
, SUFFIX
)(env
, ioaddr
, addr
, retaddr
);
211 /* Handle slow unaligned access (it spans two pages or IO). */
213 && unlikely((addr
& ~TARGET_PAGE_MASK
) + DATA_SIZE
- 1
214 >= TARGET_PAGE_SIZE
)) {
215 target_ulong addr1
, addr2
;
216 DATA_TYPE res1
, res2
;
220 cpu_unaligned_access(ENV_GET_CPU(env
), addr
, READ_ACCESS_TYPE
,
223 addr1
= addr
& ~(DATA_SIZE
- 1);
224 addr2
= addr1
+ DATA_SIZE
;
225 /* Note the adjustment at the beginning of the function.
226 Undo that for the recursion. */
227 res1
= helper_le_ld_name(env
, addr1
, mmu_idx
, retaddr
+ GETPC_ADJ
);
228 res2
= helper_le_ld_name(env
, addr2
, mmu_idx
, retaddr
+ GETPC_ADJ
);
229 shift
= (addr
& (DATA_SIZE
- 1)) * 8;
231 /* Little-endian combine. */
232 res
= (res1
>> shift
) | (res2
<< ((DATA_SIZE
* 8) - shift
));
236 /* Handle aligned access or unaligned access in the same page. */
238 if ((addr
& (DATA_SIZE
- 1)) != 0) {
239 cpu_unaligned_access(ENV_GET_CPU(env
), addr
, READ_ACCESS_TYPE
,
244 haddr
= addr
+ env
->tlb_table
[mmu_idx
][index
].addend
;
246 res
= glue(glue(ld
, LSUFFIX
), _p
)((uint8_t *)haddr
);
248 res
= glue(glue(ld
, LSUFFIX
), _le_p
)((uint8_t *)haddr
);
254 #ifdef SOFTMMU_CODE_ACCESS
255 static __attribute__((unused
))
257 WORD_TYPE
helper_be_ld_name(CPUArchState
*env
, target_ulong addr
, int mmu_idx
,
260 int index
= (addr
>> TARGET_PAGE_BITS
) & (CPU_TLB_SIZE
- 1);
261 target_ulong tlb_addr
= env
->tlb_table
[mmu_idx
][index
].ADDR_READ
;
265 /* Adjust the given return address. */
266 retaddr
-= GETPC_ADJ
;
268 /* If the TLB entry is for a different page, reload and try again. */
269 if ((addr
& TARGET_PAGE_MASK
)
270 != (tlb_addr
& (TARGET_PAGE_MASK
| TLB_INVALID_MASK
))) {
272 if ((addr
& (DATA_SIZE
- 1)) != 0) {
273 cpu_unaligned_access(ENV_GET_CPU(env
), addr
, READ_ACCESS_TYPE
,
277 if (!VICTIM_TLB_HIT(ADDR_READ
)) {
278 tlb_fill(ENV_GET_CPU(env
), addr
, READ_ACCESS_TYPE
,
281 tlb_addr
= env
->tlb_table
[mmu_idx
][index
].ADDR_READ
;
284 /* Handle an IO access. */
285 if (unlikely(tlb_addr
& ~TARGET_PAGE_MASK
)) {
287 if ((addr
& (DATA_SIZE
- 1)) != 0) {
288 goto do_unaligned_access
;
290 ioaddr
= env
->iotlb
[mmu_idx
][index
];
292 /* ??? Note that the io helpers always read data in the target
293 byte ordering. We should push the LE/BE request down into io. */
294 res
= glue(io_read
, SUFFIX
)(env
, ioaddr
, addr
, retaddr
);
299 /* Handle slow unaligned access (it spans two pages or IO). */
301 && unlikely((addr
& ~TARGET_PAGE_MASK
) + DATA_SIZE
- 1
302 >= TARGET_PAGE_SIZE
)) {
303 target_ulong addr1
, addr2
;
304 DATA_TYPE res1
, res2
;
308 cpu_unaligned_access(ENV_GET_CPU(env
), addr
, READ_ACCESS_TYPE
,
311 addr1
= addr
& ~(DATA_SIZE
- 1);
312 addr2
= addr1
+ DATA_SIZE
;
313 /* Note the adjustment at the beginning of the function.
314 Undo that for the recursion. */
315 res1
= helper_be_ld_name(env
, addr1
, mmu_idx
, retaddr
+ GETPC_ADJ
);
316 res2
= helper_be_ld_name(env
, addr2
, mmu_idx
, retaddr
+ GETPC_ADJ
);
317 shift
= (addr
& (DATA_SIZE
- 1)) * 8;
319 /* Big-endian combine. */
320 res
= (res1
<< shift
) | (res2
>> ((DATA_SIZE
* 8) - shift
));
324 /* Handle aligned access or unaligned access in the same page. */
326 if ((addr
& (DATA_SIZE
- 1)) != 0) {
327 cpu_unaligned_access(ENV_GET_CPU(env
), addr
, READ_ACCESS_TYPE
,
332 haddr
= addr
+ env
->tlb_table
[mmu_idx
][index
].addend
;
333 res
= glue(glue(ld
, LSUFFIX
), _be_p
)((uint8_t *)haddr
);
336 #endif /* DATA_SIZE > 1 */
339 glue(glue(helper_ld
, SUFFIX
), MMUSUFFIX
)(CPUArchState
*env
, target_ulong addr
,
342 return helper_te_ld_name (env
, addr
, mmu_idx
, GETRA());
345 #ifndef SOFTMMU_CODE_ACCESS
347 /* Provide signed versions of the load routines as well. We can of course
348 avoid this for 64-bit data, or for 32-bit data on 32-bit host. */
349 #if DATA_SIZE * 8 < TCG_TARGET_REG_BITS
350 WORD_TYPE
helper_le_lds_name(CPUArchState
*env
, target_ulong addr
,
351 int mmu_idx
, uintptr_t retaddr
)
353 return (SDATA_TYPE
)helper_le_ld_name(env
, addr
, mmu_idx
, retaddr
);
357 WORD_TYPE
helper_be_lds_name(CPUArchState
*env
, target_ulong addr
,
358 int mmu_idx
, uintptr_t retaddr
)
360 return (SDATA_TYPE
)helper_be_ld_name(env
, addr
, mmu_idx
, retaddr
);
365 static inline void glue(io_write
, SUFFIX
)(CPUArchState
*env
,
371 CPUState
*cpu
= ENV_GET_CPU(env
);
372 MemoryRegion
*mr
= iotlb_to_region(cpu
, physaddr
);
374 physaddr
= (physaddr
& TARGET_PAGE_MASK
) + addr
;
375 if (mr
!= &io_mem_rom
&& mr
!= &io_mem_notdirty
&& !cpu_can_do_io(cpu
)) {
376 cpu_io_recompile(cpu
, retaddr
);
379 cpu
->mem_io_vaddr
= addr
;
380 cpu
->mem_io_pc
= retaddr
;
381 io_mem_write(mr
, physaddr
, val
, 1 << SHIFT
);
384 void helper_le_st_name(CPUArchState
*env
, target_ulong addr
, DATA_TYPE val
,
385 int mmu_idx
, uintptr_t retaddr
)
387 int index
= (addr
>> TARGET_PAGE_BITS
) & (CPU_TLB_SIZE
- 1);
388 target_ulong tlb_addr
= env
->tlb_table
[mmu_idx
][index
].addr_write
;
391 /* Adjust the given return address. */
392 retaddr
-= GETPC_ADJ
;
394 /* If the TLB entry is for a different page, reload and try again. */
395 if ((addr
& TARGET_PAGE_MASK
)
396 != (tlb_addr
& (TARGET_PAGE_MASK
| TLB_INVALID_MASK
))) {
398 if ((addr
& (DATA_SIZE
- 1)) != 0) {
399 cpu_unaligned_access(ENV_GET_CPU(env
), addr
, MMU_DATA_STORE
,
403 if (!VICTIM_TLB_HIT(addr_write
)) {
404 tlb_fill(ENV_GET_CPU(env
), addr
, MMU_DATA_STORE
, mmu_idx
, retaddr
);
406 tlb_addr
= env
->tlb_table
[mmu_idx
][index
].addr_write
;
409 /* Handle an IO access. */
410 if (unlikely(tlb_addr
& ~TARGET_PAGE_MASK
)) {
412 if ((addr
& (DATA_SIZE
- 1)) != 0) {
413 goto do_unaligned_access
;
415 ioaddr
= env
->iotlb
[mmu_idx
][index
];
417 /* ??? Note that the io helpers always read data in the target
418 byte ordering. We should push the LE/BE request down into io. */
420 glue(io_write
, SUFFIX
)(env
, ioaddr
, val
, addr
, retaddr
);
424 /* Handle slow unaligned access (it spans two pages or IO). */
426 && unlikely((addr
& ~TARGET_PAGE_MASK
) + DATA_SIZE
- 1
427 >= TARGET_PAGE_SIZE
)) {
431 cpu_unaligned_access(ENV_GET_CPU(env
), addr
, MMU_DATA_STORE
,
434 /* XXX: not efficient, but simple */
435 /* Note: relies on the fact that tlb_fill() does not remove the
436 * previous page from the TLB cache. */
437 for (i
= DATA_SIZE
- 1; i
>= 0; i
--) {
438 /* Little-endian extract. */
439 uint8_t val8
= val
>> (i
* 8);
440 /* Note the adjustment at the beginning of the function.
441 Undo that for the recursion. */
442 glue(helper_ret_stb
, MMUSUFFIX
)(env
, addr
+ i
, val8
,
443 mmu_idx
, retaddr
+ GETPC_ADJ
);
448 /* Handle aligned access or unaligned access in the same page. */
450 if ((addr
& (DATA_SIZE
- 1)) != 0) {
451 cpu_unaligned_access(ENV_GET_CPU(env
), addr
, MMU_DATA_STORE
,
456 haddr
= addr
+ env
->tlb_table
[mmu_idx
][index
].addend
;
458 glue(glue(st
, SUFFIX
), _p
)((uint8_t *)haddr
, val
);
460 glue(glue(st
, SUFFIX
), _le_p
)((uint8_t *)haddr
, val
);
465 void helper_be_st_name(CPUArchState
*env
, target_ulong addr
, DATA_TYPE val
,
466 int mmu_idx
, uintptr_t retaddr
)
468 int index
= (addr
>> TARGET_PAGE_BITS
) & (CPU_TLB_SIZE
- 1);
469 target_ulong tlb_addr
= env
->tlb_table
[mmu_idx
][index
].addr_write
;
472 /* Adjust the given return address. */
473 retaddr
-= GETPC_ADJ
;
475 /* If the TLB entry is for a different page, reload and try again. */
476 if ((addr
& TARGET_PAGE_MASK
)
477 != (tlb_addr
& (TARGET_PAGE_MASK
| TLB_INVALID_MASK
))) {
479 if ((addr
& (DATA_SIZE
- 1)) != 0) {
480 cpu_unaligned_access(ENV_GET_CPU(env
), addr
, MMU_DATA_STORE
,
484 if (!VICTIM_TLB_HIT(addr_write
)) {
485 tlb_fill(ENV_GET_CPU(env
), addr
, MMU_DATA_STORE
, mmu_idx
, retaddr
);
487 tlb_addr
= env
->tlb_table
[mmu_idx
][index
].addr_write
;
490 /* Handle an IO access. */
491 if (unlikely(tlb_addr
& ~TARGET_PAGE_MASK
)) {
493 if ((addr
& (DATA_SIZE
- 1)) != 0) {
494 goto do_unaligned_access
;
496 ioaddr
= env
->iotlb
[mmu_idx
][index
];
498 /* ??? Note that the io helpers always read data in the target
499 byte ordering. We should push the LE/BE request down into io. */
501 glue(io_write
, SUFFIX
)(env
, ioaddr
, val
, addr
, retaddr
);
505 /* Handle slow unaligned access (it spans two pages or IO). */
507 && unlikely((addr
& ~TARGET_PAGE_MASK
) + DATA_SIZE
- 1
508 >= TARGET_PAGE_SIZE
)) {
512 cpu_unaligned_access(ENV_GET_CPU(env
), addr
, MMU_DATA_STORE
,
515 /* XXX: not efficient, but simple */
516 /* Note: relies on the fact that tlb_fill() does not remove the
517 * previous page from the TLB cache. */
518 for (i
= DATA_SIZE
- 1; i
>= 0; i
--) {
519 /* Big-endian extract. */
520 uint8_t val8
= val
>> (((DATA_SIZE
- 1) * 8) - (i
* 8));
521 /* Note the adjustment at the beginning of the function.
522 Undo that for the recursion. */
523 glue(helper_ret_stb
, MMUSUFFIX
)(env
, addr
+ i
, val8
,
524 mmu_idx
, retaddr
+ GETPC_ADJ
);
529 /* Handle aligned access or unaligned access in the same page. */
531 if ((addr
& (DATA_SIZE
- 1)) != 0) {
532 cpu_unaligned_access(ENV_GET_CPU(env
), addr
, MMU_DATA_STORE
,
537 haddr
= addr
+ env
->tlb_table
[mmu_idx
][index
].addend
;
538 glue(glue(st
, SUFFIX
), _be_p
)((uint8_t *)haddr
, val
);
540 #endif /* DATA_SIZE > 1 */
543 glue(glue(helper_st
, SUFFIX
), MMUSUFFIX
)(CPUArchState
*env
, target_ulong addr
,
544 DATA_TYPE val
, int mmu_idx
)
546 helper_te_st_name(env
, addr
, val
, mmu_idx
, GETRA());
549 #endif /* !defined(SOFTMMU_CODE_ACCESS) */
551 #undef READ_ACCESS_TYPE
567 #undef helper_le_ld_name
568 #undef helper_be_ld_name
569 #undef helper_le_lds_name
570 #undef helper_be_lds_name
571 #undef helper_le_st_name
572 #undef helper_be_st_name
573 #undef helper_te_ld_name
574 #undef helper_te_st_name