hw/net/ftgmac100.c

   1 /*
   2  * Faraday FTGMAC100 Gigabit Ethernet
   3  *
   4  * Copyright (C) 2016-2017, IBM Corporation.
   5  *
   6  * Based on Coldfire Fast Ethernet Controller emulation.
   7  *
   8  * Copyright (c) 2007 CodeSourcery.
   9  *
  10  * This code is licensed under the GPL version 2 or later. See the
  11  * COPYING file in the top-level directory.
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "hw/net/ftgmac100.h"
  16 #include "sysemu/dma.h"
  17 #include "qemu/log.h"
  18 #include "net/checksum.h"
  19 #include "net/eth.h"
  20 #include "hw/net/mii.h"
  21
  22 /* For crc32 */
  23 #include <zlib.h>
  24
  25 /*
  26  * FTGMAC100 registers
  27  */
  28 #define FTGMAC100_ISR             0x00
  29 #define FTGMAC100_IER             0x04
  30 #define FTGMAC100_MAC_MADR        0x08
  31 #define FTGMAC100_MAC_LADR        0x0c
  32 #define FTGMAC100_MATH0           0x10
  33 #define FTGMAC100_MATH1           0x14
  34 #define FTGMAC100_NPTXPD          0x18
  35 #define FTGMAC100_RXPD            0x1C
  36 #define FTGMAC100_NPTXR_BADR      0x20
  37 #define FTGMAC100_RXR_BADR        0x24
  38 #define FTGMAC100_HPTXPD          0x28
  39 #define FTGMAC100_HPTXR_BADR      0x2c
  40 #define FTGMAC100_ITC             0x30
  41 #define FTGMAC100_APTC            0x34
  42 #define FTGMAC100_DBLAC           0x38
  43 #define FTGMAC100_REVR            0x40
  44 #define FTGMAC100_FEAR1           0x44
  45 #define FTGMAC100_RBSR            0x4c
  46 #define FTGMAC100_TPAFCR          0x48
  47
  48 #define FTGMAC100_MACCR           0x50
  49 #define FTGMAC100_MACSR           0x54
  50 #define FTGMAC100_PHYCR           0x60
  51 #define FTGMAC100_PHYDATA         0x64
  52 #define FTGMAC100_FCR             0x68
  53
  54 /*
  55  * Interrupt status register & interrupt enable register
  56  */
  57 #define FTGMAC100_INT_RPKT_BUF    (1 << 0)
  58 #define FTGMAC100_INT_RPKT_FIFO   (1 << 1)
  59 #define FTGMAC100_INT_NO_RXBUF    (1 << 2)
  60 #define FTGMAC100_INT_RPKT_LOST   (1 << 3)
  61 #define FTGMAC100_INT_XPKT_ETH    (1 << 4)
  62 #define FTGMAC100_INT_XPKT_FIFO   (1 << 5)
  63 #define FTGMAC100_INT_NO_NPTXBUF  (1 << 6)
  64 #define FTGMAC100_INT_XPKT_LOST   (1 << 7)
  65 #define FTGMAC100_INT_AHB_ERR     (1 << 8)
  66 #define FTGMAC100_INT_PHYSTS_CHG  (1 << 9)
  67 #define FTGMAC100_INT_NO_HPTXBUF  (1 << 10)
  68
  69 /*
  70  * Automatic polling timer control register
  71  */
  72 #define FTGMAC100_APTC_RXPOLL_CNT(x)        ((x) & 0xf)
  73 #define FTGMAC100_APTC_RXPOLL_TIME_SEL      (1 << 4)
  74 #define FTGMAC100_APTC_TXPOLL_CNT(x)        (((x) >> 8) & 0xf)
  75 #define FTGMAC100_APTC_TXPOLL_TIME_SEL      (1 << 12)
  76
  77 /*
  78  * PHY control register
  79  */
  80 #define FTGMAC100_PHYCR_MIIRD               (1 << 26)
  81 #define FTGMAC100_PHYCR_MIIWR               (1 << 27)
  82
  83 #define FTGMAC100_PHYCR_DEV(x)              (((x) >> 16) & 0x1f)
  84 #define FTGMAC100_PHYCR_REG(x)              (((x) >> 21) & 0x1f)
  85
  86 /*
  87  * PHY data register
  88  */
  89 #define FTGMAC100_PHYDATA_MIIWDATA(x)       ((x) & 0xffff)
  90 #define FTGMAC100_PHYDATA_MIIRDATA(x)       (((x) >> 16) & 0xffff)
  91
  92 /*
  93  * Feature Register
  94  */
  95 #define FTGMAC100_REVR_NEW_MDIO_INTERFACE   (1 << 31)
  96
  97 /*
  98  * MAC control register
  99  */
 100 #define FTGMAC100_MACCR_TXDMA_EN         (1 << 0)
 101 #define FTGMAC100_MACCR_RXDMA_EN         (1 << 1)
 102 #define FTGMAC100_MACCR_TXMAC_EN         (1 << 2)
 103 #define FTGMAC100_MACCR_RXMAC_EN         (1 << 3)
 104 #define FTGMAC100_MACCR_RM_VLAN          (1 << 4)
 105 #define FTGMAC100_MACCR_HPTXR_EN         (1 << 5)
 106 #define FTGMAC100_MACCR_LOOP_EN          (1 << 6)
 107 #define FTGMAC100_MACCR_ENRX_IN_HALFTX   (1 << 7)
 108 #define FTGMAC100_MACCR_FULLDUP          (1 << 8)
 109 #define FTGMAC100_MACCR_GIGA_MODE        (1 << 9)
 110 #define FTGMAC100_MACCR_CRC_APD          (1 << 10) /* not needed */
 111 #define FTGMAC100_MACCR_RX_RUNT          (1 << 12)
 112 #define FTGMAC100_MACCR_JUMBO_LF         (1 << 13)
 113 #define FTGMAC100_MACCR_RX_ALL           (1 << 14)
 114 #define FTGMAC100_MACCR_HT_MULTI_EN      (1 << 15)
 115 #define FTGMAC100_MACCR_RX_MULTIPKT      (1 << 16)
 116 #define FTGMAC100_MACCR_RX_BROADPKT      (1 << 17)
 117 #define FTGMAC100_MACCR_DISCARD_CRCERR   (1 << 18)
 118 #define FTGMAC100_MACCR_FAST_MODE        (1 << 19)
 119 #define FTGMAC100_MACCR_SW_RST           (1 << 31)
 120
 121 /*
 122  * Transmit descriptor
 123  */
 124 #define FTGMAC100_TXDES0_TXBUF_SIZE(x)   ((x) & 0x3fff)
 125 #define FTGMAC100_TXDES0_EDOTR           (1 << 15)
 126 #define FTGMAC100_TXDES0_CRC_ERR         (1 << 19)
 127 #define FTGMAC100_TXDES0_LTS             (1 << 28)
 128 #define FTGMAC100_TXDES0_FTS             (1 << 29)
 129 #define FTGMAC100_TXDES0_EDOTR_ASPEED    (1 << 30)
 130 #define FTGMAC100_TXDES0_TXDMA_OWN       (1 << 31)
 131
 132 #define FTGMAC100_TXDES1_VLANTAG_CI(x)   ((x) & 0xffff)
 133 #define FTGMAC100_TXDES1_INS_VLANTAG     (1 << 16)
 134 #define FTGMAC100_TXDES1_TCP_CHKSUM      (1 << 17)
 135 #define FTGMAC100_TXDES1_UDP_CHKSUM      (1 << 18)
 136 #define FTGMAC100_TXDES1_IP_CHKSUM       (1 << 19)
 137 #define FTGMAC100_TXDES1_LLC             (1 << 22)
 138 #define FTGMAC100_TXDES1_TX2FIC          (1 << 30)
 139 #define FTGMAC100_TXDES1_TXIC            (1 << 31)
 140
 141 /*
 142  * Receive descriptor
 143  */
 144 #define FTGMAC100_RXDES0_VDBC            0x3fff
 145 #define FTGMAC100_RXDES0_EDORR           (1 << 15)
 146 #define FTGMAC100_RXDES0_MULTICAST       (1 << 16)
 147 #define FTGMAC100_RXDES0_BROADCAST       (1 << 17)
 148 #define FTGMAC100_RXDES0_RX_ERR          (1 << 18)
 149 #define FTGMAC100_RXDES0_CRC_ERR         (1 << 19)
 150 #define FTGMAC100_RXDES0_FTL             (1 << 20)
 151 #define FTGMAC100_RXDES0_RUNT            (1 << 21)
 152 #define FTGMAC100_RXDES0_RX_ODD_NB       (1 << 22)
 153 #define FTGMAC100_RXDES0_FIFO_FULL       (1 << 23)
 154 #define FTGMAC100_RXDES0_PAUSE_OPCODE    (1 << 24)
 155 #define FTGMAC100_RXDES0_PAUSE_FRAME     (1 << 25)
 156 #define FTGMAC100_RXDES0_LRS             (1 << 28)
 157 #define FTGMAC100_RXDES0_FRS             (1 << 29)
 158 #define FTGMAC100_RXDES0_EDORR_ASPEED    (1 << 30)
 159 #define FTGMAC100_RXDES0_RXPKT_RDY       (1 << 31)
 160
 161 #define FTGMAC100_RXDES1_VLANTAG_CI      0xffff
 162 #define FTGMAC100_RXDES1_PROT_MASK       (0x3 << 20)
 163 #define FTGMAC100_RXDES1_PROT_NONIP      (0x0 << 20)
 164 #define FTGMAC100_RXDES1_PROT_IP         (0x1 << 20)
 165 #define FTGMAC100_RXDES1_PROT_TCPIP      (0x2 << 20)
 166 #define FTGMAC100_RXDES1_PROT_UDPIP      (0x3 << 20)
 167 #define FTGMAC100_RXDES1_LLC             (1 << 22)
 168 #define FTGMAC100_RXDES1_DF              (1 << 23)
 169 #define FTGMAC100_RXDES1_VLANTAG_AVAIL   (1 << 24)
 170 #define FTGMAC100_RXDES1_TCP_CHKSUM_ERR  (1 << 25)
 171 #define FTGMAC100_RXDES1_UDP_CHKSUM_ERR  (1 << 26)
 172 #define FTGMAC100_RXDES1_IP_CHKSUM_ERR   (1 << 27)
 173
 174 /*
 175  * Receive and transmit Buffer Descriptor
 176  */
 177 typedef struct {
 178     uint32_t        des0;
 179     uint32_t        des1;
 180     uint32_t        des2;        /* not used by HW */
 181     uint32_t        des3;
 182 } FTGMAC100Desc;
 183
 184 /*
 185  * Specific RTL8211E MII Registers
 186  */
 187 #define RTL8211E_MII_PHYCR        16 /* PHY Specific Control */
 188 #define RTL8211E_MII_PHYSR        17 /* PHY Specific Status */
 189 #define RTL8211E_MII_INER         18 /* Interrupt Enable */
 190 #define RTL8211E_MII_INSR         19 /* Interrupt Status */
 191 #define RTL8211E_MII_RXERC        24 /* Receive Error Counter */
 192 #define RTL8211E_MII_LDPSR        27 /* Link Down Power Saving */
 193 #define RTL8211E_MII_EPAGSR       30 /* Extension Page Select */
 194 #define RTL8211E_MII_PAGSEL       31 /* Page Select */
 195
 196 /*
 197  * RTL8211E Interrupt Status
 198  */
 199 #define PHY_INT_AUTONEG_ERROR       (1 << 15)
 200 #define PHY_INT_PAGE_RECV           (1 << 12)
 201 #define PHY_INT_AUTONEG_COMPLETE    (1 << 11)
 202 #define PHY_INT_LINK_STATUS         (1 << 10)
 203 #define PHY_INT_ERROR               (1 << 9)
 204 #define PHY_INT_DOWN                (1 << 8)
 205 #define PHY_INT_JABBER              (1 << 0)
 206
 207 /*
 208  * Max frame size for the receiving buffer
 209  */
 210 #define FTGMAC100_MAX_FRAME_SIZE    10240
 211
 212 /* Limits depending on the type of the frame
 213  *
 214  *   9216 for Jumbo frames (+ 4 for VLAN)
 215  *   1518 for other frames (+ 4 for VLAN)
 216  */
 217 static int ftgmac100_max_frame_size(FTGMAC100State *s)
 218 {
 219     return (s->maccr & FTGMAC100_MACCR_JUMBO_LF ? 9216 : 1518) + 4;
 220 }
 221
 222 static void ftgmac100_update_irq(FTGMAC100State *s)
 223 {
 224     qemu_set_irq(s->irq, s->isr & s->ier);
 225 }
 226
 227 /*
 228  * The MII phy could raise a GPIO to the processor which in turn
 229  * could be handled as an interrpt by the OS.
 230  * For now we don't handle any GPIO/interrupt line, so the OS will
 231  * have to poll for the PHY status.
 232  */
 233 static void phy_update_irq(FTGMAC100State *s)
 234 {
 235     ftgmac100_update_irq(s);
 236 }
 237
 238 static void phy_update_link(FTGMAC100State *s)
 239 {
 240     /* Autonegotiation status mirrors link status.  */
 241     if (qemu_get_queue(s->nic)->link_down) {
 242         s->phy_status &= ~(MII_BMSR_LINK_ST | MII_BMSR_AN_COMP);
 243         s->phy_int |= PHY_INT_DOWN;
 244     } else {
 245         s->phy_status |= (MII_BMSR_LINK_ST | MII_BMSR_AN_COMP);
 246         s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
 247     }
 248     phy_update_irq(s);
 249 }
 250
 251 static void ftgmac100_set_link(NetClientState *nc)
 252 {
 253     phy_update_link(FTGMAC100(qemu_get_nic_opaque(nc)));
 254 }
 255
 256 static void phy_reset(FTGMAC100State *s)
 257 {
 258     s->phy_status = (MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD |
 259                      MII_BMSR_10T_HD | MII_BMSR_EXTSTAT | MII_BMSR_MFPS |
 260                      MII_BMSR_AN_COMP | MII_BMSR_AUTONEG | MII_BMSR_LINK_ST |
 261                      MII_BMSR_EXTCAP);
 262     s->phy_control = (MII_BMCR_AUTOEN | MII_BMCR_FD | MII_BMCR_SPEED1000);
 263     s->phy_advertise = (MII_ANAR_PAUSE_ASYM | MII_ANAR_PAUSE | MII_ANAR_TXFD |
 264                         MII_ANAR_TX | MII_ANAR_10FD | MII_ANAR_10 |
 265                         MII_ANAR_CSMACD);
 266     s->phy_int_mask = 0;
 267     s->phy_int = 0;
 268 }
 269
 270 static uint32_t do_phy_read(FTGMAC100State *s, int reg)
 271 {
 272     uint32_t val;
 273
 274     switch (reg) {
 275     case MII_BMCR: /* Basic Control */
 276         val = s->phy_control;
 277         break;
 278     case MII_BMSR: /* Basic Status */
 279         val = s->phy_status;
 280         break;
 281     case MII_PHYID1: /* ID1 */
 282         val = RTL8211E_PHYID1;
 283         break;
 284     case MII_PHYID2: /* ID2 */
 285         val = RTL8211E_PHYID2;
 286         break;
 287     case MII_ANAR: /* Auto-neg advertisement */
 288         val = s->phy_advertise;
 289         break;
 290     case MII_ANLPAR: /* Auto-neg Link Partner Ability */
 291         val = (MII_ANLPAR_ACK | MII_ANLPAR_PAUSE | MII_ANLPAR_TXFD |
 292                MII_ANLPAR_TX | MII_ANLPAR_10FD | MII_ANLPAR_10 |
 293                MII_ANLPAR_CSMACD);
 294         break;
 295     case MII_ANER: /* Auto-neg Expansion */
 296         val = MII_ANER_NWAY;
 297         break;
 298     case MII_CTRL1000: /* 1000BASE-T control  */
 299         val = (MII_CTRL1000_HALF | MII_CTRL1000_FULL);
 300         break;
 301     case MII_STAT1000: /* 1000BASE-T status  */
 302         val = MII_STAT1000_FULL;
 303         break;
 304     case RTL8211E_MII_INSR:  /* Interrupt status.  */
 305         val = s->phy_int;
 306         s->phy_int = 0;
 307         phy_update_irq(s);
 308         break;
 309     case RTL8211E_MII_INER:  /* Interrupt enable */
 310         val = s->phy_int_mask;
 311         break;
 312     case RTL8211E_MII_PHYCR:
 313     case RTL8211E_MII_PHYSR:
 314     case RTL8211E_MII_RXERC:
 315     case RTL8211E_MII_LDPSR:
 316     case RTL8211E_MII_EPAGSR:
 317     case RTL8211E_MII_PAGSEL:
 318         qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
 319                       __func__, reg);
 320         val = 0;
 321         break;
 322     default:
 323         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
 324                       __func__, reg);
 325         val = 0;
 326         break;
 327     }
 328
 329     return val;
 330 }
 331
 332 #define MII_BMCR_MASK (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 |          \
 333                        MII_BMCR_SPEED | MII_BMCR_AUTOEN | MII_BMCR_PDOWN | \
 334                        MII_BMCR_FD | MII_BMCR_CTST)
 335 #define MII_ANAR_MASK 0x2d7f
 336
 337 static void do_phy_write(FTGMAC100State *s, int reg, uint32_t val)
 338 {
 339     switch (reg) {
 340     case MII_BMCR:     /* Basic Control */
 341         if (val & MII_BMCR_RESET) {
 342             phy_reset(s);
 343         } else {
 344             s->phy_control = val & MII_BMCR_MASK;
 345             /* Complete autonegotiation immediately.  */
 346             if (val & MII_BMCR_AUTOEN) {
 347                 s->phy_status |= MII_BMSR_AN_COMP;
 348             }
 349         }
 350         break;
 351     case MII_ANAR:     /* Auto-neg advertisement */
 352         s->phy_advertise = (val & MII_ANAR_MASK) | MII_ANAR_TX;
 353         break;
 354     case RTL8211E_MII_INER: /* Interrupt enable */
 355         s->phy_int_mask = val & 0xff;
 356         phy_update_irq(s);
 357         break;
 358     case RTL8211E_MII_PHYCR:
 359     case RTL8211E_MII_PHYSR:
 360     case RTL8211E_MII_RXERC:
 361     case RTL8211E_MII_LDPSR:
 362     case RTL8211E_MII_EPAGSR:
 363     case RTL8211E_MII_PAGSEL:
 364         qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
 365                       __func__, reg);
 366         break;
 367     default:
 368         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
 369                       __func__, reg);
 370         break;
 371     }
 372 }
 373
 374 static int ftgmac100_read_bd(FTGMAC100Desc *bd, dma_addr_t addr)
 375 {
 376     if (dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd))) {
 377         qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read descriptor @ 0x%"
 378                       HWADDR_PRIx "\n", __func__, addr);
 379         return -1;
 380     }
 381     bd->des0 = le32_to_cpu(bd->des0);
 382     bd->des1 = le32_to_cpu(bd->des1);
 383     bd->des2 = le32_to_cpu(bd->des2);
 384     bd->des3 = le32_to_cpu(bd->des3);
 385     return 0;
 386 }
 387
 388 static int ftgmac100_write_bd(FTGMAC100Desc *bd, dma_addr_t addr)
 389 {
 390     FTGMAC100Desc lebd;
 391
 392     lebd.des0 = cpu_to_le32(bd->des0);
 393     lebd.des1 = cpu_to_le32(bd->des1);
 394     lebd.des2 = cpu_to_le32(bd->des2);
 395     lebd.des3 = cpu_to_le32(bd->des3);
 396     if (dma_memory_write(&address_space_memory, addr, &lebd, sizeof(lebd))) {
 397         qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to write descriptor @ 0x%"
 398                       HWADDR_PRIx "\n", __func__, addr);
 399         return -1;
 400     }
 401     return 0;
 402 }
 403
 404 static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,
 405                             uint32_t tx_descriptor)
 406 {
 407     int frame_size = 0;
 408     uint8_t *ptr = s->frame;
 409     uint32_t addr = tx_descriptor;
 410     uint32_t flags = 0;
 411     int max_frame_size = ftgmac100_max_frame_size(s);
 412
 413     while (1) {
 414         FTGMAC100Desc bd;
 415         int len;
 416
 417         if (ftgmac100_read_bd(&bd, addr) ||
 418             ((bd.des0 & FTGMAC100_TXDES0_TXDMA_OWN) == 0)) {
 419             /* Run out of descriptors to transmit.  */
 420             s->isr |= FTGMAC100_INT_NO_NPTXBUF;
 421             break;
 422         }
 423
 424         /* record transmit flags as they are valid only on the first
 425          * segment */
 426         if (bd.des0 & FTGMAC100_TXDES0_FTS) {
 427             flags = bd.des1;
 428         }
 429
 430         len = bd.des0 & 0x3FFF;
 431         if (frame_size + len > max_frame_size) {
 432             qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %d bytes\n",
 433                           __func__, len);
 434             len = max_frame_size - frame_size;
 435         }
 436
 437         if (dma_memory_read(&address_space_memory, bd.des3, ptr, len)) {
 438             qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read packet @ 0x%x\n",
 439                           __func__, bd.des3);
 440             s->isr |= FTGMAC100_INT_NO_NPTXBUF;
 441             break;
 442         }
 443
 444         ptr += len;
 445         frame_size += len;
 446         if (bd.des0 & FTGMAC100_TXDES0_LTS) {
 447             if (flags & FTGMAC100_TXDES1_IP_CHKSUM) {
 448                 net_checksum_calculate(s->frame, frame_size);
 449             }
 450             /* Last buffer in frame.  */
 451             qemu_send_packet(qemu_get_queue(s->nic), s->frame, frame_size);
 452             ptr = s->frame;
 453             frame_size = 0;
 454             if (flags & FTGMAC100_TXDES1_TXIC) {
 455                 s->isr |= FTGMAC100_INT_XPKT_ETH;
 456             }
 457         }
 458
 459         if (flags & FTGMAC100_TXDES1_TX2FIC) {
 460             s->isr |= FTGMAC100_INT_XPKT_FIFO;
 461         }
 462         bd.des0 &= ~FTGMAC100_TXDES0_TXDMA_OWN;
 463
 464         /* Write back the modified descriptor.  */
 465         ftgmac100_write_bd(&bd, addr);
 466         /* Advance to the next descriptor.  */
 467         if (bd.des0 & s->txdes0_edotr) {
 468             addr = tx_ring;
 469         } else {
 470             addr += sizeof(FTGMAC100Desc);
 471         }
 472     }
 473
 474     s->tx_descriptor = addr;
 475
 476     ftgmac100_update_irq(s);
 477 }
 478
 479 static int ftgmac100_can_receive(NetClientState *nc)
 480 {
 481     FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc));
 482     FTGMAC100Desc bd;
 483
 484     if ((s->maccr & (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN))
 485          != (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN)) {
 486         return 0;
 487     }
 488
 489     if (ftgmac100_read_bd(&bd, s->rx_descriptor)) {
 490         return 0;
 491     }
 492     return !(bd.des0 & FTGMAC100_RXDES0_RXPKT_RDY);
 493 }
 494
 495 /*
 496  * This is purely informative. The HW can poll the RW (and RX) ring
 497  * buffers for available descriptors but we don't need to trigger a
 498  * timer for that in qemu.
 499  */
 500 static uint32_t ftgmac100_rxpoll(FTGMAC100State *s)
 501 {
 502     /* Polling times :
 503      *
 504      * Speed      TIME_SEL=0    TIME_SEL=1
 505      *
 506      *    10         51.2 ms      819.2 ms
 507      *   100         5.12 ms      81.92 ms
 508      *  1000        1.024 ms     16.384 ms
 509      */
 510     static const int div[] = { 20, 200, 1000 };
 511
 512     uint32_t cnt = 1024 * FTGMAC100_APTC_RXPOLL_CNT(s->aptcr);
 513     uint32_t speed = (s->maccr & FTGMAC100_MACCR_FAST_MODE) ? 1 : 0;
 514     uint32_t period;
 515
 516     if (s->aptcr & FTGMAC100_APTC_RXPOLL_TIME_SEL) {
 517         cnt <<= 4;
 518     }
 519
 520     if (s->maccr & FTGMAC100_MACCR_GIGA_MODE) {
 521         speed = 2;
 522     }
 523
 524     period = cnt / div[speed];
 525
 526     return period;
 527 }
 528
 529 static void ftgmac100_reset(DeviceState *d)
 530 {
 531     FTGMAC100State *s = FTGMAC100(d);
 532
 533     /* Reset the FTGMAC100 */
 534     s->isr = 0;
 535     s->ier = 0;
 536     s->rx_enabled = 0;
 537     s->rx_ring = 0;
 538     s->rbsr = 0x640;
 539     s->rx_descriptor = 0;
 540     s->tx_ring = 0;
 541     s->tx_descriptor = 0;
 542     s->math[0] = 0;
 543     s->math[1] = 0;
 544     s->itc = 0;
 545     s->aptcr = 1;
 546     s->dblac = 0x00022f00;
 547     s->revr = 0;
 548     s->fear1 = 0;
 549     s->tpafcr = 0xf1;
 550
 551     s->maccr = 0;
 552     s->phycr = 0;
 553     s->phydata = 0;
 554     s->fcr = 0x400;
 555
 556     /* and the PHY */
 557     phy_reset(s);
 558 }
 559
 560 static uint64_t ftgmac100_read(void *opaque, hwaddr addr, unsigned size)
 561 {
 562     FTGMAC100State *s = FTGMAC100(opaque);
 563
 564     switch (addr & 0xff) {
 565     case FTGMAC100_ISR:
 566         return s->isr;
 567     case FTGMAC100_IER:
 568         return s->ier;
 569     case FTGMAC100_MAC_MADR:
 570         return (s->conf.macaddr.a[0] << 8)  | s->conf.macaddr.a[1];
 571     case FTGMAC100_MAC_LADR:
 572         return ((uint32_t) s->conf.macaddr.a[2] << 24) |
 573             (s->conf.macaddr.a[3] << 16) | (s->conf.macaddr.a[4] << 8) |
 574             s->conf.macaddr.a[5];
 575     case FTGMAC100_MATH0:
 576         return s->math[0];
 577     case FTGMAC100_MATH1:
 578         return s->math[1];
 579     case FTGMAC100_ITC:
 580         return s->itc;
 581     case FTGMAC100_DBLAC:
 582         return s->dblac;
 583     case FTGMAC100_REVR:
 584         return s->revr;
 585     case FTGMAC100_FEAR1:
 586         return s->fear1;
 587     case FTGMAC100_TPAFCR:
 588         return s->tpafcr;
 589     case FTGMAC100_FCR:
 590         return s->fcr;
 591     case FTGMAC100_MACCR:
 592         return s->maccr;
 593     case FTGMAC100_PHYCR:
 594         return s->phycr;
 595     case FTGMAC100_PHYDATA:
 596         return s->phydata;
 597
 598         /* We might want to support these one day */
 599     case FTGMAC100_HPTXPD: /* High Priority Transmit Poll Demand */
 600     case FTGMAC100_HPTXR_BADR: /* High Priority Transmit Ring Base Address */
 601     case FTGMAC100_MACSR: /* MAC Status Register (MACSR) */
 602         qemu_log_mask(LOG_UNIMP, "%s: read to unimplemented register 0x%"
 603                       HWADDR_PRIx "\n", __func__, addr);
 604         return 0;
 605     default:
 606         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset 0x%"
 607                       HWADDR_PRIx "\n", __func__, addr);
 608         return 0;
 609     }
 610 }
 611
 612 static void ftgmac100_write(void *opaque, hwaddr addr,
 613                           uint64_t value, unsigned size)
 614 {
 615     FTGMAC100State *s = FTGMAC100(opaque);
 616     int reg;
 617
 618     switch (addr & 0xff) {
 619     case FTGMAC100_ISR: /* Interrupt status */
 620         s->isr &= ~value;
 621         break;
 622     case FTGMAC100_IER: /* Interrupt control */
 623         s->ier = value;
 624         break;
 625     case FTGMAC100_MAC_MADR: /* MAC */
 626         s->conf.macaddr.a[0] = value >> 8;
 627         s->conf.macaddr.a[1] = value;
 628         break;
 629     case FTGMAC100_MAC_LADR:
 630         s->conf.macaddr.a[2] = value >> 24;
 631         s->conf.macaddr.a[3] = value >> 16;
 632         s->conf.macaddr.a[4] = value >> 8;
 633         s->conf.macaddr.a[5] = value;
 634         break;
 635     case FTGMAC100_MATH0: /* Multicast Address Hash Table 0 */
 636         s->math[0] = value;
 637         break;
 638     case FTGMAC100_MATH1: /* Multicast Address Hash Table 1 */
 639         s->math[1] = value;
 640         break;
 641     case FTGMAC100_ITC: /* TODO: Interrupt Timer Control */
 642         s->itc = value;
 643         break;
 644     case FTGMAC100_RXR_BADR: /* Ring buffer address */
 645         s->rx_ring = value;
 646         s->rx_descriptor = s->rx_ring;
 647         break;
 648
 649     case FTGMAC100_RBSR: /* DMA buffer size */
 650         s->rbsr = value;
 651         break;
 652
 653     case FTGMAC100_NPTXR_BADR: /* Transmit buffer address */
 654         s->tx_ring = value;
 655         s->tx_descriptor = s->tx_ring;
 656         break;
 657
 658     case FTGMAC100_NPTXPD: /* Trigger transmit */
 659         if ((s->maccr & (FTGMAC100_MACCR_TXDMA_EN | FTGMAC100_MACCR_TXMAC_EN))
 660             == (FTGMAC100_MACCR_TXDMA_EN | FTGMAC100_MACCR_TXMAC_EN)) {
 661             /* TODO: high priority tx ring */
 662             ftgmac100_do_tx(s, s->tx_ring, s->tx_descriptor);
 663         }
 664         if (ftgmac100_can_receive(qemu_get_queue(s->nic))) {
 665             qemu_flush_queued_packets(qemu_get_queue(s->nic));
 666         }
 667         break;
 668
 669     case FTGMAC100_RXPD: /* Receive Poll Demand Register */
 670         if (ftgmac100_can_receive(qemu_get_queue(s->nic))) {
 671             qemu_flush_queued_packets(qemu_get_queue(s->nic));
 672         }
 673         break;
 674
 675     case FTGMAC100_APTC: /* Automatic polling */
 676         s->aptcr = value;
 677
 678         if (FTGMAC100_APTC_RXPOLL_CNT(s->aptcr)) {
 679             ftgmac100_rxpoll(s);
 680         }
 681
 682         if (FTGMAC100_APTC_TXPOLL_CNT(s->aptcr)) {
 683             qemu_log_mask(LOG_UNIMP, "%s: no transmit polling\n", __func__);
 684         }
 685         break;
 686
 687     case FTGMAC100_MACCR: /* MAC Device control */
 688         s->maccr = value;
 689         if (value & FTGMAC100_MACCR_SW_RST) {
 690             ftgmac100_reset(DEVICE(s));
 691         }
 692
 693         if (ftgmac100_can_receive(qemu_get_queue(s->nic))) {
 694             qemu_flush_queued_packets(qemu_get_queue(s->nic));
 695         }
 696         break;
 697
 698     case FTGMAC100_PHYCR:  /* PHY Device control */
 699         reg = FTGMAC100_PHYCR_REG(value);
 700         s->phycr = value;
 701         if (value & FTGMAC100_PHYCR_MIIWR) {
 702             do_phy_write(s, reg, s->phydata & 0xffff);
 703             s->phycr &= ~FTGMAC100_PHYCR_MIIWR;
 704         } else {
 705             s->phydata = do_phy_read(s, reg) << 16;
 706             s->phycr &= ~FTGMAC100_PHYCR_MIIRD;
 707         }
 708         break;
 709     case FTGMAC100_PHYDATA:
 710         s->phydata = value & 0xffff;
 711         break;
 712     case FTGMAC100_DBLAC: /* DMA Burst Length and Arbitration Control */
 713         s->dblac = value;
 714         break;
 715     case FTGMAC100_REVR:  /* Feature Register */
 716         /* TODO: Only Old MDIO interface is supported */
 717         s->revr = value & ~FTGMAC100_REVR_NEW_MDIO_INTERFACE;
 718         break;
 719     case FTGMAC100_FEAR1: /* Feature Register 1 */
 720         s->fear1 = value;
 721         break;
 722     case FTGMAC100_TPAFCR: /* Transmit Priority Arbitration and FIFO Control */
 723         s->tpafcr = value;
 724         break;
 725     case FTGMAC100_FCR: /* Flow Control  */
 726         s->fcr  = value;
 727         break;
 728
 729     case FTGMAC100_HPTXPD: /* High Priority Transmit Poll Demand */
 730     case FTGMAC100_HPTXR_BADR: /* High Priority Transmit Ring Base Address */
 731     case FTGMAC100_MACSR: /* MAC Status Register (MACSR) */
 732         qemu_log_mask(LOG_UNIMP, "%s: write to unimplemented register 0x%"
 733                       HWADDR_PRIx "\n", __func__, addr);
 734         break;
 735     default:
 736         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset 0x%"
 737                       HWADDR_PRIx "\n", __func__, addr);
 738         break;
 739     }
 740
 741     ftgmac100_update_irq(s);
 742 }
 743
 744 static int ftgmac100_filter(FTGMAC100State *s, const uint8_t *buf, size_t len)
 745 {
 746     unsigned mcast_idx;
 747
 748     if (s->maccr & FTGMAC100_MACCR_RX_ALL) {
 749         return 1;
 750     }
 751
 752     switch (get_eth_packet_type(PKT_GET_ETH_HDR(buf))) {
 753     case ETH_PKT_BCAST:
 754         if (!(s->maccr & FTGMAC100_MACCR_RX_BROADPKT)) {
 755             return 0;
 756         }
 757         break;
 758     case ETH_PKT_MCAST:
 759         if (!(s->maccr & FTGMAC100_MACCR_RX_MULTIPKT)) {
 760             if (!(s->maccr & FTGMAC100_MACCR_HT_MULTI_EN)) {
 761                 return 0;
 762             }
 763
 764             /* TODO: this does not seem to work for ftgmac100 */
 765             mcast_idx = compute_mcast_idx(buf);
 766             if (!(s->math[mcast_idx / 32] & (1 << (mcast_idx % 32)))) {
 767                 return 0;
 768             }
 769         }
 770         break;
 771     case ETH_PKT_UCAST:
 772         if (memcmp(s->conf.macaddr.a, buf, 6)) {
 773             return 0;
 774         }
 775         break;
 776     }
 777
 778     return 1;
 779 }
 780
 781 static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
 782                                  size_t len)
 783 {
 784     FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc));
 785     FTGMAC100Desc bd;
 786     uint32_t flags = 0;
 787     uint32_t addr;
 788     uint32_t crc;
 789     uint32_t buf_addr;
 790     uint8_t *crc_ptr;
 791     uint32_t buf_len;
 792     size_t size = len;
 793     uint32_t first = FTGMAC100_RXDES0_FRS;
 794     int max_frame_size = ftgmac100_max_frame_size(s);
 795
 796     if ((s->maccr & (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN))
 797          != (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN)) {
 798         return -1;
 799     }
 800
 801     /* TODO : Pad to minimum Ethernet frame length */
 802     /* handle small packets.  */
 803     if (size < 10) {
 804         qemu_log_mask(LOG_GUEST_ERROR, "%s: dropped frame of %zd bytes\n",
 805                       __func__, size);
 806         return size;
 807     }
 808
 809     if (size < 64 && !(s->maccr & FTGMAC100_MACCR_RX_RUNT)) {
 810         qemu_log_mask(LOG_GUEST_ERROR, "%s: dropped runt frame of %zd bytes\n",
 811                       __func__, size);
 812         return size;
 813     }
 814
 815     if (!ftgmac100_filter(s, buf, size)) {
 816         return size;
 817     }
 818
 819     /* 4 bytes for the CRC.  */
 820     size += 4;
 821     crc = cpu_to_be32(crc32(~0, buf, size));
 822     crc_ptr = (uint8_t *) &crc;
 823
 824     /* Huge frames are truncated.  */
 825     if (size > max_frame_size) {
 826         size = max_frame_size;
 827         qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %zd bytes\n",
 828                       __func__, size);
 829         flags |= FTGMAC100_RXDES0_FTL;
 830     }
 831
 832     switch (get_eth_packet_type(PKT_GET_ETH_HDR(buf))) {
 833     case ETH_PKT_BCAST:
 834         flags |= FTGMAC100_RXDES0_BROADCAST;
 835         break;
 836     case ETH_PKT_MCAST:
 837         flags |= FTGMAC100_RXDES0_MULTICAST;
 838         break;
 839     case ETH_PKT_UCAST:
 840         break;
 841     }
 842
 843     addr = s->rx_descriptor;
 844     while (size > 0) {
 845         if (!ftgmac100_can_receive(nc)) {
 846             qemu_log_mask(LOG_GUEST_ERROR, "%s: Unexpected packet\n", __func__);
 847             return -1;
 848         }
 849
 850         if (ftgmac100_read_bd(&bd, addr) ||
 851             (bd.des0 & FTGMAC100_RXDES0_RXPKT_RDY)) {
 852             /* No descriptors available.  Bail out.  */
 853             qemu_log_mask(LOG_GUEST_ERROR, "%s: Lost end of frame\n",
 854                           __func__);
 855             s->isr |= FTGMAC100_INT_NO_RXBUF;
 856             break;
 857         }
 858         buf_len = (size <= s->rbsr) ? size : s->rbsr;
 859         bd.des0 |= buf_len & 0x3fff;
 860         size -= buf_len;
 861
 862         /* The last 4 bytes are the CRC.  */
 863         if (size < 4) {
 864             buf_len += size - 4;
 865         }
 866         buf_addr = bd.des3;
 867         dma_memory_write(&address_space_memory, buf_addr, buf, buf_len);
 868         buf += buf_len;
 869         if (size < 4) {
 870             dma_memory_write(&address_space_memory, buf_addr + buf_len,
 871                              crc_ptr, 4 - size);
 872             crc_ptr += 4 - size;
 873         }
 874
 875         bd.des0 |= first | FTGMAC100_RXDES0_RXPKT_RDY;
 876         first = 0;
 877         if (size == 0) {
 878             /* Last buffer in frame.  */
 879             bd.des0 |= flags | FTGMAC100_RXDES0_LRS;
 880             s->isr |= FTGMAC100_INT_RPKT_BUF;
 881         } else {
 882             s->isr |= FTGMAC100_INT_RPKT_FIFO;
 883         }
 884         ftgmac100_write_bd(&bd, addr);
 885         if (bd.des0 & s->rxdes0_edorr) {
 886             addr = s->rx_ring;
 887         } else {
 888             addr += sizeof(FTGMAC100Desc);
 889         }
 890     }
 891     s->rx_descriptor = addr;
 892
 893     ftgmac100_update_irq(s);
 894     return len;
 895 }
 896
 897 static const MemoryRegionOps ftgmac100_ops = {
 898     .read = ftgmac100_read,
 899     .write = ftgmac100_write,
 900     .valid.min_access_size = 4,
 901     .valid.max_access_size = 4,
 902     .endianness = DEVICE_LITTLE_ENDIAN,
 903 };
 904
 905 static void ftgmac100_cleanup(NetClientState *nc)
 906 {
 907     FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc));
 908
 909     s->nic = NULL;
 910 }
 911
 912 static NetClientInfo net_ftgmac100_info = {
 913     .type = NET_CLIENT_DRIVER_NIC,
 914     .size = sizeof(NICState),
 915     .can_receive = ftgmac100_can_receive,
 916     .receive = ftgmac100_receive,
 917     .cleanup = ftgmac100_cleanup,
 918     .link_status_changed = ftgmac100_set_link,
 919 };
 920
 921 static void ftgmac100_realize(DeviceState *dev, Error **errp)
 922 {
 923     FTGMAC100State *s = FTGMAC100(dev);
 924     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 925
 926     if (s->aspeed) {
 927         s->txdes0_edotr = FTGMAC100_TXDES0_EDOTR_ASPEED;
 928         s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR_ASPEED;
 929     } else {
 930         s->txdes0_edotr = FTGMAC100_TXDES0_EDOTR;
 931         s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR;
 932     }
 933
 934     memory_region_init_io(&s->iomem, OBJECT(dev), &ftgmac100_ops, s,
 935                           TYPE_FTGMAC100, 0x2000);
 936     sysbus_init_mmio(sbd, &s->iomem);
 937     sysbus_init_irq(sbd, &s->irq);
 938     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 939
 940     s->conf.peers.ncs[0] = nd_table[0].netdev;
 941
 942     s->nic = qemu_new_nic(&net_ftgmac100_info, &s->conf,
 943                           object_get_typename(OBJECT(dev)), DEVICE(dev)->id,
 944                           s);
 945     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 946
 947     s->frame = g_malloc(FTGMAC100_MAX_FRAME_SIZE);
 948 }
 949
 950 static const VMStateDescription vmstate_ftgmac100 = {
 951     .name = TYPE_FTGMAC100,
 952     .version_id = 1,
 953     .minimum_version_id = 1,
 954     .fields = (VMStateField[]) {
 955         VMSTATE_UINT32(irq_state, FTGMAC100State),
 956         VMSTATE_UINT32(isr, FTGMAC100State),
 957         VMSTATE_UINT32(ier, FTGMAC100State),
 958         VMSTATE_UINT32(rx_enabled, FTGMAC100State),
 959         VMSTATE_UINT32(rx_ring, FTGMAC100State),
 960         VMSTATE_UINT32(rbsr, FTGMAC100State),
 961         VMSTATE_UINT32(tx_ring, FTGMAC100State),
 962         VMSTATE_UINT32(rx_descriptor, FTGMAC100State),
 963         VMSTATE_UINT32(tx_descriptor, FTGMAC100State),
 964         VMSTATE_UINT32_ARRAY(math, FTGMAC100State, 2),
 965         VMSTATE_UINT32(itc, FTGMAC100State),
 966         VMSTATE_UINT32(aptcr, FTGMAC100State),
 967         VMSTATE_UINT32(dblac, FTGMAC100State),
 968         VMSTATE_UINT32(revr, FTGMAC100State),
 969         VMSTATE_UINT32(fear1, FTGMAC100State),
 970         VMSTATE_UINT32(tpafcr, FTGMAC100State),
 971         VMSTATE_UINT32(maccr, FTGMAC100State),
 972         VMSTATE_UINT32(phycr, FTGMAC100State),
 973         VMSTATE_UINT32(phydata, FTGMAC100State),
 974         VMSTATE_UINT32(fcr, FTGMAC100State),
 975         VMSTATE_UINT32(phy_status, FTGMAC100State),
 976         VMSTATE_UINT32(phy_control, FTGMAC100State),
 977         VMSTATE_UINT32(phy_advertise, FTGMAC100State),
 978         VMSTATE_UINT32(phy_int, FTGMAC100State),
 979         VMSTATE_UINT32(phy_int_mask, FTGMAC100State),
 980         VMSTATE_UINT32(txdes0_edotr, FTGMAC100State),
 981         VMSTATE_UINT32(rxdes0_edorr, FTGMAC100State),
 982         VMSTATE_END_OF_LIST()
 983     }
 984 };
 985
 986 static Property ftgmac100_properties[] = {
 987     DEFINE_PROP_BOOL("aspeed", FTGMAC100State, aspeed, false),
 988     DEFINE_NIC_PROPERTIES(FTGMAC100State, conf),
 989     DEFINE_PROP_END_OF_LIST(),
 990 };
 991
 992 static void ftgmac100_class_init(ObjectClass *klass, void *data)
 993 {
 994     DeviceClass *dc = DEVICE_CLASS(klass);
 995
 996     dc->vmsd = &vmstate_ftgmac100;
 997     dc->reset = ftgmac100_reset;
 998     dc->props = ftgmac100_properties;
 999     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
1000     dc->realize = ftgmac100_realize;
1001     dc->desc = "Faraday FTGMAC100 Gigabit Ethernet emulation";
1002 }
1003
1004 static const TypeInfo ftgmac100_info = {
1005     .name = TYPE_FTGMAC100,
1006     .parent = TYPE_SYS_BUS_DEVICE,
1007     .instance_size = sizeof(FTGMAC100State),
1008     .class_init = ftgmac100_class_init,
1009 };
1010
1011 static void ftgmac100_register_types(void)
1012 {
1013     type_register_static(&ftgmac100_info);
1014 }
1015
1016 type_init(ftgmac100_register_types)