hw/intc/xics.c

   1 /*
   2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
   3  *
   4  * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
   5  *
   6  * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qapi/error.h"
  30 #include "qemu-common.h"
  31 #include "cpu.h"
  32 #include "hw/hw.h"
  33 #include "trace.h"
  34 #include "qemu/timer.h"
  35 #include "hw/ppc/xics.h"
  36 #include "qemu/error-report.h"
  37 #include "qapi/visitor.h"
  38 #include "monitor/monitor.h"
  39 #include "hw/intc/intc.h"
  40
  41 void icp_pic_print_info(ICPState *icp, Monitor *mon)
  42 {
  43     int cpu_index = icp->cs ? icp->cs->cpu_index : -1;
  44
  45     if (!icp->output) {
  46         return;
  47     }
  48     monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
  49                    cpu_index, icp->xirr, icp->xirr_owner,
  50                    icp->pending_priority, icp->mfrr);
  51 }
  52
  53 void ics_pic_print_info(ICSState *ics, Monitor *mon)
  54 {
  55     uint32_t i;
  56
  57     monitor_printf(mon, "ICS %4x..%4x %p\n",
  58                    ics->offset, ics->offset + ics->nr_irqs - 1, ics);
  59
  60     if (!ics->irqs) {
  61         return;
  62     }
  63
  64     for (i = 0; i < ics->nr_irqs; i++) {
  65         ICSIRQState *irq = ics->irqs + i;
  66
  67         if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
  68             continue;
  69         }
  70         monitor_printf(mon, "  %4x %s %02x %02x\n",
  71                        ics->offset + i,
  72                        (irq->flags & XICS_FLAGS_IRQ_LSI) ?
  73                        "LSI" : "MSI",
  74                        irq->priority, irq->status);
  75     }
  76 }
  77
  78 /*
  79  * ICP: Presentation layer
  80  */
  81
  82 #define XISR_MASK  0x00ffffff
  83 #define CPPR_MASK  0xff000000
  84
  85 #define XISR(icp)   (((icp)->xirr) & XISR_MASK)
  86 #define CPPR(icp)   (((icp)->xirr) >> 24)
  87
  88 static void ics_reject(ICSState *ics, uint32_t nr)
  89 {
  90     ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
  91
  92     if (k->reject) {
  93         k->reject(ics, nr);
  94     }
  95 }
  96
  97 void ics_resend(ICSState *ics)
  98 {
  99     ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
 100
 101     if (k->resend) {
 102         k->resend(ics);
 103     }
 104 }
 105
 106 static void ics_eoi(ICSState *ics, int nr)
 107 {
 108     ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
 109
 110     if (k->eoi) {
 111         k->eoi(ics, nr);
 112     }
 113 }
 114
 115 static void icp_check_ipi(ICPState *icp)
 116 {
 117     if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) {
 118         return;
 119     }
 120
 121     trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr);
 122
 123     if (XISR(icp) && icp->xirr_owner) {
 124         ics_reject(icp->xirr_owner, XISR(icp));
 125     }
 126
 127     icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI;
 128     icp->pending_priority = icp->mfrr;
 129     icp->xirr_owner = NULL;
 130     qemu_irq_raise(icp->output);
 131 }
 132
 133 void icp_resend(ICPState *icp)
 134 {
 135     XICSFabric *xi = icp->xics;
 136     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 137
 138     if (icp->mfrr < CPPR(icp)) {
 139         icp_check_ipi(icp);
 140     }
 141
 142     xic->ics_resend(xi);
 143 }
 144
 145 void icp_set_cppr(ICPState *icp, uint8_t cppr)
 146 {
 147     uint8_t old_cppr;
 148     uint32_t old_xisr;
 149
 150     old_cppr = CPPR(icp);
 151     icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24);
 152
 153     if (cppr < old_cppr) {
 154         if (XISR(icp) && (cppr <= icp->pending_priority)) {
 155             old_xisr = XISR(icp);
 156             icp->xirr &= ~XISR_MASK; /* Clear XISR */
 157             icp->pending_priority = 0xff;
 158             qemu_irq_lower(icp->output);
 159             if (icp->xirr_owner) {
 160                 ics_reject(icp->xirr_owner, old_xisr);
 161                 icp->xirr_owner = NULL;
 162             }
 163         }
 164     } else {
 165         if (!XISR(icp)) {
 166             icp_resend(icp);
 167         }
 168     }
 169 }
 170
 171 void icp_set_mfrr(ICPState *icp, uint8_t mfrr)
 172 {
 173     icp->mfrr = mfrr;
 174     if (mfrr < CPPR(icp)) {
 175         icp_check_ipi(icp);
 176     }
 177 }
 178
 179 uint32_t icp_accept(ICPState *icp)
 180 {
 181     uint32_t xirr = icp->xirr;
 182
 183     qemu_irq_lower(icp->output);
 184     icp->xirr = icp->pending_priority << 24;
 185     icp->pending_priority = 0xff;
 186     icp->xirr_owner = NULL;
 187
 188     trace_xics_icp_accept(xirr, icp->xirr);
 189
 190     return xirr;
 191 }
 192
 193 uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr)
 194 {
 195     if (mfrr) {
 196         *mfrr = icp->mfrr;
 197     }
 198     return icp->xirr;
 199 }
 200
 201 void icp_eoi(ICPState *icp, uint32_t xirr)
 202 {
 203     XICSFabric *xi = icp->xics;
 204     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 205     ICSState *ics;
 206     uint32_t irq;
 207
 208     /* Send EOI -> ICS */
 209     icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
 210     trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr);
 211     irq = xirr & XISR_MASK;
 212
 213     ics = xic->ics_get(xi, irq);
 214     if (ics) {
 215         ics_eoi(ics, irq);
 216     }
 217     if (!XISR(icp)) {
 218         icp_resend(icp);
 219     }
 220 }
 221
 222 static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
 223 {
 224     ICPState *icp = xics_icp_get(ics->xics, server);
 225
 226     trace_xics_icp_irq(server, nr, priority);
 227
 228     if ((priority >= CPPR(icp))
 229         || (XISR(icp) && (icp->pending_priority <= priority))) {
 230         ics_reject(ics, nr);
 231     } else {
 232         if (XISR(icp) && icp->xirr_owner) {
 233             ics_reject(icp->xirr_owner, XISR(icp));
 234             icp->xirr_owner = NULL;
 235         }
 236         icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK);
 237         icp->xirr_owner = ics;
 238         icp->pending_priority = priority;
 239         trace_xics_icp_raise(icp->xirr, icp->pending_priority);
 240         qemu_irq_raise(icp->output);
 241     }
 242 }
 243
 244 static void icp_dispatch_pre_save(void *opaque)
 245 {
 246     ICPState *icp = opaque;
 247     ICPStateClass *info = ICP_GET_CLASS(icp);
 248
 249     if (info->pre_save) {
 250         info->pre_save(icp);
 251     }
 252 }
 253
 254 static int icp_dispatch_post_load(void *opaque, int version_id)
 255 {
 256     ICPState *icp = opaque;
 257     ICPStateClass *info = ICP_GET_CLASS(icp);
 258
 259     if (info->post_load) {
 260         return info->post_load(icp, version_id);
 261     }
 262
 263     return 0;
 264 }
 265
 266 static const VMStateDescription vmstate_icp_server = {
 267     .name = "icp/server",
 268     .version_id = 1,
 269     .minimum_version_id = 1,
 270     .pre_save = icp_dispatch_pre_save,
 271     .post_load = icp_dispatch_post_load,
 272     .fields = (VMStateField[]) {
 273         /* Sanity check */
 274         VMSTATE_UINT32(xirr, ICPState),
 275         VMSTATE_UINT8(pending_priority, ICPState),
 276         VMSTATE_UINT8(mfrr, ICPState),
 277         VMSTATE_END_OF_LIST()
 278     },
 279 };
 280
 281 static void icp_reset(void *dev)
 282 {
 283     ICPState *icp = ICP(dev);
 284     ICPStateClass *icpc = ICP_GET_CLASS(icp);
 285
 286     icp->xirr = 0;
 287     icp->pending_priority = 0xff;
 288     icp->mfrr = 0xff;
 289
 290     /* Make all outputs are deasserted */
 291     qemu_set_irq(icp->output, 0);
 292
 293     if (icpc->reset) {
 294         icpc->reset(icp);
 295     }
 296 }
 297
 298 static void icp_realize(DeviceState *dev, Error **errp)
 299 {
 300     ICPState *icp = ICP(dev);
 301     ICPStateClass *icpc = ICP_GET_CLASS(dev);
 302     PowerPCCPU *cpu;
 303     CPUPPCState *env;
 304     Object *obj;
 305     Error *err = NULL;
 306
 307     obj = object_property_get_link(OBJECT(dev), ICP_PROP_XICS, &err);
 308     if (!obj) {
 309         error_setg(errp, "%s: required link '" ICP_PROP_XICS "' not found: %s",
 310                    __func__, error_get_pretty(err));
 311         return;
 312     }
 313
 314     icp->xics = XICS_FABRIC(obj);
 315
 316     obj = object_property_get_link(OBJECT(dev), ICP_PROP_CPU, &err);
 317     if (!obj) {
 318         error_setg(errp, "%s: required link '" ICP_PROP_CPU "' not found: %s",
 319                    __func__, error_get_pretty(err));
 320         return;
 321     }
 322
 323     cpu = POWERPC_CPU(obj);
 324     cpu->intc = OBJECT(icp);
 325     icp->cs = CPU(obj);
 326
 327     env = &cpu->env;
 328     switch (PPC_INPUT(env)) {
 329     case PPC_FLAGS_INPUT_POWER7:
 330         icp->output = env->irq_inputs[POWER7_INPUT_INT];
 331         break;
 332
 333     case PPC_FLAGS_INPUT_970:
 334         icp->output = env->irq_inputs[PPC970_INPUT_INT];
 335         break;
 336
 337     default:
 338         error_setg(errp, "XICS interrupt controller does not support this CPU bus model");
 339         return;
 340     }
 341
 342     if (icpc->realize) {
 343         icpc->realize(icp, errp);
 344     }
 345
 346     qemu_register_reset(icp_reset, dev);
 347 }
 348
 349 static void icp_unrealize(DeviceState *dev, Error **errp)
 350 {
 351     qemu_unregister_reset(icp_reset, dev);
 352 }
 353
 354 static void icp_class_init(ObjectClass *klass, void *data)
 355 {
 356     DeviceClass *dc = DEVICE_CLASS(klass);
 357
 358     dc->vmsd = &vmstate_icp_server;
 359     dc->realize = icp_realize;
 360     dc->unrealize = icp_unrealize;
 361 }
 362
 363 static const TypeInfo icp_info = {
 364     .name = TYPE_ICP,
 365     .parent = TYPE_DEVICE,
 366     .instance_size = sizeof(ICPState),
 367     .class_init = icp_class_init,
 368     .class_size = sizeof(ICPStateClass),
 369 };
 370
 371 /*
 372  * ICS: Source layer
 373  */
 374 static void ics_simple_resend_msi(ICSState *ics, int srcno)
 375 {
 376     ICSIRQState *irq = ics->irqs + srcno;
 377
 378     /* FIXME: filter by server#? */
 379     if (irq->status & XICS_STATUS_REJECTED) {
 380         irq->status &= ~XICS_STATUS_REJECTED;
 381         if (irq->priority != 0xff) {
 382             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 383         }
 384     }
 385 }
 386
 387 static void ics_simple_resend_lsi(ICSState *ics, int srcno)
 388 {
 389     ICSIRQState *irq = ics->irqs + srcno;
 390
 391     if ((irq->priority != 0xff)
 392         && (irq->status & XICS_STATUS_ASSERTED)
 393         && !(irq->status & XICS_STATUS_SENT)) {
 394         irq->status |= XICS_STATUS_SENT;
 395         icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 396     }
 397 }
 398
 399 static void ics_simple_set_irq_msi(ICSState *ics, int srcno, int val)
 400 {
 401     ICSIRQState *irq = ics->irqs + srcno;
 402
 403     trace_xics_ics_simple_set_irq_msi(srcno, srcno + ics->offset);
 404
 405     if (val) {
 406         if (irq->priority == 0xff) {
 407             irq->status |= XICS_STATUS_MASKED_PENDING;
 408             trace_xics_masked_pending();
 409         } else  {
 410             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 411         }
 412     }
 413 }
 414
 415 static void ics_simple_set_irq_lsi(ICSState *ics, int srcno, int val)
 416 {
 417     ICSIRQState *irq = ics->irqs + srcno;
 418
 419     trace_xics_ics_simple_set_irq_lsi(srcno, srcno + ics->offset);
 420     if (val) {
 421         irq->status |= XICS_STATUS_ASSERTED;
 422     } else {
 423         irq->status &= ~XICS_STATUS_ASSERTED;
 424     }
 425     ics_simple_resend_lsi(ics, srcno);
 426 }
 427
 428 static void ics_simple_set_irq(void *opaque, int srcno, int val)
 429 {
 430     ICSState *ics = (ICSState *)opaque;
 431
 432     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 433         ics_simple_set_irq_lsi(ics, srcno, val);
 434     } else {
 435         ics_simple_set_irq_msi(ics, srcno, val);
 436     }
 437 }
 438
 439 static void ics_simple_write_xive_msi(ICSState *ics, int srcno)
 440 {
 441     ICSIRQState *irq = ics->irqs + srcno;
 442
 443     if (!(irq->status & XICS_STATUS_MASKED_PENDING)
 444         || (irq->priority == 0xff)) {
 445         return;
 446     }
 447
 448     irq->status &= ~XICS_STATUS_MASKED_PENDING;
 449     icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 450 }
 451
 452 static void ics_simple_write_xive_lsi(ICSState *ics, int srcno)
 453 {
 454     ics_simple_resend_lsi(ics, srcno);
 455 }
 456
 457 void ics_simple_write_xive(ICSState *ics, int srcno, int server,
 458                            uint8_t priority, uint8_t saved_priority)
 459 {
 460     ICSIRQState *irq = ics->irqs + srcno;
 461
 462     irq->server = server;
 463     irq->priority = priority;
 464     irq->saved_priority = saved_priority;
 465
 466     trace_xics_ics_simple_write_xive(ics->offset + srcno, srcno, server,
 467                                      priority);
 468
 469     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 470         ics_simple_write_xive_lsi(ics, srcno);
 471     } else {
 472         ics_simple_write_xive_msi(ics, srcno);
 473     }
 474 }
 475
 476 static void ics_simple_reject(ICSState *ics, uint32_t nr)
 477 {
 478     ICSIRQState *irq = ics->irqs + nr - ics->offset;
 479
 480     trace_xics_ics_simple_reject(nr, nr - ics->offset);
 481     if (irq->flags & XICS_FLAGS_IRQ_MSI) {
 482         irq->status |= XICS_STATUS_REJECTED;
 483     } else if (irq->flags & XICS_FLAGS_IRQ_LSI) {
 484         irq->status &= ~XICS_STATUS_SENT;
 485     }
 486 }
 487
 488 static void ics_simple_resend(ICSState *ics)
 489 {
 490     int i;
 491
 492     for (i = 0; i < ics->nr_irqs; i++) {
 493         /* FIXME: filter by server#? */
 494         if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
 495             ics_simple_resend_lsi(ics, i);
 496         } else {
 497             ics_simple_resend_msi(ics, i);
 498         }
 499     }
 500 }
 501
 502 static void ics_simple_eoi(ICSState *ics, uint32_t nr)
 503 {
 504     int srcno = nr - ics->offset;
 505     ICSIRQState *irq = ics->irqs + srcno;
 506
 507     trace_xics_ics_simple_eoi(nr);
 508
 509     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 510         irq->status &= ~XICS_STATUS_SENT;
 511     }
 512 }
 513
 514 static void ics_simple_reset(void *dev)
 515 {
 516     ICSState *ics = ICS_SIMPLE(dev);
 517     int i;
 518     uint8_t flags[ics->nr_irqs];
 519
 520     for (i = 0; i < ics->nr_irqs; i++) {
 521         flags[i] = ics->irqs[i].flags;
 522     }
 523
 524     memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
 525
 526     for (i = 0; i < ics->nr_irqs; i++) {
 527         ics->irqs[i].priority = 0xff;
 528         ics->irqs[i].saved_priority = 0xff;
 529         ics->irqs[i].flags = flags[i];
 530     }
 531 }
 532
 533 static void ics_simple_dispatch_pre_save(void *opaque)
 534 {
 535     ICSState *ics = opaque;
 536     ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
 537
 538     if (info->pre_save) {
 539         info->pre_save(ics);
 540     }
 541 }
 542
 543 static int ics_simple_dispatch_post_load(void *opaque, int version_id)
 544 {
 545     ICSState *ics = opaque;
 546     ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
 547
 548     if (info->post_load) {
 549         return info->post_load(ics, version_id);
 550     }
 551
 552     return 0;
 553 }
 554
 555 static const VMStateDescription vmstate_ics_simple_irq = {
 556     .name = "ics/irq",
 557     .version_id = 2,
 558     .minimum_version_id = 1,
 559     .fields = (VMStateField[]) {
 560         VMSTATE_UINT32(server, ICSIRQState),
 561         VMSTATE_UINT8(priority, ICSIRQState),
 562         VMSTATE_UINT8(saved_priority, ICSIRQState),
 563         VMSTATE_UINT8(status, ICSIRQState),
 564         VMSTATE_UINT8(flags, ICSIRQState),
 565         VMSTATE_END_OF_LIST()
 566     },
 567 };
 568
 569 static const VMStateDescription vmstate_ics_simple = {
 570     .name = "ics",
 571     .version_id = 1,
 572     .minimum_version_id = 1,
 573     .pre_save = ics_simple_dispatch_pre_save,
 574     .post_load = ics_simple_dispatch_post_load,
 575     .fields = (VMStateField[]) {
 576         /* Sanity check */
 577         VMSTATE_UINT32_EQUAL(nr_irqs, ICSState),
 578
 579         VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
 580                                              vmstate_ics_simple_irq,
 581                                              ICSIRQState),
 582         VMSTATE_END_OF_LIST()
 583     },
 584 };
 585
 586 static void ics_simple_initfn(Object *obj)
 587 {
 588     ICSState *ics = ICS_SIMPLE(obj);
 589
 590     ics->offset = XICS_IRQ_BASE;
 591 }
 592
 593 static void ics_simple_realize(ICSState *ics, Error **errp)
 594 {
 595     if (!ics->nr_irqs) {
 596         error_setg(errp, "Number of interrupts needs to be greater 0");
 597         return;
 598     }
 599     ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
 600     ics->qirqs = qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irqs);
 601
 602     qemu_register_reset(ics_simple_reset, ics);
 603 }
 604
 605 static Property ics_simple_properties[] = {
 606     DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
 607     DEFINE_PROP_END_OF_LIST(),
 608 };
 609
 610 static void ics_simple_class_init(ObjectClass *klass, void *data)
 611 {
 612     DeviceClass *dc = DEVICE_CLASS(klass);
 613     ICSStateClass *isc = ICS_BASE_CLASS(klass);
 614
 615     isc->realize = ics_simple_realize;
 616     dc->props = ics_simple_properties;
 617     dc->vmsd = &vmstate_ics_simple;
 618     isc->reject = ics_simple_reject;
 619     isc->resend = ics_simple_resend;
 620     isc->eoi = ics_simple_eoi;
 621 }
 622
 623 static const TypeInfo ics_simple_info = {
 624     .name = TYPE_ICS_SIMPLE,
 625     .parent = TYPE_ICS_BASE,
 626     .instance_size = sizeof(ICSState),
 627     .class_init = ics_simple_class_init,
 628     .class_size = sizeof(ICSStateClass),
 629     .instance_init = ics_simple_initfn,
 630 };
 631
 632 static void ics_base_realize(DeviceState *dev, Error **errp)
 633 {
 634     ICSStateClass *icsc = ICS_BASE_GET_CLASS(dev);
 635     ICSState *ics = ICS_BASE(dev);
 636     Object *obj;
 637     Error *err = NULL;
 638
 639     obj = object_property_get_link(OBJECT(dev), ICS_PROP_XICS, &err);
 640     if (!obj) {
 641         error_setg(errp, "%s: required link '" ICS_PROP_XICS "' not found: %s",
 642                    __func__, error_get_pretty(err));
 643         return;
 644     }
 645     ics->xics = XICS_FABRIC(obj);
 646
 647
 648     if (icsc->realize) {
 649         icsc->realize(ics, errp);
 650     }
 651 }
 652
 653 static void ics_base_class_init(ObjectClass *klass, void *data)
 654 {
 655     DeviceClass *dc = DEVICE_CLASS(klass);
 656
 657     dc->realize = ics_base_realize;
 658 }
 659
 660 static const TypeInfo ics_base_info = {
 661     .name = TYPE_ICS_BASE,
 662     .parent = TYPE_DEVICE,
 663     .abstract = true,
 664     .instance_size = sizeof(ICSState),
 665     .class_init = ics_base_class_init,
 666     .class_size = sizeof(ICSStateClass),
 667 };
 668
 669 static const TypeInfo xics_fabric_info = {
 670     .name = TYPE_XICS_FABRIC,
 671     .parent = TYPE_INTERFACE,
 672     .class_size = sizeof(XICSFabricClass),
 673 };
 674
 675 /*
 676  * Exported functions
 677  */
 678 qemu_irq xics_get_qirq(XICSFabric *xi, int irq)
 679 {
 680     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 681     ICSState *ics = xic->ics_get(xi, irq);
 682
 683     if (ics) {
 684         return ics->qirqs[irq - ics->offset];
 685     }
 686
 687     return NULL;
 688 }
 689
 690 ICPState *xics_icp_get(XICSFabric *xi, int server)
 691 {
 692     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 693
 694     return xic->icp_get(xi, server);
 695 }
 696
 697 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
 698 {
 699     assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
 700
 701     ics->irqs[srcno].flags |=
 702         lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
 703 }
 704
 705 static void xics_register_types(void)
 706 {
 707     type_register_static(&ics_simple_info);
 708     type_register_static(&ics_base_info);
 709     type_register_static(&icp_info);
 710     type_register_static(&xics_fabric_info);
 711 }
 712
 713 type_init(xics_register_types)