4 * Copyright (c) 2004 Jocelyn Mayer
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 * Based on OpenPic implementations:
28 * - Intel GW80314 I/O companion chip developer's manual
29 * - Motorola MPC8245 & MPC8540 user manuals.
30 * - Motorola MCP750 (aka Raven) programmer manual.
31 * - Motorola Harrier programmer manuel
33 * Serial interrupts, as implemented in Raven chipset are not supported yet.
36 #include "qemu/osdep.h"
38 #include "hw/ppc/mac.h"
39 #include "hw/pci/pci.h"
40 #include "hw/ppc/openpic.h"
41 #include "hw/ppc/ppc_e500.h"
42 #include "hw/sysbus.h"
43 #include "hw/pci/msi.h"
44 #include "qapi/error.h"
45 #include "qemu/bitops.h"
46 #include "qapi/qmp/qerror.h"
49 //#define DEBUG_OPENPIC
52 static const int debug_openpic
= 1;
54 static const int debug_openpic
= 0;
57 #define DPRINTF(fmt, ...) do { \
58 if (debug_openpic) { \
59 printf(fmt , ## __VA_ARGS__); \
65 #define VID 0x03 /* MPIC version ID */
67 /* OpenPIC capability flags */
68 #define OPENPIC_FLAG_IDR_CRIT (1 << 0)
69 #define OPENPIC_FLAG_ILR (2 << 0)
71 /* OpenPIC address map */
72 #define OPENPIC_GLB_REG_START 0x0
73 #define OPENPIC_GLB_REG_SIZE 0x10F0
74 #define OPENPIC_TMR_REG_START 0x10F0
75 #define OPENPIC_TMR_REG_SIZE 0x220
76 #define OPENPIC_MSI_REG_START 0x1600
77 #define OPENPIC_MSI_REG_SIZE 0x200
78 #define OPENPIC_SUMMARY_REG_START 0x3800
79 #define OPENPIC_SUMMARY_REG_SIZE 0x800
80 #define OPENPIC_SRC_REG_START 0x10000
81 #define OPENPIC_SRC_REG_SIZE (OPENPIC_MAX_SRC * 0x20)
82 #define OPENPIC_CPU_REG_START 0x20000
83 #define OPENPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000)
86 #define RAVEN_MAX_CPU 2
87 #define RAVEN_MAX_EXT 48
88 #define RAVEN_MAX_IRQ 64
89 #define RAVEN_MAX_TMR OPENPIC_MAX_TMR
90 #define RAVEN_MAX_IPI OPENPIC_MAX_IPI
92 /* Interrupt definitions */
93 #define RAVEN_FE_IRQ (RAVEN_MAX_EXT) /* Internal functional IRQ */
94 #define RAVEN_ERR_IRQ (RAVEN_MAX_EXT + 1) /* Error IRQ */
95 #define RAVEN_TMR_IRQ (RAVEN_MAX_EXT + 2) /* First timer IRQ */
96 #define RAVEN_IPI_IRQ (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */
97 /* First doorbell IRQ */
98 #define RAVEN_DBL_IRQ (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI))
100 typedef struct FslMpicInfo
{
104 static FslMpicInfo fsl_mpic_20
= {
108 static FslMpicInfo fsl_mpic_42
= {
112 #define FRR_NIRQ_SHIFT 16
113 #define FRR_NCPU_SHIFT 8
114 #define FRR_VID_SHIFT 0
116 #define VID_REVISION_1_2 2
117 #define VID_REVISION_1_3 3
119 #define VIR_GENERIC 0x00000000 /* Generic Vendor ID */
121 #define GCR_RESET 0x80000000
122 #define GCR_MODE_PASS 0x00000000
123 #define GCR_MODE_MIXED 0x20000000
124 #define GCR_MODE_PROXY 0x60000000
126 #define TBCR_CI 0x80000000 /* count inhibit */
127 #define TCCR_TOG 0x80000000 /* toggles when decrement to zero */
129 #define IDR_EP_SHIFT 31
130 #define IDR_EP_MASK (1U << IDR_EP_SHIFT)
131 #define IDR_CI0_SHIFT 30
132 #define IDR_CI1_SHIFT 29
133 #define IDR_P1_SHIFT 1
134 #define IDR_P0_SHIFT 0
136 #define ILR_INTTGT_MASK 0x000000ff
137 #define ILR_INTTGT_INT 0x00
138 #define ILR_INTTGT_CINT 0x01 /* critical */
139 #define ILR_INTTGT_MCP 0x02 /* machine check */
141 /* The currently supported INTTGT values happen to be the same as QEMU's
142 * openpic output codes, but don't depend on this. The output codes
143 * could change (unlikely, but...) or support could be added for
144 * more INTTGT values.
146 static const int inttgt_output
[][2] = {
147 { ILR_INTTGT_INT
, OPENPIC_OUTPUT_INT
},
148 { ILR_INTTGT_CINT
, OPENPIC_OUTPUT_CINT
},
149 { ILR_INTTGT_MCP
, OPENPIC_OUTPUT_MCK
},
152 static int inttgt_to_output(int inttgt
)
156 for (i
= 0; i
< ARRAY_SIZE(inttgt_output
); i
++) {
157 if (inttgt_output
[i
][0] == inttgt
) {
158 return inttgt_output
[i
][1];
162 fprintf(stderr
, "%s: unsupported inttgt %d\n", __func__
, inttgt
);
163 return OPENPIC_OUTPUT_INT
;
166 static int output_to_inttgt(int output
)
170 for (i
= 0; i
< ARRAY_SIZE(inttgt_output
); i
++) {
171 if (inttgt_output
[i
][1] == output
) {
172 return inttgt_output
[i
][0];
179 #define MSIIR_OFFSET 0x140
180 #define MSIIR_SRS_SHIFT 29
181 #define MSIIR_SRS_MASK (0x7 << MSIIR_SRS_SHIFT)
182 #define MSIIR_IBS_SHIFT 24
183 #define MSIIR_IBS_MASK (0x1f << MSIIR_IBS_SHIFT)
185 static int get_current_cpu(void)
191 return current_cpu
->cpu_index
;
194 static uint32_t openpic_cpu_read_internal(void *opaque
, hwaddr addr
,
196 static void openpic_cpu_write_internal(void *opaque
, hwaddr addr
,
197 uint32_t val
, int idx
);
198 static void openpic_reset(DeviceState
*d
);
200 typedef enum IRQType
{
202 IRQ_TYPE_FSLINT
, /* FSL internal interrupt -- level only */
203 IRQ_TYPE_FSLSPECIAL
, /* FSL timer/IPI interrupt, edge, no polarity */
206 /* Round up to the nearest 64 IRQs so that the queue length
207 * won't change when moving between 32 and 64 bit hosts.
209 #define IRQQUEUE_SIZE_BITS ((OPENPIC_MAX_IRQ + 63) & ~63)
211 typedef struct IRQQueue
{
212 unsigned long *queue
;
213 int32_t queue_size
; /* Only used for VMSTATE_BITMAP */
218 typedef struct IRQSource
{
219 uint32_t ivpr
; /* IRQ vector/priority register */
220 uint32_t idr
; /* IRQ destination register */
221 uint32_t destmask
; /* bitmap of CPU destinations */
223 int output
; /* IRQ level, e.g. OPENPIC_OUTPUT_INT */
224 int pending
; /* TRUE if IRQ is pending */
226 bool level
:1; /* level-triggered */
227 bool nomask
:1; /* critical interrupts ignore mask on some FSL MPICs */
230 #define IVPR_MASK_SHIFT 31
231 #define IVPR_MASK_MASK (1U << IVPR_MASK_SHIFT)
232 #define IVPR_ACTIVITY_SHIFT 30
233 #define IVPR_ACTIVITY_MASK (1U << IVPR_ACTIVITY_SHIFT)
234 #define IVPR_MODE_SHIFT 29
235 #define IVPR_MODE_MASK (1U << IVPR_MODE_SHIFT)
236 #define IVPR_POLARITY_SHIFT 23
237 #define IVPR_POLARITY_MASK (1U << IVPR_POLARITY_SHIFT)
238 #define IVPR_SENSE_SHIFT 22
239 #define IVPR_SENSE_MASK (1U << IVPR_SENSE_SHIFT)
241 #define IVPR_PRIORITY_MASK (0xFU << 16)
242 #define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16))
243 #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)
245 /* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */
246 #define IDR_EP 0x80000000 /* external pin */
247 #define IDR_CI 0x40000000 /* critical interrupt */
249 typedef struct OpenPICTimer
{
250 uint32_t tccr
; /* Global timer current count register */
251 uint32_t tbcr
; /* Global timer base count register */
254 typedef struct OpenPICMSI
{
255 uint32_t msir
; /* Shared Message Signaled Interrupt Register */
258 typedef struct IRQDest
{
259 int32_t ctpr
; /* CPU current task priority */
264 /* Count of IRQ sources asserting on non-INT outputs */
265 uint32_t outputs_active
[OPENPIC_OUTPUT_NB
];
268 #define OPENPIC(obj) OBJECT_CHECK(OpenPICState, (obj), TYPE_OPENPIC)
270 typedef struct OpenPICState
{
272 SysBusDevice parent_obj
;
277 /* Behavior control */
283 uint32_t vir
; /* Vendor identification register */
284 uint32_t vector_mask
;
289 uint32_t mpic_mode_mask
;
292 MemoryRegion sub_io_mem
[6];
294 /* Global registers */
295 uint32_t frr
; /* Feature reporting register */
296 uint32_t gcr
; /* Global configuration register */
297 uint32_t pir
; /* Processor initialization register */
298 uint32_t spve
; /* Spurious vector register */
299 uint32_t tfrr
; /* Timer frequency reporting register */
300 /* Source registers */
301 IRQSource src
[OPENPIC_MAX_IRQ
];
302 /* Local registers per output pin */
303 IRQDest dst
[MAX_CPU
];
305 /* Timer registers */
306 OpenPICTimer timers
[OPENPIC_MAX_TMR
];
307 /* Shared MSI registers */
308 OpenPICMSI msi
[MAX_MSI
];
315 static inline void IRQ_setbit(IRQQueue
*q
, int n_IRQ
)
317 set_bit(n_IRQ
, q
->queue
);
320 static inline void IRQ_resetbit(IRQQueue
*q
, int n_IRQ
)
322 clear_bit(n_IRQ
, q
->queue
);
325 static void IRQ_check(OpenPICState
*opp
, IRQQueue
*q
)
332 irq
= find_next_bit(q
->queue
, opp
->max_irq
, irq
+ 1);
333 if (irq
== opp
->max_irq
) {
337 DPRINTF("IRQ_check: irq %d set ivpr_pr=%d pr=%d\n",
338 irq
, IVPR_PRIORITY(opp
->src
[irq
].ivpr
), priority
);
340 if (IVPR_PRIORITY(opp
->src
[irq
].ivpr
) > priority
) {
342 priority
= IVPR_PRIORITY(opp
->src
[irq
].ivpr
);
347 q
->priority
= priority
;
350 static int IRQ_get_next(OpenPICState
*opp
, IRQQueue
*q
)
358 static void IRQ_local_pipe(OpenPICState
*opp
, int n_CPU
, int n_IRQ
,
359 bool active
, bool was_active
)
365 dst
= &opp
->dst
[n_CPU
];
366 src
= &opp
->src
[n_IRQ
];
368 DPRINTF("%s: IRQ %d active %d was %d\n",
369 __func__
, n_IRQ
, active
, was_active
);
371 if (src
->output
!= OPENPIC_OUTPUT_INT
) {
372 DPRINTF("%s: output %d irq %d active %d was %d count %d\n",
373 __func__
, src
->output
, n_IRQ
, active
, was_active
,
374 dst
->outputs_active
[src
->output
]);
376 /* On Freescale MPIC, critical interrupts ignore priority,
377 * IACK, EOI, etc. Before MPIC v4.1 they also ignore
381 if (!was_active
&& dst
->outputs_active
[src
->output
]++ == 0) {
382 DPRINTF("%s: Raise OpenPIC output %d cpu %d irq %d\n",
383 __func__
, src
->output
, n_CPU
, n_IRQ
);
384 qemu_irq_raise(dst
->irqs
[src
->output
]);
387 if (was_active
&& --dst
->outputs_active
[src
->output
] == 0) {
388 DPRINTF("%s: Lower OpenPIC output %d cpu %d irq %d\n",
389 __func__
, src
->output
, n_CPU
, n_IRQ
);
390 qemu_irq_lower(dst
->irqs
[src
->output
]);
397 priority
= IVPR_PRIORITY(src
->ivpr
);
399 /* Even if the interrupt doesn't have enough priority,
400 * it is still raised, in case ctpr is lowered later.
403 IRQ_setbit(&dst
->raised
, n_IRQ
);
405 IRQ_resetbit(&dst
->raised
, n_IRQ
);
408 IRQ_check(opp
, &dst
->raised
);
410 if (active
&& priority
<= dst
->ctpr
) {
411 DPRINTF("%s: IRQ %d priority %d too low for ctpr %d on CPU %d\n",
412 __func__
, n_IRQ
, priority
, dst
->ctpr
, n_CPU
);
417 if (IRQ_get_next(opp
, &dst
->servicing
) >= 0 &&
418 priority
<= dst
->servicing
.priority
) {
419 DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n",
420 __func__
, n_IRQ
, dst
->servicing
.next
, n_CPU
);
422 DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d/%d\n",
423 __func__
, n_CPU
, n_IRQ
, dst
->raised
.next
);
424 qemu_irq_raise(opp
->dst
[n_CPU
].irqs
[OPENPIC_OUTPUT_INT
]);
427 IRQ_get_next(opp
, &dst
->servicing
);
428 if (dst
->raised
.priority
> dst
->ctpr
&&
429 dst
->raised
.priority
> dst
->servicing
.priority
) {
430 DPRINTF("%s: IRQ %d inactive, IRQ %d prio %d above %d/%d, CPU %d\n",
431 __func__
, n_IRQ
, dst
->raised
.next
, dst
->raised
.priority
,
432 dst
->ctpr
, dst
->servicing
.priority
, n_CPU
);
433 /* IRQ line stays asserted */
435 DPRINTF("%s: IRQ %d inactive, current prio %d/%d, CPU %d\n",
436 __func__
, n_IRQ
, dst
->ctpr
, dst
->servicing
.priority
, n_CPU
);
437 qemu_irq_lower(opp
->dst
[n_CPU
].irqs
[OPENPIC_OUTPUT_INT
]);
442 /* update pic state because registers for n_IRQ have changed value */
443 static void openpic_update_irq(OpenPICState
*opp
, int n_IRQ
)
446 bool active
, was_active
;
449 src
= &opp
->src
[n_IRQ
];
450 active
= src
->pending
;
452 if ((src
->ivpr
& IVPR_MASK_MASK
) && !src
->nomask
) {
453 /* Interrupt source is disabled */
454 DPRINTF("%s: IRQ %d is disabled\n", __func__
, n_IRQ
);
458 was_active
= !!(src
->ivpr
& IVPR_ACTIVITY_MASK
);
461 * We don't have a similar check for already-active because
462 * ctpr may have changed and we need to withdraw the interrupt.
464 if (!active
&& !was_active
) {
465 DPRINTF("%s: IRQ %d is already inactive\n", __func__
, n_IRQ
);
470 src
->ivpr
|= IVPR_ACTIVITY_MASK
;
472 src
->ivpr
&= ~IVPR_ACTIVITY_MASK
;
475 if (src
->destmask
== 0) {
477 DPRINTF("%s: IRQ %d has no target\n", __func__
, n_IRQ
);
481 if (src
->destmask
== (1 << src
->last_cpu
)) {
482 /* Only one CPU is allowed to receive this IRQ */
483 IRQ_local_pipe(opp
, src
->last_cpu
, n_IRQ
, active
, was_active
);
484 } else if (!(src
->ivpr
& IVPR_MODE_MASK
)) {
485 /* Directed delivery mode */
486 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
487 if (src
->destmask
& (1 << i
)) {
488 IRQ_local_pipe(opp
, i
, n_IRQ
, active
, was_active
);
492 /* Distributed delivery mode */
493 for (i
= src
->last_cpu
+ 1; i
!= src
->last_cpu
; i
++) {
494 if (i
== opp
->nb_cpus
) {
497 if (src
->destmask
& (1 << i
)) {
498 IRQ_local_pipe(opp
, i
, n_IRQ
, active
, was_active
);
506 static void openpic_set_irq(void *opaque
, int n_IRQ
, int level
)
508 OpenPICState
*opp
= opaque
;
511 if (n_IRQ
>= OPENPIC_MAX_IRQ
) {
512 fprintf(stderr
, "%s: IRQ %d out of range\n", __func__
, n_IRQ
);
516 src
= &opp
->src
[n_IRQ
];
517 DPRINTF("openpic: set irq %d = %d ivpr=0x%08x\n",
518 n_IRQ
, level
, src
->ivpr
);
520 /* level-sensitive irq */
521 src
->pending
= level
;
522 openpic_update_irq(opp
, n_IRQ
);
524 /* edge-sensitive irq */
527 openpic_update_irq(opp
, n_IRQ
);
530 if (src
->output
!= OPENPIC_OUTPUT_INT
) {
531 /* Edge-triggered interrupts shouldn't be used
532 * with non-INT delivery, but just in case,
533 * try to make it do something sane rather than
534 * cause an interrupt storm. This is close to
535 * what you'd probably see happen in real hardware.
538 openpic_update_irq(opp
, n_IRQ
);
543 static inline uint32_t read_IRQreg_idr(OpenPICState
*opp
, int n_IRQ
)
545 return opp
->src
[n_IRQ
].idr
;
548 static inline uint32_t read_IRQreg_ilr(OpenPICState
*opp
, int n_IRQ
)
550 if (opp
->flags
& OPENPIC_FLAG_ILR
) {
551 return output_to_inttgt(opp
->src
[n_IRQ
].output
);
557 static inline uint32_t read_IRQreg_ivpr(OpenPICState
*opp
, int n_IRQ
)
559 return opp
->src
[n_IRQ
].ivpr
;
562 static inline void write_IRQreg_idr(OpenPICState
*opp
, int n_IRQ
, uint32_t val
)
564 IRQSource
*src
= &opp
->src
[n_IRQ
];
565 uint32_t normal_mask
= (1UL << opp
->nb_cpus
) - 1;
566 uint32_t crit_mask
= 0;
567 uint32_t mask
= normal_mask
;
568 int crit_shift
= IDR_EP_SHIFT
- opp
->nb_cpus
;
571 if (opp
->flags
& OPENPIC_FLAG_IDR_CRIT
) {
572 crit_mask
= mask
<< crit_shift
;
573 mask
|= crit_mask
| IDR_EP
;
576 src
->idr
= val
& mask
;
577 DPRINTF("Set IDR %d to 0x%08x\n", n_IRQ
, src
->idr
);
579 if (opp
->flags
& OPENPIC_FLAG_IDR_CRIT
) {
580 if (src
->idr
& crit_mask
) {
581 if (src
->idr
& normal_mask
) {
582 DPRINTF("%s: IRQ configured for multiple output types, using "
583 "critical\n", __func__
);
586 src
->output
= OPENPIC_OUTPUT_CINT
;
590 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
591 int n_ci
= IDR_CI0_SHIFT
- i
;
593 if (src
->idr
& (1UL << n_ci
)) {
594 src
->destmask
|= 1UL << i
;
598 src
->output
= OPENPIC_OUTPUT_INT
;
600 src
->destmask
= src
->idr
& normal_mask
;
603 src
->destmask
= src
->idr
;
607 static inline void write_IRQreg_ilr(OpenPICState
*opp
, int n_IRQ
, uint32_t val
)
609 if (opp
->flags
& OPENPIC_FLAG_ILR
) {
610 IRQSource
*src
= &opp
->src
[n_IRQ
];
612 src
->output
= inttgt_to_output(val
& ILR_INTTGT_MASK
);
613 DPRINTF("Set ILR %d to 0x%08x, output %d\n", n_IRQ
, src
->idr
,
616 /* TODO: on MPIC v4.0 only, set nomask for non-INT */
620 static inline void write_IRQreg_ivpr(OpenPICState
*opp
, int n_IRQ
, uint32_t val
)
624 /* NOTE when implementing newer FSL MPIC models: starting with v4.0,
625 * the polarity bit is read-only on internal interrupts.
627 mask
= IVPR_MASK_MASK
| IVPR_PRIORITY_MASK
| IVPR_SENSE_MASK
|
628 IVPR_POLARITY_MASK
| opp
->vector_mask
;
630 /* ACTIVITY bit is read-only */
631 opp
->src
[n_IRQ
].ivpr
=
632 (opp
->src
[n_IRQ
].ivpr
& IVPR_ACTIVITY_MASK
) | (val
& mask
);
634 /* For FSL internal interrupts, The sense bit is reserved and zero,
635 * and the interrupt is always level-triggered. Timers and IPIs
636 * have no sense or polarity bits, and are edge-triggered.
638 switch (opp
->src
[n_IRQ
].type
) {
639 case IRQ_TYPE_NORMAL
:
640 opp
->src
[n_IRQ
].level
= !!(opp
->src
[n_IRQ
].ivpr
& IVPR_SENSE_MASK
);
643 case IRQ_TYPE_FSLINT
:
644 opp
->src
[n_IRQ
].ivpr
&= ~IVPR_SENSE_MASK
;
647 case IRQ_TYPE_FSLSPECIAL
:
648 opp
->src
[n_IRQ
].ivpr
&= ~(IVPR_POLARITY_MASK
| IVPR_SENSE_MASK
);
652 openpic_update_irq(opp
, n_IRQ
);
653 DPRINTF("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ
, val
,
654 opp
->src
[n_IRQ
].ivpr
);
657 static void openpic_gcr_write(OpenPICState
*opp
, uint64_t val
)
659 bool mpic_proxy
= false;
661 if (val
& GCR_RESET
) {
662 openpic_reset(DEVICE(opp
));
666 opp
->gcr
&= ~opp
->mpic_mode_mask
;
667 opp
->gcr
|= val
& opp
->mpic_mode_mask
;
669 /* Set external proxy mode */
670 if ((val
& opp
->mpic_mode_mask
) == GCR_MODE_PROXY
) {
674 ppce500_set_mpic_proxy(mpic_proxy
);
677 static void openpic_gbl_write(void *opaque
, hwaddr addr
, uint64_t val
,
680 OpenPICState
*opp
= opaque
;
684 DPRINTF("%s: addr %#" HWADDR_PRIx
" <= %08" PRIx64
"\n",
685 __func__
, addr
, val
);
690 case 0x00: /* Block Revision Register1 (BRR1) is Readonly */
700 openpic_cpu_write_internal(opp
, addr
, val
, get_current_cpu());
702 case 0x1000: /* FRR */
704 case 0x1020: /* GCR */
705 openpic_gcr_write(opp
, val
);
707 case 0x1080: /* VIR */
709 case 0x1090: /* PIR */
710 for (idx
= 0; idx
< opp
->nb_cpus
; idx
++) {
711 if ((val
& (1 << idx
)) && !(opp
->pir
& (1 << idx
))) {
712 DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx
);
713 dst
= &opp
->dst
[idx
];
714 qemu_irq_raise(dst
->irqs
[OPENPIC_OUTPUT_RESET
]);
715 } else if (!(val
& (1 << idx
)) && (opp
->pir
& (1 << idx
))) {
716 DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx
);
717 dst
= &opp
->dst
[idx
];
718 qemu_irq_lower(dst
->irqs
[OPENPIC_OUTPUT_RESET
]);
723 case 0x10A0: /* IPI_IVPR */
729 idx
= (addr
- 0x10A0) >> 4;
730 write_IRQreg_ivpr(opp
, opp
->irq_ipi0
+ idx
, val
);
733 case 0x10E0: /* SPVE */
734 opp
->spve
= val
& opp
->vector_mask
;
741 static uint64_t openpic_gbl_read(void *opaque
, hwaddr addr
, unsigned len
)
743 OpenPICState
*opp
= opaque
;
746 DPRINTF("%s: addr %#" HWADDR_PRIx
"\n", __func__
, addr
);
752 case 0x1000: /* FRR */
755 case 0x1020: /* GCR */
758 case 0x1080: /* VIR */
761 case 0x1090: /* PIR */
764 case 0x00: /* Block Revision Register1 (BRR1) */
775 retval
= openpic_cpu_read_internal(opp
, addr
, get_current_cpu());
777 case 0x10A0: /* IPI_IVPR */
783 idx
= (addr
- 0x10A0) >> 4;
784 retval
= read_IRQreg_ivpr(opp
, opp
->irq_ipi0
+ idx
);
787 case 0x10E0: /* SPVE */
793 DPRINTF("%s: => 0x%08x\n", __func__
, retval
);
798 static void openpic_tmr_write(void *opaque
, hwaddr addr
, uint64_t val
,
801 OpenPICState
*opp
= opaque
;
804 DPRINTF("%s: addr %#" HWADDR_PRIx
" <= %08" PRIx64
"\n",
805 __func__
, (addr
+ 0x10f0), val
);
815 addr
-= 0x10; /* correct for TFRR */
816 idx
= (addr
>> 6) & 0x3;
818 switch (addr
& 0x30) {
819 case 0x00: /* TCCR */
821 case 0x10: /* TBCR */
822 if ((opp
->timers
[idx
].tccr
& TCCR_TOG
) != 0 &&
823 (val
& TBCR_CI
) == 0 &&
824 (opp
->timers
[idx
].tbcr
& TBCR_CI
) != 0) {
825 opp
->timers
[idx
].tccr
&= ~TCCR_TOG
;
827 opp
->timers
[idx
].tbcr
= val
;
829 case 0x20: /* TVPR */
830 write_IRQreg_ivpr(opp
, opp
->irq_tim0
+ idx
, val
);
833 write_IRQreg_idr(opp
, opp
->irq_tim0
+ idx
, val
);
838 static uint64_t openpic_tmr_read(void *opaque
, hwaddr addr
, unsigned len
)
840 OpenPICState
*opp
= opaque
;
841 uint32_t retval
= -1;
844 DPRINTF("%s: addr %#" HWADDR_PRIx
"\n", __func__
, addr
+ 0x10f0);
853 addr
-= 0x10; /* correct for TFRR */
854 idx
= (addr
>> 6) & 0x3;
855 switch (addr
& 0x30) {
856 case 0x00: /* TCCR */
857 retval
= opp
->timers
[idx
].tccr
;
859 case 0x10: /* TBCR */
860 retval
= opp
->timers
[idx
].tbcr
;
862 case 0x20: /* TVPR */
863 retval
= read_IRQreg_ivpr(opp
, opp
->irq_tim0
+ idx
);
866 retval
= read_IRQreg_idr(opp
, opp
->irq_tim0
+ idx
);
871 DPRINTF("%s: => 0x%08x\n", __func__
, retval
);
876 static void openpic_src_write(void *opaque
, hwaddr addr
, uint64_t val
,
879 OpenPICState
*opp
= opaque
;
882 DPRINTF("%s: addr %#" HWADDR_PRIx
" <= %08" PRIx64
"\n",
883 __func__
, addr
, val
);
885 addr
= addr
& 0xffff;
888 switch (addr
& 0x1f) {
890 write_IRQreg_ivpr(opp
, idx
, val
);
893 write_IRQreg_idr(opp
, idx
, val
);
896 write_IRQreg_ilr(opp
, idx
, val
);
901 static uint64_t openpic_src_read(void *opaque
, uint64_t addr
, unsigned len
)
903 OpenPICState
*opp
= opaque
;
907 DPRINTF("%s: addr %#" HWADDR_PRIx
"\n", __func__
, addr
);
910 addr
= addr
& 0xffff;
913 switch (addr
& 0x1f) {
915 retval
= read_IRQreg_ivpr(opp
, idx
);
918 retval
= read_IRQreg_idr(opp
, idx
);
921 retval
= read_IRQreg_ilr(opp
, idx
);
925 DPRINTF("%s: => 0x%08x\n", __func__
, retval
);
929 static void openpic_msi_write(void *opaque
, hwaddr addr
, uint64_t val
,
932 OpenPICState
*opp
= opaque
;
933 int idx
= opp
->irq_msi
;
936 DPRINTF("%s: addr %#" HWADDR_PRIx
" <= 0x%08" PRIx64
"\n",
937 __func__
, addr
, val
);
944 srs
= val
>> MSIIR_SRS_SHIFT
;
946 ibs
= (val
& MSIIR_IBS_MASK
) >> MSIIR_IBS_SHIFT
;
947 opp
->msi
[srs
].msir
|= 1 << ibs
;
948 openpic_set_irq(opp
, idx
, 1);
951 /* most registers are read-only, thus ignored */
956 static uint64_t openpic_msi_read(void *opaque
, hwaddr addr
, unsigned size
)
958 OpenPICState
*opp
= opaque
;
962 DPRINTF("%s: addr %#" HWADDR_PRIx
"\n", __func__
, addr
);
977 case 0x70: /* MSIRs */
978 r
= opp
->msi
[srs
].msir
;
980 opp
->msi
[srs
].msir
= 0;
981 openpic_set_irq(opp
, opp
->irq_msi
+ srs
, 0);
983 case 0x120: /* MSISR */
984 for (i
= 0; i
< MAX_MSI
; i
++) {
985 r
|= (opp
->msi
[i
].msir
? 1 : 0) << i
;
993 static uint64_t openpic_summary_read(void *opaque
, hwaddr addr
, unsigned size
)
997 DPRINTF("%s: addr %#" HWADDR_PRIx
"\n", __func__
, addr
);
999 /* TODO: EISR/EIMR */
1004 static void openpic_summary_write(void *opaque
, hwaddr addr
, uint64_t val
,
1007 DPRINTF("%s: addr %#" HWADDR_PRIx
" <= 0x%08" PRIx64
"\n",
1008 __func__
, addr
, val
);
1010 /* TODO: EISR/EIMR */
1013 static void openpic_cpu_write_internal(void *opaque
, hwaddr addr
,
1014 uint32_t val
, int idx
)
1016 OpenPICState
*opp
= opaque
;
1021 DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx
" <= 0x%08x\n", __func__
, idx
,
1024 if (idx
< 0 || idx
>= opp
->nb_cpus
) {
1031 dst
= &opp
->dst
[idx
];
1034 case 0x40: /* IPIDR */
1038 idx
= (addr
- 0x40) >> 4;
1039 /* we use IDE as mask which CPUs to deliver the IPI to still. */
1040 opp
->src
[opp
->irq_ipi0
+ idx
].destmask
|= val
;
1041 openpic_set_irq(opp
, opp
->irq_ipi0
+ idx
, 1);
1042 openpic_set_irq(opp
, opp
->irq_ipi0
+ idx
, 0);
1044 case 0x80: /* CTPR */
1045 dst
->ctpr
= val
& 0x0000000F;
1047 DPRINTF("%s: set CPU %d ctpr to %d, raised %d servicing %d\n",
1048 __func__
, idx
, dst
->ctpr
, dst
->raised
.priority
,
1049 dst
->servicing
.priority
);
1051 if (dst
->raised
.priority
<= dst
->ctpr
) {
1052 DPRINTF("%s: Lower OpenPIC INT output cpu %d due to ctpr\n",
1054 qemu_irq_lower(dst
->irqs
[OPENPIC_OUTPUT_INT
]);
1055 } else if (dst
->raised
.priority
> dst
->servicing
.priority
) {
1056 DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d\n",
1057 __func__
, idx
, dst
->raised
.next
);
1058 qemu_irq_raise(dst
->irqs
[OPENPIC_OUTPUT_INT
]);
1062 case 0x90: /* WHOAMI */
1063 /* Read-only register */
1065 case 0xA0: /* IACK */
1066 /* Read-only register */
1068 case 0xB0: /* EOI */
1070 s_IRQ
= IRQ_get_next(opp
, &dst
->servicing
);
1073 DPRINTF("%s: EOI with no interrupt in service\n", __func__
);
1077 IRQ_resetbit(&dst
->servicing
, s_IRQ
);
1078 /* Set up next servicing IRQ */
1079 s_IRQ
= IRQ_get_next(opp
, &dst
->servicing
);
1080 /* Check queued interrupts. */
1081 n_IRQ
= IRQ_get_next(opp
, &dst
->raised
);
1082 src
= &opp
->src
[n_IRQ
];
1085 IVPR_PRIORITY(src
->ivpr
) > dst
->servicing
.priority
)) {
1086 DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n",
1088 qemu_irq_raise(opp
->dst
[idx
].irqs
[OPENPIC_OUTPUT_INT
]);
1096 static void openpic_cpu_write(void *opaque
, hwaddr addr
, uint64_t val
,
1099 openpic_cpu_write_internal(opaque
, addr
, val
, (addr
& 0x1f000) >> 12);
1103 static uint32_t openpic_iack(OpenPICState
*opp
, IRQDest
*dst
, int cpu
)
1108 DPRINTF("Lower OpenPIC INT output\n");
1109 qemu_irq_lower(dst
->irqs
[OPENPIC_OUTPUT_INT
]);
1111 irq
= IRQ_get_next(opp
, &dst
->raised
);
1112 DPRINTF("IACK: irq=%d\n", irq
);
1115 /* No more interrupt pending */
1119 src
= &opp
->src
[irq
];
1120 if (!(src
->ivpr
& IVPR_ACTIVITY_MASK
) ||
1121 !(IVPR_PRIORITY(src
->ivpr
) > dst
->ctpr
)) {
1122 fprintf(stderr
, "%s: bad raised IRQ %d ctpr %d ivpr 0x%08x\n",
1123 __func__
, irq
, dst
->ctpr
, src
->ivpr
);
1124 openpic_update_irq(opp
, irq
);
1127 /* IRQ enter servicing state */
1128 IRQ_setbit(&dst
->servicing
, irq
);
1129 retval
= IVPR_VECTOR(opp
, src
->ivpr
);
1133 /* edge-sensitive IRQ */
1134 src
->ivpr
&= ~IVPR_ACTIVITY_MASK
;
1136 IRQ_resetbit(&dst
->raised
, irq
);
1139 if ((irq
>= opp
->irq_ipi0
) && (irq
< (opp
->irq_ipi0
+ OPENPIC_MAX_IPI
))) {
1140 src
->destmask
&= ~(1 << cpu
);
1141 if (src
->destmask
&& !src
->level
) {
1142 /* trigger on CPUs that didn't know about it yet */
1143 openpic_set_irq(opp
, irq
, 1);
1144 openpic_set_irq(opp
, irq
, 0);
1145 /* if all CPUs knew about it, set active bit again */
1146 src
->ivpr
|= IVPR_ACTIVITY_MASK
;
1153 static uint32_t openpic_cpu_read_internal(void *opaque
, hwaddr addr
,
1156 OpenPICState
*opp
= opaque
;
1160 DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx
"\n", __func__
, idx
, addr
);
1161 retval
= 0xFFFFFFFF;
1163 if (idx
< 0 || idx
>= opp
->nb_cpus
) {
1170 dst
= &opp
->dst
[idx
];
1173 case 0x80: /* CTPR */
1176 case 0x90: /* WHOAMI */
1179 case 0xA0: /* IACK */
1180 retval
= openpic_iack(opp
, dst
, idx
);
1182 case 0xB0: /* EOI */
1188 DPRINTF("%s: => 0x%08x\n", __func__
, retval
);
1193 static uint64_t openpic_cpu_read(void *opaque
, hwaddr addr
, unsigned len
)
1195 return openpic_cpu_read_internal(opaque
, addr
, (addr
& 0x1f000) >> 12);
1198 static const MemoryRegionOps openpic_glb_ops_le
= {
1199 .write
= openpic_gbl_write
,
1200 .read
= openpic_gbl_read
,
1201 .endianness
= DEVICE_LITTLE_ENDIAN
,
1203 .min_access_size
= 4,
1204 .max_access_size
= 4,
1208 static const MemoryRegionOps openpic_glb_ops_be
= {
1209 .write
= openpic_gbl_write
,
1210 .read
= openpic_gbl_read
,
1211 .endianness
= DEVICE_BIG_ENDIAN
,
1213 .min_access_size
= 4,
1214 .max_access_size
= 4,
1218 static const MemoryRegionOps openpic_tmr_ops_le
= {
1219 .write
= openpic_tmr_write
,
1220 .read
= openpic_tmr_read
,
1221 .endianness
= DEVICE_LITTLE_ENDIAN
,
1223 .min_access_size
= 4,
1224 .max_access_size
= 4,
1228 static const MemoryRegionOps openpic_tmr_ops_be
= {
1229 .write
= openpic_tmr_write
,
1230 .read
= openpic_tmr_read
,
1231 .endianness
= DEVICE_BIG_ENDIAN
,
1233 .min_access_size
= 4,
1234 .max_access_size
= 4,
1238 static const MemoryRegionOps openpic_cpu_ops_le
= {
1239 .write
= openpic_cpu_write
,
1240 .read
= openpic_cpu_read
,
1241 .endianness
= DEVICE_LITTLE_ENDIAN
,
1243 .min_access_size
= 4,
1244 .max_access_size
= 4,
1248 static const MemoryRegionOps openpic_cpu_ops_be
= {
1249 .write
= openpic_cpu_write
,
1250 .read
= openpic_cpu_read
,
1251 .endianness
= DEVICE_BIG_ENDIAN
,
1253 .min_access_size
= 4,
1254 .max_access_size
= 4,
1258 static const MemoryRegionOps openpic_src_ops_le
= {
1259 .write
= openpic_src_write
,
1260 .read
= openpic_src_read
,
1261 .endianness
= DEVICE_LITTLE_ENDIAN
,
1263 .min_access_size
= 4,
1264 .max_access_size
= 4,
1268 static const MemoryRegionOps openpic_src_ops_be
= {
1269 .write
= openpic_src_write
,
1270 .read
= openpic_src_read
,
1271 .endianness
= DEVICE_BIG_ENDIAN
,
1273 .min_access_size
= 4,
1274 .max_access_size
= 4,
1278 static const MemoryRegionOps openpic_msi_ops_be
= {
1279 .read
= openpic_msi_read
,
1280 .write
= openpic_msi_write
,
1281 .endianness
= DEVICE_BIG_ENDIAN
,
1283 .min_access_size
= 4,
1284 .max_access_size
= 4,
1288 static const MemoryRegionOps openpic_summary_ops_be
= {
1289 .read
= openpic_summary_read
,
1290 .write
= openpic_summary_write
,
1291 .endianness
= DEVICE_BIG_ENDIAN
,
1293 .min_access_size
= 4,
1294 .max_access_size
= 4,
1298 static void openpic_reset(DeviceState
*d
)
1300 OpenPICState
*opp
= OPENPIC(d
);
1303 opp
->gcr
= GCR_RESET
;
1304 /* Initialise controller registers */
1305 opp
->frr
= ((opp
->nb_irqs
- 1) << FRR_NIRQ_SHIFT
) |
1306 ((opp
->nb_cpus
- 1) << FRR_NCPU_SHIFT
) |
1307 (opp
->vid
<< FRR_VID_SHIFT
);
1310 opp
->spve
= -1 & opp
->vector_mask
;
1311 opp
->tfrr
= opp
->tfrr_reset
;
1312 /* Initialise IRQ sources */
1313 for (i
= 0; i
< opp
->max_irq
; i
++) {
1314 opp
->src
[i
].ivpr
= opp
->ivpr_reset
;
1315 switch (opp
->src
[i
].type
) {
1316 case IRQ_TYPE_NORMAL
:
1317 opp
->src
[i
].level
= !!(opp
->ivpr_reset
& IVPR_SENSE_MASK
);
1320 case IRQ_TYPE_FSLINT
:
1321 opp
->src
[i
].ivpr
|= IVPR_POLARITY_MASK
;
1324 case IRQ_TYPE_FSLSPECIAL
:
1328 write_IRQreg_idr(opp
, i
, opp
->idr_reset
);
1330 /* Initialise IRQ destinations */
1331 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
1332 opp
->dst
[i
].ctpr
= 15;
1333 opp
->dst
[i
].raised
.next
= -1;
1334 opp
->dst
[i
].raised
.priority
= 0;
1335 bitmap_clear(opp
->dst
[i
].raised
.queue
, 0, IRQQUEUE_SIZE_BITS
);
1336 opp
->dst
[i
].servicing
.next
= -1;
1337 opp
->dst
[i
].servicing
.priority
= 0;
1338 bitmap_clear(opp
->dst
[i
].servicing
.queue
, 0, IRQQUEUE_SIZE_BITS
);
1340 /* Initialise timers */
1341 for (i
= 0; i
< OPENPIC_MAX_TMR
; i
++) {
1342 opp
->timers
[i
].tccr
= 0;
1343 opp
->timers
[i
].tbcr
= TBCR_CI
;
1345 /* Go out of RESET state */
1349 typedef struct MemReg
{
1351 MemoryRegionOps
const *ops
;
1356 static void fsl_common_init(OpenPICState
*opp
)
1359 int virq
= OPENPIC_MAX_SRC
;
1361 opp
->vid
= VID_REVISION_1_2
;
1362 opp
->vir
= VIR_GENERIC
;
1363 opp
->vector_mask
= 0xFFFF;
1364 opp
->tfrr_reset
= 0;
1365 opp
->ivpr_reset
= IVPR_MASK_MASK
;
1366 opp
->idr_reset
= 1 << 0;
1367 opp
->max_irq
= OPENPIC_MAX_IRQ
;
1369 opp
->irq_ipi0
= virq
;
1370 virq
+= OPENPIC_MAX_IPI
;
1371 opp
->irq_tim0
= virq
;
1372 virq
+= OPENPIC_MAX_TMR
;
1374 assert(virq
<= OPENPIC_MAX_IRQ
);
1378 msi_nonbroken
= true;
1379 for (i
= 0; i
< opp
->fsl
->max_ext
; i
++) {
1380 opp
->src
[i
].level
= false;
1383 /* Internal interrupts, including message and MSI */
1384 for (i
= 16; i
< OPENPIC_MAX_SRC
; i
++) {
1385 opp
->src
[i
].type
= IRQ_TYPE_FSLINT
;
1386 opp
->src
[i
].level
= true;
1389 /* timers and IPIs */
1390 for (i
= OPENPIC_MAX_SRC
; i
< virq
; i
++) {
1391 opp
->src
[i
].type
= IRQ_TYPE_FSLSPECIAL
;
1392 opp
->src
[i
].level
= false;
1396 static void map_list(OpenPICState
*opp
, const MemReg
*list
, int *count
)
1398 while (list
->name
) {
1399 assert(*count
< ARRAY_SIZE(opp
->sub_io_mem
));
1401 memory_region_init_io(&opp
->sub_io_mem
[*count
], OBJECT(opp
), list
->ops
,
1402 opp
, list
->name
, list
->size
);
1404 memory_region_add_subregion(&opp
->mem
, list
->start_addr
,
1405 &opp
->sub_io_mem
[*count
]);
1412 static const VMStateDescription vmstate_openpic_irq_queue
= {
1413 .name
= "openpic_irq_queue",
1415 .minimum_version_id
= 0,
1416 .fields
= (VMStateField
[]) {
1417 VMSTATE_BITMAP(queue
, IRQQueue
, 0, queue_size
),
1418 VMSTATE_INT32(next
, IRQQueue
),
1419 VMSTATE_INT32(priority
, IRQQueue
),
1420 VMSTATE_END_OF_LIST()
1424 static const VMStateDescription vmstate_openpic_irqdest
= {
1425 .name
= "openpic_irqdest",
1427 .minimum_version_id
= 0,
1428 .fields
= (VMStateField
[]) {
1429 VMSTATE_INT32(ctpr
, IRQDest
),
1430 VMSTATE_STRUCT(raised
, IRQDest
, 0, vmstate_openpic_irq_queue
,
1432 VMSTATE_STRUCT(servicing
, IRQDest
, 0, vmstate_openpic_irq_queue
,
1434 VMSTATE_UINT32_ARRAY(outputs_active
, IRQDest
, OPENPIC_OUTPUT_NB
),
1435 VMSTATE_END_OF_LIST()
1439 static const VMStateDescription vmstate_openpic_irqsource
= {
1440 .name
= "openpic_irqsource",
1442 .minimum_version_id
= 0,
1443 .fields
= (VMStateField
[]) {
1444 VMSTATE_UINT32(ivpr
, IRQSource
),
1445 VMSTATE_UINT32(idr
, IRQSource
),
1446 VMSTATE_UINT32(destmask
, IRQSource
),
1447 VMSTATE_INT32(last_cpu
, IRQSource
),
1448 VMSTATE_INT32(pending
, IRQSource
),
1449 VMSTATE_END_OF_LIST()
1453 static const VMStateDescription vmstate_openpic_timer
= {
1454 .name
= "openpic_timer",
1456 .minimum_version_id
= 0,
1457 .fields
= (VMStateField
[]) {
1458 VMSTATE_UINT32(tccr
, OpenPICTimer
),
1459 VMSTATE_UINT32(tbcr
, OpenPICTimer
),
1460 VMSTATE_END_OF_LIST()
1464 static const VMStateDescription vmstate_openpic_msi
= {
1465 .name
= "openpic_msi",
1467 .minimum_version_id
= 0,
1468 .fields
= (VMStateField
[]) {
1469 VMSTATE_UINT32(msir
, OpenPICMSI
),
1470 VMSTATE_END_OF_LIST()
1474 static int openpic_post_load(void *opaque
, int version_id
)
1476 OpenPICState
*opp
= (OpenPICState
*)opaque
;
1479 /* Update internal ivpr and idr variables */
1480 for (i
= 0; i
< opp
->max_irq
; i
++) {
1481 write_IRQreg_idr(opp
, i
, opp
->src
[i
].idr
);
1482 write_IRQreg_ivpr(opp
, i
, opp
->src
[i
].ivpr
);
1488 static const VMStateDescription vmstate_openpic
= {
1491 .minimum_version_id
= 3,
1492 .post_load
= openpic_post_load
,
1493 .fields
= (VMStateField
[]) {
1494 VMSTATE_UINT32(gcr
, OpenPICState
),
1495 VMSTATE_UINT32(vir
, OpenPICState
),
1496 VMSTATE_UINT32(pir
, OpenPICState
),
1497 VMSTATE_UINT32(spve
, OpenPICState
),
1498 VMSTATE_UINT32(tfrr
, OpenPICState
),
1499 VMSTATE_UINT32(max_irq
, OpenPICState
),
1500 VMSTATE_STRUCT_VARRAY_UINT32(src
, OpenPICState
, max_irq
, 0,
1501 vmstate_openpic_irqsource
, IRQSource
),
1502 VMSTATE_UINT32_EQUAL(nb_cpus
, OpenPICState
),
1503 VMSTATE_STRUCT_VARRAY_UINT32(dst
, OpenPICState
, nb_cpus
, 0,
1504 vmstate_openpic_irqdest
, IRQDest
),
1505 VMSTATE_STRUCT_ARRAY(timers
, OpenPICState
, OPENPIC_MAX_TMR
, 0,
1506 vmstate_openpic_timer
, OpenPICTimer
),
1507 VMSTATE_STRUCT_ARRAY(msi
, OpenPICState
, MAX_MSI
, 0,
1508 vmstate_openpic_msi
, OpenPICMSI
),
1509 VMSTATE_UINT32(irq_ipi0
, OpenPICState
),
1510 VMSTATE_UINT32(irq_tim0
, OpenPICState
),
1511 VMSTATE_UINT32(irq_msi
, OpenPICState
),
1512 VMSTATE_END_OF_LIST()
1516 static void openpic_init(Object
*obj
)
1518 OpenPICState
*opp
= OPENPIC(obj
);
1520 memory_region_init(&opp
->mem
, obj
, "openpic", 0x40000);
1523 static void openpic_realize(DeviceState
*dev
, Error
**errp
)
1525 SysBusDevice
*d
= SYS_BUS_DEVICE(dev
);
1526 OpenPICState
*opp
= OPENPIC(dev
);
1529 static const MemReg list_le
[] = {
1530 {"glb", &openpic_glb_ops_le
,
1531 OPENPIC_GLB_REG_START
, OPENPIC_GLB_REG_SIZE
},
1532 {"tmr", &openpic_tmr_ops_le
,
1533 OPENPIC_TMR_REG_START
, OPENPIC_TMR_REG_SIZE
},
1534 {"src", &openpic_src_ops_le
,
1535 OPENPIC_SRC_REG_START
, OPENPIC_SRC_REG_SIZE
},
1536 {"cpu", &openpic_cpu_ops_le
,
1537 OPENPIC_CPU_REG_START
, OPENPIC_CPU_REG_SIZE
},
1540 static const MemReg list_be
[] = {
1541 {"glb", &openpic_glb_ops_be
,
1542 OPENPIC_GLB_REG_START
, OPENPIC_GLB_REG_SIZE
},
1543 {"tmr", &openpic_tmr_ops_be
,
1544 OPENPIC_TMR_REG_START
, OPENPIC_TMR_REG_SIZE
},
1545 {"src", &openpic_src_ops_be
,
1546 OPENPIC_SRC_REG_START
, OPENPIC_SRC_REG_SIZE
},
1547 {"cpu", &openpic_cpu_ops_be
,
1548 OPENPIC_CPU_REG_START
, OPENPIC_CPU_REG_SIZE
},
1551 static const MemReg list_fsl
[] = {
1552 {"msi", &openpic_msi_ops_be
,
1553 OPENPIC_MSI_REG_START
, OPENPIC_MSI_REG_SIZE
},
1554 {"summary", &openpic_summary_ops_be
,
1555 OPENPIC_SUMMARY_REG_START
, OPENPIC_SUMMARY_REG_SIZE
},
1559 if (opp
->nb_cpus
> MAX_CPU
) {
1560 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
,
1561 TYPE_OPENPIC
, "nb_cpus", (uint64_t)opp
->nb_cpus
,
1562 (uint64_t)0, (uint64_t)MAX_CPU
);
1566 switch (opp
->model
) {
1567 case OPENPIC_MODEL_FSL_MPIC_20
:
1569 opp
->fsl
= &fsl_mpic_20
;
1570 opp
->brr1
= 0x00400200;
1571 opp
->flags
|= OPENPIC_FLAG_IDR_CRIT
;
1573 opp
->mpic_mode_mask
= GCR_MODE_MIXED
;
1575 fsl_common_init(opp
);
1576 map_list(opp
, list_be
, &list_count
);
1577 map_list(opp
, list_fsl
, &list_count
);
1581 case OPENPIC_MODEL_FSL_MPIC_42
:
1582 opp
->fsl
= &fsl_mpic_42
;
1583 opp
->brr1
= 0x00400402;
1584 opp
->flags
|= OPENPIC_FLAG_ILR
;
1586 opp
->mpic_mode_mask
= GCR_MODE_PROXY
;
1588 fsl_common_init(opp
);
1589 map_list(opp
, list_be
, &list_count
);
1590 map_list(opp
, list_fsl
, &list_count
);
1594 case OPENPIC_MODEL_RAVEN
:
1595 opp
->nb_irqs
= RAVEN_MAX_EXT
;
1596 opp
->vid
= VID_REVISION_1_3
;
1597 opp
->vir
= VIR_GENERIC
;
1598 opp
->vector_mask
= 0xFF;
1599 opp
->tfrr_reset
= 4160000;
1600 opp
->ivpr_reset
= IVPR_MASK_MASK
| IVPR_MODE_MASK
;
1602 opp
->max_irq
= RAVEN_MAX_IRQ
;
1603 opp
->irq_ipi0
= RAVEN_IPI_IRQ
;
1604 opp
->irq_tim0
= RAVEN_TMR_IRQ
;
1606 opp
->mpic_mode_mask
= GCR_MODE_MIXED
;
1608 if (opp
->nb_cpus
!= 1) {
1609 error_setg(errp
, "Only UP supported today");
1613 map_list(opp
, list_le
, &list_count
);
1617 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
1618 opp
->dst
[i
].irqs
= g_new0(qemu_irq
, OPENPIC_OUTPUT_NB
);
1619 for (j
= 0; j
< OPENPIC_OUTPUT_NB
; j
++) {
1620 sysbus_init_irq(d
, &opp
->dst
[i
].irqs
[j
]);
1623 opp
->dst
[i
].raised
.queue_size
= IRQQUEUE_SIZE_BITS
;
1624 opp
->dst
[i
].raised
.queue
= bitmap_new(IRQQUEUE_SIZE_BITS
);
1625 opp
->dst
[i
].servicing
.queue_size
= IRQQUEUE_SIZE_BITS
;
1626 opp
->dst
[i
].servicing
.queue
= bitmap_new(IRQQUEUE_SIZE_BITS
);
1629 sysbus_init_mmio(d
, &opp
->mem
);
1630 qdev_init_gpio_in(dev
, openpic_set_irq
, opp
->max_irq
);
1633 static Property openpic_properties
[] = {
1634 DEFINE_PROP_UINT32("model", OpenPICState
, model
, OPENPIC_MODEL_FSL_MPIC_20
),
1635 DEFINE_PROP_UINT32("nb_cpus", OpenPICState
, nb_cpus
, 1),
1636 DEFINE_PROP_END_OF_LIST(),
1639 static void openpic_class_init(ObjectClass
*oc
, void *data
)
1641 DeviceClass
*dc
= DEVICE_CLASS(oc
);
1643 dc
->realize
= openpic_realize
;
1644 dc
->props
= openpic_properties
;
1645 dc
->reset
= openpic_reset
;
1646 dc
->vmsd
= &vmstate_openpic
;
1647 set_bit(DEVICE_CATEGORY_MISC
, dc
->categories
);
1650 static const TypeInfo openpic_info
= {
1651 .name
= TYPE_OPENPIC
,
1652 .parent
= TYPE_SYS_BUS_DEVICE
,
1653 .instance_size
= sizeof(OpenPICState
),
1654 .instance_init
= openpic_init
,
1655 .class_init
= openpic_class_init
,
1658 static void openpic_register_types(void)
1660 type_register_static(&openpic_info
);
1663 type_init(openpic_register_types
)