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hw/arm: Move virt's PSCI DT fixup code to arm/boot.c
[qemu/ar7.git] / hw / audio / intel-hda.c
blob948268afd8122b38290f90045f8fe44e92f4a395
1 /*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Gerd Hoffmann <kraxel@redhat.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "hw/hw.h"
22 #include "hw/pci/pci.h"
23 #include "hw/pci/msi.h"
24 #include "qemu/timer.h"
25 #include "qemu/bitops.h"
26 #include "hw/audio/soundhw.h"
27 #include "intel-hda.h"
28 #include "intel-hda-defs.h"
29 #include "sysemu/dma.h"
30 #include "qapi/error.h"
31
32 /* --------------------------------------------------------------------- */
33 /* hda bus */
34
35 static Property hda_props[] = {
36 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1),
37 DEFINE_PROP_END_OF_LIST()
38 };
39
40 static const TypeInfo hda_codec_bus_info = {
41 .name = TYPE_HDA_BUS,
42 .parent = TYPE_BUS,
43 .instance_size = sizeof(HDACodecBus),
44 };
45
46 void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size,
47 hda_codec_response_func response,
48 hda_codec_xfer_func xfer)
49 {
50 qbus_create_inplace(bus, bus_size, TYPE_HDA_BUS, dev, NULL);
51 bus->response = response;
52 bus->xfer = xfer;
53 }
54
55 static void hda_codec_dev_realize(DeviceState *qdev, Error **errp)
56 {
57 HDACodecBus *bus = HDA_BUS(qdev->parent_bus);
58 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev);
59 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
60
61 if (dev->cad == -1) {
62 dev->cad = bus->next_cad;
63 }
64 if (dev->cad >= 15) {
65 error_setg(errp, "HDA audio codec address is full");
66 return;
67 }
68 bus->next_cad = dev->cad + 1;
69 if (cdc->init(dev) != 0) {
70 error_setg(errp, "HDA audio init failed");
71 }
72 }
73
74 static void hda_codec_dev_unrealize(DeviceState *qdev, Error **errp)
75 {
76 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev);
77 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
78
79 if (cdc->exit) {
80 cdc->exit(dev);
81 }
82 }
83
84 HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad)
85 {
86 BusChild *kid;
87 HDACodecDevice *cdev;
88
89 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
90 DeviceState *qdev = kid->child;
91 cdev = HDA_CODEC_DEVICE(qdev);
92 if (cdev->cad == cad) {
93 return cdev;
94 }
95 }
96 return NULL;
97 }
98
99 void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response)
100 {
101 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
102 bus->response(dev, solicited, response);
103 }
104
105 bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
106 uint8_t *buf, uint32_t len)
107 {
108 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
109 return bus->xfer(dev, stnr, output, buf, len);
110 }
111
112 /* --------------------------------------------------------------------- */
113 /* intel hda emulation */
114
115 typedef struct IntelHDAStream IntelHDAStream;
116 typedef struct IntelHDAState IntelHDAState;
117 typedef struct IntelHDAReg IntelHDAReg;
118
119 typedef struct bpl {
120 uint64_t addr;
121 uint32_t len;
122 uint32_t flags;
123 } bpl;
124
125 struct IntelHDAStream {
126 /* registers */
127 uint32_t ctl;
128 uint32_t lpib;
129 uint32_t cbl;
130 uint32_t lvi;
131 uint32_t fmt;
132 uint32_t bdlp_lbase;
133 uint32_t bdlp_ubase;
134
135 /* state */
136 bpl *bpl;
137 uint32_t bentries;
138 uint32_t bsize, be, bp;
139 };
140
141 struct IntelHDAState {
142 PCIDevice pci;
143 const char *name;
144 HDACodecBus codecs;
145
146 /* registers */
147 uint32_t g_ctl;
148 uint32_t wake_en;
149 uint32_t state_sts;
150 uint32_t int_ctl;
151 uint32_t int_sts;
152 uint32_t wall_clk;
153
154 uint32_t corb_lbase;
155 uint32_t corb_ubase;
156 uint32_t corb_rp;
157 uint32_t corb_wp;
158 uint32_t corb_ctl;
159 uint32_t corb_sts;
160 uint32_t corb_size;
161
162 uint32_t rirb_lbase;
163 uint32_t rirb_ubase;
164 uint32_t rirb_wp;
165 uint32_t rirb_cnt;
166 uint32_t rirb_ctl;
167 uint32_t rirb_sts;
168 uint32_t rirb_size;
169
170 uint32_t dp_lbase;
171 uint32_t dp_ubase;
172
173 uint32_t icw;
174 uint32_t irr;
175 uint32_t ics;
176
177 /* streams */
178 IntelHDAStream st[8];
179
180 /* state */
181 MemoryRegion mmio;
182 uint32_t rirb_count;
183 int64_t wall_base_ns;
184
185 /* debug logging */
186 const IntelHDAReg *last_reg;
187 uint32_t last_val;
188 uint32_t last_write;
189 uint32_t last_sec;
190 uint32_t repeat_count;
191
192 /* properties */
193 uint32_t debug;
194 OnOffAuto msi;
195 bool old_msi_addr;
196 };
197
198 #define TYPE_INTEL_HDA_GENERIC "intel-hda-generic"
199
200 #define INTEL_HDA(obj) \
201 OBJECT_CHECK(IntelHDAState, (obj), TYPE_INTEL_HDA_GENERIC)
202
203 struct IntelHDAReg {
204 const char *name; /* register name */
205 uint32_t size; /* size in bytes */
206 uint32_t reset; /* reset value */
207 uint32_t wmask; /* write mask */
208 uint32_t wclear; /* write 1 to clear bits */
209 uint32_t offset; /* location in IntelHDAState */
210 uint32_t shift; /* byte access entries for dwords */
211 uint32_t stream;
212 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old);
213 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg);
214 };
215
216 static void intel_hda_reset(DeviceState *dev);
217
218 /* --------------------------------------------------------------------- */
219
220 static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase)
221 {
222 return ((uint64_t)ubase << 32) | lbase;
223 }
224
225 static void intel_hda_update_int_sts(IntelHDAState *d)
226 {
227 uint32_t sts = 0;
228 uint32_t i;
229
230 /* update controller status */
231 if (d->rirb_sts & ICH6_RBSTS_IRQ) {
232 sts |= (1 << 30);
233 }
234 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) {
235 sts |= (1 << 30);
236 }
237 if (d->state_sts & d->wake_en) {
238 sts |= (1 << 30);
239 }
240
241 /* update stream status */
242 for (i = 0; i < 8; i++) {
243 /* buffer completion interrupt */
244 if (d->st[i].ctl & (1 << 26)) {
245 sts |= (1 << i);
246 }
247 }
248
249 /* update global status */
250 if (sts & d->int_ctl) {
251 sts |= (1U << 31);
252 }
253
254 d->int_sts = sts;
255 }
256
257 static void intel_hda_update_irq(IntelHDAState *d)
258 {
259 bool msi = msi_enabled(&d->pci);
260 int level;
261
262 intel_hda_update_int_sts(d);
263 if (d->int_sts & (1U << 31) && d->int_ctl & (1U << 31)) {
264 level = 1;
265 } else {
266 level = 0;
267 }
268 dprint(d, 2, "%s: level %d [%s]\n", __func__,
269 level, msi ? "msi" : "intx");
270 if (msi) {
271 if (level) {
272 msi_notify(&d->pci, 0);
273 }
274 } else {
275 pci_set_irq(&d->pci, level);
276 }
277 }
278
279 static int intel_hda_send_command(IntelHDAState *d, uint32_t verb)
280 {
281 uint32_t cad, nid, data;
282 HDACodecDevice *codec;
283 HDACodecDeviceClass *cdc;
284
285 cad = (verb >> 28) & 0x0f;
286 if (verb & (1 << 27)) {
287 /* indirect node addressing, not specified in HDA 1.0 */
288 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __func__);
289 return -1;
290 }
291 nid = (verb >> 20) & 0x7f;
292 data = verb & 0xfffff;
293
294 codec = hda_codec_find(&d->codecs, cad);
295 if (codec == NULL) {
296 dprint(d, 1, "%s: addressed non-existing codec\n", __func__);
297 return -1;
298 }
299 cdc = HDA_CODEC_DEVICE_GET_CLASS(codec);
300 cdc->command(codec, nid, data);
301 return 0;
302 }
303
304 static void intel_hda_corb_run(IntelHDAState *d)
305 {
306 hwaddr addr;
307 uint32_t rp, verb;
308
309 if (d->ics & ICH6_IRS_BUSY) {
310 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __func__, d->icw);
311 intel_hda_send_command(d, d->icw);
312 return;
313 }
314
315 for (;;) {
316 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) {
317 dprint(d, 2, "%s: !run\n", __func__);
318 return;
319 }
320 if ((d->corb_rp & 0xff) == d->corb_wp) {
321 dprint(d, 2, "%s: corb ring empty\n", __func__);
322 return;
323 }
324 if (d->rirb_count == d->rirb_cnt) {
325 dprint(d, 2, "%s: rirb count reached\n", __func__);
326 return;
327 }
328
329 rp = (d->corb_rp + 1) & 0xff;
330 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase);
331 verb = ldl_le_pci_dma(&d->pci, addr + 4*rp);
332 d->corb_rp = rp;
333
334 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __func__, rp, verb);
335 intel_hda_send_command(d, verb);
336 }
337 }
338
339 static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response)
340 {
341 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
342 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
343 hwaddr addr;
344 uint32_t wp, ex;
345
346 if (d->ics & ICH6_IRS_BUSY) {
347 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
348 __func__, response, dev->cad);
349 d->irr = response;
350 d->ics &= ~(ICH6_IRS_BUSY | 0xf0);
351 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4));
352 return;
353 }
354
355 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) {
356 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __func__);
357 return;
358 }
359
360 ex = (solicited ? 0 : (1 << 4)) | dev->cad;
361 wp = (d->rirb_wp + 1) & 0xff;
362 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase);
363 stl_le_pci_dma(&d->pci, addr + 8*wp, response);
364 stl_le_pci_dma(&d->pci, addr + 8*wp + 4, ex);
365 d->rirb_wp = wp;
366
367 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
368 __func__, wp, response, ex);
369
370 d->rirb_count++;
371 if (d->rirb_count == d->rirb_cnt) {
372 dprint(d, 2, "%s: rirb count reached (%d)\n", __func__, d->rirb_count);
373 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
374 d->rirb_sts |= ICH6_RBSTS_IRQ;
375 intel_hda_update_irq(d);
376 }
377 } else if ((d->corb_rp & 0xff) == d->corb_wp) {
378 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __func__,
379 d->rirb_count, d->rirb_cnt);
380 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
381 d->rirb_sts |= ICH6_RBSTS_IRQ;
382 intel_hda_update_irq(d);
383 }
384 }
385 }
386
387 static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
388 uint8_t *buf, uint32_t len)
389 {
390 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
391 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
392 hwaddr addr;
393 uint32_t s, copy, left;
394 IntelHDAStream *st;
395 bool irq = false;
396
397 st = output ? d->st + 4 : d->st;
398 for (s = 0; s < 4; s++) {
399 if (stnr == ((st[s].ctl >> 20) & 0x0f)) {
400 st = st + s;
401 break;
402 }
403 }
404 if (s == 4) {
405 return false;
406 }
407 if (st->bpl == NULL) {
408 return false;
409 }
410 if (st->ctl & (1 << 26)) {
411 /*
412 * Wait with the next DMA xfer until the guest
413 * has acked the buffer completion interrupt
414 */
415 return false;
416 }
417
418 left = len;
419 s = st->bentries;
420 while (left > 0 && s-- > 0) {
421 copy = left;
422 if (copy > st->bsize - st->lpib)
423 copy = st->bsize - st->lpib;
424 if (copy > st->bpl[st->be].len - st->bp)
425 copy = st->bpl[st->be].len - st->bp;
426
427 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n",
428 st->be, st->bp, st->bpl[st->be].len, copy);
429
430 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output);
431 st->lpib += copy;
432 st->bp += copy;
433 buf += copy;
434 left -= copy;
435
436 if (st->bpl[st->be].len == st->bp) {
437 /* bpl entry filled */
438 if (st->bpl[st->be].flags & 0x01) {
439 irq = true;
440 }
441 st->bp = 0;
442 st->be++;
443 if (st->be == st->bentries) {
444 /* bpl wrap around */
445 st->be = 0;
446 st->lpib = 0;
447 }
448 }
449 }
450 if (d->dp_lbase & 0x01) {
451 s = st - d->st;
452 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase);
453 stl_le_pci_dma(&d->pci, addr + 8*s, st->lpib);
454 }
455 dprint(d, 3, "dma: --\n");
456
457 if (irq) {
458 st->ctl |= (1 << 26); /* buffer completion interrupt */
459 intel_hda_update_irq(d);
460 }
461 return true;
462 }
463
464 static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st)
465 {
466 hwaddr addr;
467 uint8_t buf[16];
468 uint32_t i;
469
470 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase);
471 st->bentries = st->lvi +1;
472 g_free(st->bpl);
473 st->bpl = g_malloc(sizeof(bpl) * st->bentries);
474 for (i = 0; i < st->bentries; i++, addr += 16) {
475 pci_dma_read(&d->pci, addr, buf, 16);
476 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf);
477 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8));
478 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12));
479 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n",
480 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags);
481 }
482
483 st->bsize = st->cbl;
484 st->lpib = 0;
485 st->be = 0;
486 st->bp = 0;
487 }
488
489 static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output)
490 {
491 BusChild *kid;
492 HDACodecDevice *cdev;
493
494 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
495 DeviceState *qdev = kid->child;
496 HDACodecDeviceClass *cdc;
497
498 cdev = HDA_CODEC_DEVICE(qdev);
499 cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev);
500 if (cdc->stream) {
501 cdc->stream(cdev, stream, running, output);
502 }
503 }
504 }
505
506 /* --------------------------------------------------------------------- */
507
508 static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
509 {
510 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) {
511 intel_hda_reset(DEVICE(d));
512 }
513 }
514
515 static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
516 {
517 intel_hda_update_irq(d);
518 }
519
520 static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
521 {
522 intel_hda_update_irq(d);
523 }
524
525 static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
526 {
527 intel_hda_update_irq(d);
528 }
529
530 static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg)
531 {
532 int64_t ns;
533
534 ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - d->wall_base_ns;
535 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */
536 }
537
538 static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
539 {
540 intel_hda_corb_run(d);
541 }
542
543 static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
544 {
545 intel_hda_corb_run(d);
546 }
547
548 static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
549 {
550 if (d->rirb_wp & ICH6_RIRBWP_RST) {
551 d->rirb_wp = 0;
552 }
553 }
554
555 static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
556 {
557 intel_hda_update_irq(d);
558
559 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) {
560 /* cleared ICH6_RBSTS_IRQ */
561 d->rirb_count = 0;
562 intel_hda_corb_run(d);
563 }
564 }
565
566 static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
567 {
568 if (d->ics & ICH6_IRS_BUSY) {
569 intel_hda_corb_run(d);
570 }
571 }
572
573 static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
574 {
575 bool output = reg->stream >= 4;
576 IntelHDAStream *st = d->st + reg->stream;
577
578 if (st->ctl & 0x01) {
579 /* reset */
580 dprint(d, 1, "st #%d: reset\n", reg->stream);
581 st->ctl = SD_STS_FIFO_READY << 24;
582 }
583 if ((st->ctl & 0x02) != (old & 0x02)) {
584 uint32_t stnr = (st->ctl >> 20) & 0x0f;
585 /* run bit flipped */
586 if (st->ctl & 0x02) {
587 /* start */
588 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n",
589 reg->stream, stnr, st->cbl);
590 intel_hda_parse_bdl(d, st);
591 intel_hda_notify_codecs(d, stnr, true, output);
592 } else {
593 /* stop */
594 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr);
595 intel_hda_notify_codecs(d, stnr, false, output);
596 }
597 }
598 intel_hda_update_irq(d);
599 }
600
601 /* --------------------------------------------------------------------- */
602
603 #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o))
604
605 static const struct IntelHDAReg regtab[] = {
606 /* global */
607 [ ICH6_REG_GCAP ] = {
608 .name = "GCAP",
609 .size = 2,
610 .reset = 0x4401,
611 },
612 [ ICH6_REG_VMIN ] = {
613 .name = "VMIN",
614 .size = 1,
615 },
616 [ ICH6_REG_VMAJ ] = {
617 .name = "VMAJ",
618 .size = 1,
619 .reset = 1,
620 },
621 [ ICH6_REG_OUTPAY ] = {
622 .name = "OUTPAY",
623 .size = 2,
624 .reset = 0x3c,
625 },
626 [ ICH6_REG_INPAY ] = {
627 .name = "INPAY",
628 .size = 2,
629 .reset = 0x1d,
630 },
631 [ ICH6_REG_GCTL ] = {
632 .name = "GCTL",
633 .size = 4,
634 .wmask = 0x0103,
635 .offset = offsetof(IntelHDAState, g_ctl),
636 .whandler = intel_hda_set_g_ctl,
637 },
638 [ ICH6_REG_WAKEEN ] = {
639 .name = "WAKEEN",
640 .size = 2,
641 .wmask = 0x7fff,
642 .offset = offsetof(IntelHDAState, wake_en),
643 .whandler = intel_hda_set_wake_en,
644 },
645 [ ICH6_REG_STATESTS ] = {
646 .name = "STATESTS",
647 .size = 2,
648 .wmask = 0x7fff,
649 .wclear = 0x7fff,
650 .offset = offsetof(IntelHDAState, state_sts),
651 .whandler = intel_hda_set_state_sts,
652 },
653
654 /* interrupts */
655 [ ICH6_REG_INTCTL ] = {
656 .name = "INTCTL",
657 .size = 4,
658 .wmask = 0xc00000ff,
659 .offset = offsetof(IntelHDAState, int_ctl),
660 .whandler = intel_hda_set_int_ctl,
661 },
662 [ ICH6_REG_INTSTS ] = {
663 .name = "INTSTS",
664 .size = 4,
665 .wmask = 0xc00000ff,
666 .wclear = 0xc00000ff,
667 .offset = offsetof(IntelHDAState, int_sts),
668 },
669
670 /* misc */
671 [ ICH6_REG_WALLCLK ] = {
672 .name = "WALLCLK",
673 .size = 4,
674 .offset = offsetof(IntelHDAState, wall_clk),
675 .rhandler = intel_hda_get_wall_clk,
676 },
677 [ ICH6_REG_WALLCLK + 0x2000 ] = {
678 .name = "WALLCLK(alias)",
679 .size = 4,
680 .offset = offsetof(IntelHDAState, wall_clk),
681 .rhandler = intel_hda_get_wall_clk,
682 },
683
684 /* dma engine */
685 [ ICH6_REG_CORBLBASE ] = {
686 .name = "CORBLBASE",
687 .size = 4,
688 .wmask = 0xffffff80,
689 .offset = offsetof(IntelHDAState, corb_lbase),
690 },
691 [ ICH6_REG_CORBUBASE ] = {
692 .name = "CORBUBASE",
693 .size = 4,
694 .wmask = 0xffffffff,
695 .offset = offsetof(IntelHDAState, corb_ubase),
696 },
697 [ ICH6_REG_CORBWP ] = {
698 .name = "CORBWP",
699 .size = 2,
700 .wmask = 0xff,
701 .offset = offsetof(IntelHDAState, corb_wp),
702 .whandler = intel_hda_set_corb_wp,
703 },
704 [ ICH6_REG_CORBRP ] = {
705 .name = "CORBRP",
706 .size = 2,
707 .wmask = 0x80ff,
708 .offset = offsetof(IntelHDAState, corb_rp),
709 },
710 [ ICH6_REG_CORBCTL ] = {
711 .name = "CORBCTL",
712 .size = 1,
713 .wmask = 0x03,
714 .offset = offsetof(IntelHDAState, corb_ctl),
715 .whandler = intel_hda_set_corb_ctl,
716 },
717 [ ICH6_REG_CORBSTS ] = {
718 .name = "CORBSTS",
719 .size = 1,
720 .wmask = 0x01,
721 .wclear = 0x01,
722 .offset = offsetof(IntelHDAState, corb_sts),
723 },
724 [ ICH6_REG_CORBSIZE ] = {
725 .name = "CORBSIZE",
726 .size = 1,
727 .reset = 0x42,
728 .offset = offsetof(IntelHDAState, corb_size),
729 },
730 [ ICH6_REG_RIRBLBASE ] = {
731 .name = "RIRBLBASE",
732 .size = 4,
733 .wmask = 0xffffff80,
734 .offset = offsetof(IntelHDAState, rirb_lbase),
735 },
736 [ ICH6_REG_RIRBUBASE ] = {
737 .name = "RIRBUBASE",
738 .size = 4,
739 .wmask = 0xffffffff,
740 .offset = offsetof(IntelHDAState, rirb_ubase),
741 },
742 [ ICH6_REG_RIRBWP ] = {
743 .name = "RIRBWP",
744 .size = 2,
745 .wmask = 0x8000,
746 .offset = offsetof(IntelHDAState, rirb_wp),
747 .whandler = intel_hda_set_rirb_wp,
748 },
749 [ ICH6_REG_RINTCNT ] = {
750 .name = "RINTCNT",
751 .size = 2,
752 .wmask = 0xff,
753 .offset = offsetof(IntelHDAState, rirb_cnt),
754 },
755 [ ICH6_REG_RIRBCTL ] = {
756 .name = "RIRBCTL",
757 .size = 1,
758 .wmask = 0x07,
759 .offset = offsetof(IntelHDAState, rirb_ctl),
760 },
761 [ ICH6_REG_RIRBSTS ] = {
762 .name = "RIRBSTS",
763 .size = 1,
764 .wmask = 0x05,
765 .wclear = 0x05,
766 .offset = offsetof(IntelHDAState, rirb_sts),
767 .whandler = intel_hda_set_rirb_sts,
768 },
769 [ ICH6_REG_RIRBSIZE ] = {
770 .name = "RIRBSIZE",
771 .size = 1,
772 .reset = 0x42,
773 .offset = offsetof(IntelHDAState, rirb_size),
774 },
775
776 [ ICH6_REG_DPLBASE ] = {
777 .name = "DPLBASE",
778 .size = 4,
779 .wmask = 0xffffff81,
780 .offset = offsetof(IntelHDAState, dp_lbase),
781 },
782 [ ICH6_REG_DPUBASE ] = {
783 .name = "DPUBASE",
784 .size = 4,
785 .wmask = 0xffffffff,
786 .offset = offsetof(IntelHDAState, dp_ubase),
787 },
788
789 [ ICH6_REG_IC ] = {
790 .name = "ICW",
791 .size = 4,
792 .wmask = 0xffffffff,
793 .offset = offsetof(IntelHDAState, icw),
794 },
795 [ ICH6_REG_IR ] = {
796 .name = "IRR",
797 .size = 4,
798 .offset = offsetof(IntelHDAState, irr),
799 },
800 [ ICH6_REG_IRS ] = {
801 .name = "ICS",
802 .size = 2,
803 .wmask = 0x0003,
804 .wclear = 0x0002,
805 .offset = offsetof(IntelHDAState, ics),
806 .whandler = intel_hda_set_ics,
807 },
808
809 #define HDA_STREAM(_t, _i) \
810 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \
811 .stream = _i, \
812 .name = _t stringify(_i) " CTL", \
813 .size = 4, \
814 .wmask = 0x1cff001f, \
815 .offset = offsetof(IntelHDAState, st[_i].ctl), \
816 .whandler = intel_hda_set_st_ctl, \
817 }, \
818 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \
819 .stream = _i, \
820 .name = _t stringify(_i) " CTL(stnr)", \
821 .size = 1, \
822 .shift = 16, \
823 .wmask = 0x00ff0000, \
824 .offset = offsetof(IntelHDAState, st[_i].ctl), \
825 .whandler = intel_hda_set_st_ctl, \
826 }, \
827 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \
828 .stream = _i, \
829 .name = _t stringify(_i) " CTL(sts)", \
830 .size = 1, \
831 .shift = 24, \
832 .wmask = 0x1c000000, \
833 .wclear = 0x1c000000, \
834 .offset = offsetof(IntelHDAState, st[_i].ctl), \
835 .whandler = intel_hda_set_st_ctl, \
836 .reset = SD_STS_FIFO_READY << 24 \
837 }, \
838 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \
839 .stream = _i, \
840 .name = _t stringify(_i) " LPIB", \
841 .size = 4, \
842 .offset = offsetof(IntelHDAState, st[_i].lpib), \
843 }, \
844 [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \
845 .stream = _i, \
846 .name = _t stringify(_i) " LPIB(alias)", \
847 .size = 4, \
848 .offset = offsetof(IntelHDAState, st[_i].lpib), \
849 }, \
850 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \
851 .stream = _i, \
852 .name = _t stringify(_i) " CBL", \
853 .size = 4, \
854 .wmask = 0xffffffff, \
855 .offset = offsetof(IntelHDAState, st[_i].cbl), \
856 }, \
857 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \
858 .stream = _i, \
859 .name = _t stringify(_i) " LVI", \
860 .size = 2, \
861 .wmask = 0x00ff, \
862 .offset = offsetof(IntelHDAState, st[_i].lvi), \
863 }, \
864 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \
865 .stream = _i, \
866 .name = _t stringify(_i) " FIFOS", \
867 .size = 2, \
868 .reset = HDA_BUFFER_SIZE, \
869 }, \
870 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \
871 .stream = _i, \
872 .name = _t stringify(_i) " FMT", \
873 .size = 2, \
874 .wmask = 0x7f7f, \
875 .offset = offsetof(IntelHDAState, st[_i].fmt), \
876 }, \
877 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \
878 .stream = _i, \
879 .name = _t stringify(_i) " BDLPL", \
880 .size = 4, \
881 .wmask = 0xffffff80, \
882 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \
883 }, \
884 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \
885 .stream = _i, \
886 .name = _t stringify(_i) " BDLPU", \
887 .size = 4, \
888 .wmask = 0xffffffff, \
889 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \
890 }, \
891
892 HDA_STREAM("IN", 0)
893 HDA_STREAM("IN", 1)
894 HDA_STREAM("IN", 2)
895 HDA_STREAM("IN", 3)
896
897 HDA_STREAM("OUT", 4)
898 HDA_STREAM("OUT", 5)
899 HDA_STREAM("OUT", 6)
900 HDA_STREAM("OUT", 7)
901
902 };
903
904 static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr)
905 {
906 const IntelHDAReg *reg;
907
908 if (addr >= ARRAY_SIZE(regtab)) {
909 goto noreg;
910 }
911 reg = regtab+addr;
912 if (reg->name == NULL) {
913 goto noreg;
914 }
915 return reg;
916
917 noreg:
918 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr);
919 return NULL;
920 }
921
922 static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg)
923 {
924 uint8_t *addr = (void*)d;
925
926 addr += reg->offset;
927 return (uint32_t*)addr;
928 }
929
930 static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val,
931 uint32_t wmask)
932 {
933 uint32_t *addr;
934 uint32_t old;
935
936 if (!reg) {
937 return;
938 }
939
940 if (d->debug) {
941 time_t now = time(NULL);
942 if (d->last_write && d->last_reg == reg && d->last_val == val) {
943 d->repeat_count++;
944 if (d->last_sec != now) {
945 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
946 d->last_sec = now;
947 d->repeat_count = 0;
948 }
949 } else {
950 if (d->repeat_count) {
951 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
952 }
953 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask);
954 d->last_write = 1;
955 d->last_reg = reg;
956 d->last_val = val;
957 d->last_sec = now;
958 d->repeat_count = 0;
959 }
960 }
961 assert(reg->offset != 0);
962
963 addr = intel_hda_reg_addr(d, reg);
964 old = *addr;
965
966 if (reg->shift) {
967 val <<= reg->shift;
968 wmask <<= reg->shift;
969 }
970 wmask &= reg->wmask;
971 *addr &= ~wmask;
972 *addr |= wmask & val;
973 *addr &= ~(val & reg->wclear);
974
975 if (reg->whandler) {
976 reg->whandler(d, reg, old);
977 }
978 }
979
980 static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg,
981 uint32_t rmask)
982 {
983 uint32_t *addr, ret;
984
985 if (!reg) {
986 return 0;
987 }
988
989 if (reg->rhandler) {
990 reg->rhandler(d, reg);
991 }
992
993 if (reg->offset == 0) {
994 /* constant read-only register */
995 ret = reg->reset;
996 } else {
997 addr = intel_hda_reg_addr(d, reg);
998 ret = *addr;
999 if (reg->shift) {
1000 ret >>= reg->shift;
1001 }
1002 ret &= rmask;
1003 }
1004 if (d->debug) {
1005 time_t now = time(NULL);
1006 if (!d->last_write && d->last_reg == reg && d->last_val == ret) {
1007 d->repeat_count++;
1008 if (d->last_sec != now) {
1009 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1010 d->last_sec = now;
1011 d->repeat_count = 0;
1012 }
1013 } else {
1014 if (d->repeat_count) {
1015 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1016 }
1017 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask);
1018 d->last_write = 0;
1019 d->last_reg = reg;
1020 d->last_val = ret;
1021 d->last_sec = now;
1022 d->repeat_count = 0;
1023 }
1024 }
1025 return ret;
1026 }
1027
1028 static void intel_hda_regs_reset(IntelHDAState *d)
1029 {
1030 uint32_t *addr;
1031 int i;
1032
1033 for (i = 0; i < ARRAY_SIZE(regtab); i++) {
1034 if (regtab[i].name == NULL) {
1035 continue;
1036 }
1037 if (regtab[i].offset == 0) {
1038 continue;
1039 }
1040 addr = intel_hda_reg_addr(d, regtab + i);
1041 *addr = regtab[i].reset;
1042 }
1043 }
1044
1045 /* --------------------------------------------------------------------- */
1046
1047 static void intel_hda_mmio_write(void *opaque, hwaddr addr, uint64_t val,
1048 unsigned size)
1049 {
1050 IntelHDAState *d = opaque;
1051 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1052
1053 intel_hda_reg_write(d, reg, val, MAKE_64BIT_MASK(0, size * 8));
1054 }
1055
1056 static uint64_t intel_hda_mmio_read(void *opaque, hwaddr addr, unsigned size)
1057 {
1058 IntelHDAState *d = opaque;
1059 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1060
1061 return intel_hda_reg_read(d, reg, MAKE_64BIT_MASK(0, size * 8));
1062 }
1063
1064 static const MemoryRegionOps intel_hda_mmio_ops = {
1065 .read = intel_hda_mmio_read,
1066 .write = intel_hda_mmio_write,
1067 .impl = {
1068 .min_access_size = 1,
1069 .max_access_size = 4,
1070 },
1071 .endianness = DEVICE_NATIVE_ENDIAN,
1072 };
1073
1074 /* --------------------------------------------------------------------- */
1075
1076 static void intel_hda_reset(DeviceState *dev)
1077 {
1078 BusChild *kid;
1079 IntelHDAState *d = INTEL_HDA(dev);
1080 HDACodecDevice *cdev;
1081
1082 intel_hda_regs_reset(d);
1083 d->wall_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1084
1085 /* reset codecs */
1086 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
1087 DeviceState *qdev = kid->child;
1088 cdev = HDA_CODEC_DEVICE(qdev);
1089 device_reset(DEVICE(cdev));
1090 d->state_sts |= (1 << cdev->cad);
1091 }
1092 intel_hda_update_irq(d);
1093 }
1094
1095 static void intel_hda_realize(PCIDevice *pci, Error **errp)
1096 {
1097 IntelHDAState *d = INTEL_HDA(pci);
1098 uint8_t *conf = d->pci.config;
1099 Error *err = NULL;
1100 int ret;
1101
1102 d->name = object_get_typename(OBJECT(d));
1103
1104 pci_config_set_interrupt_pin(conf, 1);
1105
1106 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1107 conf[0x40] = 0x01;
1108
1109 if (d->msi != ON_OFF_AUTO_OFF) {
1110 ret = msi_init(&d->pci, d->old_msi_addr ? 0x50 : 0x60,
1111 1, true, false, &err);
1112 /* Any error other than -ENOTSUP(board's MSI support is broken)
1113 * is a programming error */
1114 assert(!ret || ret == -ENOTSUP);
1115 if (ret && d->msi == ON_OFF_AUTO_ON) {
1116 /* Can't satisfy user's explicit msi=on request, fail */
1117 error_append_hint(&err, "You have to use msi=auto (default) or "
1118 "msi=off with this machine type.\n");
1119 error_propagate(errp, err);
1120 return;
1121 }
1122 assert(!err || d->msi == ON_OFF_AUTO_AUTO);
1123 /* With msi=auto, we fall back to MSI off silently */
1124 error_free(err);
1125 }
1126
1127 memory_region_init_io(&d->mmio, OBJECT(d), &intel_hda_mmio_ops, d,
1128 "intel-hda", 0x4000);
1129 pci_register_bar(&d->pci, 0, 0, &d->mmio);
1130
1131 hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs),
1132 intel_hda_response, intel_hda_xfer);
1133 }
1134
1135 static void intel_hda_exit(PCIDevice *pci)
1136 {
1137 IntelHDAState *d = INTEL_HDA(pci);
1138
1139 msi_uninit(&d->pci);
1140 }
1141
1142 static int intel_hda_post_load(void *opaque, int version)
1143 {
1144 IntelHDAState* d = opaque;
1145 int i;
1146
1147 dprint(d, 1, "%s\n", __func__);
1148 for (i = 0; i < ARRAY_SIZE(d->st); i++) {
1149 if (d->st[i].ctl & 0x02) {
1150 intel_hda_parse_bdl(d, &d->st[i]);
1151 }
1152 }
1153 intel_hda_update_irq(d);
1154 return 0;
1155 }
1156
1157 static const VMStateDescription vmstate_intel_hda_stream = {
1158 .name = "intel-hda-stream",
1159 .version_id = 1,
1160 .fields = (VMStateField[]) {
1161 VMSTATE_UINT32(ctl, IntelHDAStream),
1162 VMSTATE_UINT32(lpib, IntelHDAStream),
1163 VMSTATE_UINT32(cbl, IntelHDAStream),
1164 VMSTATE_UINT32(lvi, IntelHDAStream),
1165 VMSTATE_UINT32(fmt, IntelHDAStream),
1166 VMSTATE_UINT32(bdlp_lbase, IntelHDAStream),
1167 VMSTATE_UINT32(bdlp_ubase, IntelHDAStream),
1168 VMSTATE_END_OF_LIST()
1169 }
1170 };
1171
1172 static const VMStateDescription vmstate_intel_hda = {
1173 .name = "intel-hda",
1174 .version_id = 1,
1175 .post_load = intel_hda_post_load,
1176 .fields = (VMStateField[]) {
1177 VMSTATE_PCI_DEVICE(pci, IntelHDAState),
1178
1179 /* registers */
1180 VMSTATE_UINT32(g_ctl, IntelHDAState),
1181 VMSTATE_UINT32(wake_en, IntelHDAState),
1182 VMSTATE_UINT32(state_sts, IntelHDAState),
1183 VMSTATE_UINT32(int_ctl, IntelHDAState),
1184 VMSTATE_UINT32(int_sts, IntelHDAState),
1185 VMSTATE_UINT32(wall_clk, IntelHDAState),
1186 VMSTATE_UINT32(corb_lbase, IntelHDAState),
1187 VMSTATE_UINT32(corb_ubase, IntelHDAState),
1188 VMSTATE_UINT32(corb_rp, IntelHDAState),
1189 VMSTATE_UINT32(corb_wp, IntelHDAState),
1190 VMSTATE_UINT32(corb_ctl, IntelHDAState),
1191 VMSTATE_UINT32(corb_sts, IntelHDAState),
1192 VMSTATE_UINT32(corb_size, IntelHDAState),
1193 VMSTATE_UINT32(rirb_lbase, IntelHDAState),
1194 VMSTATE_UINT32(rirb_ubase, IntelHDAState),
1195 VMSTATE_UINT32(rirb_wp, IntelHDAState),
1196 VMSTATE_UINT32(rirb_cnt, IntelHDAState),
1197 VMSTATE_UINT32(rirb_ctl, IntelHDAState),
1198 VMSTATE_UINT32(rirb_sts, IntelHDAState),
1199 VMSTATE_UINT32(rirb_size, IntelHDAState),
1200 VMSTATE_UINT32(dp_lbase, IntelHDAState),
1201 VMSTATE_UINT32(dp_ubase, IntelHDAState),
1202 VMSTATE_UINT32(icw, IntelHDAState),
1203 VMSTATE_UINT32(irr, IntelHDAState),
1204 VMSTATE_UINT32(ics, IntelHDAState),
1205 VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0,
1206 vmstate_intel_hda_stream,
1207 IntelHDAStream),
1208
1209 /* additional state info */
1210 VMSTATE_UINT32(rirb_count, IntelHDAState),
1211 VMSTATE_INT64(wall_base_ns, IntelHDAState),
1212
1213 VMSTATE_END_OF_LIST()
1214 }
1215 };
1216
1217 static Property intel_hda_properties[] = {
1218 DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0),
1219 DEFINE_PROP_ON_OFF_AUTO("msi", IntelHDAState, msi, ON_OFF_AUTO_AUTO),
1220 DEFINE_PROP_BOOL("old_msi_addr", IntelHDAState, old_msi_addr, false),
1221 DEFINE_PROP_END_OF_LIST(),
1222 };
1223
1224 static void intel_hda_class_init(ObjectClass *klass, void *data)
1225 {
1226 DeviceClass *dc = DEVICE_CLASS(klass);
1227 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1228
1229 k->realize = intel_hda_realize;
1230 k->exit = intel_hda_exit;
1231 k->vendor_id = PCI_VENDOR_ID_INTEL;
1232 k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO;
1233 dc->reset = intel_hda_reset;
1234 dc->vmsd = &vmstate_intel_hda;
1235 dc->props = intel_hda_properties;
1236 }
1237
1238 static void intel_hda_class_init_ich6(ObjectClass *klass, void *data)
1239 {
1240 DeviceClass *dc = DEVICE_CLASS(klass);
1241 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1242
1243 k->device_id = 0x2668;
1244 k->revision = 1;
1245 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
1246 dc->desc = "Intel HD Audio Controller (ich6)";
1247 }
1248
1249 static void intel_hda_class_init_ich9(ObjectClass *klass, void *data)
1250 {
1251 DeviceClass *dc = DEVICE_CLASS(klass);
1252 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1253
1254 k->device_id = 0x293e;
1255 k->revision = 3;
1256 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
1257 dc->desc = "Intel HD Audio Controller (ich9)";
1258 }
1259
1260 static const TypeInfo intel_hda_info = {
1261 .name = TYPE_INTEL_HDA_GENERIC,
1262 .parent = TYPE_PCI_DEVICE,
1263 .instance_size = sizeof(IntelHDAState),
1264 .class_init = intel_hda_class_init,
1265 .abstract = true,
1266 .interfaces = (InterfaceInfo[]) {
1267 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1268 { },
1269 },
1270 };
1271
1272 static const TypeInfo intel_hda_info_ich6 = {
1273 .name = "intel-hda",
1274 .parent = TYPE_INTEL_HDA_GENERIC,
1275 .class_init = intel_hda_class_init_ich6,
1276 };
1277
1278 static const TypeInfo intel_hda_info_ich9 = {
1279 .name = "ich9-intel-hda",
1280 .parent = TYPE_INTEL_HDA_GENERIC,
1281 .class_init = intel_hda_class_init_ich9,
1282 };
1283
1284 static void hda_codec_device_class_init(ObjectClass *klass, void *data)
1285 {
1286 DeviceClass *k = DEVICE_CLASS(klass);
1287 k->realize = hda_codec_dev_realize;
1288 k->unrealize = hda_codec_dev_unrealize;
1289 set_bit(DEVICE_CATEGORY_SOUND, k->categories);
1290 k->bus_type = TYPE_HDA_BUS;
1291 k->props = hda_props;
1292 }
1293
1294 static const TypeInfo hda_codec_device_type_info = {
1295 .name = TYPE_HDA_CODEC_DEVICE,
1296 .parent = TYPE_DEVICE,
1297 .instance_size = sizeof(HDACodecDevice),
1298 .abstract = true,
1299 .class_size = sizeof(HDACodecDeviceClass),
1300 .class_init = hda_codec_device_class_init,
1301 };
1302
1303 /*
1304 * create intel hda controller with codec attached to it,
1305 * so '-soundhw hda' works.
1306 */
1307 static int intel_hda_and_codec_init(PCIBus *bus)
1308 {
1309 DeviceState *controller;
1310 BusState *hdabus;
1311 DeviceState *codec;
1312
1313 controller = DEVICE(pci_create_simple(bus, -1, "intel-hda"));
1314 hdabus = QLIST_FIRST(&controller->child_bus);
1315 codec = qdev_create(hdabus, "hda-duplex");
1316 qdev_init_nofail(codec);
1317 return 0;
1318 }
1319
1320 static void intel_hda_register_types(void)
1321 {
1322 type_register_static(&hda_codec_bus_info);
1323 type_register_static(&intel_hda_info);
1324 type_register_static(&intel_hda_info_ich6);
1325 type_register_static(&intel_hda_info_ich9);
1326 type_register_static(&hda_codec_device_type_info);
1327 pci_register_soundhw("hda", "Intel HD Audio", intel_hda_and_codec_init);
1328 }
1329
1330 type_init(intel_hda_register_types)
AR7 emulation for QEMU