2 * Private peripheral timer/watchdog blocks for ARM 11MPCore and A9MP
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Copyright (c) 2011 Linaro Limited
6 * Written by Paul Brook, Peter Maydell
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu/timer.h"
25 /* This device implements the per-cpu private timer and watchdog block
26 * which is used in both the ARM11MPCore and Cortex-A9MP.
31 /* State of a single timer or watchdog block */
46 TimerBlock timerblock
[MAX_CPUS
];
50 static inline int get_current_cpu(ARMMPTimerState
*s
)
52 CPUState
*cpu_single_cpu
= ENV_GET_CPU(cpu_single_env
);
54 if (cpu_single_cpu
->cpu_index
>= s
->num_cpu
) {
55 hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n",
56 s
->num_cpu
, cpu_single_cpu
->cpu_index
);
58 return cpu_single_cpu
->cpu_index
;
61 static inline void timerblock_update_irq(TimerBlock
*tb
)
63 qemu_set_irq(tb
->irq
, tb
->status
);
66 /* Return conversion factor from mpcore timer ticks to qemu timer ticks. */
67 static inline uint32_t timerblock_scale(TimerBlock
*tb
)
69 return (((tb
->control
>> 8) & 0xff) + 1) * 10;
72 static void timerblock_reload(TimerBlock
*tb
, int restart
)
78 tb
->tick
= qemu_get_clock_ns(vm_clock
);
80 tb
->tick
+= (int64_t)tb
->count
* timerblock_scale(tb
);
81 qemu_mod_timer(tb
->timer
, tb
->tick
);
84 static void timerblock_tick(void *opaque
)
86 TimerBlock
*tb
= (TimerBlock
*)opaque
;
88 if (tb
->control
& 2) {
90 timerblock_reload(tb
, 0);
94 timerblock_update_irq(tb
);
97 static uint64_t timerblock_read(void *opaque
, hwaddr addr
,
100 TimerBlock
*tb
= (TimerBlock
*)opaque
;
105 case 4: /* Counter. */
106 if (((tb
->control
& 1) == 0) || (tb
->count
== 0)) {
109 /* Slow and ugly, but hopefully won't happen too often. */
110 val
= tb
->tick
- qemu_get_clock_ns(vm_clock
);
111 val
/= timerblock_scale(tb
);
116 case 8: /* Control. */
118 case 12: /* Interrupt status. */
125 static void timerblock_write(void *opaque
, hwaddr addr
,
126 uint64_t value
, unsigned size
)
128 TimerBlock
*tb
= (TimerBlock
*)opaque
;
134 case 4: /* Counter. */
135 if ((tb
->control
& 1) && tb
->count
) {
136 /* Cancel the previous timer. */
137 qemu_del_timer(tb
->timer
);
140 if (tb
->control
& 1) {
141 timerblock_reload(tb
, 1);
144 case 8: /* Control. */
147 if (((old
& 1) == 0) && (value
& 1)) {
148 if (tb
->count
== 0 && (tb
->control
& 2)) {
149 tb
->count
= tb
->load
;
151 timerblock_reload(tb
, 1);
154 case 12: /* Interrupt status. */
155 tb
->status
&= ~value
;
156 timerblock_update_irq(tb
);
161 /* Wrapper functions to implement the "read timer/watchdog for
162 * the current CPU" memory regions.
164 static uint64_t arm_thistimer_read(void *opaque
, hwaddr addr
,
167 ARMMPTimerState
*s
= (ARMMPTimerState
*)opaque
;
168 int id
= get_current_cpu(s
);
169 return timerblock_read(&s
->timerblock
[id
], addr
, size
);
172 static void arm_thistimer_write(void *opaque
, hwaddr addr
,
173 uint64_t value
, unsigned size
)
175 ARMMPTimerState
*s
= (ARMMPTimerState
*)opaque
;
176 int id
= get_current_cpu(s
);
177 timerblock_write(&s
->timerblock
[id
], addr
, value
, size
);
180 static const MemoryRegionOps arm_thistimer_ops
= {
181 .read
= arm_thistimer_read
,
182 .write
= arm_thistimer_write
,
184 .min_access_size
= 4,
185 .max_access_size
= 4,
187 .endianness
= DEVICE_NATIVE_ENDIAN
,
190 static const MemoryRegionOps timerblock_ops
= {
191 .read
= timerblock_read
,
192 .write
= timerblock_write
,
194 .min_access_size
= 4,
195 .max_access_size
= 4,
197 .endianness
= DEVICE_NATIVE_ENDIAN
,
200 static void timerblock_reset(TimerBlock
*tb
)
208 qemu_del_timer(tb
->timer
);
212 static void arm_mptimer_reset(DeviceState
*dev
)
215 FROM_SYSBUS(ARMMPTimerState
, SYS_BUS_DEVICE(dev
));
217 for (i
= 0; i
< ARRAY_SIZE(s
->timerblock
); i
++) {
218 timerblock_reset(&s
->timerblock
[i
]);
222 static int arm_mptimer_init(SysBusDevice
*dev
)
224 ARMMPTimerState
*s
= FROM_SYSBUS(ARMMPTimerState
, dev
);
226 if (s
->num_cpu
< 1 || s
->num_cpu
> MAX_CPUS
) {
227 hw_error("%s: num-cpu must be between 1 and %d\n", __func__
, MAX_CPUS
);
229 /* We implement one timer block per CPU, and expose multiple MMIO regions:
230 * * region 0 is "timer for this core"
231 * * region 1 is "timer for core 0"
232 * * region 2 is "timer for core 1"
234 * The outgoing interrupt lines are
239 memory_region_init_io(&s
->iomem
, &arm_thistimer_ops
, s
,
240 "arm_mptimer_timer", 0x20);
241 sysbus_init_mmio(dev
, &s
->iomem
);
242 for (i
= 0; i
< s
->num_cpu
; i
++) {
243 TimerBlock
*tb
= &s
->timerblock
[i
];
244 tb
->timer
= qemu_new_timer_ns(vm_clock
, timerblock_tick
, tb
);
245 sysbus_init_irq(dev
, &tb
->irq
);
246 memory_region_init_io(&tb
->iomem
, &timerblock_ops
, tb
,
247 "arm_mptimer_timerblock", 0x20);
248 sysbus_init_mmio(dev
, &tb
->iomem
);
254 static const VMStateDescription vmstate_timerblock
= {
255 .name
= "arm_mptimer_timerblock",
257 .minimum_version_id
= 1,
258 .fields
= (VMStateField
[]) {
259 VMSTATE_UINT32(count
, TimerBlock
),
260 VMSTATE_UINT32(load
, TimerBlock
),
261 VMSTATE_UINT32(control
, TimerBlock
),
262 VMSTATE_UINT32(status
, TimerBlock
),
263 VMSTATE_INT64(tick
, TimerBlock
),
264 VMSTATE_END_OF_LIST()
268 static const VMStateDescription vmstate_arm_mptimer
= {
269 .name
= "arm_mptimer",
271 .minimum_version_id
= 2,
272 .fields
= (VMStateField
[]) {
273 VMSTATE_STRUCT_VARRAY_UINT32(timerblock
, ARMMPTimerState
, num_cpu
,
274 2, vmstate_timerblock
, TimerBlock
),
275 VMSTATE_END_OF_LIST()
279 static Property arm_mptimer_properties
[] = {
280 DEFINE_PROP_UINT32("num-cpu", ARMMPTimerState
, num_cpu
, 0),
281 DEFINE_PROP_END_OF_LIST()
284 static void arm_mptimer_class_init(ObjectClass
*klass
, void *data
)
286 DeviceClass
*dc
= DEVICE_CLASS(klass
);
287 SysBusDeviceClass
*sbc
= SYS_BUS_DEVICE_CLASS(klass
);
289 sbc
->init
= arm_mptimer_init
;
290 dc
->vmsd
= &vmstate_arm_mptimer
;
291 dc
->reset
= arm_mptimer_reset
;
293 dc
->props
= arm_mptimer_properties
;
296 static const TypeInfo arm_mptimer_info
= {
297 .name
= "arm_mptimer",
298 .parent
= TYPE_SYS_BUS_DEVICE
,
299 .instance_size
= sizeof(ARMMPTimerState
),
300 .class_init
= arm_mptimer_class_init
,
303 static void arm_mptimer_register_types(void)
305 type_register_static(&arm_mptimer_info
);
308 type_init(arm_mptimer_register_types
)