include/exec/exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef EXEC_ALL_H
  21 #define EXEC_ALL_H
  22
  23 #include "cpu.h"
  24 #if defined(CONFIG_USER_ONLY)
  25 #include "exec/cpu_ldst.h"
  26 #endif
  27 #include "exec/translation-block.h"
  28 #include "qemu/clang-tsa.h"
  29
  30 /**
  31  * cpu_loop_exit_requested:
  32  * @cpu: The CPU state to be tested
  33  *
  34  * Indicate if somebody asked for a return of the CPU to the main loop
  35  * (e.g., via cpu_exit() or cpu_interrupt()).
  36  *
  37  * This is helpful for architectures that support interruptible
  38  * instructions. After writing back all state to registers/memory, this
  39  * call can be used to check if it makes sense to return to the main loop
  40  * or to continue executing the interruptible instruction.
  41  */
  42 static inline bool cpu_loop_exit_requested(CPUState *cpu)
  43 {
  44     return (int32_t)qatomic_read(&cpu->neg.icount_decr.u32) < 0;
  45 }
  46
  47 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
  48 /* cputlb.c */
  49 /**
  50  * tlb_init - initialize a CPU's TLB
  51  * @cpu: CPU whose TLB should be initialized
  52  */
  53 void tlb_init(CPUState *cpu);
  54 /**
  55  * tlb_destroy - destroy a CPU's TLB
  56  * @cpu: CPU whose TLB should be destroyed
  57  */
  58 void tlb_destroy(CPUState *cpu);
  59 /**
  60  * tlb_flush_page:
  61  * @cpu: CPU whose TLB should be flushed
  62  * @addr: virtual address of page to be flushed
  63  *
  64  * Flush one page from the TLB of the specified CPU, for all
  65  * MMU indexes.
  66  */
  67 void tlb_flush_page(CPUState *cpu, vaddr addr);
  68 /**
  69  * tlb_flush_page_all_cpus:
  70  * @cpu: src CPU of the flush
  71  * @addr: virtual address of page to be flushed
  72  *
  73  * Flush one page from the TLB of the specified CPU, for all
  74  * MMU indexes.
  75  */
  76 void tlb_flush_page_all_cpus(CPUState *src, vaddr addr);
  77 /**
  78  * tlb_flush_page_all_cpus_synced:
  79  * @cpu: src CPU of the flush
  80  * @addr: virtual address of page to be flushed
  81  *
  82  * Flush one page from the TLB of the specified CPU, for all MMU
  83  * indexes like tlb_flush_page_all_cpus except the source vCPUs work
  84  * is scheduled as safe work meaning all flushes will be complete once
  85  * the source vCPUs safe work is complete. This will depend on when
  86  * the guests translation ends the TB.
  87  */
  88 void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr);
  89 /**
  90  * tlb_flush:
  91  * @cpu: CPU whose TLB should be flushed
  92  *
  93  * Flush the entire TLB for the specified CPU. Most CPU architectures
  94  * allow the implementation to drop entries from the TLB at any time
  95  * so this is generally safe. If more selective flushing is required
  96  * use one of the other functions for efficiency.
  97  */
  98 void tlb_flush(CPUState *cpu);
  99 /**
 100  * tlb_flush_all_cpus:
 101  * @cpu: src CPU of the flush
 102  */
 103 void tlb_flush_all_cpus(CPUState *src_cpu);
 104 /**
 105  * tlb_flush_all_cpus_synced:
 106  * @cpu: src CPU of the flush
 107  *
 108  * Like tlb_flush_all_cpus except this except the source vCPUs work is
 109  * scheduled as safe work meaning all flushes will be complete once
 110  * the source vCPUs safe work is complete. This will depend on when
 111  * the guests translation ends the TB.
 112  */
 113 void tlb_flush_all_cpus_synced(CPUState *src_cpu);
 114 /**
 115  * tlb_flush_page_by_mmuidx:
 116  * @cpu: CPU whose TLB should be flushed
 117  * @addr: virtual address of page to be flushed
 118  * @idxmap: bitmap of MMU indexes to flush
 119  *
 120  * Flush one page from the TLB of the specified CPU, for the specified
 121  * MMU indexes.
 122  */
 123 void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr,
 124                               uint16_t idxmap);
 125 /**
 126  * tlb_flush_page_by_mmuidx_all_cpus:
 127  * @cpu: Originating CPU of the flush
 128  * @addr: virtual address of page to be flushed
 129  * @idxmap: bitmap of MMU indexes to flush
 130  *
 131  * Flush one page from the TLB of all CPUs, for the specified
 132  * MMU indexes.
 133  */
 134 void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, vaddr addr,
 135                                        uint16_t idxmap);
 136 /**
 137  * tlb_flush_page_by_mmuidx_all_cpus_synced:
 138  * @cpu: Originating CPU of the flush
 139  * @addr: virtual address of page to be flushed
 140  * @idxmap: bitmap of MMU indexes to flush
 141  *
 142  * Flush one page from the TLB of all CPUs, for the specified MMU
 143  * indexes like tlb_flush_page_by_mmuidx_all_cpus except the source
 144  * vCPUs work is scheduled as safe work meaning all flushes will be
 145  * complete once  the source vCPUs safe work is complete. This will
 146  * depend on when the guests translation ends the TB.
 147  */
 148 void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
 149                                               uint16_t idxmap);
 150 /**
 151  * tlb_flush_by_mmuidx:
 152  * @cpu: CPU whose TLB should be flushed
 153  * @wait: If true ensure synchronisation by exiting the cpu_loop
 154  * @idxmap: bitmap of MMU indexes to flush
 155  *
 156  * Flush all entries from the TLB of the specified CPU, for the specified
 157  * MMU indexes.
 158  */
 159 void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap);
 160 /**
 161  * tlb_flush_by_mmuidx_all_cpus:
 162  * @cpu: Originating CPU of the flush
 163  * @idxmap: bitmap of MMU indexes to flush
 164  *
 165  * Flush all entries from all TLBs of all CPUs, for the specified
 166  * MMU indexes.
 167  */
 168 void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap);
 169 /**
 170  * tlb_flush_by_mmuidx_all_cpus_synced:
 171  * @cpu: Originating CPU of the flush
 172  * @idxmap: bitmap of MMU indexes to flush
 173  *
 174  * Flush all entries from all TLBs of all CPUs, for the specified
 175  * MMU indexes like tlb_flush_by_mmuidx_all_cpus except except the source
 176  * vCPUs work is scheduled as safe work meaning all flushes will be
 177  * complete once  the source vCPUs safe work is complete. This will
 178  * depend on when the guests translation ends the TB.
 179  */
 180 void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap);
 181
 182 /**
 183  * tlb_flush_page_bits_by_mmuidx
 184  * @cpu: CPU whose TLB should be flushed
 185  * @addr: virtual address of page to be flushed
 186  * @idxmap: bitmap of mmu indexes to flush
 187  * @bits: number of significant bits in address
 188  *
 189  * Similar to tlb_flush_page_mask, but with a bitmap of indexes.
 190  */
 191 void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr,
 192                                    uint16_t idxmap, unsigned bits);
 193
 194 /* Similarly, with broadcast and syncing. */
 195 void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, vaddr addr,
 196                                             uint16_t idxmap, unsigned bits);
 197 void tlb_flush_page_bits_by_mmuidx_all_cpus_synced
 198     (CPUState *cpu, vaddr addr, uint16_t idxmap, unsigned bits);
 199
 200 /**
 201  * tlb_flush_range_by_mmuidx
 202  * @cpu: CPU whose TLB should be flushed
 203  * @addr: virtual address of the start of the range to be flushed
 204  * @len: length of range to be flushed
 205  * @idxmap: bitmap of mmu indexes to flush
 206  * @bits: number of significant bits in address
 207  *
 208  * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len),
 209  * comparing only the low @bits worth of each virtual page.
 210  */
 211 void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
 212                                vaddr len, uint16_t idxmap,
 213                                unsigned bits);
 214
 215 /* Similarly, with broadcast and syncing. */
 216 void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, vaddr addr,
 217                                         vaddr len, uint16_t idxmap,
 218                                         unsigned bits);
 219 void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
 220                                                vaddr addr,
 221                                                vaddr len,
 222                                                uint16_t idxmap,
 223                                                unsigned bits);
 224
 225 /**
 226  * tlb_set_page_full:
 227  * @cpu: CPU context
 228  * @mmu_idx: mmu index of the tlb to modify
 229  * @addr: virtual address of the entry to add
 230  * @full: the details of the tlb entry
 231  *
 232  * Add an entry to @cpu tlb index @mmu_idx.  All of the fields of
 233  * @full must be filled, except for xlat_section, and constitute
 234  * the complete description of the translated page.
 235  *
 236  * This is generally called by the target tlb_fill function after
 237  * having performed a successful page table walk to find the physical
 238  * address and attributes for the translation.
 239  *
 240  * At most one entry for a given virtual address is permitted. Only a
 241  * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only
 242  * used by tlb_flush_page.
 243  */
 244 void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr,
 245                        CPUTLBEntryFull *full);
 246
 247 /**
 248  * tlb_set_page_with_attrs:
 249  * @cpu: CPU to add this TLB entry for
 250  * @addr: virtual address of page to add entry for
 251  * @paddr: physical address of the page
 252  * @attrs: memory transaction attributes
 253  * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)
 254  * @mmu_idx: MMU index to insert TLB entry for
 255  * @size: size of the page in bytes
 256  *
 257  * Add an entry to this CPU's TLB (a mapping from virtual address
 258  * @addr to physical address @paddr) with the specified memory
 259  * transaction attributes. This is generally called by the target CPU
 260  * specific code after it has been called through the tlb_fill()
 261  * entry point and performed a successful page table walk to find
 262  * the physical address and attributes for the virtual address
 263  * which provoked the TLB miss.
 264  *
 265  * At most one entry for a given virtual address is permitted. Only a
 266  * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only
 267  * used by tlb_flush_page.
 268  */
 269 void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr,
 270                              hwaddr paddr, MemTxAttrs attrs,
 271                              int prot, int mmu_idx, vaddr size);
 272 /* tlb_set_page:
 273  *
 274  * This function is equivalent to calling tlb_set_page_with_attrs()
 275  * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided
 276  * as a convenience for CPUs which don't use memory transaction attributes.
 277  */
 278 void tlb_set_page(CPUState *cpu, vaddr addr,
 279                   hwaddr paddr, int prot,
 280                   int mmu_idx, vaddr size);
 281 #else
 282 static inline void tlb_init(CPUState *cpu)
 283 {
 284 }
 285 static inline void tlb_destroy(CPUState *cpu)
 286 {
 287 }
 288 static inline void tlb_flush_page(CPUState *cpu, vaddr addr)
 289 {
 290 }
 291 static inline void tlb_flush_page_all_cpus(CPUState *src, vaddr addr)
 292 {
 293 }
 294 static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr)
 295 {
 296 }
 297 static inline void tlb_flush(CPUState *cpu)
 298 {
 299 }
 300 static inline void tlb_flush_all_cpus(CPUState *src_cpu)
 301 {
 302 }
 303 static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu)
 304 {
 305 }
 306 static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
 307                                             vaddr addr, uint16_t idxmap)
 308 {
 309 }
 310
 311 static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
 312 {
 313 }
 314 static inline void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu,
 315                                                      vaddr addr,
 316                                                      uint16_t idxmap)
 317 {
 318 }
 319 static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu,
 320                                                             vaddr addr,
 321                                                             uint16_t idxmap)
 322 {
 323 }
 324 static inline void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap)
 325 {
 326 }
 327
 328 static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
 329                                                        uint16_t idxmap)
 330 {
 331 }
 332 static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu,
 333                                                  vaddr addr,
 334                                                  uint16_t idxmap,
 335                                                  unsigned bits)
 336 {
 337 }
 338 static inline void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu,
 339                                                           vaddr addr,
 340                                                           uint16_t idxmap,
 341                                                           unsigned bits)
 342 {
 343 }
 344 static inline void
 345 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
 346                                               uint16_t idxmap, unsigned bits)
 347 {
 348 }
 349 static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
 350                                              vaddr len, uint16_t idxmap,
 351                                              unsigned bits)
 352 {
 353 }
 354 static inline void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu,
 355                                                       vaddr addr,
 356                                                       vaddr len,
 357                                                       uint16_t idxmap,
 358                                                       unsigned bits)
 359 {
 360 }
 361 static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
 362                                                              vaddr addr,
 363                                                              vaddr len,
 364                                                              uint16_t idxmap,
 365                                                              unsigned bits)
 366 {
 367 }
 368 #endif
 369 /**
 370  * probe_access:
 371  * @env: CPUArchState
 372  * @addr: guest virtual address to look up
 373  * @size: size of the access
 374  * @access_type: read, write or execute permission
 375  * @mmu_idx: MMU index to use for lookup
 376  * @retaddr: return address for unwinding
 377  *
 378  * Look up the guest virtual address @addr.  Raise an exception if the
 379  * page does not satisfy @access_type.  Raise an exception if the
 380  * access (@addr, @size) hits a watchpoint.  For writes, mark a clean
 381  * page as dirty.
 382  *
 383  * Finally, return the host address for a page that is backed by RAM,
 384  * or NULL if the page requires I/O.
 385  */
 386 void *probe_access(CPUArchState *env, vaddr addr, int size,
 387                    MMUAccessType access_type, int mmu_idx, uintptr_t retaddr);
 388
 389 static inline void *probe_write(CPUArchState *env, vaddr addr, int size,
 390                                 int mmu_idx, uintptr_t retaddr)
 391 {
 392     return probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, retaddr);
 393 }
 394
 395 static inline void *probe_read(CPUArchState *env, vaddr addr, int size,
 396                                int mmu_idx, uintptr_t retaddr)
 397 {
 398     return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr);
 399 }
 400
 401 /**
 402  * probe_access_flags:
 403  * @env: CPUArchState
 404  * @addr: guest virtual address to look up
 405  * @size: size of the access
 406  * @access_type: read, write or execute permission
 407  * @mmu_idx: MMU index to use for lookup
 408  * @nonfault: suppress the fault
 409  * @phost: return value for host address
 410  * @retaddr: return address for unwinding
 411  *
 412  * Similar to probe_access, loosely returning the TLB_FLAGS_MASK for
 413  * the page, and storing the host address for RAM in @phost.
 414  *
 415  * If @nonfault is set, do not raise an exception but return TLB_INVALID_MASK.
 416  * Do not handle watchpoints, but include TLB_WATCHPOINT in the returned flags.
 417  * Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags.
 418  * For simplicity, all "mmio-like" flags are folded to TLB_MMIO.
 419  */
 420 int probe_access_flags(CPUArchState *env, vaddr addr, int size,
 421                        MMUAccessType access_type, int mmu_idx,
 422                        bool nonfault, void **phost, uintptr_t retaddr);
 423
 424 #ifndef CONFIG_USER_ONLY
 425 /**
 426  * probe_access_full:
 427  * Like probe_access_flags, except also return into @pfull.
 428  *
 429  * The CPUTLBEntryFull structure returned via @pfull is transient
 430  * and must be consumed or copied immediately, before any further
 431  * access or changes to TLB @mmu_idx.
 432  */
 433 int probe_access_full(CPUArchState *env, vaddr addr, int size,
 434                       MMUAccessType access_type, int mmu_idx,
 435                       bool nonfault, void **phost,
 436                       CPUTLBEntryFull **pfull, uintptr_t retaddr);
 437
 438 /**
 439  * probe_access_mmu() - Like probe_access_full except cannot fault and
 440  * doesn't trigger instrumentation.
 441  *
 442  * @env: CPUArchState
 443  * @vaddr: virtual address to probe
 444  * @size: size of the probe
 445  * @access_type: read, write or execute permission
 446  * @mmu_idx: softmmu index
 447  * @phost: ptr to return value host address or NULL
 448  * @pfull: ptr to return value CPUTLBEntryFull structure or NULL
 449  *
 450  * The CPUTLBEntryFull structure returned via @pfull is transient
 451  * and must be consumed or copied immediately, before any further
 452  * access or changes to TLB @mmu_idx.
 453  *
 454  * Returns: TLB flags as per probe_access_flags()
 455  */
 456 int probe_access_full_mmu(CPUArchState *env, vaddr addr, int size,
 457                           MMUAccessType access_type, int mmu_idx,
 458                           void **phost, CPUTLBEntryFull **pfull);
 459
 460 #endif
 461
 462 static inline tb_page_addr_t tb_page_addr0(const TranslationBlock *tb)
 463 {
 464 #ifdef CONFIG_USER_ONLY
 465     return tb->itree.start;
 466 #else
 467     return tb->page_addr[0];
 468 #endif
 469 }
 470
 471 static inline tb_page_addr_t tb_page_addr1(const TranslationBlock *tb)
 472 {
 473 #ifdef CONFIG_USER_ONLY
 474     tb_page_addr_t next = tb->itree.last & TARGET_PAGE_MASK;
 475     return next == (tb->itree.start & TARGET_PAGE_MASK) ? -1 : next;
 476 #else
 477     return tb->page_addr[1];
 478 #endif
 479 }
 480
 481 static inline void tb_set_page_addr0(TranslationBlock *tb,
 482                                      tb_page_addr_t addr)
 483 {
 484 #ifdef CONFIG_USER_ONLY
 485     tb->itree.start = addr;
 486     /*
 487      * To begin, we record an interval of one byte.  When the translation
 488      * loop encounters a second page, the interval will be extended to
 489      * include the first byte of the second page, which is sufficient to
 490      * allow tb_page_addr1() above to work properly.  The final corrected
 491      * interval will be set by tb_page_add() from tb->size before the
 492      * node is added to the interval tree.
 493      */
 494     tb->itree.last = addr;
 495 #else
 496     tb->page_addr[0] = addr;
 497 #endif
 498 }
 499
 500 static inline void tb_set_page_addr1(TranslationBlock *tb,
 501                                      tb_page_addr_t addr)
 502 {
 503 #ifdef CONFIG_USER_ONLY
 504     /* Extend the interval to the first byte of the second page.  See above. */
 505     tb->itree.last = addr;
 506 #else
 507     tb->page_addr[1] = addr;
 508 #endif
 509 }
 510
 511 /* current cflags for hashing/comparison */
 512 uint32_t curr_cflags(CPUState *cpu);
 513
 514 /* TranslationBlock invalidate API */
 515 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
 516 void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t last);
 517 void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr);
 518
 519 /* GETPC is the true target of the return instruction that we'll execute.  */
 520 #if defined(CONFIG_TCG_INTERPRETER)
 521 extern __thread uintptr_t tci_tb_ptr;
 522 # define GETPC() tci_tb_ptr
 523 #else
 524 # define GETPC() \
 525     ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
 526 #endif
 527
 528 /* The true return address will often point to a host insn that is part of
 529    the next translated guest insn.  Adjust the address backward to point to
 530    the middle of the call insn.  Subtracting one would do the job except for
 531    several compressed mode architectures (arm, mips) which set the low bit
 532    to indicate the compressed mode; subtracting two works around that.  It
 533    is also the case that there are no host isas that contain a call insn
 534    smaller than 4 bytes, so we don't worry about special-casing this.  */
 535 #define GETPC_ADJ   2
 536
 537 #if !defined(CONFIG_USER_ONLY)
 538
 539 /**
 540  * iotlb_to_section:
 541  * @cpu: CPU performing the access
 542  * @index: TCG CPU IOTLB entry
 543  *
 544  * Given a TCG CPU IOTLB entry, return the MemoryRegionSection that
 545  * it refers to. @index will have been initially created and returned
 546  * by memory_region_section_get_iotlb().
 547  */
 548 struct MemoryRegionSection *iotlb_to_section(CPUState *cpu,
 549                                              hwaddr index, MemTxAttrs attrs);
 550 #endif
 551
 552 /**
 553  * get_page_addr_code_hostp()
 554  * @env: CPUArchState
 555  * @addr: guest virtual address of guest code
 556  *
 557  * See get_page_addr_code() (full-system version) for documentation on the
 558  * return value.
 559  *
 560  * Sets *@hostp (when @hostp is non-NULL) as follows.
 561  * If the return value is -1, sets *@hostp to NULL. Otherwise, sets *@hostp
 562  * to the host address where @addr's content is kept.
 563  *
 564  * Note: this function can trigger an exception.
 565  */
 566 tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, vaddr addr,
 567                                         void **hostp);
 568
 569 /**
 570  * get_page_addr_code()
 571  * @env: CPUArchState
 572  * @addr: guest virtual address of guest code
 573  *
 574  * If we cannot translate and execute from the entire RAM page, or if
 575  * the region is not backed by RAM, returns -1. Otherwise, returns the
 576  * ram_addr_t corresponding to the guest code at @addr.
 577  *
 578  * Note: this function can trigger an exception.
 579  */
 580 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env,
 581                                                 vaddr addr)
 582 {
 583     return get_page_addr_code_hostp(env, addr, NULL);
 584 }
 585
 586 #if defined(CONFIG_USER_ONLY)
 587 void TSA_NO_TSA mmap_lock(void);
 588 void TSA_NO_TSA mmap_unlock(void);
 589 bool have_mmap_lock(void);
 590
 591 static inline void mmap_unlock_guard(void *unused)
 592 {
 593     mmap_unlock();
 594 }
 595
 596 #define WITH_MMAP_LOCK_GUARD()                                            \
 597     for (int _mmap_lock_iter __attribute__((cleanup(mmap_unlock_guard)))  \
 598          = (mmap_lock(), 0); _mmap_lock_iter == 0; _mmap_lock_iter = 1)
 599
 600 /**
 601  * adjust_signal_pc:
 602  * @pc: raw pc from the host signal ucontext_t.
 603  * @is_write: host memory operation was write, or read-modify-write.
 604  *
 605  * Alter @pc as required for unwinding.  Return the type of the
 606  * guest memory access -- host reads may be for guest execution.
 607  */
 608 MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write);
 609
 610 /**
 611  * handle_sigsegv_accerr_write:
 612  * @cpu: the cpu context
 613  * @old_set: the sigset_t from the signal ucontext_t
 614  * @host_pc: the host pc, adjusted for the signal
 615  * @host_addr: the host address of the fault
 616  *
 617  * Return true if the write fault has been handled, and should be re-tried.
 618  */
 619 bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set,
 620                                  uintptr_t host_pc, abi_ptr guest_addr);
 621
 622 /**
 623  * cpu_loop_exit_sigsegv:
 624  * @cpu: the cpu context
 625  * @addr: the guest address of the fault
 626  * @access_type: access was read/write/execute
 627  * @maperr: true for invalid page, false for permission fault
 628  * @ra: host pc for unwinding
 629  *
 630  * Use the TCGCPUOps hook to record cpu state, do guest operating system
 631  * specific things to raise SIGSEGV, and jump to the main cpu loop.
 632  */
 633 G_NORETURN void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
 634                                       MMUAccessType access_type,
 635                                       bool maperr, uintptr_t ra);
 636
 637 /**
 638  * cpu_loop_exit_sigbus:
 639  * @cpu: the cpu context
 640  * @addr: the guest address of the alignment fault
 641  * @access_type: access was read/write/execute
 642  * @ra: host pc for unwinding
 643  *
 644  * Use the TCGCPUOps hook to record cpu state, do guest operating system
 645  * specific things to raise SIGBUS, and jump to the main cpu loop.
 646  */
 647 G_NORETURN void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr,
 648                                      MMUAccessType access_type,
 649                                      uintptr_t ra);
 650
 651 #else
 652 static inline void mmap_lock(void) {}
 653 static inline void mmap_unlock(void) {}
 654 #define WITH_MMAP_LOCK_GUARD()
 655
 656 void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
 657 void tlb_set_dirty(CPUState *cpu, vaddr addr);
 658
 659 MemoryRegionSection *
 660 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
 661                                   hwaddr *xlat, hwaddr *plen,
 662                                   MemTxAttrs attrs, int *prot);
 663 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
 664                                        MemoryRegionSection *section);
 665 #endif
 666
 667 #endif