hw/intc/arm_gic_kvm.c

   1 /*
   2  * ARM Generic Interrupt Controller using KVM in-kernel support
   3  *
   4  * Copyright (c) 2012 Linaro Limited
   5  * Written by Peter Maydell
   6  * Save/Restore logic added by Christoffer Dall.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation, either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "hw/sysbus.h"
  23 #include "sysemu/kvm.h"
  24 #include "kvm_arm.h"
  25 #include "gic_internal.h"
  26
  27 //#define DEBUG_GIC_KVM
  28
  29 #ifdef DEBUG_GIC_KVM
  30 static const int debug_gic_kvm = 1;
  31 #else
  32 static const int debug_gic_kvm = 0;
  33 #endif
  34
  35 #define DPRINTF(fmt, ...) do { \
  36         if (debug_gic_kvm) { \
  37             printf("arm_gic: " fmt , ## __VA_ARGS__); \
  38         } \
  39     } while (0)
  40
  41 #define TYPE_KVM_ARM_GIC "kvm-arm-gic"
  42 #define KVM_ARM_GIC(obj) \
  43      OBJECT_CHECK(GICState, (obj), TYPE_KVM_ARM_GIC)
  44 #define KVM_ARM_GIC_CLASS(klass) \
  45      OBJECT_CLASS_CHECK(KVMARMGICClass, (klass), TYPE_KVM_ARM_GIC)
  46 #define KVM_ARM_GIC_GET_CLASS(obj) \
  47      OBJECT_GET_CLASS(KVMARMGICClass, (obj), TYPE_KVM_ARM_GIC)
  48
  49 typedef struct KVMARMGICClass {
  50     ARMGICCommonClass parent_class;
  51     DeviceRealize parent_realize;
  52     void (*parent_reset)(DeviceState *dev);
  53 } KVMARMGICClass;
  54
  55 static void kvm_arm_gic_set_irq(void *opaque, int irq, int level)
  56 {
  57     /* Meaning of the 'irq' parameter:
  58      *  [0..N-1] : external interrupts
  59      *  [N..N+31] : PPI (internal) interrupts for CPU 0
  60      *  [N+32..N+63] : PPI (internal interrupts for CPU 1
  61      *  ...
  62      * Convert this to the kernel's desired encoding, which
  63      * has separate fields in the irq number for type,
  64      * CPU number and interrupt number.
  65      */
  66     GICState *s = (GICState *)opaque;
  67     int kvm_irq, irqtype, cpu;
  68
  69     if (irq < (s->num_irq - GIC_INTERNAL)) {
  70         /* External interrupt. The kernel numbers these like the GIC
  71          * hardware, with external interrupt IDs starting after the
  72          * internal ones.
  73          */
  74         irqtype = KVM_ARM_IRQ_TYPE_SPI;
  75         cpu = 0;
  76         irq += GIC_INTERNAL;
  77     } else {
  78         /* Internal interrupt: decode into (cpu, interrupt id) */
  79         irqtype = KVM_ARM_IRQ_TYPE_PPI;
  80         irq -= (s->num_irq - GIC_INTERNAL);
  81         cpu = irq / GIC_INTERNAL;
  82         irq %= GIC_INTERNAL;
  83     }
  84     kvm_irq = (irqtype << KVM_ARM_IRQ_TYPE_SHIFT)
  85         | (cpu << KVM_ARM_IRQ_VCPU_SHIFT) | irq;
  86
  87     kvm_set_irq(kvm_state, kvm_irq, !!level);
  88 }
  89
  90 static bool kvm_arm_gic_can_save_restore(GICState *s)
  91 {
  92     return s->dev_fd >= 0;
  93 }
  94
  95 static bool kvm_gic_supports_attr(GICState *s, int group, int attrnum)
  96 {
  97     struct kvm_device_attr attr = {
  98         .group = group,
  99         .attr = attrnum,
 100         .flags = 0,
 101     };
 102
 103     if (s->dev_fd == -1) {
 104         return false;
 105     }
 106
 107     return kvm_device_ioctl(s->dev_fd, KVM_HAS_DEVICE_ATTR, &attr) == 0;
 108 }
 109
 110 static void kvm_gic_access(GICState *s, int group, int offset,
 111                                    int cpu, uint32_t *val, bool write)
 112 {
 113     struct kvm_device_attr attr;
 114     int type;
 115     int err;
 116
 117     cpu = cpu & 0xff;
 118
 119     attr.flags = 0;
 120     attr.group = group;
 121     attr.attr = (((uint64_t)cpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) &
 122                  KVM_DEV_ARM_VGIC_CPUID_MASK) |
 123                 (((uint64_t)offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) &
 124                  KVM_DEV_ARM_VGIC_OFFSET_MASK);
 125     attr.addr = (uintptr_t)val;
 126
 127     if (write) {
 128         type = KVM_SET_DEVICE_ATTR;
 129     } else {
 130         type = KVM_GET_DEVICE_ATTR;
 131     }
 132
 133     err = kvm_device_ioctl(s->dev_fd, type, &attr);
 134     if (err < 0) {
 135         fprintf(stderr, "KVM_{SET/GET}_DEVICE_ATTR failed: %s\n",
 136                 strerror(-err));
 137         abort();
 138     }
 139 }
 140
 141 static void kvm_gicd_access(GICState *s, int offset, int cpu,
 142                             uint32_t *val, bool write)
 143 {
 144     kvm_gic_access(s, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
 145                    offset, cpu, val, write);
 146 }
 147
 148 static void kvm_gicc_access(GICState *s, int offset, int cpu,
 149                             uint32_t *val, bool write)
 150 {
 151     kvm_gic_access(s, KVM_DEV_ARM_VGIC_GRP_CPU_REGS,
 152                    offset, cpu, val, write);
 153 }
 154
 155 #define for_each_irq_reg(_ctr, _max_irq, _field_width) \
 156     for (_ctr = 0; _ctr < ((_max_irq) / (32 / (_field_width))); _ctr++)
 157
 158 /*
 159  * Translate from the in-kernel field for an IRQ value to/from the qemu
 160  * representation.
 161  */
 162 typedef void (*vgic_translate_fn)(GICState *s, int irq, int cpu,
 163                                   uint32_t *field, bool to_kernel);
 164
 165 /* synthetic translate function used for clear/set registers to completely
 166  * clear a setting using a clear-register before setting the remaining bits
 167  * using a set-register */
 168 static void translate_clear(GICState *s, int irq, int cpu,
 169                             uint32_t *field, bool to_kernel)
 170 {
 171     if (to_kernel) {
 172         *field = ~0;
 173     } else {
 174         /* does not make sense: qemu model doesn't use set/clear regs */
 175         abort();
 176     }
 177 }
 178
 179 static void translate_enabled(GICState *s, int irq, int cpu,
 180                               uint32_t *field, bool to_kernel)
 181 {
 182     int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
 183
 184     if (to_kernel) {
 185         *field = GIC_TEST_ENABLED(irq, cm);
 186     } else {
 187         if (*field & 1) {
 188             GIC_SET_ENABLED(irq, cm);
 189         }
 190     }
 191 }
 192
 193 static void translate_pending(GICState *s, int irq, int cpu,
 194                               uint32_t *field, bool to_kernel)
 195 {
 196     int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
 197
 198     if (to_kernel) {
 199         *field = gic_test_pending(s, irq, cm);
 200     } else {
 201         if (*field & 1) {
 202             GIC_SET_PENDING(irq, cm);
 203             /* TODO: Capture is level-line is held high in the kernel */
 204         }
 205     }
 206 }
 207
 208 static void translate_active(GICState *s, int irq, int cpu,
 209                              uint32_t *field, bool to_kernel)
 210 {
 211     int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
 212
 213     if (to_kernel) {
 214         *field = GIC_TEST_ACTIVE(irq, cm);
 215     } else {
 216         if (*field & 1) {
 217             GIC_SET_ACTIVE(irq, cm);
 218         }
 219     }
 220 }
 221
 222 static void translate_trigger(GICState *s, int irq, int cpu,
 223                               uint32_t *field, bool to_kernel)
 224 {
 225     if (to_kernel) {
 226         *field = (GIC_TEST_EDGE_TRIGGER(irq)) ? 0x2 : 0x0;
 227     } else {
 228         if (*field & 0x2) {
 229             GIC_SET_EDGE_TRIGGER(irq);
 230         }
 231     }
 232 }
 233
 234 static void translate_priority(GICState *s, int irq, int cpu,
 235                                uint32_t *field, bool to_kernel)
 236 {
 237     if (to_kernel) {
 238         *field = GIC_GET_PRIORITY(irq, cpu) & 0xff;
 239     } else {
 240         gic_set_priority(s, cpu, irq, *field & 0xff);
 241     }
 242 }
 243
 244 static void translate_targets(GICState *s, int irq, int cpu,
 245                               uint32_t *field, bool to_kernel)
 246 {
 247     if (to_kernel) {
 248         *field = s->irq_target[irq] & 0xff;
 249     } else {
 250         s->irq_target[irq] = *field & 0xff;
 251     }
 252 }
 253
 254 static void translate_sgisource(GICState *s, int irq, int cpu,
 255                                 uint32_t *field, bool to_kernel)
 256 {
 257     if (to_kernel) {
 258         *field = s->sgi_pending[irq][cpu] & 0xff;
 259     } else {
 260         s->sgi_pending[irq][cpu] = *field & 0xff;
 261     }
 262 }
 263
 264 /* Read a register group from the kernel VGIC */
 265 static void kvm_dist_get(GICState *s, uint32_t offset, int width,
 266                          int maxirq, vgic_translate_fn translate_fn)
 267 {
 268     uint32_t reg;
 269     int i;
 270     int j;
 271     int irq;
 272     int cpu;
 273     int regsz = 32 / width; /* irqs per kernel register */
 274     uint32_t field;
 275
 276     for_each_irq_reg(i, maxirq, width) {
 277         irq = i * regsz;
 278         cpu = 0;
 279         while ((cpu < s->num_cpu && irq < GIC_INTERNAL) || cpu == 0) {
 280             kvm_gicd_access(s, offset, cpu, &reg, false);
 281             for (j = 0; j < regsz; j++) {
 282                 field = extract32(reg, j * width, width);
 283                 translate_fn(s, irq + j, cpu, &field, false);
 284             }
 285
 286             cpu++;
 287         }
 288         offset += 4;
 289     }
 290 }
 291
 292 /* Write a register group to the kernel VGIC */
 293 static void kvm_dist_put(GICState *s, uint32_t offset, int width,
 294                          int maxirq, vgic_translate_fn translate_fn)
 295 {
 296     uint32_t reg;
 297     int i;
 298     int j;
 299     int irq;
 300     int cpu;
 301     int regsz = 32 / width; /* irqs per kernel register */
 302     uint32_t field;
 303
 304     for_each_irq_reg(i, maxirq, width) {
 305         irq = i * regsz;
 306         cpu = 0;
 307         while ((cpu < s->num_cpu && irq < GIC_INTERNAL) || cpu == 0) {
 308             reg = 0;
 309             for (j = 0; j < regsz; j++) {
 310                 translate_fn(s, irq + j, cpu, &field, true);
 311                 reg = deposit32(reg, j * width, width, field);
 312             }
 313             kvm_gicd_access(s, offset, cpu, &reg, true);
 314
 315             cpu++;
 316         }
 317         offset += 4;
 318     }
 319 }
 320
 321 static void kvm_arm_gic_put(GICState *s)
 322 {
 323     uint32_t reg;
 324     int i;
 325     int cpu;
 326     int num_cpu;
 327     int num_irq;
 328
 329     if (!kvm_arm_gic_can_save_restore(s)) {
 330             DPRINTF("Cannot put kernel gic state, no kernel interface");
 331             return;
 332     }
 333
 334     /* Note: We do the restore in a slightly different order than the save
 335      * (where the order doesn't matter and is simply ordered according to the
 336      * register offset values */
 337
 338     /*****************************************************************
 339      * Distributor State
 340      */
 341
 342     /* s->enabled -> GICD_CTLR */
 343     reg = s->enabled;
 344     kvm_gicd_access(s, 0x0, 0, &reg, true);
 345
 346     /* Sanity checking on GICD_TYPER and s->num_irq, s->num_cpu */
 347     kvm_gicd_access(s, 0x4, 0, &reg, false);
 348     num_irq = ((reg & 0x1f) + 1) * 32;
 349     num_cpu = ((reg & 0xe0) >> 5) + 1;
 350
 351     if (num_irq < s->num_irq) {
 352             fprintf(stderr, "Restoring %u IRQs, but kernel supports max %d\n",
 353                     s->num_irq, num_irq);
 354             abort();
 355     } else if (num_cpu != s->num_cpu) {
 356             fprintf(stderr, "Restoring %u CPU interfaces, kernel only has %d\n",
 357                     s->num_cpu, num_cpu);
 358             /* Did we not create the VCPUs in the kernel yet? */
 359             abort();
 360     }
 361
 362     /* TODO: Consider checking compatibility with the IIDR ? */
 363
 364     /* irq_state[n].enabled -> GICD_ISENABLERn */
 365     kvm_dist_put(s, 0x180, 1, s->num_irq, translate_clear);
 366     kvm_dist_put(s, 0x100, 1, s->num_irq, translate_enabled);
 367
 368     /* s->irq_target[irq] -> GICD_ITARGETSRn
 369      * (restore targets before pending to ensure the pending state is set on
 370      * the appropriate CPU interfaces in the kernel) */
 371     kvm_dist_put(s, 0x800, 8, s->num_irq, translate_targets);
 372
 373     /* irq_state[n].pending + irq_state[n].level -> GICD_ISPENDRn */
 374     kvm_dist_put(s, 0x280, 1, s->num_irq, translate_clear);
 375     kvm_dist_put(s, 0x200, 1, s->num_irq, translate_pending);
 376
 377     /* irq_state[n].active -> GICD_ISACTIVERn */
 378     kvm_dist_put(s, 0x380, 1, s->num_irq, translate_clear);
 379     kvm_dist_put(s, 0x300, 1, s->num_irq, translate_active);
 380
 381     /* irq_state[n].trigger -> GICD_ICFRn */
 382     kvm_dist_put(s, 0xc00, 2, s->num_irq, translate_trigger);
 383
 384     /* s->priorityX[irq] -> ICD_IPRIORITYRn */
 385     kvm_dist_put(s, 0x400, 8, s->num_irq, translate_priority);
 386
 387     /* s->sgi_pending -> ICD_CPENDSGIRn */
 388     kvm_dist_put(s, 0xf10, 8, GIC_NR_SGIS, translate_clear);
 389     kvm_dist_put(s, 0xf20, 8, GIC_NR_SGIS, translate_sgisource);
 390
 391
 392     /*****************************************************************
 393      * CPU Interface(s) State
 394      */
 395
 396     for (cpu = 0; cpu < s->num_cpu; cpu++) {
 397         /* s->cpu_enabled[cpu] -> GICC_CTLR */
 398         reg = s->cpu_enabled[cpu];
 399         kvm_gicc_access(s, 0x00, cpu, &reg, true);
 400
 401         /* s->priority_mask[cpu] -> GICC_PMR */
 402         reg = (s->priority_mask[cpu] & 0xff);
 403         kvm_gicc_access(s, 0x04, cpu, &reg, true);
 404
 405         /* s->bpr[cpu] -> GICC_BPR */
 406         reg = (s->bpr[cpu] & 0x7);
 407         kvm_gicc_access(s, 0x08, cpu, &reg, true);
 408
 409         /* s->abpr[cpu] -> GICC_ABPR */
 410         reg = (s->abpr[cpu] & 0x7);
 411         kvm_gicc_access(s, 0x1c, cpu, &reg, true);
 412
 413         /* s->apr[n][cpu] -> GICC_APRn */
 414         for (i = 0; i < 4; i++) {
 415             reg = s->apr[i][cpu];
 416             kvm_gicc_access(s, 0xd0 + i * 4, cpu, &reg, true);
 417         }
 418     }
 419 }
 420
 421 static void kvm_arm_gic_get(GICState *s)
 422 {
 423     uint32_t reg;
 424     int i;
 425     int cpu;
 426
 427     if (!kvm_arm_gic_can_save_restore(s)) {
 428             DPRINTF("Cannot get kernel gic state, no kernel interface");
 429             return;
 430     }
 431
 432     /*****************************************************************
 433      * Distributor State
 434      */
 435
 436     /* GICD_CTLR -> s->enabled */
 437     kvm_gicd_access(s, 0x0, 0, &reg, false);
 438     s->enabled = reg & 1;
 439
 440     /* Sanity checking on GICD_TYPER -> s->num_irq, s->num_cpu */
 441     kvm_gicd_access(s, 0x4, 0, &reg, false);
 442     s->num_irq = ((reg & 0x1f) + 1) * 32;
 443     s->num_cpu = ((reg & 0xe0) >> 5) + 1;
 444
 445     if (s->num_irq > GIC_MAXIRQ) {
 446             fprintf(stderr, "Too many IRQs reported from the kernel: %d\n",
 447                     s->num_irq);
 448             abort();
 449     }
 450
 451     /* GICD_IIDR -> ? */
 452     kvm_gicd_access(s, 0x8, 0, &reg, false);
 453
 454     /* Verify no GROUP 1 interrupts configured in the kernel */
 455     for_each_irq_reg(i, s->num_irq, 1) {
 456         kvm_gicd_access(s, 0x80 + (i * 4), 0, &reg, false);
 457         if (reg != 0) {
 458             fprintf(stderr, "Unsupported GICD_IGROUPRn value: %08x\n",
 459                     reg);
 460             abort();
 461         }
 462     }
 463
 464     /* Clear all the IRQ settings */
 465     for (i = 0; i < s->num_irq; i++) {
 466         memset(&s->irq_state[i], 0, sizeof(s->irq_state[0]));
 467     }
 468
 469     /* GICD_ISENABLERn -> irq_state[n].enabled */
 470     kvm_dist_get(s, 0x100, 1, s->num_irq, translate_enabled);
 471
 472     /* GICD_ISPENDRn -> irq_state[n].pending + irq_state[n].level */
 473     kvm_dist_get(s, 0x200, 1, s->num_irq, translate_pending);
 474
 475     /* GICD_ISACTIVERn -> irq_state[n].active */
 476     kvm_dist_get(s, 0x300, 1, s->num_irq, translate_active);
 477
 478     /* GICD_ICFRn -> irq_state[n].trigger */
 479     kvm_dist_get(s, 0xc00, 2, s->num_irq, translate_trigger);
 480
 481     /* GICD_IPRIORITYRn -> s->priorityX[irq] */
 482     kvm_dist_get(s, 0x400, 8, s->num_irq, translate_priority);
 483
 484     /* GICD_ITARGETSRn -> s->irq_target[irq] */
 485     kvm_dist_get(s, 0x800, 8, s->num_irq, translate_targets);
 486
 487     /* GICD_CPENDSGIRn -> s->sgi_pending */
 488     kvm_dist_get(s, 0xf10, 8, GIC_NR_SGIS, translate_sgisource);
 489
 490
 491     /*****************************************************************
 492      * CPU Interface(s) State
 493      */
 494
 495     for (cpu = 0; cpu < s->num_cpu; cpu++) {
 496         /* GICC_CTLR -> s->cpu_enabled[cpu] */
 497         kvm_gicc_access(s, 0x00, cpu, &reg, false);
 498         s->cpu_enabled[cpu] = (reg & 1);
 499
 500         /* GICC_PMR -> s->priority_mask[cpu] */
 501         kvm_gicc_access(s, 0x04, cpu, &reg, false);
 502         s->priority_mask[cpu] = (reg & 0xff);
 503
 504         /* GICC_BPR -> s->bpr[cpu] */
 505         kvm_gicc_access(s, 0x08, cpu, &reg, false);
 506         s->bpr[cpu] = (reg & 0x7);
 507
 508         /* GICC_ABPR -> s->abpr[cpu] */
 509         kvm_gicc_access(s, 0x1c, cpu, &reg, false);
 510         s->abpr[cpu] = (reg & 0x7);
 511
 512         /* GICC_APRn -> s->apr[n][cpu] */
 513         for (i = 0; i < 4; i++) {
 514             kvm_gicc_access(s, 0xd0 + i * 4, cpu, &reg, false);
 515             s->apr[i][cpu] = reg;
 516         }
 517     }
 518 }
 519
 520 static void kvm_arm_gic_reset(DeviceState *dev)
 521 {
 522     GICState *s = ARM_GIC_COMMON(dev);
 523     KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
 524
 525     kgc->parent_reset(dev);
 526     kvm_arm_gic_put(s);
 527 }
 528
 529 static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
 530 {
 531     int i;
 532     GICState *s = KVM_ARM_GIC(dev);
 533     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 534     KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
 535     Error *local_err = NULL;
 536     int ret;
 537
 538     kgc->parent_realize(dev, &local_err);
 539     if (local_err) {
 540         error_propagate(errp, local_err);
 541         return;
 542     }
 543
 544     i = s->num_irq - GIC_INTERNAL;
 545     /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
 546      * GPIO array layout is thus:
 547      *  [0..N-1] SPIs
 548      *  [N..N+31] PPIs for CPU 0
 549      *  [N+32..N+63] PPIs for CPU 1
 550      *   ...
 551      */
 552     i += (GIC_INTERNAL * s->num_cpu);
 553     qdev_init_gpio_in(dev, kvm_arm_gic_set_irq, i);
 554     /* We never use our outbound IRQ lines but provide them so that
 555      * we maintain the same interface as the non-KVM GIC.
 556      */
 557     for (i = 0; i < s->num_cpu; i++) {
 558         sysbus_init_irq(sbd, &s->parent_irq[i]);
 559     }
 560
 561     /* Try to create the device via the device control API */
 562     s->dev_fd = -1;
 563     ret = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V2, false);
 564     if (ret >= 0) {
 565         s->dev_fd = ret;
 566     } else if (ret != -ENODEV && ret != -ENOTSUP) {
 567         error_setg_errno(errp, -ret, "error creating in-kernel VGIC");
 568         return;
 569     }
 570
 571     if (kvm_gic_supports_attr(s, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0)) {
 572         uint32_t numirqs = s->num_irq;
 573         kvm_gic_access(s, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0, 0, &numirqs, 1);
 574     }
 575
 576     /* Distributor */
 577     memory_region_init_reservation(&s->iomem, OBJECT(s),
 578                                    "kvm-gic_dist", 0x1000);
 579     sysbus_init_mmio(sbd, &s->iomem);
 580     kvm_arm_register_device(&s->iomem,
 581                             (KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT)
 582                             | KVM_VGIC_V2_ADDR_TYPE_DIST,
 583                             KVM_DEV_ARM_VGIC_GRP_ADDR,
 584                             KVM_VGIC_V2_ADDR_TYPE_DIST,
 585                             s->dev_fd);
 586     /* CPU interface for current core. Unlike arm_gic, we don't
 587      * provide the "interface for core #N" memory regions, because
 588      * cores with a VGIC don't have those.
 589      */
 590     memory_region_init_reservation(&s->cpuiomem[0], OBJECT(s),
 591                                    "kvm-gic_cpu", 0x1000);
 592     sysbus_init_mmio(sbd, &s->cpuiomem[0]);
 593     kvm_arm_register_device(&s->cpuiomem[0],
 594                             (KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT)
 595                             | KVM_VGIC_V2_ADDR_TYPE_CPU,
 596                             KVM_DEV_ARM_VGIC_GRP_ADDR,
 597                             KVM_VGIC_V2_ADDR_TYPE_CPU,
 598                             s->dev_fd);
 599 }
 600
 601 static void kvm_arm_gic_class_init(ObjectClass *klass, void *data)
 602 {
 603     DeviceClass *dc = DEVICE_CLASS(klass);
 604     ARMGICCommonClass *agcc = ARM_GIC_COMMON_CLASS(klass);
 605     KVMARMGICClass *kgc = KVM_ARM_GIC_CLASS(klass);
 606
 607     agcc->pre_save = kvm_arm_gic_get;
 608     agcc->post_load = kvm_arm_gic_put;
 609     kgc->parent_realize = dc->realize;
 610     kgc->parent_reset = dc->reset;
 611     dc->realize = kvm_arm_gic_realize;
 612     dc->reset = kvm_arm_gic_reset;
 613 }
 614
 615 static const TypeInfo kvm_arm_gic_info = {
 616     .name = TYPE_KVM_ARM_GIC,
 617     .parent = TYPE_ARM_GIC_COMMON,
 618     .instance_size = sizeof(GICState),
 619     .class_init = kvm_arm_gic_class_init,
 620     .class_size = sizeof(KVMARMGICClass),
 621 };
 622
 623 static void kvm_arm_gic_register_types(void)
 624 {
 625     type_register_static(&kvm_arm_gic_info);
 626 }
 627
 628 type_init(kvm_arm_gic_register_types)