hw/arm/stellaris.c

   1 /*
   2  * Luminary Micro Stellaris peripherals
   3  *
   4  * Copyright (c) 2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "qapi/error.h"
  12 #include "hw/sysbus.h"
  13 #include "hw/ssi/ssi.h"
  14 #include "hw/arm/boot.h"
  15 #include "qemu/timer.h"
  16 #include "hw/i2c/i2c.h"
  17 #include "net/net.h"
  18 #include "hw/boards.h"
  19 #include "qemu/log.h"
  20 #include "exec/address-spaces.h"
  21 #include "sysemu/sysemu.h"
  22 #include "hw/arm/armv7m.h"
  23 #include "hw/char/pl011.h"
  24 #include "hw/input/gamepad.h"
  25 #include "hw/irq.h"
  26 #include "hw/watchdog/cmsdk-apb-watchdog.h"
  27 #include "migration/vmstate.h"
  28 #include "hw/misc/unimp.h"
  29 #include "cpu.h"
  30 #include "qom/object.h"
  31
  32 #define GPIO_A 0
  33 #define GPIO_B 1
  34 #define GPIO_C 2
  35 #define GPIO_D 3
  36 #define GPIO_E 4
  37 #define GPIO_F 5
  38 #define GPIO_G 6
  39
  40 #define BP_OLED_I2C  0x01
  41 #define BP_OLED_SSI  0x02
  42 #define BP_GAMEPAD   0x04
  43
  44 #define NUM_IRQ_LINES 64
  45
  46 typedef const struct {
  47     const char *name;
  48     uint32_t did0;
  49     uint32_t did1;
  50     uint32_t dc0;
  51     uint32_t dc1;
  52     uint32_t dc2;
  53     uint32_t dc3;
  54     uint32_t dc4;
  55     uint32_t peripherals;
  56 } stellaris_board_info;
  57
  58 /* General purpose timer module.  */
  59
  60 #define TYPE_STELLARIS_GPTM "stellaris-gptm"
  61 OBJECT_DECLARE_SIMPLE_TYPE(gptm_state, STELLARIS_GPTM)
  62
  63 struct gptm_state {
  64     SysBusDevice parent_obj;
  65
  66     MemoryRegion iomem;
  67     uint32_t config;
  68     uint32_t mode[2];
  69     uint32_t control;
  70     uint32_t state;
  71     uint32_t mask;
  72     uint32_t load[2];
  73     uint32_t match[2];
  74     uint32_t prescale[2];
  75     uint32_t match_prescale[2];
  76     uint32_t rtc;
  77     int64_t tick[2];
  78     struct gptm_state *opaque[2];
  79     QEMUTimer *timer[2];
  80     /* The timers have an alternate output used to trigger the ADC.  */
  81     qemu_irq trigger;
  82     qemu_irq irq;
  83 };
  84
  85 static void gptm_update_irq(gptm_state *s)
  86 {
  87     int level;
  88     level = (s->state & s->mask) != 0;
  89     qemu_set_irq(s->irq, level);
  90 }
  91
  92 static void gptm_stop(gptm_state *s, int n)
  93 {
  94     timer_del(s->timer[n]);
  95 }
  96
  97 static void gptm_reload(gptm_state *s, int n, int reset)
  98 {
  99     int64_t tick;
 100     if (reset)
 101         tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 102     else
 103         tick = s->tick[n];
 104
 105     if (s->config == 0) {
 106         /* 32-bit CountDown.  */
 107         uint32_t count;
 108         count = s->load[0] | (s->load[1] << 16);
 109         tick += (int64_t)count * system_clock_scale;
 110     } else if (s->config == 1) {
 111         /* 32-bit RTC.  1Hz tick.  */
 112         tick += NANOSECONDS_PER_SECOND;
 113     } else if (s->mode[n] == 0xa) {
 114         /* PWM mode.  Not implemented.  */
 115     } else {
 116         qemu_log_mask(LOG_UNIMP,
 117                       "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
 118                       s->mode[n]);
 119         return;
 120     }
 121     s->tick[n] = tick;
 122     timer_mod(s->timer[n], tick);
 123 }
 124
 125 static void gptm_tick(void *opaque)
 126 {
 127     gptm_state **p = (gptm_state **)opaque;
 128     gptm_state *s;
 129     int n;
 130
 131     s = *p;
 132     n = p - s->opaque;
 133     if (s->config == 0) {
 134         s->state |= 1;
 135         if ((s->control & 0x20)) {
 136             /* Output trigger.  */
 137             qemu_irq_pulse(s->trigger);
 138         }
 139         if (s->mode[0] & 1) {
 140             /* One-shot.  */
 141             s->control &= ~1;
 142         } else {
 143             /* Periodic.  */
 144             gptm_reload(s, 0, 0);
 145         }
 146     } else if (s->config == 1) {
 147         /* RTC.  */
 148         uint32_t match;
 149         s->rtc++;
 150         match = s->match[0] | (s->match[1] << 16);
 151         if (s->rtc > match)
 152             s->rtc = 0;
 153         if (s->rtc == 0) {
 154             s->state |= 8;
 155         }
 156         gptm_reload(s, 0, 0);
 157     } else if (s->mode[n] == 0xa) {
 158         /* PWM mode.  Not implemented.  */
 159     } else {
 160         qemu_log_mask(LOG_UNIMP,
 161                       "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
 162                       s->mode[n]);
 163     }
 164     gptm_update_irq(s);
 165 }
 166
 167 static uint64_t gptm_read(void *opaque, hwaddr offset,
 168                           unsigned size)
 169 {
 170     gptm_state *s = (gptm_state *)opaque;
 171
 172     switch (offset) {
 173     case 0x00: /* CFG */
 174         return s->config;
 175     case 0x04: /* TAMR */
 176         return s->mode[0];
 177     case 0x08: /* TBMR */
 178         return s->mode[1];
 179     case 0x0c: /* CTL */
 180         return s->control;
 181     case 0x18: /* IMR */
 182         return s->mask;
 183     case 0x1c: /* RIS */
 184         return s->state;
 185     case 0x20: /* MIS */
 186         return s->state & s->mask;
 187     case 0x24: /* CR */
 188         return 0;
 189     case 0x28: /* TAILR */
 190         return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0);
 191     case 0x2c: /* TBILR */
 192         return s->load[1];
 193     case 0x30: /* TAMARCHR */
 194         return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0);
 195     case 0x34: /* TBMATCHR */
 196         return s->match[1];
 197     case 0x38: /* TAPR */
 198         return s->prescale[0];
 199     case 0x3c: /* TBPR */
 200         return s->prescale[1];
 201     case 0x40: /* TAPMR */
 202         return s->match_prescale[0];
 203     case 0x44: /* TBPMR */
 204         return s->match_prescale[1];
 205     case 0x48: /* TAR */
 206         if (s->config == 1) {
 207             return s->rtc;
 208         }
 209         qemu_log_mask(LOG_UNIMP,
 210                       "GPTM: read of TAR but timer read not supported\n");
 211         return 0;
 212     case 0x4c: /* TBR */
 213         qemu_log_mask(LOG_UNIMP,
 214                       "GPTM: read of TBR but timer read not supported\n");
 215         return 0;
 216     default:
 217         qemu_log_mask(LOG_GUEST_ERROR,
 218                       "GPTM: read at bad offset 0x02%" HWADDR_PRIx "\n",
 219                       offset);
 220         return 0;
 221     }
 222 }
 223
 224 static void gptm_write(void *opaque, hwaddr offset,
 225                        uint64_t value, unsigned size)
 226 {
 227     gptm_state *s = (gptm_state *)opaque;
 228     uint32_t oldval;
 229
 230     /* The timers should be disabled before changing the configuration.
 231        We take advantage of this and defer everything until the timer
 232        is enabled.  */
 233     switch (offset) {
 234     case 0x00: /* CFG */
 235         s->config = value;
 236         break;
 237     case 0x04: /* TAMR */
 238         s->mode[0] = value;
 239         break;
 240     case 0x08: /* TBMR */
 241         s->mode[1] = value;
 242         break;
 243     case 0x0c: /* CTL */
 244         oldval = s->control;
 245         s->control = value;
 246         /* TODO: Implement pause.  */
 247         if ((oldval ^ value) & 1) {
 248             if (value & 1) {
 249                 gptm_reload(s, 0, 1);
 250             } else {
 251                 gptm_stop(s, 0);
 252             }
 253         }
 254         if (((oldval ^ value) & 0x100) && s->config >= 4) {
 255             if (value & 0x100) {
 256                 gptm_reload(s, 1, 1);
 257             } else {
 258                 gptm_stop(s, 1);
 259             }
 260         }
 261         break;
 262     case 0x18: /* IMR */
 263         s->mask = value & 0x77;
 264         gptm_update_irq(s);
 265         break;
 266     case 0x24: /* CR */
 267         s->state &= ~value;
 268         break;
 269     case 0x28: /* TAILR */
 270         s->load[0] = value & 0xffff;
 271         if (s->config < 4) {
 272             s->load[1] = value >> 16;
 273         }
 274         break;
 275     case 0x2c: /* TBILR */
 276         s->load[1] = value & 0xffff;
 277         break;
 278     case 0x30: /* TAMARCHR */
 279         s->match[0] = value & 0xffff;
 280         if (s->config < 4) {
 281             s->match[1] = value >> 16;
 282         }
 283         break;
 284     case 0x34: /* TBMATCHR */
 285         s->match[1] = value >> 16;
 286         break;
 287     case 0x38: /* TAPR */
 288         s->prescale[0] = value;
 289         break;
 290     case 0x3c: /* TBPR */
 291         s->prescale[1] = value;
 292         break;
 293     case 0x40: /* TAPMR */
 294         s->match_prescale[0] = value;
 295         break;
 296     case 0x44: /* TBPMR */
 297         s->match_prescale[0] = value;
 298         break;
 299     default:
 300         qemu_log_mask(LOG_GUEST_ERROR,
 301                       "GPTM: write at bad offset 0x02%" HWADDR_PRIx "\n",
 302                       offset);
 303     }
 304     gptm_update_irq(s);
 305 }
 306
 307 static const MemoryRegionOps gptm_ops = {
 308     .read = gptm_read,
 309     .write = gptm_write,
 310     .endianness = DEVICE_NATIVE_ENDIAN,
 311 };
 312
 313 static const VMStateDescription vmstate_stellaris_gptm = {
 314     .name = "stellaris_gptm",
 315     .version_id = 1,
 316     .minimum_version_id = 1,
 317     .fields = (VMStateField[]) {
 318         VMSTATE_UINT32(config, gptm_state),
 319         VMSTATE_UINT32_ARRAY(mode, gptm_state, 2),
 320         VMSTATE_UINT32(control, gptm_state),
 321         VMSTATE_UINT32(state, gptm_state),
 322         VMSTATE_UINT32(mask, gptm_state),
 323         VMSTATE_UNUSED(8),
 324         VMSTATE_UINT32_ARRAY(load, gptm_state, 2),
 325         VMSTATE_UINT32_ARRAY(match, gptm_state, 2),
 326         VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2),
 327         VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2),
 328         VMSTATE_UINT32(rtc, gptm_state),
 329         VMSTATE_INT64_ARRAY(tick, gptm_state, 2),
 330         VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2),
 331         VMSTATE_END_OF_LIST()
 332     }
 333 };
 334
 335 static void stellaris_gptm_init(Object *obj)
 336 {
 337     DeviceState *dev = DEVICE(obj);
 338     gptm_state *s = STELLARIS_GPTM(obj);
 339     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 340
 341     sysbus_init_irq(sbd, &s->irq);
 342     qdev_init_gpio_out(dev, &s->trigger, 1);
 343
 344     memory_region_init_io(&s->iomem, obj, &gptm_ops, s,
 345                           "gptm", 0x1000);
 346     sysbus_init_mmio(sbd, &s->iomem);
 347
 348     s->opaque[0] = s->opaque[1] = s;
 349 }
 350
 351 static void stellaris_gptm_realize(DeviceState *dev, Error **errp)
 352 {
 353     gptm_state *s = STELLARIS_GPTM(dev);
 354     s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]);
 355     s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]);
 356 }
 357
 358 /* System controller.  */
 359
 360 #define TYPE_STELLARIS_SYS "stellaris-sys"
 361 OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS)
 362
 363 struct ssys_state {
 364     SysBusDevice parent_obj;
 365
 366     MemoryRegion iomem;
 367     uint32_t pborctl;
 368     uint32_t ldopctl;
 369     uint32_t int_status;
 370     uint32_t int_mask;
 371     uint32_t resc;
 372     uint32_t rcc;
 373     uint32_t rcc2;
 374     uint32_t rcgc[3];
 375     uint32_t scgc[3];
 376     uint32_t dcgc[3];
 377     uint32_t clkvclr;
 378     uint32_t ldoarst;
 379     qemu_irq irq;
 380     /* Properties (all read-only registers) */
 381     uint32_t user0;
 382     uint32_t user1;
 383     uint32_t did0;
 384     uint32_t did1;
 385     uint32_t dc0;
 386     uint32_t dc1;
 387     uint32_t dc2;
 388     uint32_t dc3;
 389     uint32_t dc4;
 390 };
 391
 392 static void ssys_update(ssys_state *s)
 393 {
 394   qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
 395 }
 396
 397 static uint32_t pllcfg_sandstorm[16] = {
 398     0x31c0, /* 1 Mhz */
 399     0x1ae0, /* 1.8432 Mhz */
 400     0x18c0, /* 2 Mhz */
 401     0xd573, /* 2.4576 Mhz */
 402     0x37a6, /* 3.57954 Mhz */
 403     0x1ae2, /* 3.6864 Mhz */
 404     0x0c40, /* 4 Mhz */
 405     0x98bc, /* 4.906 Mhz */
 406     0x935b, /* 4.9152 Mhz */
 407     0x09c0, /* 5 Mhz */
 408     0x4dee, /* 5.12 Mhz */
 409     0x0c41, /* 6 Mhz */
 410     0x75db, /* 6.144 Mhz */
 411     0x1ae6, /* 7.3728 Mhz */
 412     0x0600, /* 8 Mhz */
 413     0x585b /* 8.192 Mhz */
 414 };
 415
 416 static uint32_t pllcfg_fury[16] = {
 417     0x3200, /* 1 Mhz */
 418     0x1b20, /* 1.8432 Mhz */
 419     0x1900, /* 2 Mhz */
 420     0xf42b, /* 2.4576 Mhz */
 421     0x37e3, /* 3.57954 Mhz */
 422     0x1b21, /* 3.6864 Mhz */
 423     0x0c80, /* 4 Mhz */
 424     0x98ee, /* 4.906 Mhz */
 425     0xd5b4, /* 4.9152 Mhz */
 426     0x0a00, /* 5 Mhz */
 427     0x4e27, /* 5.12 Mhz */
 428     0x1902, /* 6 Mhz */
 429     0xec1c, /* 6.144 Mhz */
 430     0x1b23, /* 7.3728 Mhz */
 431     0x0640, /* 8 Mhz */
 432     0xb11c /* 8.192 Mhz */
 433 };
 434
 435 #define DID0_VER_MASK        0x70000000
 436 #define DID0_VER_0           0x00000000
 437 #define DID0_VER_1           0x10000000
 438
 439 #define DID0_CLASS_MASK      0x00FF0000
 440 #define DID0_CLASS_SANDSTORM 0x00000000
 441 #define DID0_CLASS_FURY      0x00010000
 442
 443 static int ssys_board_class(const ssys_state *s)
 444 {
 445     uint32_t did0 = s->did0;
 446     switch (did0 & DID0_VER_MASK) {
 447     case DID0_VER_0:
 448         return DID0_CLASS_SANDSTORM;
 449     case DID0_VER_1:
 450         switch (did0 & DID0_CLASS_MASK) {
 451         case DID0_CLASS_SANDSTORM:
 452         case DID0_CLASS_FURY:
 453             return did0 & DID0_CLASS_MASK;
 454         }
 455         /* for unknown classes, fall through */
 456     default:
 457         /* This can only happen if the hardwired constant did0 value
 458          * in this board's stellaris_board_info struct is wrong.
 459          */
 460         g_assert_not_reached();
 461     }
 462 }
 463
 464 static uint64_t ssys_read(void *opaque, hwaddr offset,
 465                           unsigned size)
 466 {
 467     ssys_state *s = (ssys_state *)opaque;
 468
 469     switch (offset) {
 470     case 0x000: /* DID0 */
 471         return s->did0;
 472     case 0x004: /* DID1 */
 473         return s->did1;
 474     case 0x008: /* DC0 */
 475         return s->dc0;
 476     case 0x010: /* DC1 */
 477         return s->dc1;
 478     case 0x014: /* DC2 */
 479         return s->dc2;
 480     case 0x018: /* DC3 */
 481         return s->dc3;
 482     case 0x01c: /* DC4 */
 483         return s->dc4;
 484     case 0x030: /* PBORCTL */
 485         return s->pborctl;
 486     case 0x034: /* LDOPCTL */
 487         return s->ldopctl;
 488     case 0x040: /* SRCR0 */
 489         return 0;
 490     case 0x044: /* SRCR1 */
 491         return 0;
 492     case 0x048: /* SRCR2 */
 493         return 0;
 494     case 0x050: /* RIS */
 495         return s->int_status;
 496     case 0x054: /* IMC */
 497         return s->int_mask;
 498     case 0x058: /* MISC */
 499         return s->int_status & s->int_mask;
 500     case 0x05c: /* RESC */
 501         return s->resc;
 502     case 0x060: /* RCC */
 503         return s->rcc;
 504     case 0x064: /* PLLCFG */
 505         {
 506             int xtal;
 507             xtal = (s->rcc >> 6) & 0xf;
 508             switch (ssys_board_class(s)) {
 509             case DID0_CLASS_FURY:
 510                 return pllcfg_fury[xtal];
 511             case DID0_CLASS_SANDSTORM:
 512                 return pllcfg_sandstorm[xtal];
 513             default:
 514                 g_assert_not_reached();
 515             }
 516         }
 517     case 0x070: /* RCC2 */
 518         return s->rcc2;
 519     case 0x100: /* RCGC0 */
 520         return s->rcgc[0];
 521     case 0x104: /* RCGC1 */
 522         return s->rcgc[1];
 523     case 0x108: /* RCGC2 */
 524         return s->rcgc[2];
 525     case 0x110: /* SCGC0 */
 526         return s->scgc[0];
 527     case 0x114: /* SCGC1 */
 528         return s->scgc[1];
 529     case 0x118: /* SCGC2 */
 530         return s->scgc[2];
 531     case 0x120: /* DCGC0 */
 532         return s->dcgc[0];
 533     case 0x124: /* DCGC1 */
 534         return s->dcgc[1];
 535     case 0x128: /* DCGC2 */
 536         return s->dcgc[2];
 537     case 0x150: /* CLKVCLR */
 538         return s->clkvclr;
 539     case 0x160: /* LDOARST */
 540         return s->ldoarst;
 541     case 0x1e0: /* USER0 */
 542         return s->user0;
 543     case 0x1e4: /* USER1 */
 544         return s->user1;
 545     default:
 546         qemu_log_mask(LOG_GUEST_ERROR,
 547                       "SSYS: read at bad offset 0x%x\n", (int)offset);
 548         return 0;
 549     }
 550 }
 551
 552 static bool ssys_use_rcc2(ssys_state *s)
 553 {
 554     return (s->rcc2 >> 31) & 0x1;
 555 }
 556
 557 /*
 558  * Caculate the sys. clock period in ms.
 559  */
 560 static void ssys_calculate_system_clock(ssys_state *s)
 561 {
 562     if (ssys_use_rcc2(s)) {
 563         system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
 564     } else {
 565         system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
 566     }
 567 }
 568
 569 static void ssys_write(void *opaque, hwaddr offset,
 570                        uint64_t value, unsigned size)
 571 {
 572     ssys_state *s = (ssys_state *)opaque;
 573
 574     switch (offset) {
 575     case 0x030: /* PBORCTL */
 576         s->pborctl = value & 0xffff;
 577         break;
 578     case 0x034: /* LDOPCTL */
 579         s->ldopctl = value & 0x1f;
 580         break;
 581     case 0x040: /* SRCR0 */
 582     case 0x044: /* SRCR1 */
 583     case 0x048: /* SRCR2 */
 584         qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n");
 585         break;
 586     case 0x054: /* IMC */
 587         s->int_mask = value & 0x7f;
 588         break;
 589     case 0x058: /* MISC */
 590         s->int_status &= ~value;
 591         break;
 592     case 0x05c: /* RESC */
 593         s->resc = value & 0x3f;
 594         break;
 595     case 0x060: /* RCC */
 596         if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
 597             /* PLL enable.  */
 598             s->int_status |= (1 << 6);
 599         }
 600         s->rcc = value;
 601         ssys_calculate_system_clock(s);
 602         break;
 603     case 0x070: /* RCC2 */
 604         if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
 605             break;
 606         }
 607
 608         if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
 609             /* PLL enable.  */
 610             s->int_status |= (1 << 6);
 611         }
 612         s->rcc2 = value;
 613         ssys_calculate_system_clock(s);
 614         break;
 615     case 0x100: /* RCGC0 */
 616         s->rcgc[0] = value;
 617         break;
 618     case 0x104: /* RCGC1 */
 619         s->rcgc[1] = value;
 620         break;
 621     case 0x108: /* RCGC2 */
 622         s->rcgc[2] = value;
 623         break;
 624     case 0x110: /* SCGC0 */
 625         s->scgc[0] = value;
 626         break;
 627     case 0x114: /* SCGC1 */
 628         s->scgc[1] = value;
 629         break;
 630     case 0x118: /* SCGC2 */
 631         s->scgc[2] = value;
 632         break;
 633     case 0x120: /* DCGC0 */
 634         s->dcgc[0] = value;
 635         break;
 636     case 0x124: /* DCGC1 */
 637         s->dcgc[1] = value;
 638         break;
 639     case 0x128: /* DCGC2 */
 640         s->dcgc[2] = value;
 641         break;
 642     case 0x150: /* CLKVCLR */
 643         s->clkvclr = value;
 644         break;
 645     case 0x160: /* LDOARST */
 646         s->ldoarst = value;
 647         break;
 648     default:
 649         qemu_log_mask(LOG_GUEST_ERROR,
 650                       "SSYS: write at bad offset 0x%x\n", (int)offset);
 651     }
 652     ssys_update(s);
 653 }
 654
 655 static const MemoryRegionOps ssys_ops = {
 656     .read = ssys_read,
 657     .write = ssys_write,
 658     .endianness = DEVICE_NATIVE_ENDIAN,
 659 };
 660
 661 static void stellaris_sys_reset_enter(Object *obj, ResetType type)
 662 {
 663     ssys_state *s = STELLARIS_SYS(obj);
 664
 665     s->pborctl = 0x7ffd;
 666     s->rcc = 0x078e3ac0;
 667
 668     if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
 669         s->rcc2 = 0;
 670     } else {
 671         s->rcc2 = 0x07802810;
 672     }
 673     s->rcgc[0] = 1;
 674     s->scgc[0] = 1;
 675     s->dcgc[0] = 1;
 676 }
 677
 678 static void stellaris_sys_reset_hold(Object *obj)
 679 {
 680     ssys_state *s = STELLARIS_SYS(obj);
 681
 682     ssys_calculate_system_clock(s);
 683 }
 684
 685 static void stellaris_sys_reset_exit(Object *obj)
 686 {
 687 }
 688
 689 static int stellaris_sys_post_load(void *opaque, int version_id)
 690 {
 691     ssys_state *s = opaque;
 692
 693     ssys_calculate_system_clock(s);
 694
 695     return 0;
 696 }
 697
 698 static const VMStateDescription vmstate_stellaris_sys = {
 699     .name = "stellaris_sys",
 700     .version_id = 2,
 701     .minimum_version_id = 1,
 702     .post_load = stellaris_sys_post_load,
 703     .fields = (VMStateField[]) {
 704         VMSTATE_UINT32(pborctl, ssys_state),
 705         VMSTATE_UINT32(ldopctl, ssys_state),
 706         VMSTATE_UINT32(int_mask, ssys_state),
 707         VMSTATE_UINT32(int_status, ssys_state),
 708         VMSTATE_UINT32(resc, ssys_state),
 709         VMSTATE_UINT32(rcc, ssys_state),
 710         VMSTATE_UINT32_V(rcc2, ssys_state, 2),
 711         VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3),
 712         VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3),
 713         VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3),
 714         VMSTATE_UINT32(clkvclr, ssys_state),
 715         VMSTATE_UINT32(ldoarst, ssys_state),
 716         VMSTATE_END_OF_LIST()
 717     }
 718 };
 719
 720 static Property stellaris_sys_properties[] = {
 721     DEFINE_PROP_UINT32("user0", ssys_state, user0, 0),
 722     DEFINE_PROP_UINT32("user1", ssys_state, user1, 0),
 723     DEFINE_PROP_UINT32("did0", ssys_state, did0, 0),
 724     DEFINE_PROP_UINT32("did1", ssys_state, did1, 0),
 725     DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0),
 726     DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0),
 727     DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0),
 728     DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0),
 729     DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0),
 730     DEFINE_PROP_END_OF_LIST()
 731 };
 732
 733 static void stellaris_sys_instance_init(Object *obj)
 734 {
 735     ssys_state *s = STELLARIS_SYS(obj);
 736     SysBusDevice *sbd = SYS_BUS_DEVICE(s);
 737
 738     memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000);
 739     sysbus_init_mmio(sbd, &s->iomem);
 740     sysbus_init_irq(sbd, &s->irq);
 741 }
 742
 743 static int stellaris_sys_init(uint32_t base, qemu_irq irq,
 744                               stellaris_board_info * board,
 745                               uint8_t *macaddr)
 746 {
 747     DeviceState *dev = qdev_new(TYPE_STELLARIS_SYS);
 748     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 749
 750     /* Most devices come preprogrammed with a MAC address in the user data. */
 751     qdev_prop_set_uint32(dev, "user0",
 752                          macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16));
 753     qdev_prop_set_uint32(dev, "user1",
 754                          macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16));
 755     qdev_prop_set_uint32(dev, "did0", board->did0);
 756     qdev_prop_set_uint32(dev, "did1", board->did1);
 757     qdev_prop_set_uint32(dev, "dc0", board->dc0);
 758     qdev_prop_set_uint32(dev, "dc1", board->dc1);
 759     qdev_prop_set_uint32(dev, "dc2", board->dc2);
 760     qdev_prop_set_uint32(dev, "dc3", board->dc3);
 761     qdev_prop_set_uint32(dev, "dc4", board->dc4);
 762
 763     sysbus_realize_and_unref(sbd, &error_fatal);
 764     sysbus_mmio_map(sbd, 0, base);
 765     sysbus_connect_irq(sbd, 0, irq);
 766
 767     /*
 768      * Normally we should not be resetting devices like this during
 769      * board creation. For the moment we need to do so, because
 770      * system_clock_scale will only get set when the STELLARIS_SYS
 771      * device is reset, and we need its initial value to pass to
 772      * the watchdog device. This hack can be removed once the
 773      * watchdog has been converted to use a Clock input instead.
 774      */
 775     device_cold_reset(dev);
 776
 777     return 0;
 778 }
 779
 780 /* I2C controller.  */
 781
 782 #define TYPE_STELLARIS_I2C "stellaris-i2c"
 783 OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C)
 784
 785 struct stellaris_i2c_state {
 786     SysBusDevice parent_obj;
 787
 788     I2CBus *bus;
 789     qemu_irq irq;
 790     MemoryRegion iomem;
 791     uint32_t msa;
 792     uint32_t mcs;
 793     uint32_t mdr;
 794     uint32_t mtpr;
 795     uint32_t mimr;
 796     uint32_t mris;
 797     uint32_t mcr;
 798 };
 799
 800 #define STELLARIS_I2C_MCS_BUSY    0x01
 801 #define STELLARIS_I2C_MCS_ERROR   0x02
 802 #define STELLARIS_I2C_MCS_ADRACK  0x04
 803 #define STELLARIS_I2C_MCS_DATACK  0x08
 804 #define STELLARIS_I2C_MCS_ARBLST  0x10
 805 #define STELLARIS_I2C_MCS_IDLE    0x20
 806 #define STELLARIS_I2C_MCS_BUSBSY  0x40
 807
 808 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
 809                                    unsigned size)
 810 {
 811     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 812
 813     switch (offset) {
 814     case 0x00: /* MSA */
 815         return s->msa;
 816     case 0x04: /* MCS */
 817         /* We don't emulate timing, so the controller is never busy.  */
 818         return s->mcs | STELLARIS_I2C_MCS_IDLE;
 819     case 0x08: /* MDR */
 820         return s->mdr;
 821     case 0x0c: /* MTPR */
 822         return s->mtpr;
 823     case 0x10: /* MIMR */
 824         return s->mimr;
 825     case 0x14: /* MRIS */
 826         return s->mris;
 827     case 0x18: /* MMIS */
 828         return s->mris & s->mimr;
 829     case 0x20: /* MCR */
 830         return s->mcr;
 831     default:
 832         qemu_log_mask(LOG_GUEST_ERROR,
 833                       "stellaris_i2c: read at bad offset 0x%x\n", (int)offset);
 834         return 0;
 835     }
 836 }
 837
 838 static void stellaris_i2c_update(stellaris_i2c_state *s)
 839 {
 840     int level;
 841
 842     level = (s->mris & s->mimr) != 0;
 843     qemu_set_irq(s->irq, level);
 844 }
 845
 846 static void stellaris_i2c_write(void *opaque, hwaddr offset,
 847                                 uint64_t value, unsigned size)
 848 {
 849     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 850
 851     switch (offset) {
 852     case 0x00: /* MSA */
 853         s->msa = value & 0xff;
 854         break;
 855     case 0x04: /* MCS */
 856         if ((s->mcr & 0x10) == 0) {
 857             /* Disabled.  Do nothing.  */
 858             break;
 859         }
 860         /* Grab the bus if this is starting a transfer.  */
 861         if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
 862             if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) {
 863                 s->mcs |= STELLARIS_I2C_MCS_ARBLST;
 864             } else {
 865                 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST;
 866                 s->mcs |= STELLARIS_I2C_MCS_BUSBSY;
 867             }
 868         }
 869         /* If we don't have the bus then indicate an error.  */
 870         if (!i2c_bus_busy(s->bus)
 871                 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
 872             s->mcs |= STELLARIS_I2C_MCS_ERROR;
 873             break;
 874         }
 875         s->mcs &= ~STELLARIS_I2C_MCS_ERROR;
 876         if (value & 1) {
 877             /* Transfer a byte.  */
 878             /* TODO: Handle errors.  */
 879             if (s->msa & 1) {
 880                 /* Recv */
 881                 s->mdr = i2c_recv(s->bus);
 882             } else {
 883                 /* Send */
 884                 i2c_send(s->bus, s->mdr);
 885             }
 886             /* Raise an interrupt.  */
 887             s->mris |= 1;
 888         }
 889         if (value & 4) {
 890             /* Finish transfer.  */
 891             i2c_end_transfer(s->bus);
 892             s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY;
 893         }
 894         break;
 895     case 0x08: /* MDR */
 896         s->mdr = value & 0xff;
 897         break;
 898     case 0x0c: /* MTPR */
 899         s->mtpr = value & 0xff;
 900         break;
 901     case 0x10: /* MIMR */
 902         s->mimr = 1;
 903         break;
 904     case 0x1c: /* MICR */
 905         s->mris &= ~value;
 906         break;
 907     case 0x20: /* MCR */
 908         if (value & 1) {
 909             qemu_log_mask(LOG_UNIMP,
 910                           "stellaris_i2c: Loopback not implemented\n");
 911         }
 912         if (value & 0x20) {
 913             qemu_log_mask(LOG_UNIMP,
 914                           "stellaris_i2c: Slave mode not implemented\n");
 915         }
 916         s->mcr = value & 0x31;
 917         break;
 918     default:
 919         qemu_log_mask(LOG_GUEST_ERROR,
 920                       "stellaris_i2c: write at bad offset 0x%x\n", (int)offset);
 921     }
 922     stellaris_i2c_update(s);
 923 }
 924
 925 static void stellaris_i2c_reset(stellaris_i2c_state *s)
 926 {
 927     if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
 928         i2c_end_transfer(s->bus);
 929
 930     s->msa = 0;
 931     s->mcs = 0;
 932     s->mdr = 0;
 933     s->mtpr = 1;
 934     s->mimr = 0;
 935     s->mris = 0;
 936     s->mcr = 0;
 937     stellaris_i2c_update(s);
 938 }
 939
 940 static const MemoryRegionOps stellaris_i2c_ops = {
 941     .read = stellaris_i2c_read,
 942     .write = stellaris_i2c_write,
 943     .endianness = DEVICE_NATIVE_ENDIAN,
 944 };
 945
 946 static const VMStateDescription vmstate_stellaris_i2c = {
 947     .name = "stellaris_i2c",
 948     .version_id = 1,
 949     .minimum_version_id = 1,
 950     .fields = (VMStateField[]) {
 951         VMSTATE_UINT32(msa, stellaris_i2c_state),
 952         VMSTATE_UINT32(mcs, stellaris_i2c_state),
 953         VMSTATE_UINT32(mdr, stellaris_i2c_state),
 954         VMSTATE_UINT32(mtpr, stellaris_i2c_state),
 955         VMSTATE_UINT32(mimr, stellaris_i2c_state),
 956         VMSTATE_UINT32(mris, stellaris_i2c_state),
 957         VMSTATE_UINT32(mcr, stellaris_i2c_state),
 958         VMSTATE_END_OF_LIST()
 959     }
 960 };
 961
 962 static void stellaris_i2c_init(Object *obj)
 963 {
 964     DeviceState *dev = DEVICE(obj);
 965     stellaris_i2c_state *s = STELLARIS_I2C(obj);
 966     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 967     I2CBus *bus;
 968
 969     sysbus_init_irq(sbd, &s->irq);
 970     bus = i2c_init_bus(dev, "i2c");
 971     s->bus = bus;
 972
 973     memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s,
 974                           "i2c", 0x1000);
 975     sysbus_init_mmio(sbd, &s->iomem);
 976     /* ??? For now we only implement the master interface.  */
 977     stellaris_i2c_reset(s);
 978 }
 979
 980 /* Analogue to Digital Converter.  This is only partially implemented,
 981    enough for applications that use a combined ADC and timer tick.  */
 982
 983 #define STELLARIS_ADC_EM_CONTROLLER 0
 984 #define STELLARIS_ADC_EM_COMP       1
 985 #define STELLARIS_ADC_EM_EXTERNAL   4
 986 #define STELLARIS_ADC_EM_TIMER      5
 987 #define STELLARIS_ADC_EM_PWM0       6
 988 #define STELLARIS_ADC_EM_PWM1       7
 989 #define STELLARIS_ADC_EM_PWM2       8
 990
 991 #define STELLARIS_ADC_FIFO_EMPTY    0x0100
 992 #define STELLARIS_ADC_FIFO_FULL     0x1000
 993
 994 #define TYPE_STELLARIS_ADC "stellaris-adc"
 995 typedef struct StellarisADCState stellaris_adc_state;
 996 DECLARE_INSTANCE_CHECKER(stellaris_adc_state, STELLARIS_ADC,
 997                          TYPE_STELLARIS_ADC)
 998
 999 struct StellarisADCState {
1000     SysBusDevice parent_obj;
1001
1002     MemoryRegion iomem;
1003     uint32_t actss;
1004     uint32_t ris;
1005     uint32_t im;
1006     uint32_t emux;
1007     uint32_t ostat;
1008     uint32_t ustat;
1009     uint32_t sspri;
1010     uint32_t sac;
1011     struct {
1012         uint32_t state;
1013         uint32_t data[16];
1014     } fifo[4];
1015     uint32_t ssmux[4];
1016     uint32_t ssctl[4];
1017     uint32_t noise;
1018     qemu_irq irq[4];
1019 };
1020
1021 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
1022 {
1023     int tail;
1024
1025     tail = s->fifo[n].state & 0xf;
1026     if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
1027         s->ustat |= 1 << n;
1028     } else {
1029         s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);
1030         s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;
1031         if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))
1032             s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;
1033     }
1034     return s->fifo[n].data[tail];
1035 }
1036
1037 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
1038                                      uint32_t value)
1039 {
1040     int head;
1041
1042     /* TODO: Real hardware has limited size FIFOs.  We have a full 16 entry
1043        FIFO fir each sequencer.  */
1044     head = (s->fifo[n].state >> 4) & 0xf;
1045     if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
1046         s->ostat |= 1 << n;
1047         return;
1048     }
1049     s->fifo[n].data[head] = value;
1050     head = (head + 1) & 0xf;
1051     s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY;
1052     s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4);
1053     if ((s->fifo[n].state & 0xf) == head)
1054         s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
1055 }
1056
1057 static void stellaris_adc_update(stellaris_adc_state *s)
1058 {
1059     int level;
1060     int n;
1061
1062     for (n = 0; n < 4; n++) {
1063         level = (s->ris & s->im & (1 << n)) != 0;
1064         qemu_set_irq(s->irq[n], level);
1065     }
1066 }
1067
1068 static void stellaris_adc_trigger(void *opaque, int irq, int level)
1069 {
1070     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1071     int n;
1072
1073     for (n = 0; n < 4; n++) {
1074         if ((s->actss & (1 << n)) == 0) {
1075             continue;
1076         }
1077
1078         if (((s->emux >> (n * 4)) & 0xff) != 5) {
1079             continue;
1080         }
1081
1082         /* Some applications use the ADC as a random number source, so introduce
1083            some variation into the signal.  */
1084         s->noise = s->noise * 314159 + 1;
1085         /* ??? actual inputs not implemented.  Return an arbitrary value.  */
1086         stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7));
1087         s->ris |= (1 << n);
1088         stellaris_adc_update(s);
1089     }
1090 }
1091
1092 static void stellaris_adc_reset(stellaris_adc_state *s)
1093 {
1094     int n;
1095
1096     for (n = 0; n < 4; n++) {
1097         s->ssmux[n] = 0;
1098         s->ssctl[n] = 0;
1099         s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY;
1100     }
1101 }
1102
1103 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
1104                                    unsigned size)
1105 {
1106     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1107
1108     /* TODO: Implement this.  */
1109     if (offset >= 0x40 && offset < 0xc0) {
1110         int n;
1111         n = (offset - 0x40) >> 5;
1112         switch (offset & 0x1f) {
1113         case 0x00: /* SSMUX */
1114             return s->ssmux[n];
1115         case 0x04: /* SSCTL */
1116             return s->ssctl[n];
1117         case 0x08: /* SSFIFO */
1118             return stellaris_adc_fifo_read(s, n);
1119         case 0x0c: /* SSFSTAT */
1120             return s->fifo[n].state;
1121         default:
1122             break;
1123         }
1124     }
1125     switch (offset) {
1126     case 0x00: /* ACTSS */
1127         return s->actss;
1128     case 0x04: /* RIS */
1129         return s->ris;
1130     case 0x08: /* IM */
1131         return s->im;
1132     case 0x0c: /* ISC */
1133         return s->ris & s->im;
1134     case 0x10: /* OSTAT */
1135         return s->ostat;
1136     case 0x14: /* EMUX */
1137         return s->emux;
1138     case 0x18: /* USTAT */
1139         return s->ustat;
1140     case 0x20: /* SSPRI */
1141         return s->sspri;
1142     case 0x30: /* SAC */
1143         return s->sac;
1144     default:
1145         qemu_log_mask(LOG_GUEST_ERROR,
1146                       "stellaris_adc: read at bad offset 0x%x\n", (int)offset);
1147         return 0;
1148     }
1149 }
1150
1151 static void stellaris_adc_write(void *opaque, hwaddr offset,
1152                                 uint64_t value, unsigned size)
1153 {
1154     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1155
1156     /* TODO: Implement this.  */
1157     if (offset >= 0x40 && offset < 0xc0) {
1158         int n;
1159         n = (offset - 0x40) >> 5;
1160         switch (offset & 0x1f) {
1161         case 0x00: /* SSMUX */
1162             s->ssmux[n] = value & 0x33333333;
1163             return;
1164         case 0x04: /* SSCTL */
1165             if (value != 6) {
1166                 qemu_log_mask(LOG_UNIMP,
1167                               "ADC: Unimplemented sequence %" PRIx64 "\n",
1168                               value);
1169             }
1170             s->ssctl[n] = value;
1171             return;
1172         default:
1173             break;
1174         }
1175     }
1176     switch (offset) {
1177     case 0x00: /* ACTSS */
1178         s->actss = value & 0xf;
1179         break;
1180     case 0x08: /* IM */
1181         s->im = value;
1182         break;
1183     case 0x0c: /* ISC */
1184         s->ris &= ~value;
1185         break;
1186     case 0x10: /* OSTAT */
1187         s->ostat &= ~value;
1188         break;
1189     case 0x14: /* EMUX */
1190         s->emux = value;
1191         break;
1192     case 0x18: /* USTAT */
1193         s->ustat &= ~value;
1194         break;
1195     case 0x20: /* SSPRI */
1196         s->sspri = value;
1197         break;
1198     case 0x28: /* PSSI */
1199         qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n");
1200         break;
1201     case 0x30: /* SAC */
1202         s->sac = value;
1203         break;
1204     default:
1205         qemu_log_mask(LOG_GUEST_ERROR,
1206                       "stellaris_adc: write at bad offset 0x%x\n", (int)offset);
1207     }
1208     stellaris_adc_update(s);
1209 }
1210
1211 static const MemoryRegionOps stellaris_adc_ops = {
1212     .read = stellaris_adc_read,
1213     .write = stellaris_adc_write,
1214     .endianness = DEVICE_NATIVE_ENDIAN,
1215 };
1216
1217 static const VMStateDescription vmstate_stellaris_adc = {
1218     .name = "stellaris_adc",
1219     .version_id = 1,
1220     .minimum_version_id = 1,
1221     .fields = (VMStateField[]) {
1222         VMSTATE_UINT32(actss, stellaris_adc_state),
1223         VMSTATE_UINT32(ris, stellaris_adc_state),
1224         VMSTATE_UINT32(im, stellaris_adc_state),
1225         VMSTATE_UINT32(emux, stellaris_adc_state),
1226         VMSTATE_UINT32(ostat, stellaris_adc_state),
1227         VMSTATE_UINT32(ustat, stellaris_adc_state),
1228         VMSTATE_UINT32(sspri, stellaris_adc_state),
1229         VMSTATE_UINT32(sac, stellaris_adc_state),
1230         VMSTATE_UINT32(fifo[0].state, stellaris_adc_state),
1231         VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16),
1232         VMSTATE_UINT32(ssmux[0], stellaris_adc_state),
1233         VMSTATE_UINT32(ssctl[0], stellaris_adc_state),
1234         VMSTATE_UINT32(fifo[1].state, stellaris_adc_state),
1235         VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16),
1236         VMSTATE_UINT32(ssmux[1], stellaris_adc_state),
1237         VMSTATE_UINT32(ssctl[1], stellaris_adc_state),
1238         VMSTATE_UINT32(fifo[2].state, stellaris_adc_state),
1239         VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16),
1240         VMSTATE_UINT32(ssmux[2], stellaris_adc_state),
1241         VMSTATE_UINT32(ssctl[2], stellaris_adc_state),
1242         VMSTATE_UINT32(fifo[3].state, stellaris_adc_state),
1243         VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16),
1244         VMSTATE_UINT32(ssmux[3], stellaris_adc_state),
1245         VMSTATE_UINT32(ssctl[3], stellaris_adc_state),
1246         VMSTATE_UINT32(noise, stellaris_adc_state),
1247         VMSTATE_END_OF_LIST()
1248     }
1249 };
1250
1251 static void stellaris_adc_init(Object *obj)
1252 {
1253     DeviceState *dev = DEVICE(obj);
1254     stellaris_adc_state *s = STELLARIS_ADC(obj);
1255     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1256     int n;
1257
1258     for (n = 0; n < 4; n++) {
1259         sysbus_init_irq(sbd, &s->irq[n]);
1260     }
1261
1262     memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s,
1263                           "adc", 0x1000);
1264     sysbus_init_mmio(sbd, &s->iomem);
1265     stellaris_adc_reset(s);
1266     qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
1267 }
1268
1269 /* Board init.  */
1270 static stellaris_board_info stellaris_boards[] = {
1271   { "LM3S811EVB",
1272     0,
1273     0x0032000e,
1274     0x001f001f, /* dc0 */
1275     0x001132bf,
1276     0x01071013,
1277     0x3f0f01ff,
1278     0x0000001f,
1279     BP_OLED_I2C
1280   },
1281   { "LM3S6965EVB",
1282     0x10010002,
1283     0x1073402e,
1284     0x00ff007f, /* dc0 */
1285     0x001133ff,
1286     0x030f5317,
1287     0x0f0f87ff,
1288     0x5000007f,
1289     BP_OLED_SSI | BP_GAMEPAD
1290   }
1291 };
1292
1293 static void stellaris_init(MachineState *ms, stellaris_board_info *board)
1294 {
1295     static const int uart_irq[] = {5, 6, 33, 34};
1296     static const int timer_irq[] = {19, 21, 23, 35};
1297     static const uint32_t gpio_addr[7] =
1298       { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1299         0x40024000, 0x40025000, 0x40026000};
1300     static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
1301
1302     /* Memory map of SoC devices, from
1303      * Stellaris LM3S6965 Microcontroller Data Sheet (rev I)
1304      * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
1305      *
1306      * 40000000 wdtimer
1307      * 40002000 i2c (unimplemented)
1308      * 40004000 GPIO
1309      * 40005000 GPIO
1310      * 40006000 GPIO
1311      * 40007000 GPIO
1312      * 40008000 SSI
1313      * 4000c000 UART
1314      * 4000d000 UART
1315      * 4000e000 UART
1316      * 40020000 i2c
1317      * 40021000 i2c (unimplemented)
1318      * 40024000 GPIO
1319      * 40025000 GPIO
1320      * 40026000 GPIO
1321      * 40028000 PWM (unimplemented)
1322      * 4002c000 QEI (unimplemented)
1323      * 4002d000 QEI (unimplemented)
1324      * 40030000 gptimer
1325      * 40031000 gptimer
1326      * 40032000 gptimer
1327      * 40033000 gptimer
1328      * 40038000 ADC
1329      * 4003c000 analogue comparator (unimplemented)
1330      * 40048000 ethernet
1331      * 400fc000 hibernation module (unimplemented)
1332      * 400fd000 flash memory control (unimplemented)
1333      * 400fe000 system control
1334      */
1335
1336     DeviceState *gpio_dev[7], *nvic;
1337     qemu_irq gpio_in[7][8];
1338     qemu_irq gpio_out[7][8];
1339     qemu_irq adc;
1340     int sram_size;
1341     int flash_size;
1342     I2CBus *i2c;
1343     DeviceState *dev;
1344     int i;
1345     int j;
1346
1347     MemoryRegion *sram = g_new(MemoryRegion, 1);
1348     MemoryRegion *flash = g_new(MemoryRegion, 1);
1349     MemoryRegion *system_memory = get_system_memory();
1350
1351     flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
1352     sram_size = ((board->dc0 >> 18) + 1) * 1024;
1353
1354     /* Flash programming is done via the SCU, so pretend it is ROM.  */
1355     memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size,
1356                            &error_fatal);
1357     memory_region_add_subregion(system_memory, 0, flash);
1358
1359     memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size,
1360                            &error_fatal);
1361     memory_region_add_subregion(system_memory, 0x20000000, sram);
1362
1363     nvic = qdev_new(TYPE_ARMV7M);
1364     qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
1365     qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
1366     qdev_prop_set_bit(nvic, "enable-bitband", true);
1367     object_property_set_link(OBJECT(nvic), "memory",
1368                              OBJECT(get_system_memory()), &error_abort);
1369     /* This will exit with an error if the user passed us a bad cpu_type */
1370     sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal);
1371
1372     if (board->dc1 & (1 << 16)) {
1373         dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
1374                                     qdev_get_gpio_in(nvic, 14),
1375                                     qdev_get_gpio_in(nvic, 15),
1376                                     qdev_get_gpio_in(nvic, 16),
1377                                     qdev_get_gpio_in(nvic, 17),
1378                                     NULL);
1379         adc = qdev_get_gpio_in(dev, 0);
1380     } else {
1381         adc = NULL;
1382     }
1383     for (i = 0; i < 4; i++) {
1384         if (board->dc2 & (0x10000 << i)) {
1385             dev = sysbus_create_simple(TYPE_STELLARIS_GPTM,
1386                                        0x40030000 + i * 0x1000,
1387                                        qdev_get_gpio_in(nvic, timer_irq[i]));
1388             /* TODO: This is incorrect, but we get away with it because
1389                the ADC output is only ever pulsed.  */
1390             qdev_connect_gpio_out(dev, 0, adc);
1391         }
1392     }
1393
1394     stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28),
1395                        board, nd_table[0].macaddr.a);
1396
1397
1398     if (board->dc1 & (1 << 3)) { /* watchdog present */
1399         dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
1400
1401         /* system_clock_scale is valid now */
1402         uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale;
1403         qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk);
1404
1405         sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1406         sysbus_mmio_map(SYS_BUS_DEVICE(dev),
1407                         0,
1408                         0x40000000u);
1409         sysbus_connect_irq(SYS_BUS_DEVICE(dev),
1410                            0,
1411                            qdev_get_gpio_in(nvic, 18));
1412     }
1413
1414
1415     for (i = 0; i < 7; i++) {
1416         if (board->dc4 & (1 << i)) {
1417             gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],
1418                                                qdev_get_gpio_in(nvic,
1419                                                                 gpio_irq[i]));
1420             for (j = 0; j < 8; j++) {
1421                 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j);
1422                 gpio_out[i][j] = NULL;
1423             }
1424         }
1425     }
1426
1427     if (board->dc2 & (1 << 12)) {
1428         dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000,
1429                                    qdev_get_gpio_in(nvic, 8));
1430         i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
1431         if (board->peripherals & BP_OLED_I2C) {
1432             i2c_slave_create_simple(i2c, "ssd0303", 0x3d);
1433         }
1434     }
1435
1436     for (i = 0; i < 4; i++) {
1437         if (board->dc2 & (1 << i)) {
1438             pl011_luminary_create(0x4000c000 + i * 0x1000,
1439                                   qdev_get_gpio_in(nvic, uart_irq[i]),
1440                                   serial_hd(i));
1441         }
1442     }
1443     if (board->dc2 & (1 << 4)) {
1444         dev = sysbus_create_simple("pl022", 0x40008000,
1445                                    qdev_get_gpio_in(nvic, 7));
1446         if (board->peripherals & BP_OLED_SSI) {
1447             void *bus;
1448             DeviceState *sddev;
1449             DeviceState *ssddev;
1450
1451             /* Some boards have both an OLED controller and SD card connected to
1452              * the same SSI port, with the SD card chip select connected to a
1453              * GPIO pin.  Technically the OLED chip select is connected to the
1454              * SSI Fss pin.  We do not bother emulating that as both devices
1455              * should never be selected simultaneously, and our OLED controller
1456              * ignores stray 0xff commands that occur when deselecting the SD
1457              * card.
1458              */
1459             bus = qdev_get_child_bus(dev, "ssi");
1460
1461             sddev = ssi_create_peripheral(bus, "ssi-sd");
1462             ssddev = ssi_create_peripheral(bus, "ssd0323");
1463             gpio_out[GPIO_D][0] = qemu_irq_split(
1464                     qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0),
1465                     qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0));
1466             gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0);
1467
1468             /* Make sure the select pin is high.  */
1469             qemu_irq_raise(gpio_out[GPIO_D][0]);
1470         }
1471     }
1472     if (board->dc4 & (1 << 28)) {
1473         DeviceState *enet;
1474
1475         qemu_check_nic_model(&nd_table[0], "stellaris");
1476
1477         enet = qdev_new("stellaris_enet");
1478         qdev_set_nic_properties(enet, &nd_table[0]);
1479         sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal);
1480         sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000);
1481         sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42));
1482     }
1483     if (board->peripherals & BP_GAMEPAD) {
1484         qemu_irq gpad_irq[5];
1485         static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1486
1487         gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */
1488         gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */
1489         gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */
1490         gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */
1491         gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */
1492
1493         stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
1494     }
1495     for (i = 0; i < 7; i++) {
1496         if (board->dc4 & (1 << i)) {
1497             for (j = 0; j < 8; j++) {
1498                 if (gpio_out[i][j]) {
1499                     qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]);
1500                 }
1501             }
1502         }
1503     }
1504
1505     /* Add dummy regions for the devices we don't implement yet,
1506      * so guest accesses don't cause unlogged crashes.
1507      */
1508     create_unimplemented_device("i2c-0", 0x40002000, 0x1000);
1509     create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
1510     create_unimplemented_device("PWM", 0x40028000, 0x1000);
1511     create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
1512     create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);
1513     create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);
1514     create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
1515     create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
1516
1517     armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, flash_size);
1518 }
1519
1520 /* FIXME: Figure out how to generate these from stellaris_boards.  */
1521 static void lm3s811evb_init(MachineState *machine)
1522 {
1523     stellaris_init(machine, &stellaris_boards[0]);
1524 }
1525
1526 static void lm3s6965evb_init(MachineState *machine)
1527 {
1528     stellaris_init(machine, &stellaris_boards[1]);
1529 }
1530
1531 static void lm3s811evb_class_init(ObjectClass *oc, void *data)
1532 {
1533     MachineClass *mc = MACHINE_CLASS(oc);
1534
1535     mc->desc = "Stellaris LM3S811EVB";
1536     mc->init = lm3s811evb_init;
1537     mc->ignore_memory_transaction_failures = true;
1538     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
1539 }
1540
1541 static const TypeInfo lm3s811evb_type = {
1542     .name = MACHINE_TYPE_NAME("lm3s811evb"),
1543     .parent = TYPE_MACHINE,
1544     .class_init = lm3s811evb_class_init,
1545 };
1546
1547 static void lm3s6965evb_class_init(ObjectClass *oc, void *data)
1548 {
1549     MachineClass *mc = MACHINE_CLASS(oc);
1550
1551     mc->desc = "Stellaris LM3S6965EVB";
1552     mc->init = lm3s6965evb_init;
1553     mc->ignore_memory_transaction_failures = true;
1554     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
1555 }
1556
1557 static const TypeInfo lm3s6965evb_type = {
1558     .name = MACHINE_TYPE_NAME("lm3s6965evb"),
1559     .parent = TYPE_MACHINE,
1560     .class_init = lm3s6965evb_class_init,
1561 };
1562
1563 static void stellaris_machine_init(void)
1564 {
1565     type_register_static(&lm3s811evb_type);
1566     type_register_static(&lm3s6965evb_type);
1567 }
1568
1569 type_init(stellaris_machine_init)
1570
1571 static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
1572 {
1573     DeviceClass *dc = DEVICE_CLASS(klass);
1574
1575     dc->vmsd = &vmstate_stellaris_i2c;
1576 }
1577
1578 static const TypeInfo stellaris_i2c_info = {
1579     .name          = TYPE_STELLARIS_I2C,
1580     .parent        = TYPE_SYS_BUS_DEVICE,
1581     .instance_size = sizeof(stellaris_i2c_state),
1582     .instance_init = stellaris_i2c_init,
1583     .class_init    = stellaris_i2c_class_init,
1584 };
1585
1586 static void stellaris_gptm_class_init(ObjectClass *klass, void *data)
1587 {
1588     DeviceClass *dc = DEVICE_CLASS(klass);
1589
1590     dc->vmsd = &vmstate_stellaris_gptm;
1591     dc->realize = stellaris_gptm_realize;
1592 }
1593
1594 static const TypeInfo stellaris_gptm_info = {
1595     .name          = TYPE_STELLARIS_GPTM,
1596     .parent        = TYPE_SYS_BUS_DEVICE,
1597     .instance_size = sizeof(gptm_state),
1598     .instance_init = stellaris_gptm_init,
1599     .class_init    = stellaris_gptm_class_init,
1600 };
1601
1602 static void stellaris_adc_class_init(ObjectClass *klass, void *data)
1603 {
1604     DeviceClass *dc = DEVICE_CLASS(klass);
1605
1606     dc->vmsd = &vmstate_stellaris_adc;
1607 }
1608
1609 static const TypeInfo stellaris_adc_info = {
1610     .name          = TYPE_STELLARIS_ADC,
1611     .parent        = TYPE_SYS_BUS_DEVICE,
1612     .instance_size = sizeof(stellaris_adc_state),
1613     .instance_init = stellaris_adc_init,
1614     .class_init    = stellaris_adc_class_init,
1615 };
1616
1617 static void stellaris_sys_class_init(ObjectClass *klass, void *data)
1618 {
1619     DeviceClass *dc = DEVICE_CLASS(klass);
1620     ResettableClass *rc = RESETTABLE_CLASS(klass);
1621
1622     dc->vmsd = &vmstate_stellaris_sys;
1623     rc->phases.enter = stellaris_sys_reset_enter;
1624     rc->phases.hold = stellaris_sys_reset_hold;
1625     rc->phases.exit = stellaris_sys_reset_exit;
1626     device_class_set_props(dc, stellaris_sys_properties);
1627 }
1628
1629 static const TypeInfo stellaris_sys_info = {
1630     .name = TYPE_STELLARIS_SYS,
1631     .parent = TYPE_SYS_BUS_DEVICE,
1632     .instance_size = sizeof(ssys_state),
1633     .instance_init = stellaris_sys_instance_init,
1634     .class_init = stellaris_sys_class_init,
1635 };
1636
1637 static void stellaris_register_types(void)
1638 {
1639     type_register_static(&stellaris_i2c_info);
1640     type_register_static(&stellaris_gptm_info);
1641     type_register_static(&stellaris_adc_info);
1642     type_register_static(&stellaris_sys_info);
1643 }
1644
1645 type_init(stellaris_register_types)