2 * Nordic Semiconductor nRF51 SoC
3 * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
5 * Copyright 2018 Joel Stanley <joel@jms.id.au>
7 * This code is licensed under the GPL version 2 or later. See
8 * the COPYING file in the top-level directory.
11 #include "qemu/osdep.h"
12 #include "qapi/error.h"
13 #include "hw/arm/boot.h"
14 #include "hw/sysbus.h"
15 #include "hw/misc/unimp.h"
16 #include "exec/address-spaces.h"
20 #include "hw/arm/nrf51.h"
21 #include "hw/arm/nrf51_soc.h"
24 * The size and base is for the NRF51822 part. If other parts
25 * are supported in the future, add a sub-class of NRF51SoC for
26 * the specific variants
28 #define NRF51822_FLASH_PAGES 256
29 #define NRF51822_SRAM_PAGES 16
30 #define NRF51822_FLASH_SIZE (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE)
31 #define NRF51822_SRAM_SIZE (NRF51822_SRAM_PAGES * NRF51_PAGE_SIZE)
33 #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)
35 static uint64_t clock_read(void *opaque
, hwaddr addr
, unsigned int size
)
37 qemu_log_mask(LOG_UNIMP
, "%s: 0x%" HWADDR_PRIx
" [%u]\n",
38 __func__
, addr
, size
);
42 static void clock_write(void *opaque
, hwaddr addr
, uint64_t data
,
45 qemu_log_mask(LOG_UNIMP
, "%s: 0x%" HWADDR_PRIx
" <- 0x%" PRIx64
" [%u]\n",
46 __func__
, addr
, data
, size
);
49 static const MemoryRegionOps clock_ops
= {
55 static void nrf51_soc_realize(DeviceState
*dev_soc
, Error
**errp
)
57 NRF51State
*s
= NRF51_SOC(dev_soc
);
63 if (!s
->board_memory
) {
64 error_setg(errp
, "memory property was not set");
68 object_property_set_link(OBJECT(&s
->cpu
), OBJECT(&s
->container
), "memory",
70 sysbus_realize(SYS_BUS_DEVICE(&s
->cpu
), &err
);
72 error_propagate(errp
, err
);
76 memory_region_add_subregion_overlap(&s
->container
, 0, s
->board_memory
, -1);
78 memory_region_init_ram(&s
->sram
, OBJECT(s
), "nrf51.sram", s
->sram_size
,
81 error_propagate(errp
, err
);
84 memory_region_add_subregion(&s
->container
, NRF51_SRAM_BASE
, &s
->sram
);
87 sysbus_realize(SYS_BUS_DEVICE(&s
->uart
), &err
);
89 error_propagate(errp
, err
);
92 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->uart
), 0);
93 memory_region_add_subregion_overlap(&s
->container
, NRF51_UART_BASE
, mr
, 0);
94 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->uart
), 0,
95 qdev_get_gpio_in(DEVICE(&s
->cpu
),
96 BASE_TO_IRQ(NRF51_UART_BASE
)));
99 sysbus_realize(SYS_BUS_DEVICE(&s
->rng
), &err
);
101 error_propagate(errp
, err
);
105 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->rng
), 0);
106 memory_region_add_subregion_overlap(&s
->container
, NRF51_RNG_BASE
, mr
, 0);
107 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->rng
), 0,
108 qdev_get_gpio_in(DEVICE(&s
->cpu
),
109 BASE_TO_IRQ(NRF51_RNG_BASE
)));
111 /* UICR, FICR, NVMC, FLASH */
112 object_property_set_uint(OBJECT(&s
->nvm
), s
->flash_size
, "flash-size",
115 error_propagate(errp
, err
);
119 sysbus_realize(SYS_BUS_DEVICE(&s
->nvm
), &err
);
121 error_propagate(errp
, err
);
125 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->nvm
), 0);
126 memory_region_add_subregion_overlap(&s
->container
, NRF51_NVMC_BASE
, mr
, 0);
127 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->nvm
), 1);
128 memory_region_add_subregion_overlap(&s
->container
, NRF51_FICR_BASE
, mr
, 0);
129 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->nvm
), 2);
130 memory_region_add_subregion_overlap(&s
->container
, NRF51_UICR_BASE
, mr
, 0);
131 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->nvm
), 3);
132 memory_region_add_subregion_overlap(&s
->container
, NRF51_FLASH_BASE
, mr
, 0);
135 sysbus_realize(SYS_BUS_DEVICE(&s
->gpio
), &err
);
137 error_propagate(errp
, err
);
141 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->gpio
), 0);
142 memory_region_add_subregion_overlap(&s
->container
, NRF51_GPIO_BASE
, mr
, 0);
144 /* Pass all GPIOs to the SOC layer so they are available to the board */
145 qdev_pass_gpios(DEVICE(&s
->gpio
), dev_soc
, NULL
);
148 for (i
= 0; i
< NRF51_NUM_TIMERS
; i
++) {
149 object_property_set_uint(OBJECT(&s
->timer
[i
]), i
, "id", &err
);
151 error_propagate(errp
, err
);
154 sysbus_realize(SYS_BUS_DEVICE(&s
->timer
[i
]), &err
);
156 error_propagate(errp
, err
);
160 base_addr
= NRF51_TIMER_BASE
+ i
* NRF51_PERIPHERAL_SIZE
;
162 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->timer
[i
]), 0, base_addr
);
163 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->timer
[i
]), 0,
164 qdev_get_gpio_in(DEVICE(&s
->cpu
),
165 BASE_TO_IRQ(base_addr
)));
168 /* STUB Peripherals */
169 memory_region_init_io(&s
->clock
, OBJECT(dev_soc
), &clock_ops
, NULL
,
170 "nrf51_soc.clock", NRF51_PERIPHERAL_SIZE
);
171 memory_region_add_subregion_overlap(&s
->container
,
172 NRF51_IOMEM_BASE
, &s
->clock
, -1);
174 create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE
,
176 create_unimplemented_device("nrf51_soc.private",
177 NRF51_PRIVATE_BASE
, NRF51_PRIVATE_SIZE
);
180 static void nrf51_soc_init(Object
*obj
)
184 NRF51State
*s
= NRF51_SOC(obj
);
186 memory_region_init(&s
->container
, obj
, "nrf51-container", UINT64_MAX
);
188 object_initialize_child(OBJECT(s
), "armv6m", &s
->cpu
, TYPE_ARMV7M
);
189 qdev_prop_set_string(DEVICE(&s
->cpu
), "cpu-type",
190 ARM_CPU_TYPE_NAME("cortex-m0"));
191 qdev_prop_set_uint32(DEVICE(&s
->cpu
), "num-irq", 32);
193 object_initialize_child(obj
, "uart", &s
->uart
, TYPE_NRF51_UART
);
194 object_property_add_alias(obj
, "serial0", OBJECT(&s
->uart
), "chardev");
196 object_initialize_child(obj
, "rng", &s
->rng
, TYPE_NRF51_RNG
);
198 object_initialize_child(obj
, "nvm", &s
->nvm
, TYPE_NRF51_NVM
);
200 object_initialize_child(obj
, "gpio", &s
->gpio
, TYPE_NRF51_GPIO
);
202 for (i
= 0; i
< NRF51_NUM_TIMERS
; i
++) {
203 object_initialize_child(obj
, "timer[*]", &s
->timer
[i
],
209 static Property nrf51_soc_properties
[] = {
210 DEFINE_PROP_LINK("memory", NRF51State
, board_memory
, TYPE_MEMORY_REGION
,
212 DEFINE_PROP_UINT32("sram-size", NRF51State
, sram_size
, NRF51822_SRAM_SIZE
),
213 DEFINE_PROP_UINT32("flash-size", NRF51State
, flash_size
,
214 NRF51822_FLASH_SIZE
),
215 DEFINE_PROP_END_OF_LIST(),
218 static void nrf51_soc_class_init(ObjectClass
*klass
, void *data
)
220 DeviceClass
*dc
= DEVICE_CLASS(klass
);
222 dc
->realize
= nrf51_soc_realize
;
223 device_class_set_props(dc
, nrf51_soc_properties
);
226 static const TypeInfo nrf51_soc_info
= {
227 .name
= TYPE_NRF51_SOC
,
228 .parent
= TYPE_SYS_BUS_DEVICE
,
229 .instance_size
= sizeof(NRF51State
),
230 .instance_init
= nrf51_soc_init
,
231 .class_init
= nrf51_soc_class_init
,
234 static void nrf51_soc_types(void)
236 type_register_static(&nrf51_soc_info
);
238 type_init(nrf51_soc_types
)