2 * ARMV7M System emulation.
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 #include "qemu/osdep.h"
11 #include "hw/arm/armv7m.h"
12 #include "qapi/error.h"
14 #include "hw/sysbus.h"
15 #include "hw/arm/boot.h"
16 #include "hw/loader.h"
17 #include "hw/qdev-properties.h"
19 #include "sysemu/qtest.h"
20 #include "sysemu/reset.h"
21 #include "qemu/error-report.h"
22 #include "qemu/module.h"
23 #include "exec/address-spaces.h"
24 #include "target/arm/idau.h"
26 /* Bitbanded IO. Each word corresponds to a single bit. */
28 /* Get the byte address of the real memory for a bitband access. */
29 static inline hwaddr
bitband_addr(BitBandState
*s
, hwaddr offset
)
31 return s
->base
| (offset
& 0x1ffffff) >> 5;
34 static MemTxResult
bitband_read(void *opaque
, hwaddr offset
,
35 uint64_t *data
, unsigned size
, MemTxAttrs attrs
)
37 BitBandState
*s
= opaque
;
45 /* Find address in underlying memory and round down to multiple of size */
46 addr
= bitband_addr(s
, offset
) & (-size
);
47 res
= address_space_read(&s
->source_as
, addr
, attrs
, buf
, size
);
51 /* Bit position in the N bytes read... */
52 bitpos
= (offset
>> 2) & ((size
* 8) - 1);
53 /* ...converted to byte in buffer and bit in byte */
54 bit
= (buf
[bitpos
>> 3] >> (bitpos
& 7)) & 1;
59 static MemTxResult
bitband_write(void *opaque
, hwaddr offset
, uint64_t value
,
60 unsigned size
, MemTxAttrs attrs
)
62 BitBandState
*s
= opaque
;
70 /* Find address in underlying memory and round down to multiple of size */
71 addr
= bitband_addr(s
, offset
) & (-size
);
72 res
= address_space_read(&s
->source_as
, addr
, attrs
, buf
, size
);
76 /* Bit position in the N bytes read... */
77 bitpos
= (offset
>> 2) & ((size
* 8) - 1);
78 /* ...converted to byte in buffer and bit in byte */
79 bit
= 1 << (bitpos
& 7);
81 buf
[bitpos
>> 3] |= bit
;
83 buf
[bitpos
>> 3] &= ~bit
;
85 return address_space_write(&s
->source_as
, addr
, attrs
, buf
, size
);
88 static const MemoryRegionOps bitband_ops
= {
89 .read_with_attrs
= bitband_read
,
90 .write_with_attrs
= bitband_write
,
91 .endianness
= DEVICE_NATIVE_ENDIAN
,
92 .impl
.min_access_size
= 1,
93 .impl
.max_access_size
= 4,
94 .valid
.min_access_size
= 1,
95 .valid
.max_access_size
= 4,
98 static void bitband_init(Object
*obj
)
100 BitBandState
*s
= BITBAND(obj
);
101 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
103 memory_region_init_io(&s
->iomem
, obj
, &bitband_ops
, s
,
104 "bitband", 0x02000000);
105 sysbus_init_mmio(dev
, &s
->iomem
);
108 static void bitband_realize(DeviceState
*dev
, Error
**errp
)
110 BitBandState
*s
= BITBAND(dev
);
112 if (!s
->source_memory
) {
113 error_setg(errp
, "source-memory property not set");
117 address_space_init(&s
->source_as
, s
->source_memory
, "bitband-source");
122 static const hwaddr bitband_input_addr
[ARMV7M_NUM_BITBANDS
] = {
123 0x20000000, 0x40000000
126 static const hwaddr bitband_output_addr
[ARMV7M_NUM_BITBANDS
] = {
127 0x22000000, 0x42000000
130 static void armv7m_instance_init(Object
*obj
)
132 ARMv7MState
*s
= ARMV7M(obj
);
135 /* Can't init the cpu here, we don't yet know which model to use */
137 memory_region_init(&s
->container
, obj
, "armv7m-container", UINT64_MAX
);
139 object_initialize_child(obj
, "nvnic", &s
->nvic
, TYPE_NVIC
);
140 object_property_add_alias(obj
, "num-irq",
141 OBJECT(&s
->nvic
), "num-irq");
143 for (i
= 0; i
< ARRAY_SIZE(s
->bitband
); i
++) {
144 object_initialize_child(obj
, "bitband[*]", &s
->bitband
[i
],
149 static void armv7m_realize(DeviceState
*dev
, Error
**errp
)
151 ARMv7MState
*s
= ARMV7M(dev
);
156 if (!s
->board_memory
) {
157 error_setg(errp
, "memory property was not set");
161 memory_region_add_subregion_overlap(&s
->container
, 0, s
->board_memory
, -1);
163 s
->cpu
= ARM_CPU(object_new_with_props(s
->cpu_type
, OBJECT(s
), "cpu",
166 error_propagate(errp
, err
);
170 object_property_set_link(OBJECT(s
->cpu
), OBJECT(&s
->container
), "memory",
172 if (object_property_find(OBJECT(s
->cpu
), "idau", NULL
)) {
173 object_property_set_link(OBJECT(s
->cpu
), s
->idau
, "idau",
176 if (object_property_find(OBJECT(s
->cpu
), "init-svtor", NULL
)) {
177 object_property_set_uint(OBJECT(s
->cpu
), s
->init_svtor
,
180 error_propagate(errp
, err
);
184 if (object_property_find(OBJECT(s
->cpu
), "start-powered-off", NULL
)) {
185 object_property_set_bool(OBJECT(s
->cpu
), s
->start_powered_off
,
186 "start-powered-off", &err
);
188 error_propagate(errp
, err
);
192 if (object_property_find(OBJECT(s
->cpu
), "vfp", NULL
)) {
193 object_property_set_bool(OBJECT(s
->cpu
), s
->vfp
,
196 error_propagate(errp
, err
);
200 if (object_property_find(OBJECT(s
->cpu
), "dsp", NULL
)) {
201 object_property_set_bool(OBJECT(s
->cpu
), s
->dsp
,
204 error_propagate(errp
, err
);
210 * Tell the CPU where the NVIC is; it will fail realize if it doesn't
211 * have one. Similarly, tell the NVIC where its CPU is.
213 s
->cpu
->env
.nvic
= &s
->nvic
;
214 s
->nvic
.cpu
= s
->cpu
;
216 qdev_realize(DEVICE(s
->cpu
), NULL
, &err
);
218 error_propagate(errp
, err
);
222 /* Note that we must realize the NVIC after the CPU */
223 sysbus_realize(SYS_BUS_DEVICE(&s
->nvic
), &err
);
225 error_propagate(errp
, err
);
229 /* Alias the NVIC's input and output GPIOs as our own so the board
230 * code can wire them up. (We do this in realize because the
231 * NVIC doesn't create the input GPIO array until realize.)
233 qdev_pass_gpios(DEVICE(&s
->nvic
), dev
, NULL
);
234 qdev_pass_gpios(DEVICE(&s
->nvic
), dev
, "SYSRESETREQ");
235 qdev_pass_gpios(DEVICE(&s
->nvic
), dev
, "NMI");
237 /* Wire the NVIC up to the CPU */
238 sbd
= SYS_BUS_DEVICE(&s
->nvic
);
239 sysbus_connect_irq(sbd
, 0,
240 qdev_get_gpio_in(DEVICE(s
->cpu
), ARM_CPU_IRQ
));
242 memory_region_add_subregion(&s
->container
, 0xe000e000,
243 sysbus_mmio_get_region(sbd
, 0));
245 for (i
= 0; i
< ARRAY_SIZE(s
->bitband
); i
++) {
246 if (s
->enable_bitband
) {
247 Object
*obj
= OBJECT(&s
->bitband
[i
]);
248 SysBusDevice
*sbd
= SYS_BUS_DEVICE(&s
->bitband
[i
]);
250 object_property_set_int(obj
, bitband_input_addr
[i
], "base", &err
);
252 error_propagate(errp
, err
);
255 object_property_set_link(obj
, OBJECT(s
->board_memory
),
256 "source-memory", &error_abort
);
257 sysbus_realize(SYS_BUS_DEVICE(obj
), &err
);
259 error_propagate(errp
, err
);
263 memory_region_add_subregion(&s
->container
, bitband_output_addr
[i
],
264 sysbus_mmio_get_region(sbd
, 0));
266 object_unparent(OBJECT(&s
->bitband
[i
]));
271 static Property armv7m_properties
[] = {
272 DEFINE_PROP_STRING("cpu-type", ARMv7MState
, cpu_type
),
273 DEFINE_PROP_LINK("memory", ARMv7MState
, board_memory
, TYPE_MEMORY_REGION
,
275 DEFINE_PROP_LINK("idau", ARMv7MState
, idau
, TYPE_IDAU_INTERFACE
, Object
*),
276 DEFINE_PROP_UINT32("init-svtor", ARMv7MState
, init_svtor
, 0),
277 DEFINE_PROP_BOOL("enable-bitband", ARMv7MState
, enable_bitband
, false),
278 DEFINE_PROP_BOOL("start-powered-off", ARMv7MState
, start_powered_off
,
280 DEFINE_PROP_BOOL("vfp", ARMv7MState
, vfp
, true),
281 DEFINE_PROP_BOOL("dsp", ARMv7MState
, dsp
, true),
282 DEFINE_PROP_END_OF_LIST(),
285 static void armv7m_class_init(ObjectClass
*klass
, void *data
)
287 DeviceClass
*dc
= DEVICE_CLASS(klass
);
289 dc
->realize
= armv7m_realize
;
290 device_class_set_props(dc
, armv7m_properties
);
293 static const TypeInfo armv7m_info
= {
295 .parent
= TYPE_SYS_BUS_DEVICE
,
296 .instance_size
= sizeof(ARMv7MState
),
297 .instance_init
= armv7m_instance_init
,
298 .class_init
= armv7m_class_init
,
301 static void armv7m_reset(void *opaque
)
303 ARMCPU
*cpu
= opaque
;
308 void armv7m_load_kernel(ARMCPU
*cpu
, const char *kernel_filename
, int mem_size
)
316 CPUState
*cs
= CPU(cpu
);
318 #ifdef TARGET_WORDS_BIGENDIAN
324 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
329 as
= cpu_get_address_space(cs
, asidx
);
331 if (kernel_filename
) {
332 image_size
= load_elf_as(kernel_filename
, NULL
, NULL
, NULL
,
333 &entry
, &lowaddr
, NULL
,
334 NULL
, big_endian
, EM_ARM
, 1, 0, as
);
335 if (image_size
< 0) {
336 image_size
= load_image_targphys_as(kernel_filename
, 0,
340 if (image_size
< 0) {
341 error_report("Could not load kernel '%s'", kernel_filename
);
346 /* CPU objects (unlike devices) are not automatically reset on system
347 * reset, so we must always register a handler to do so. Unlike
348 * A-profile CPUs, we don't need to do anything special in the
349 * handler to arrange that it starts correctly.
350 * This is arguably the wrong place to do this, but it matches the
351 * way A-profile does it. Note that this means that every M profile
352 * board must call this function!
354 qemu_register_reset(armv7m_reset
, cpu
);
357 static Property bitband_properties
[] = {
358 DEFINE_PROP_UINT32("base", BitBandState
, base
, 0),
359 DEFINE_PROP_LINK("source-memory", BitBandState
, source_memory
,
360 TYPE_MEMORY_REGION
, MemoryRegion
*),
361 DEFINE_PROP_END_OF_LIST(),
364 static void bitband_class_init(ObjectClass
*klass
, void *data
)
366 DeviceClass
*dc
= DEVICE_CLASS(klass
);
368 dc
->realize
= bitband_realize
;
369 device_class_set_props(dc
, bitband_properties
);
372 static const TypeInfo bitband_info
= {
373 .name
= TYPE_BITBAND
,
374 .parent
= TYPE_SYS_BUS_DEVICE
,
375 .instance_size
= sizeof(BitBandState
),
376 .instance_init
= bitband_init
,
377 .class_init
= bitband_class_init
,
380 static void armv7m_register_types(void)
382 type_register_static(&bitband_info
);
383 type_register_static(&armv7m_info
);
386 type_init(armv7m_register_types
)