?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
target-mips: add mips32r6-generic CPU definition
[qemu/ar7.git] / target-tricore / translate.c
blob7dc7a325b410501f6a6dd66cbf48f30da054c8ea
1 /*
2 * TriCore emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "exec/cpu_ldst.h"
25
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
28
29 #include "tricore-opcodes.h"
30
31 /*
32 * TCG registers
33 */
34 static TCGv cpu_PC;
35 static TCGv cpu_PCXI;
36 static TCGv cpu_PSW;
37 static TCGv cpu_ICR;
38 /* GPR registers */
39 static TCGv cpu_gpr_a[16];
40 static TCGv cpu_gpr_d[16];
41 /* PSW Flag cache */
42 static TCGv cpu_PSW_C;
43 static TCGv cpu_PSW_V;
44 static TCGv cpu_PSW_SV;
45 static TCGv cpu_PSW_AV;
46 static TCGv cpu_PSW_SAV;
47 /* CPU env */
48 static TCGv_ptr cpu_env;
49
50 #include "exec/gen-icount.h"
51
52 static const char *regnames_a[] = {
53 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
54 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" ,
55 "a12" , "a13" , "a14" , "a15",
56 };
57
58 static const char *regnames_d[] = {
59 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" ,
60 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" ,
61 "d12" , "d13" , "d14" , "d15",
62 };
63
64 typedef struct DisasContext {
65 struct TranslationBlock *tb;
66 target_ulong pc, saved_pc, next_pc;
67 uint32_t opcode;
68 int singlestep_enabled;
69 /* Routine used to access memory */
70 int mem_idx;
71 uint32_t hflags, saved_hflags;
72 int bstate;
73 } DisasContext;
74
75 enum {
76
77 BS_NONE = 0,
78 BS_STOP = 1,
79 BS_BRANCH = 2,
80 BS_EXCP = 3,
81 };
82
83 enum {
84 MODE_LL = 0,
85 MODE_LU = 1,
86 MODE_UL = 2,
87 MODE_UU = 3,
88 };
89
90 void tricore_cpu_dump_state(CPUState *cs, FILE *f,
91 fprintf_function cpu_fprintf, int flags)
92 {
93 TriCoreCPU *cpu = TRICORE_CPU(cs);
94 CPUTriCoreState *env = &cpu->env;
95 uint32_t psw;
96 int i;
97
98 psw = psw_read(env);
99
100 cpu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC);
101 cpu_fprintf(f, " PSW: " TARGET_FMT_lx, psw);
102 cpu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR);
103 cpu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI);
104 cpu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX);
105 cpu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX);
106
107 for (i = 0; i < 16; ++i) {
108 if ((i & 3) == 0) {
109 cpu_fprintf(f, "\nGPR A%02d:", i);
110 }
111 cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]);
112 }
113 for (i = 0; i < 16; ++i) {
114 if ((i & 3) == 0) {
115 cpu_fprintf(f, "\nGPR D%02d:", i);
116 }
117 cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]);
118 }
119 cpu_fprintf(f, "\n");
120 }
121
122 /*
123 * Functions to generate micro-ops
124 */
125
126 /* Makros for generating helpers */
127
128 #define gen_helper_1arg(name, arg) do { \
129 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
130 gen_helper_##name(cpu_env, helper_tmp); \
131 tcg_temp_free_i32(helper_tmp); \
132 } while (0)
133
134 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \
135 TCGv arg00 = tcg_temp_new(); \
136 TCGv arg01 = tcg_temp_new(); \
137 TCGv arg11 = tcg_temp_new(); \
138 tcg_gen_sari_tl(arg00, arg0, 16); \
139 tcg_gen_ext16s_tl(arg01, arg0); \
140 tcg_gen_ext16s_tl(arg11, arg1); \
141 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
142 tcg_temp_free(arg00); \
143 tcg_temp_free(arg01); \
144 tcg_temp_free(arg11); \
145 } while (0)
146
147 #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \
148 TCGv arg00 = tcg_temp_new(); \
149 TCGv arg01 = tcg_temp_new(); \
150 TCGv arg10 = tcg_temp_new(); \
151 TCGv arg11 = tcg_temp_new(); \
152 tcg_gen_sari_tl(arg00, arg0, 16); \
153 tcg_gen_ext16s_tl(arg01, arg0); \
154 tcg_gen_sari_tl(arg11, arg1, 16); \
155 tcg_gen_ext16s_tl(arg10, arg1); \
156 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
157 tcg_temp_free(arg00); \
158 tcg_temp_free(arg01); \
159 tcg_temp_free(arg10); \
160 tcg_temp_free(arg11); \
161 } while (0)
162
163 #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \
164 TCGv arg00 = tcg_temp_new(); \
165 TCGv arg01 = tcg_temp_new(); \
166 TCGv arg10 = tcg_temp_new(); \
167 TCGv arg11 = tcg_temp_new(); \
168 tcg_gen_sari_tl(arg00, arg0, 16); \
169 tcg_gen_ext16s_tl(arg01, arg0); \
170 tcg_gen_sari_tl(arg10, arg1, 16); \
171 tcg_gen_ext16s_tl(arg11, arg1); \
172 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
173 tcg_temp_free(arg00); \
174 tcg_temp_free(arg01); \
175 tcg_temp_free(arg10); \
176 tcg_temp_free(arg11); \
177 } while (0)
178
179 #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \
180 TCGv arg00 = tcg_temp_new(); \
181 TCGv arg01 = tcg_temp_new(); \
182 TCGv arg11 = tcg_temp_new(); \
183 tcg_gen_sari_tl(arg01, arg0, 16); \
184 tcg_gen_ext16s_tl(arg00, arg0); \
185 tcg_gen_sari_tl(arg11, arg1, 16); \
186 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
187 tcg_temp_free(arg00); \
188 tcg_temp_free(arg01); \
189 tcg_temp_free(arg11); \
190 } while (0)
191
192 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \
193 TCGv_i64 ret = tcg_temp_new_i64(); \
194 TCGv_i64 arg1 = tcg_temp_new_i64(); \
195 \
196 tcg_gen_concat_i32_i64(arg1, al1, ah1); \
197 gen_helper_##name(ret, arg1, arg2); \
198 tcg_gen_extr_i64_i32(rl, rh, ret); \
199 \
200 tcg_temp_free_i64(ret); \
201 tcg_temp_free_i64(arg1); \
202 } while (0)
203
204 #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \
205 TCGv_i64 ret = tcg_temp_new_i64(); \
206 \
207 gen_helper_##name(ret, cpu_env, arg1, arg2); \
208 tcg_gen_extr_i64_i32(rl, rh, ret); \
209 \
210 tcg_temp_free_i64(ret); \
211 } while (0)
212
213 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF))
214 #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \
215 ((offset & 0x0fffff) << 1))
216
217 /* Functions for load/save to/from memory */
218
219 static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
220 int16_t con, TCGMemOp mop)
221 {
222 TCGv temp = tcg_temp_new();
223 tcg_gen_addi_tl(temp, r2, con);
224 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
225 tcg_temp_free(temp);
226 }
227
228 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
229 int16_t con, TCGMemOp mop)
230 {
231 TCGv temp = tcg_temp_new();
232 tcg_gen_addi_tl(temp, r2, con);
233 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
234 tcg_temp_free(temp);
235 }
236
237 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
238 {
239 TCGv_i64 temp = tcg_temp_new_i64();
240
241 tcg_gen_concat_i32_i64(temp, rl, rh);
242 tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEQ);
243
244 tcg_temp_free_i64(temp);
245 }
246
247 static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
248 DisasContext *ctx)
249 {
250 TCGv temp = tcg_temp_new();
251 tcg_gen_addi_tl(temp, base, con);
252 gen_st_2regs_64(rh, rl, temp, ctx);
253 tcg_temp_free(temp);
254 }
255
256 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
257 {
258 TCGv_i64 temp = tcg_temp_new_i64();
259
260 tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEQ);
261 /* write back to two 32 bit regs */
262 tcg_gen_extr_i64_i32(rl, rh, temp);
263
264 tcg_temp_free_i64(temp);
265 }
266
267 static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
268 DisasContext *ctx)
269 {
270 TCGv temp = tcg_temp_new();
271 tcg_gen_addi_tl(temp, base, con);
272 gen_ld_2regs_64(rh, rl, temp, ctx);
273 tcg_temp_free(temp);
274 }
275
276 static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
277 TCGMemOp mop)
278 {
279 TCGv temp = tcg_temp_new();
280 tcg_gen_addi_tl(temp, r2, off);
281 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
282 tcg_gen_mov_tl(r2, temp);
283 tcg_temp_free(temp);
284 }
285
286 static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
287 TCGMemOp mop)
288 {
289 TCGv temp = tcg_temp_new();
290 tcg_gen_addi_tl(temp, r2, off);
291 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
292 tcg_gen_mov_tl(r2, temp);
293 tcg_temp_free(temp);
294 }
295
296 /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */
297 static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea)
298 {
299 TCGv temp = tcg_temp_new();
300 TCGv temp2 = tcg_temp_new();
301
302 /* temp = (M(EA, word) */
303 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
304 /* temp = temp & ~E[a][63:32]) */
305 tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]);
306 /* temp2 = (E[a][31:0] & E[a][63:32]); */
307 tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]);
308 /* temp = temp | temp2; */
309 tcg_gen_or_tl(temp, temp, temp2);
310 /* M(EA, word) = temp; */
311 tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL);
312
313 tcg_temp_free(temp);
314 tcg_temp_free(temp2);
315 }
316
317 /* tmp = M(EA, word);
318 M(EA, word) = D[a];
319 D[a] = tmp[31:0];*/
320 static void gen_swap(DisasContext *ctx, int reg, TCGv ea)
321 {
322 TCGv temp = tcg_temp_new();
323
324 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
325 tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL);
326 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
327
328 tcg_temp_free(temp);
329 }
330
331 static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea)
332 {
333 TCGv temp = tcg_temp_new();
334 TCGv temp2 = tcg_temp_new();
335 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
336 tcg_gen_movcond_tl(TCG_COND_EQ, temp2, cpu_gpr_d[reg+1], temp,
337 cpu_gpr_d[reg], temp);
338 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
339 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
340
341 tcg_temp_free(temp);
342 tcg_temp_free(temp2);
343 }
344
345 static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea)
346 {
347 TCGv temp = tcg_temp_new();
348 TCGv temp2 = tcg_temp_new();
349 TCGv temp3 = tcg_temp_new();
350
351 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
352 tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]);
353 tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]);
354 tcg_gen_or_tl(temp2, temp2, temp3);
355 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
356 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
357
358 tcg_temp_free(temp);
359 tcg_temp_free(temp2);
360 tcg_temp_free(temp3);
361 }
362
363
364 /* We generate loads and store to core special function register (csfr) through
365 the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3
366 makros R, A and E, which allow read-only, all and endinit protected access.
367 These makros also specify in which ISA version the csfr was introduced. */
368 #define R(ADDRESS, REG, FEATURE) \
369 case ADDRESS: \
370 if (tricore_feature(env, FEATURE)) { \
371 tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \
372 } \
373 break;
374 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
375 #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
376 static inline void gen_mfcr(CPUTriCoreState *env, TCGv ret, int32_t offset)
377 {
378 /* since we're caching PSW make this a special case */
379 if (offset == 0xfe04) {
380 gen_helper_psw_read(ret, cpu_env);
381 } else {
382 switch (offset) {
383 #include "csfr.def"
384 }
385 }
386 }
387 #undef R
388 #undef A
389 #undef E
390
391 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg,
392 since no execption occurs */
393 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \
394 case ADDRESS: \
395 if (tricore_feature(env, FEATURE)) { \
396 tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \
397 } \
398 break;
399 /* Endinit protected registers
400 TODO: Since the endinit bit is in a register of a not yet implemented
401 watchdog device, we handle endinit protected registers like
402 all-access registers for now. */
403 #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE)
404 static inline void gen_mtcr(CPUTriCoreState *env, DisasContext *ctx, TCGv r1,
405 int32_t offset)
406 {
407 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
408 /* since we're caching PSW make this a special case */
409 if (offset == 0xfe04) {
410 gen_helper_psw_write(cpu_env, r1);
411 } else {
412 switch (offset) {
413 #include "csfr.def"
414 }
415 }
416 } else {
417 /* generate privilege trap */
418 }
419 }
420
421 /* Functions for arithmetic instructions */
422
423 static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
424 {
425 TCGv t0 = tcg_temp_new_i32();
426 TCGv result = tcg_temp_new_i32();
427 /* Addition and set V/SV bits */
428 tcg_gen_add_tl(result, r1, r2);
429 /* calc V bit */
430 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
431 tcg_gen_xor_tl(t0, r1, r2);
432 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
433 /* Calc SV bit */
434 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
435 /* Calc AV/SAV bits */
436 tcg_gen_add_tl(cpu_PSW_AV, result, result);
437 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
438 /* calc SAV */
439 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
440 /* write back result */
441 tcg_gen_mov_tl(ret, result);
442
443 tcg_temp_free(result);
444 tcg_temp_free(t0);
445 }
446
447 static inline void
448 gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
449 {
450 TCGv temp = tcg_temp_new();
451 TCGv_i64 t0 = tcg_temp_new_i64();
452 TCGv_i64 t1 = tcg_temp_new_i64();
453 TCGv_i64 result = tcg_temp_new_i64();
454
455 tcg_gen_add_i64(result, r1, r2);
456 /* calc v bit */
457 tcg_gen_xor_i64(t1, result, r1);
458 tcg_gen_xor_i64(t0, r1, r2);
459 tcg_gen_andc_i64(t1, t1, t0);
460 tcg_gen_trunc_shr_i64_i32(cpu_PSW_V, t1, 32);
461 /* calc SV bit */
462 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
463 /* calc AV/SAV bits */
464 tcg_gen_trunc_shr_i64_i32(temp, result, 32);
465 tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
466 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
467 /* calc SAV */
468 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
469 /* write back result */
470 tcg_gen_mov_i64(ret, result);
471
472 tcg_temp_free(temp);
473 tcg_temp_free_i64(result);
474 tcg_temp_free_i64(t0);
475 tcg_temp_free_i64(t1);
476 }
477
478 static inline void
479 gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
480 TCGv r3, void(*op1)(TCGv, TCGv, TCGv),
481 void(*op2)(TCGv, TCGv, TCGv))
482 {
483 TCGv temp = tcg_temp_new();
484 TCGv temp2 = tcg_temp_new();
485 TCGv temp3 = tcg_temp_new();
486 TCGv temp4 = tcg_temp_new();
487
488 (*op1)(temp, r1_low, r2);
489 /* calc V0 bit */
490 tcg_gen_xor_tl(temp2, temp, r1_low);
491 tcg_gen_xor_tl(temp3, r1_low, r2);
492 if (op1 == tcg_gen_add_tl) {
493 tcg_gen_andc_tl(temp2, temp2, temp3);
494 } else {
495 tcg_gen_and_tl(temp2, temp2, temp3);
496 }
497
498 (*op2)(temp3, r1_high, r3);
499 /* calc V1 bit */
500 tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high);
501 tcg_gen_xor_tl(temp4, r1_high, r3);
502 if (op2 == tcg_gen_add_tl) {
503 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4);
504 } else {
505 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4);
506 }
507 /* combine V0/V1 bits */
508 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2);
509 /* calc sv bit */
510 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
511 /* write result */
512 tcg_gen_mov_tl(ret_low, temp);
513 tcg_gen_mov_tl(ret_high, temp3);
514 /* calc AV bit */
515 tcg_gen_add_tl(temp, ret_low, ret_low);
516 tcg_gen_xor_tl(temp, temp, ret_low);
517 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
518 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high);
519 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
520 /* calc SAV bit */
521 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
522
523 tcg_temp_free(temp);
524 tcg_temp_free(temp2);
525 tcg_temp_free(temp3);
526 tcg_temp_free(temp4);
527 }
528
529 /* ret = r2 + (r1 * r3); */
530 static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
531 {
532 TCGv_i64 t1 = tcg_temp_new_i64();
533 TCGv_i64 t2 = tcg_temp_new_i64();
534 TCGv_i64 t3 = tcg_temp_new_i64();
535
536 tcg_gen_ext_i32_i64(t1, r1);
537 tcg_gen_ext_i32_i64(t2, r2);
538 tcg_gen_ext_i32_i64(t3, r3);
539
540 tcg_gen_mul_i64(t1, t1, t3);
541 tcg_gen_add_i64(t1, t2, t1);
542
543 tcg_gen_trunc_i64_i32(ret, t1);
544 /* calc V
545 t1 > 0x7fffffff */
546 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
547 /* t1 < -0x80000000 */
548 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
549 tcg_gen_or_i64(t2, t2, t3);
550 tcg_gen_trunc_i64_i32(cpu_PSW_V, t2);
551 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
552 /* Calc SV bit */
553 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
554 /* Calc AV/SAV bits */
555 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
556 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
557 /* calc SAV */
558 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
559
560 tcg_temp_free_i64(t1);
561 tcg_temp_free_i64(t2);
562 tcg_temp_free_i64(t3);
563 }
564
565 static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
566 {
567 TCGv temp = tcg_const_i32(con);
568 gen_madd32_d(ret, r1, r2, temp);
569 tcg_temp_free(temp);
570 }
571
572 static inline void
573 gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
574 TCGv r3)
575 {
576 TCGv t1 = tcg_temp_new();
577 TCGv t2 = tcg_temp_new();
578 TCGv t3 = tcg_temp_new();
579 TCGv t4 = tcg_temp_new();
580
581 tcg_gen_muls2_tl(t1, t2, r1, r3);
582 /* only the add can overflow */
583 tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2);
584 /* calc V bit */
585 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
586 tcg_gen_xor_tl(t1, r2_high, t2);
587 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1);
588 /* Calc SV bit */
589 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
590 /* Calc AV/SAV bits */
591 tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
592 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
593 /* calc SAV */
594 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
595 /* write back the result */
596 tcg_gen_mov_tl(ret_low, t3);
597 tcg_gen_mov_tl(ret_high, t4);
598
599 tcg_temp_free(t1);
600 tcg_temp_free(t2);
601 tcg_temp_free(t3);
602 tcg_temp_free(t4);
603 }
604
605 static inline void
606 gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
607 TCGv r3)
608 {
609 TCGv_i64 t1 = tcg_temp_new_i64();
610 TCGv_i64 t2 = tcg_temp_new_i64();
611 TCGv_i64 t3 = tcg_temp_new_i64();
612
613 tcg_gen_extu_i32_i64(t1, r1);
614 tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
615 tcg_gen_extu_i32_i64(t3, r3);
616
617 tcg_gen_mul_i64(t1, t1, t3);
618 tcg_gen_add_i64(t2, t2, t1);
619 /* write back result */
620 tcg_gen_extr_i64_i32(ret_low, ret_high, t2);
621 /* only the add overflows, if t2 < t1
622 calc V bit */
623 tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1);
624 tcg_gen_trunc_i64_i32(cpu_PSW_V, t2);
625 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
626 /* Calc SV bit */
627 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
628 /* Calc AV/SAV bits */
629 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
630 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
631 /* calc SAV */
632 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
633
634 tcg_temp_free_i64(t1);
635 tcg_temp_free_i64(t2);
636 tcg_temp_free_i64(t3);
637 }
638
639 static inline void
640 gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
641 int32_t con)
642 {
643 TCGv temp = tcg_const_i32(con);
644 gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
645 tcg_temp_free(temp);
646 }
647
648 static inline void
649 gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
650 int32_t con)
651 {
652 TCGv temp = tcg_const_i32(con);
653 gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
654 tcg_temp_free(temp);
655 }
656
657 static inline void
658 gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
659 TCGv r3, uint32_t n, uint32_t mode)
660 {
661 TCGv temp = tcg_const_i32(n);
662 TCGv temp2 = tcg_temp_new();
663 TCGv_i64 temp64 = tcg_temp_new_i64();
664 switch (mode) {
665 case MODE_LL:
666 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
667 break;
668 case MODE_LU:
669 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
670 break;
671 case MODE_UL:
672 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
673 break;
674 case MODE_UU:
675 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
676 break;
677 }
678 tcg_gen_extr_i64_i32(temp, temp2, temp64);
679 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
680 tcg_gen_add_tl, tcg_gen_add_tl);
681 tcg_temp_free(temp);
682 tcg_temp_free(temp2);
683 tcg_temp_free_i64(temp64);
684 }
685
686 static inline void
687 gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
688 TCGv r3, uint32_t n, uint32_t mode)
689 {
690 TCGv temp = tcg_const_i32(n);
691 TCGv temp2 = tcg_temp_new();
692 TCGv_i64 temp64 = tcg_temp_new_i64();
693 switch (mode) {
694 case MODE_LL:
695 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
696 break;
697 case MODE_LU:
698 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
699 break;
700 case MODE_UL:
701 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
702 break;
703 case MODE_UU:
704 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
705 break;
706 }
707 tcg_gen_extr_i64_i32(temp, temp2, temp64);
708 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
709 tcg_gen_sub_tl, tcg_gen_add_tl);
710 tcg_temp_free(temp);
711 tcg_temp_free(temp2);
712 tcg_temp_free_i64(temp64);
713 }
714
715 static inline void
716 gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
717 TCGv r3, uint32_t n, uint32_t mode)
718 {
719 TCGv temp = tcg_const_i32(n);
720 TCGv_i64 temp64 = tcg_temp_new_i64();
721 TCGv_i64 temp64_2 = tcg_temp_new_i64();
722 TCGv_i64 temp64_3 = tcg_temp_new_i64();
723 switch (mode) {
724 case MODE_LL:
725 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
726 break;
727 case MODE_LU:
728 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
729 break;
730 case MODE_UL:
731 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
732 break;
733 case MODE_UU:
734 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
735 break;
736 }
737 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
738 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
739 tcg_gen_ext32s_i64(temp64, temp64); /* low */
740 tcg_gen_sub_i64(temp64, temp64_2, temp64);
741 tcg_gen_shli_i64(temp64, temp64, 16);
742
743 gen_add64_d(temp64_2, temp64_3, temp64);
744 /* write back result */
745 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
746
747 tcg_temp_free(temp);
748 tcg_temp_free_i64(temp64);
749 tcg_temp_free_i64(temp64_2);
750 tcg_temp_free_i64(temp64_3);
751 }
752
753 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2);
754
755 static inline void
756 gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
757 TCGv r3, uint32_t n, uint32_t mode)
758 {
759 TCGv temp = tcg_const_i32(n);
760 TCGv temp2 = tcg_temp_new();
761 TCGv temp3 = tcg_temp_new();
762 TCGv_i64 temp64 = tcg_temp_new_i64();
763
764 switch (mode) {
765 case MODE_LL:
766 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
767 break;
768 case MODE_LU:
769 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
770 break;
771 case MODE_UL:
772 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
773 break;
774 case MODE_UU:
775 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
776 break;
777 }
778 tcg_gen_extr_i64_i32(temp, temp2, temp64);
779 gen_adds(ret_low, r1_low, temp);
780 tcg_gen_mov_tl(temp, cpu_PSW_V);
781 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
782 gen_adds(ret_high, r1_high, temp2);
783 /* combine v bits */
784 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
785 /* combine av bits */
786 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
787
788 tcg_temp_free(temp);
789 tcg_temp_free(temp2);
790 tcg_temp_free(temp3);
791 tcg_temp_free_i64(temp64);
792
793 }
794
795 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2);
796
797 static inline void
798 gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
799 TCGv r3, uint32_t n, uint32_t mode)
800 {
801 TCGv temp = tcg_const_i32(n);
802 TCGv temp2 = tcg_temp_new();
803 TCGv temp3 = tcg_temp_new();
804 TCGv_i64 temp64 = tcg_temp_new_i64();
805
806 switch (mode) {
807 case MODE_LL:
808 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
809 break;
810 case MODE_LU:
811 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
812 break;
813 case MODE_UL:
814 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
815 break;
816 case MODE_UU:
817 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
818 break;
819 }
820 tcg_gen_extr_i64_i32(temp, temp2, temp64);
821 gen_subs(ret_low, r1_low, temp);
822 tcg_gen_mov_tl(temp, cpu_PSW_V);
823 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
824 gen_adds(ret_high, r1_high, temp2);
825 /* combine v bits */
826 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
827 /* combine av bits */
828 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
829
830 tcg_temp_free(temp);
831 tcg_temp_free(temp2);
832 tcg_temp_free(temp3);
833 tcg_temp_free_i64(temp64);
834
835 }
836
837 static inline void
838 gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
839 TCGv r3, uint32_t n, uint32_t mode)
840 {
841 TCGv temp = tcg_const_i32(n);
842 TCGv_i64 temp64 = tcg_temp_new_i64();
843 TCGv_i64 temp64_2 = tcg_temp_new_i64();
844
845 switch (mode) {
846 case MODE_LL:
847 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
848 break;
849 case MODE_LU:
850 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
851 break;
852 case MODE_UL:
853 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
854 break;
855 case MODE_UU:
856 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
857 break;
858 }
859 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
860 tcg_gen_ext32s_i64(temp64, temp64); /* low */
861 tcg_gen_sub_i64(temp64, temp64_2, temp64);
862 tcg_gen_shli_i64(temp64, temp64, 16);
863 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
864
865 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
866 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
867
868 tcg_temp_free(temp);
869 tcg_temp_free_i64(temp64);
870 tcg_temp_free_i64(temp64_2);
871 }
872
873
874 static inline void
875 gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
876 TCGv r3, uint32_t n, uint32_t mode)
877 {
878 TCGv temp = tcg_const_i32(n);
879 TCGv_i64 temp64 = tcg_temp_new_i64();
880 TCGv_i64 temp64_2 = tcg_temp_new_i64();
881 TCGv_i64 temp64_3 = tcg_temp_new_i64();
882 switch (mode) {
883 case MODE_LL:
884 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
885 break;
886 case MODE_LU:
887 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
888 break;
889 case MODE_UL:
890 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
891 break;
892 case MODE_UU:
893 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
894 break;
895 }
896 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
897 gen_add64_d(temp64_3, temp64_2, temp64);
898 /* write back result */
899 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
900
901 tcg_temp_free(temp);
902 tcg_temp_free_i64(temp64);
903 tcg_temp_free_i64(temp64_2);
904 tcg_temp_free_i64(temp64_3);
905 }
906
907 static inline void
908 gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
909 TCGv r3, uint32_t n, uint32_t mode)
910 {
911 TCGv temp = tcg_const_i32(n);
912 TCGv_i64 temp64 = tcg_temp_new_i64();
913 TCGv_i64 temp64_2 = tcg_temp_new_i64();
914 switch (mode) {
915 case MODE_LL:
916 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
917 break;
918 case MODE_LU:
919 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
920 break;
921 case MODE_UL:
922 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
923 break;
924 case MODE_UU:
925 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
926 break;
927 }
928 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
929 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
930 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
931
932 tcg_temp_free(temp);
933 tcg_temp_free_i64(temp64);
934 tcg_temp_free_i64(temp64_2);
935 }
936
937 static inline void
938 gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
939 uint32_t mode)
940 {
941 TCGv temp = tcg_const_i32(n);
942 TCGv_i64 temp64 = tcg_temp_new_i64();
943 switch (mode) {
944 case MODE_LL:
945 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
946 break;
947 case MODE_LU:
948 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
949 break;
950 case MODE_UL:
951 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
952 break;
953 case MODE_UU:
954 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
955 break;
956 }
957 gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high);
958
959 tcg_temp_free(temp);
960 tcg_temp_free_i64(temp64);
961 }
962
963 static inline void
964 gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
965 {
966 TCGv temp = tcg_temp_new();
967 TCGv temp2 = tcg_temp_new();
968
969 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
970 tcg_gen_shli_tl(temp, r1, 16);
971 gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode);
972
973 tcg_temp_free(temp);
974 tcg_temp_free(temp2);
975 }
976
977 static inline void
978 gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
979 {
980 TCGv temp = tcg_const_i32(n);
981 TCGv temp2 = tcg_temp_new();
982 TCGv_i64 temp64 = tcg_temp_new_i64();
983 switch (mode) {
984 case MODE_LL:
985 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
986 break;
987 case MODE_LU:
988 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
989 break;
990 case MODE_UL:
991 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
992 break;
993 case MODE_UU:
994 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
995 break;
996 }
997 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
998 tcg_gen_shli_tl(temp, r1, 16);
999 gen_helper_addsur_h(ret, cpu_env, temp64, temp, temp2);
1000
1001 tcg_temp_free(temp);
1002 tcg_temp_free(temp2);
1003 tcg_temp_free_i64(temp64);
1004 }
1005
1006
1007 static inline void
1008 gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
1009 uint32_t n, uint32_t mode)
1010 {
1011 TCGv temp = tcg_const_i32(n);
1012 TCGv_i64 temp64 = tcg_temp_new_i64();
1013 switch (mode) {
1014 case MODE_LL:
1015 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1016 break;
1017 case MODE_LU:
1018 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1019 break;
1020 case MODE_UL:
1021 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1022 break;
1023 case MODE_UU:
1024 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1025 break;
1026 }
1027 gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
1028
1029 tcg_temp_free(temp);
1030 tcg_temp_free_i64(temp64);
1031 }
1032
1033 static inline void
1034 gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1035 {
1036 TCGv temp = tcg_temp_new();
1037 TCGv temp2 = tcg_temp_new();
1038
1039 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1040 tcg_gen_shli_tl(temp, r1, 16);
1041 gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode);
1042
1043 tcg_temp_free(temp);
1044 tcg_temp_free(temp2);
1045 }
1046
1047 static inline void
1048 gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1049 {
1050 TCGv temp = tcg_const_i32(n);
1051 TCGv temp2 = tcg_temp_new();
1052 TCGv_i64 temp64 = tcg_temp_new_i64();
1053 switch (mode) {
1054 case MODE_LL:
1055 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1056 break;
1057 case MODE_LU:
1058 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1059 break;
1060 case MODE_UL:
1061 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1062 break;
1063 case MODE_UU:
1064 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1065 break;
1066 }
1067 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1068 tcg_gen_shli_tl(temp, r1, 16);
1069 gen_helper_addsur_h_ssov(ret, cpu_env, temp64, temp, temp2);
1070
1071 tcg_temp_free(temp);
1072 tcg_temp_free(temp2);
1073 tcg_temp_free_i64(temp64);
1074 }
1075
1076 static inline void
1077 gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1078 {
1079 TCGv temp = tcg_const_i32(n);
1080 gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, temp);
1081 tcg_temp_free(temp);
1082 }
1083
1084 static inline void
1085 gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1086 {
1087 TCGv temp = tcg_const_i32(n);
1088 gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, temp);
1089 tcg_temp_free(temp);
1090 }
1091
1092 static inline void
1093 gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1094 uint32_t up_shift, CPUTriCoreState *env)
1095 {
1096 TCGv temp = tcg_temp_new();
1097 TCGv temp2 = tcg_temp_new();
1098 TCGv temp3 = tcg_temp_new();
1099 TCGv_i64 t1 = tcg_temp_new_i64();
1100 TCGv_i64 t2 = tcg_temp_new_i64();
1101 TCGv_i64 t3 = tcg_temp_new_i64();
1102
1103 tcg_gen_ext_i32_i64(t2, arg2);
1104 tcg_gen_ext_i32_i64(t3, arg3);
1105
1106 tcg_gen_mul_i64(t2, t2, t3);
1107 tcg_gen_shli_i64(t2, t2, n);
1108
1109 tcg_gen_ext_i32_i64(t1, arg1);
1110 tcg_gen_sari_i64(t2, t2, up_shift);
1111
1112 tcg_gen_add_i64(t3, t1, t2);
1113 tcg_gen_trunc_i64_i32(temp3, t3);
1114 /* calc v bit */
1115 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
1116 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
1117 tcg_gen_or_i64(t1, t1, t2);
1118 tcg_gen_trunc_i64_i32(cpu_PSW_V, t1);
1119 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1120 /* We produce an overflow on the host if the mul before was
1121 (0x80000000 * 0x80000000) << 1). If this is the
1122 case, we negate the ovf. */
1123 if (n == 1) {
1124 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1125 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1126 tcg_gen_and_tl(temp, temp, temp2);
1127 tcg_gen_shli_tl(temp, temp, 31);
1128 /* negate v bit, if special condition */
1129 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1130 }
1131 /* Calc SV bit */
1132 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1133 /* Calc AV/SAV bits */
1134 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
1135 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
1136 /* calc SAV */
1137 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1138 /* write back result */
1139 tcg_gen_mov_tl(ret, temp3);
1140
1141 tcg_temp_free(temp);
1142 tcg_temp_free(temp2);
1143 tcg_temp_free(temp3);
1144 tcg_temp_free_i64(t1);
1145 tcg_temp_free_i64(t2);
1146 tcg_temp_free_i64(t3);
1147 }
1148
1149 static inline void
1150 gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1151 {
1152 TCGv temp = tcg_temp_new();
1153 TCGv temp2 = tcg_temp_new();
1154 if (n == 0) {
1155 tcg_gen_mul_tl(temp, arg2, arg3);
1156 } else { /* n is expected to be 1 */
1157 tcg_gen_mul_tl(temp, arg2, arg3);
1158 tcg_gen_shli_tl(temp, temp, 1);
1159 /* catch special case r1 = r2 = 0x8000 */
1160 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1161 tcg_gen_sub_tl(temp, temp, temp2);
1162 }
1163 gen_add_d(ret, arg1, temp);
1164
1165 tcg_temp_free(temp);
1166 tcg_temp_free(temp2);
1167 }
1168
1169 static inline void
1170 gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1171 {
1172 TCGv temp = tcg_temp_new();
1173 TCGv temp2 = tcg_temp_new();
1174 if (n == 0) {
1175 tcg_gen_mul_tl(temp, arg2, arg3);
1176 } else { /* n is expected to be 1 */
1177 tcg_gen_mul_tl(temp, arg2, arg3);
1178 tcg_gen_shli_tl(temp, temp, 1);
1179 /* catch special case r1 = r2 = 0x8000 */
1180 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1181 tcg_gen_sub_tl(temp, temp, temp2);
1182 }
1183 gen_adds(ret, arg1, temp);
1184
1185 tcg_temp_free(temp);
1186 tcg_temp_free(temp2);
1187 }
1188
1189 static inline void
1190 gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1191 TCGv arg3, uint32_t n)
1192 {
1193 TCGv temp = tcg_temp_new();
1194 TCGv temp2 = tcg_temp_new();
1195 TCGv_i64 t1 = tcg_temp_new_i64();
1196 TCGv_i64 t2 = tcg_temp_new_i64();
1197 TCGv_i64 t3 = tcg_temp_new_i64();
1198
1199 if (n == 0) {
1200 tcg_gen_mul_tl(temp, arg2, arg3);
1201 } else { /* n is expected to be 1 */
1202 tcg_gen_mul_tl(temp, arg2, arg3);
1203 tcg_gen_shli_tl(temp, temp, 1);
1204 /* catch special case r1 = r2 = 0x8000 */
1205 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1206 tcg_gen_sub_tl(temp, temp, temp2);
1207 }
1208 tcg_gen_ext_i32_i64(t2, temp);
1209 tcg_gen_shli_i64(t2, t2, 16);
1210 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1211 gen_add64_d(t3, t1, t2);
1212 /* write back result */
1213 tcg_gen_extr_i64_i32(rl, rh, t3);
1214
1215 tcg_temp_free_i64(t1);
1216 tcg_temp_free_i64(t2);
1217 tcg_temp_free_i64(t3);
1218 tcg_temp_free(temp);
1219 tcg_temp_free(temp2);
1220 }
1221
1222 static inline void
1223 gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1224 TCGv arg3, uint32_t n)
1225 {
1226 TCGv temp = tcg_temp_new();
1227 TCGv temp2 = tcg_temp_new();
1228 TCGv_i64 t1 = tcg_temp_new_i64();
1229 TCGv_i64 t2 = tcg_temp_new_i64();
1230
1231 if (n == 0) {
1232 tcg_gen_mul_tl(temp, arg2, arg3);
1233 } else { /* n is expected to be 1 */
1234 tcg_gen_mul_tl(temp, arg2, arg3);
1235 tcg_gen_shli_tl(temp, temp, 1);
1236 /* catch special case r1 = r2 = 0x8000 */
1237 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1238 tcg_gen_sub_tl(temp, temp, temp2);
1239 }
1240 tcg_gen_ext_i32_i64(t2, temp);
1241 tcg_gen_shli_i64(t2, t2, 16);
1242 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1243
1244 gen_helper_add64_ssov(t1, cpu_env, t1, t2);
1245 tcg_gen_extr_i64_i32(rl, rh, t1);
1246
1247 tcg_temp_free(temp);
1248 tcg_temp_free(temp2);
1249 tcg_temp_free_i64(t1);
1250 tcg_temp_free_i64(t2);
1251 }
1252
1253 static inline void
1254 gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1255 TCGv arg3, uint32_t n, CPUTriCoreState *env)
1256 {
1257 TCGv_i64 t1 = tcg_temp_new_i64();
1258 TCGv_i64 t2 = tcg_temp_new_i64();
1259 TCGv_i64 t3 = tcg_temp_new_i64();
1260 TCGv_i64 t4 = tcg_temp_new_i64();
1261 TCGv temp, temp2;
1262
1263 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1264 tcg_gen_ext_i32_i64(t2, arg2);
1265 tcg_gen_ext_i32_i64(t3, arg3);
1266
1267 tcg_gen_mul_i64(t2, t2, t3);
1268 if (n != 0) {
1269 tcg_gen_shli_i64(t2, t2, 1);
1270 }
1271 tcg_gen_add_i64(t4, t1, t2);
1272 /* calc v bit */
1273 tcg_gen_xor_i64(t3, t4, t1);
1274 tcg_gen_xor_i64(t2, t1, t2);
1275 tcg_gen_andc_i64(t3, t3, t2);
1276 tcg_gen_trunc_shr_i64_i32(cpu_PSW_V, t3, 32);
1277 /* We produce an overflow on the host if the mul before was
1278 (0x80000000 * 0x80000000) << 1). If this is the
1279 case, we negate the ovf. */
1280 if (n == 1) {
1281 temp = tcg_temp_new();
1282 temp2 = tcg_temp_new();
1283 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1284 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1285 tcg_gen_and_tl(temp, temp, temp2);
1286 tcg_gen_shli_tl(temp, temp, 31);
1287 /* negate v bit, if special condition */
1288 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1289
1290 tcg_temp_free(temp);
1291 tcg_temp_free(temp2);
1292 }
1293 /* write back result */
1294 tcg_gen_extr_i64_i32(rl, rh, t4);
1295 /* Calc SV bit */
1296 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1297 /* Calc AV/SAV bits */
1298 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
1299 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
1300 /* calc SAV */
1301 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1302
1303 tcg_temp_free_i64(t1);
1304 tcg_temp_free_i64(t2);
1305 tcg_temp_free_i64(t3);
1306 tcg_temp_free_i64(t4);
1307 }
1308
1309 static inline void
1310 gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1311 uint32_t up_shift)
1312 {
1313 TCGv_i64 t1 = tcg_temp_new_i64();
1314 TCGv_i64 t2 = tcg_temp_new_i64();
1315 TCGv_i64 t3 = tcg_temp_new_i64();
1316
1317 tcg_gen_ext_i32_i64(t1, arg1);
1318 tcg_gen_ext_i32_i64(t2, arg2);
1319 tcg_gen_ext_i32_i64(t3, arg3);
1320
1321 tcg_gen_mul_i64(t2, t2, t3);
1322 tcg_gen_sari_i64(t2, t2, up_shift - n);
1323
1324 gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2);
1325
1326 tcg_temp_free_i64(t1);
1327 tcg_temp_free_i64(t2);
1328 tcg_temp_free_i64(t3);
1329 }
1330
1331 static inline void
1332 gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1333 TCGv arg3, uint32_t n)
1334 {
1335 TCGv_i64 r1 = tcg_temp_new_i64();
1336 TCGv temp = tcg_const_i32(n);
1337
1338 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
1339 gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp);
1340 tcg_gen_extr_i64_i32(rl, rh, r1);
1341
1342 tcg_temp_free_i64(r1);
1343 tcg_temp_free(temp);
1344 }
1345 /* ret = r2 - (r1 * r3); */
1346 static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
1347 {
1348 TCGv_i64 t1 = tcg_temp_new_i64();
1349 TCGv_i64 t2 = tcg_temp_new_i64();
1350 TCGv_i64 t3 = tcg_temp_new_i64();
1351
1352 tcg_gen_ext_i32_i64(t1, r1);
1353 tcg_gen_ext_i32_i64(t2, r2);
1354 tcg_gen_ext_i32_i64(t3, r3);
1355
1356 tcg_gen_mul_i64(t1, t1, t3);
1357 tcg_gen_sub_i64(t1, t2, t1);
1358
1359 tcg_gen_trunc_i64_i32(ret, t1);
1360 /* calc V
1361 t2 > 0x7fffffff */
1362 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
1363 /* result < -0x80000000 */
1364 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
1365 tcg_gen_or_i64(t2, t2, t3);
1366 tcg_gen_trunc_i64_i32(cpu_PSW_V, t2);
1367 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1368
1369 /* Calc SV bit */
1370 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1371 /* Calc AV/SAV bits */
1372 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
1373 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
1374 /* calc SAV */
1375 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1376
1377 tcg_temp_free_i64(t1);
1378 tcg_temp_free_i64(t2);
1379 tcg_temp_free_i64(t3);
1380 }
1381
1382 static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
1383 {
1384 TCGv temp = tcg_const_i32(con);
1385 gen_msub32_d(ret, r1, r2, temp);
1386 tcg_temp_free(temp);
1387 }
1388
1389 static inline void
1390 gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1391 TCGv r3)
1392 {
1393 TCGv t1 = tcg_temp_new();
1394 TCGv t2 = tcg_temp_new();
1395 TCGv t3 = tcg_temp_new();
1396 TCGv t4 = tcg_temp_new();
1397
1398 tcg_gen_muls2_tl(t1, t2, r1, r3);
1399 /* only the sub can overflow */
1400 tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2);
1401 /* calc V bit */
1402 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
1403 tcg_gen_xor_tl(t1, r2_high, t2);
1404 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1);
1405 /* Calc SV bit */
1406 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1407 /* Calc AV/SAV bits */
1408 tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
1409 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
1410 /* calc SAV */
1411 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1412 /* write back the result */
1413 tcg_gen_mov_tl(ret_low, t3);
1414 tcg_gen_mov_tl(ret_high, t4);
1415
1416 tcg_temp_free(t1);
1417 tcg_temp_free(t2);
1418 tcg_temp_free(t3);
1419 tcg_temp_free(t4);
1420 }
1421
1422 static inline void
1423 gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1424 int32_t con)
1425 {
1426 TCGv temp = tcg_const_i32(con);
1427 gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
1428 tcg_temp_free(temp);
1429 }
1430
1431 static inline void
1432 gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1433 TCGv r3)
1434 {
1435 TCGv_i64 t1 = tcg_temp_new_i64();
1436 TCGv_i64 t2 = tcg_temp_new_i64();
1437 TCGv_i64 t3 = tcg_temp_new_i64();
1438
1439 tcg_gen_extu_i32_i64(t1, r1);
1440 tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
1441 tcg_gen_extu_i32_i64(t3, r3);
1442
1443 tcg_gen_mul_i64(t1, t1, t3);
1444 tcg_gen_sub_i64(t3, t2, t1);
1445 tcg_gen_extr_i64_i32(ret_low, ret_high, t3);
1446 /* calc V bit, only the sub can overflow, if t1 > t2 */
1447 tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2);
1448 tcg_gen_trunc_i64_i32(cpu_PSW_V, t1);
1449 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1450 /* Calc SV bit */
1451 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1452 /* Calc AV/SAV bits */
1453 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
1454 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
1455 /* calc SAV */
1456 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1457
1458 tcg_temp_free_i64(t1);
1459 tcg_temp_free_i64(t2);
1460 tcg_temp_free_i64(t3);
1461 }
1462
1463 static inline void
1464 gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1465 int32_t con)
1466 {
1467 TCGv temp = tcg_const_i32(con);
1468 gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
1469 tcg_temp_free(temp);
1470 }
1471
1472 static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2)
1473 {
1474 TCGv temp = tcg_const_i32(r2);
1475 gen_add_d(ret, r1, temp);
1476 tcg_temp_free(temp);
1477 }
1478 /* calculate the carry bit too */
1479 static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2)
1480 {
1481 TCGv t0 = tcg_temp_new_i32();
1482 TCGv result = tcg_temp_new_i32();
1483
1484 tcg_gen_movi_tl(t0, 0);
1485 /* Addition and set C/V/SV bits */
1486 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0);
1487 /* calc V bit */
1488 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1489 tcg_gen_xor_tl(t0, r1, r2);
1490 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
1491 /* Calc SV bit */
1492 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1493 /* Calc AV/SAV bits */
1494 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1495 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1496 /* calc SAV */
1497 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1498 /* write back result */
1499 tcg_gen_mov_tl(ret, result);
1500
1501 tcg_temp_free(result);
1502 tcg_temp_free(t0);
1503 }
1504
1505 static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con)
1506 {
1507 TCGv temp = tcg_const_i32(con);
1508 gen_add_CC(ret, r1, temp);
1509 tcg_temp_free(temp);
1510 }
1511
1512 static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2)
1513 {
1514 TCGv carry = tcg_temp_new_i32();
1515 TCGv t0 = tcg_temp_new_i32();
1516 TCGv result = tcg_temp_new_i32();
1517
1518 tcg_gen_movi_tl(t0, 0);
1519 tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0);
1520 /* Addition, carry and set C/V/SV bits */
1521 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0);
1522 tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0);
1523 /* calc V bit */
1524 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1525 tcg_gen_xor_tl(t0, r1, r2);
1526 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
1527 /* Calc SV bit */
1528 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1529 /* Calc AV/SAV bits */
1530 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1531 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1532 /* calc SAV */
1533 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1534 /* write back result */
1535 tcg_gen_mov_tl(ret, result);
1536
1537 tcg_temp_free(result);
1538 tcg_temp_free(t0);
1539 tcg_temp_free(carry);
1540 }
1541
1542 static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con)
1543 {
1544 TCGv temp = tcg_const_i32(con);
1545 gen_addc_CC(ret, r1, temp);
1546 tcg_temp_free(temp);
1547 }
1548
1549 static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
1550 TCGv r4)
1551 {
1552 TCGv temp = tcg_temp_new();
1553 TCGv temp2 = tcg_temp_new();
1554 TCGv result = tcg_temp_new();
1555 TCGv mask = tcg_temp_new();
1556 TCGv t0 = tcg_const_i32(0);
1557
1558 /* create mask for sticky bits */
1559 tcg_gen_setcond_tl(cond, mask, r4, t0);
1560 tcg_gen_shli_tl(mask, mask, 31);
1561
1562 tcg_gen_add_tl(result, r1, r2);
1563 /* Calc PSW_V */
1564 tcg_gen_xor_tl(temp, result, r1);
1565 tcg_gen_xor_tl(temp2, r1, r2);
1566 tcg_gen_andc_tl(temp, temp, temp2);
1567 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
1568 /* Set PSW_SV */
1569 tcg_gen_and_tl(temp, temp, mask);
1570 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
1571 /* calc AV bit */
1572 tcg_gen_add_tl(temp, result, result);
1573 tcg_gen_xor_tl(temp, temp, result);
1574 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
1575 /* calc SAV bit */
1576 tcg_gen_and_tl(temp, temp, mask);
1577 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
1578 /* write back result */
1579 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
1580
1581 tcg_temp_free(t0);
1582 tcg_temp_free(temp);
1583 tcg_temp_free(temp2);
1584 tcg_temp_free(result);
1585 tcg_temp_free(mask);
1586 }
1587
1588 static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2,
1589 TCGv r3, TCGv r4)
1590 {
1591 TCGv temp = tcg_const_i32(r2);
1592 gen_cond_add(cond, r1, temp, r3, r4);
1593 tcg_temp_free(temp);
1594 }
1595
1596 static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
1597 {
1598 TCGv temp = tcg_temp_new_i32();
1599 TCGv result = tcg_temp_new_i32();
1600
1601 tcg_gen_sub_tl(result, r1, r2);
1602 /* calc V bit */
1603 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1604 tcg_gen_xor_tl(temp, r1, r2);
1605 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1606 /* calc SV bit */
1607 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1608 /* Calc AV bit */
1609 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1610 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1611 /* calc SAV bit */
1612 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1613 /* write back result */
1614 tcg_gen_mov_tl(ret, result);
1615
1616 tcg_temp_free(temp);
1617 tcg_temp_free(result);
1618 }
1619
1620 static inline void
1621 gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
1622 {
1623 TCGv temp = tcg_temp_new();
1624 TCGv_i64 t0 = tcg_temp_new_i64();
1625 TCGv_i64 t1 = tcg_temp_new_i64();
1626 TCGv_i64 result = tcg_temp_new_i64();
1627
1628 tcg_gen_sub_i64(result, r1, r2);
1629 /* calc v bit */
1630 tcg_gen_xor_i64(t1, result, r1);
1631 tcg_gen_xor_i64(t0, r1, r2);
1632 tcg_gen_and_i64(t1, t1, t0);
1633 tcg_gen_trunc_shr_i64_i32(cpu_PSW_V, t1, 32);
1634 /* calc SV bit */
1635 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1636 /* calc AV/SAV bits */
1637 tcg_gen_trunc_shr_i64_i32(temp, result, 32);
1638 tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
1639 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
1640 /* calc SAV */
1641 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1642 /* write back result */
1643 tcg_gen_mov_i64(ret, result);
1644
1645 tcg_temp_free(temp);
1646 tcg_temp_free_i64(result);
1647 tcg_temp_free_i64(t0);
1648 tcg_temp_free_i64(t1);
1649 }
1650
1651 static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2)
1652 {
1653 TCGv result = tcg_temp_new();
1654 TCGv temp = tcg_temp_new();
1655
1656 tcg_gen_sub_tl(result, r1, r2);
1657 /* calc C bit */
1658 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2);
1659 /* calc V bit */
1660 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1661 tcg_gen_xor_tl(temp, r1, r2);
1662 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1663 /* calc SV bit */
1664 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1665 /* Calc AV bit */
1666 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1667 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1668 /* calc SAV bit */
1669 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1670 /* write back result */
1671 tcg_gen_mov_tl(ret, result);
1672
1673 tcg_temp_free(result);
1674 tcg_temp_free(temp);
1675 }
1676
1677 static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2)
1678 {
1679 TCGv temp = tcg_temp_new();
1680 tcg_gen_not_tl(temp, r2);
1681 gen_addc_CC(ret, r1, temp);
1682 tcg_temp_free(temp);
1683 }
1684
1685 static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
1686 TCGv r4)
1687 {
1688 TCGv temp = tcg_temp_new();
1689 TCGv temp2 = tcg_temp_new();
1690 TCGv result = tcg_temp_new();
1691 TCGv mask = tcg_temp_new();
1692 TCGv t0 = tcg_const_i32(0);
1693
1694 /* create mask for sticky bits */
1695 tcg_gen_setcond_tl(cond, mask, r4, t0);
1696 tcg_gen_shli_tl(mask, mask, 31);
1697
1698 tcg_gen_sub_tl(result, r1, r2);
1699 /* Calc PSW_V */
1700 tcg_gen_xor_tl(temp, result, r1);
1701 tcg_gen_xor_tl(temp2, r1, r2);
1702 tcg_gen_and_tl(temp, temp, temp2);
1703 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
1704 /* Set PSW_SV */
1705 tcg_gen_and_tl(temp, temp, mask);
1706 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
1707 /* calc AV bit */
1708 tcg_gen_add_tl(temp, result, result);
1709 tcg_gen_xor_tl(temp, temp, result);
1710 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
1711 /* calc SAV bit */
1712 tcg_gen_and_tl(temp, temp, mask);
1713 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
1714 /* write back result */
1715 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
1716
1717 tcg_temp_free(t0);
1718 tcg_temp_free(temp);
1719 tcg_temp_free(temp2);
1720 tcg_temp_free(result);
1721 tcg_temp_free(mask);
1722 }
1723
1724 static inline void
1725 gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1726 TCGv r3, uint32_t n, uint32_t mode)
1727 {
1728 TCGv temp = tcg_const_i32(n);
1729 TCGv temp2 = tcg_temp_new();
1730 TCGv_i64 temp64 = tcg_temp_new_i64();
1731 switch (mode) {
1732 case MODE_LL:
1733 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1734 break;
1735 case MODE_LU:
1736 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1737 break;
1738 case MODE_UL:
1739 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1740 break;
1741 case MODE_UU:
1742 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1743 break;
1744 }
1745 tcg_gen_extr_i64_i32(temp, temp2, temp64);
1746 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
1747 tcg_gen_sub_tl, tcg_gen_sub_tl);
1748 tcg_temp_free(temp);
1749 tcg_temp_free(temp2);
1750 tcg_temp_free_i64(temp64);
1751 }
1752
1753 static inline void
1754 gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1755 TCGv r3, uint32_t n, uint32_t mode)
1756 {
1757 TCGv temp = tcg_const_i32(n);
1758 TCGv temp2 = tcg_temp_new();
1759 TCGv temp3 = tcg_temp_new();
1760 TCGv_i64 temp64 = tcg_temp_new_i64();
1761
1762 switch (mode) {
1763 case MODE_LL:
1764 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1765 break;
1766 case MODE_LU:
1767 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1768 break;
1769 case MODE_UL:
1770 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1771 break;
1772 case MODE_UU:
1773 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1774 break;
1775 }
1776 tcg_gen_extr_i64_i32(temp, temp2, temp64);
1777 gen_subs(ret_low, r1_low, temp);
1778 tcg_gen_mov_tl(temp, cpu_PSW_V);
1779 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
1780 gen_subs(ret_high, r1_high, temp2);
1781 /* combine v bits */
1782 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
1783 /* combine av bits */
1784 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
1785
1786 tcg_temp_free(temp);
1787 tcg_temp_free(temp2);
1788 tcg_temp_free(temp3);
1789 tcg_temp_free_i64(temp64);
1790 }
1791
1792 static inline void
1793 gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1794 TCGv r3, uint32_t n, uint32_t mode)
1795 {
1796 TCGv temp = tcg_const_i32(n);
1797 TCGv_i64 temp64 = tcg_temp_new_i64();
1798 TCGv_i64 temp64_2 = tcg_temp_new_i64();
1799 TCGv_i64 temp64_3 = tcg_temp_new_i64();
1800 switch (mode) {
1801 case MODE_LL:
1802 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
1803 break;
1804 case MODE_LU:
1805 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
1806 break;
1807 case MODE_UL:
1808 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
1809 break;
1810 case MODE_UU:
1811 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
1812 break;
1813 }
1814 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
1815 gen_sub64_d(temp64_3, temp64_2, temp64);
1816 /* write back result */
1817 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
1818
1819 tcg_temp_free(temp);
1820 tcg_temp_free_i64(temp64);
1821 tcg_temp_free_i64(temp64_2);
1822 tcg_temp_free_i64(temp64_3);
1823 }
1824
1825 static inline void
1826 gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1827 TCGv r3, uint32_t n, uint32_t mode)
1828 {
1829 TCGv temp = tcg_const_i32(n);
1830 TCGv_i64 temp64 = tcg_temp_new_i64();
1831 TCGv_i64 temp64_2 = tcg_temp_new_i64();
1832 switch (mode) {
1833 case MODE_LL:
1834 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
1835 break;
1836 case MODE_LU:
1837 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
1838 break;
1839 case MODE_UL:
1840 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
1841 break;
1842 case MODE_UU:
1843 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
1844 break;
1845 }
1846 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
1847 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64);
1848 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
1849
1850 tcg_temp_free(temp);
1851 tcg_temp_free_i64(temp64);
1852 tcg_temp_free_i64(temp64_2);
1853 }
1854
1855 static inline void
1856 gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
1857 uint32_t mode)
1858 {
1859 TCGv temp = tcg_const_i32(n);
1860 TCGv_i64 temp64 = tcg_temp_new_i64();
1861 switch (mode) {
1862 case MODE_LL:
1863 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1864 break;
1865 case MODE_LU:
1866 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1867 break;
1868 case MODE_UL:
1869 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1870 break;
1871 case MODE_UU:
1872 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1873 break;
1874 }
1875 gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high);
1876
1877 tcg_temp_free(temp);
1878 tcg_temp_free_i64(temp64);
1879 }
1880
1881 static inline void
1882 gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1883 {
1884 TCGv temp = tcg_temp_new();
1885 TCGv temp2 = tcg_temp_new();
1886
1887 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1888 tcg_gen_shli_tl(temp, r1, 16);
1889 gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode);
1890
1891 tcg_temp_free(temp);
1892 tcg_temp_free(temp2);
1893 }
1894
1895 static inline void
1896 gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
1897 uint32_t n, uint32_t mode)
1898 {
1899 TCGv temp = tcg_const_i32(n);
1900 TCGv_i64 temp64 = tcg_temp_new_i64();
1901 switch (mode) {
1902 case MODE_LL:
1903 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1904 break;
1905 case MODE_LU:
1906 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1907 break;
1908 case MODE_UL:
1909 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1910 break;
1911 case MODE_UU:
1912 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1913 break;
1914 }
1915 gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
1916
1917 tcg_temp_free(temp);
1918 tcg_temp_free_i64(temp64);
1919 }
1920
1921 static inline void
1922 gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1923 {
1924 TCGv temp = tcg_temp_new();
1925 TCGv temp2 = tcg_temp_new();
1926
1927 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1928 tcg_gen_shli_tl(temp, r1, 16);
1929 gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode);
1930
1931 tcg_temp_free(temp);
1932 tcg_temp_free(temp2);
1933 }
1934
1935 static inline void
1936 gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1937 {
1938 TCGv temp = tcg_const_i32(n);
1939 gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp);
1940 tcg_temp_free(temp);
1941 }
1942
1943 static inline void
1944 gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1945 {
1946 TCGv temp = tcg_const_i32(n);
1947 gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp);
1948 tcg_temp_free(temp);
1949 }
1950
1951 static inline void
1952 gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1953 uint32_t up_shift, CPUTriCoreState *env)
1954 {
1955 TCGv temp = tcg_temp_new();
1956 TCGv temp2 = tcg_temp_new();
1957 TCGv temp3 = tcg_temp_new();
1958 TCGv_i64 t1 = tcg_temp_new_i64();
1959 TCGv_i64 t2 = tcg_temp_new_i64();
1960 TCGv_i64 t3 = tcg_temp_new_i64();
1961 TCGv_i64 t4 = tcg_temp_new_i64();
1962
1963 tcg_gen_ext_i32_i64(t2, arg2);
1964 tcg_gen_ext_i32_i64(t3, arg3);
1965
1966 tcg_gen_mul_i64(t2, t2, t3);
1967
1968 tcg_gen_ext_i32_i64(t1, arg1);
1969 /* if we shift part of the fraction out, we need to round up */
1970 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1);
1971 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0);
1972 tcg_gen_sari_i64(t2, t2, up_shift - n);
1973 tcg_gen_add_i64(t2, t2, t4);
1974
1975 tcg_gen_sub_i64(t3, t1, t2);
1976 tcg_gen_trunc_i64_i32(temp3, t3);
1977 /* calc v bit */
1978 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
1979 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
1980 tcg_gen_or_i64(t1, t1, t2);
1981 tcg_gen_trunc_i64_i32(cpu_PSW_V, t1);
1982 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1983 /* Calc SV bit */
1984 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1985 /* Calc AV/SAV bits */
1986 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
1987 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
1988 /* calc SAV */
1989 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1990 /* write back result */
1991 tcg_gen_mov_tl(ret, temp3);
1992
1993 tcg_temp_free(temp);
1994 tcg_temp_free(temp2);
1995 tcg_temp_free(temp3);
1996 tcg_temp_free_i64(t1);
1997 tcg_temp_free_i64(t2);
1998 tcg_temp_free_i64(t3);
1999 tcg_temp_free_i64(t4);
2000 }
2001
2002 static inline void
2003 gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
2004 {
2005 TCGv temp = tcg_temp_new();
2006 TCGv temp2 = tcg_temp_new();
2007 if (n == 0) {
2008 tcg_gen_mul_tl(temp, arg2, arg3);
2009 } else { /* n is expected to be 1 */
2010 tcg_gen_mul_tl(temp, arg2, arg3);
2011 tcg_gen_shli_tl(temp, temp, 1);
2012 /* catch special case r1 = r2 = 0x8000 */
2013 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
2014 tcg_gen_sub_tl(temp, temp, temp2);
2015 }
2016 gen_sub_d(ret, arg1, temp);
2017
2018 tcg_temp_free(temp);
2019 tcg_temp_free(temp2);
2020 }
2021
2022 static inline void
2023 gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
2024 {
2025 TCGv temp = tcg_temp_new();
2026 TCGv temp2 = tcg_temp_new();
2027 if (n == 0) {
2028 tcg_gen_mul_tl(temp, arg2, arg3);
2029 } else { /* n is expected to be 1 */
2030 tcg_gen_mul_tl(temp, arg2, arg3);
2031 tcg_gen_shli_tl(temp, temp, 1);
2032 /* catch special case r1 = r2 = 0x8000 */
2033 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
2034 tcg_gen_sub_tl(temp, temp, temp2);
2035 }
2036 gen_subs(ret, arg1, temp);
2037
2038 tcg_temp_free(temp);
2039 tcg_temp_free(temp2);
2040 }
2041
2042 static inline void
2043 gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
2044 TCGv arg3, uint32_t n)
2045 {
2046 TCGv temp = tcg_temp_new();
2047 TCGv temp2 = tcg_temp_new();
2048 TCGv_i64 t1 = tcg_temp_new_i64();
2049 TCGv_i64 t2 = tcg_temp_new_i64();
2050 TCGv_i64 t3 = tcg_temp_new_i64();
2051
2052 if (n == 0) {
2053 tcg_gen_mul_tl(temp, arg2, arg3);
2054 } else { /* n is expected to be 1 */
2055 tcg_gen_mul_tl(temp, arg2, arg3);
2056 tcg_gen_shli_tl(temp, temp, 1);
2057 /* catch special case r1 = r2 = 0x8000 */
2058 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
2059 tcg_gen_sub_tl(temp, temp, temp2);
2060 }
2061 tcg_gen_ext_i32_i64(t2, temp);
2062 tcg_gen_shli_i64(t2, t2, 16);
2063 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
2064 gen_sub64_d(t3, t1, t2);
2065 /* write back result */
2066 tcg_gen_extr_i64_i32(rl, rh, t3);
2067
2068 tcg_temp_free_i64(t1);
2069 tcg_temp_free_i64(t2);
2070 tcg_temp_free_i64(t3);
2071 tcg_temp_free(temp);
2072 tcg_temp_free(temp2);
2073 }
2074
2075 static inline void
2076 gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
2077 TCGv arg3, uint32_t n)
2078 {
2079 TCGv temp = tcg_temp_new();
2080 TCGv temp2 = tcg_temp_new();
2081 TCGv_i64 t1 = tcg_temp_new_i64();
2082 TCGv_i64 t2 = tcg_temp_new_i64();
2083
2084 if (n == 0) {
2085 tcg_gen_mul_tl(temp, arg2, arg3);
2086 } else { /* n is expected to be 1 */
2087 tcg_gen_mul_tl(temp, arg2, arg3);
2088 tcg_gen_shli_tl(temp, temp, 1);
2089 /* catch special case r1 = r2 = 0x8000 */
2090 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
2091 tcg_gen_sub_tl(temp, temp, temp2);
2092 }
2093 tcg_gen_ext_i32_i64(t2, temp);
2094 tcg_gen_shli_i64(t2, t2, 16);
2095 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
2096
2097 gen_helper_sub64_ssov(t1, cpu_env, t1, t2);
2098 tcg_gen_extr_i64_i32(rl, rh, t1);
2099
2100 tcg_temp_free(temp);
2101 tcg_temp_free(temp2);
2102 tcg_temp_free_i64(t1);
2103 tcg_temp_free_i64(t2);
2104 }
2105
2106 static inline void
2107 gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
2108 TCGv arg3, uint32_t n, CPUTriCoreState *env)
2109 {
2110 TCGv_i64 t1 = tcg_temp_new_i64();
2111 TCGv_i64 t2 = tcg_temp_new_i64();
2112 TCGv_i64 t3 = tcg_temp_new_i64();
2113 TCGv_i64 t4 = tcg_temp_new_i64();
2114 TCGv temp, temp2;
2115
2116 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
2117 tcg_gen_ext_i32_i64(t2, arg2);
2118 tcg_gen_ext_i32_i64(t3, arg3);
2119
2120 tcg_gen_mul_i64(t2, t2, t3);
2121 if (n != 0) {
2122 tcg_gen_shli_i64(t2, t2, 1);
2123 }
2124 tcg_gen_sub_i64(t4, t1, t2);
2125 /* calc v bit */
2126 tcg_gen_xor_i64(t3, t4, t1);
2127 tcg_gen_xor_i64(t2, t1, t2);
2128 tcg_gen_and_i64(t3, t3, t2);
2129 tcg_gen_trunc_shr_i64_i32(cpu_PSW_V, t3, 32);
2130 /* We produce an overflow on the host if the mul before was
2131 (0x80000000 * 0x80000000) << 1). If this is the
2132 case, we negate the ovf. */
2133 if (n == 1) {
2134 temp = tcg_temp_new();
2135 temp2 = tcg_temp_new();
2136 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
2137 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
2138 tcg_gen_and_tl(temp, temp, temp2);
2139 tcg_gen_shli_tl(temp, temp, 31);
2140 /* negate v bit, if special condition */
2141 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
2142
2143 tcg_temp_free(temp);
2144 tcg_temp_free(temp2);
2145 }
2146 /* write back result */
2147 tcg_gen_extr_i64_i32(rl, rh, t4);
2148 /* Calc SV bit */
2149 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2150 /* Calc AV/SAV bits */
2151 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
2152 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
2153 /* calc SAV */
2154 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2155
2156 tcg_temp_free_i64(t1);
2157 tcg_temp_free_i64(t2);
2158 tcg_temp_free_i64(t3);
2159 tcg_temp_free_i64(t4);
2160 }
2161
2162 static inline void
2163 gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
2164 uint32_t up_shift)
2165 {
2166 TCGv_i64 t1 = tcg_temp_new_i64();
2167 TCGv_i64 t2 = tcg_temp_new_i64();
2168 TCGv_i64 t3 = tcg_temp_new_i64();
2169 TCGv_i64 t4 = tcg_temp_new_i64();
2170
2171 tcg_gen_ext_i32_i64(t1, arg1);
2172 tcg_gen_ext_i32_i64(t2, arg2);
2173 tcg_gen_ext_i32_i64(t3, arg3);
2174
2175 tcg_gen_mul_i64(t2, t2, t3);
2176 /* if we shift part of the fraction out, we need to round up */
2177 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1);
2178 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0);
2179 tcg_gen_sari_i64(t3, t2, up_shift - n);
2180 tcg_gen_add_i64(t3, t3, t4);
2181
2182 gen_helper_msub32_q_sub_ssov(ret, cpu_env, t1, t3);
2183
2184 tcg_temp_free_i64(t1);
2185 tcg_temp_free_i64(t2);
2186 tcg_temp_free_i64(t3);
2187 tcg_temp_free_i64(t4);
2188 }
2189
2190 static inline void
2191 gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
2192 TCGv arg3, uint32_t n)
2193 {
2194 TCGv_i64 r1 = tcg_temp_new_i64();
2195 TCGv temp = tcg_const_i32(n);
2196
2197 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
2198 gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp);
2199 tcg_gen_extr_i64_i32(rl, rh, r1);
2200
2201 tcg_temp_free_i64(r1);
2202 tcg_temp_free(temp);
2203 }
2204
2205 static inline void
2206 gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2207 TCGv r3, uint32_t n, uint32_t mode)
2208 {
2209 TCGv temp = tcg_const_i32(n);
2210 TCGv temp2 = tcg_temp_new();
2211 TCGv_i64 temp64 = tcg_temp_new_i64();
2212 switch (mode) {
2213 case MODE_LL:
2214 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2215 break;
2216 case MODE_LU:
2217 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2218 break;
2219 case MODE_UL:
2220 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2221 break;
2222 case MODE_UU:
2223 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2224 break;
2225 }
2226 tcg_gen_extr_i64_i32(temp, temp2, temp64);
2227 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
2228 tcg_gen_add_tl, tcg_gen_sub_tl);
2229 tcg_temp_free(temp);
2230 tcg_temp_free(temp2);
2231 tcg_temp_free_i64(temp64);
2232 }
2233
2234 static inline void
2235 gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2236 TCGv r3, uint32_t n, uint32_t mode)
2237 {
2238 TCGv temp = tcg_const_i32(n);
2239 TCGv_i64 temp64 = tcg_temp_new_i64();
2240 TCGv_i64 temp64_2 = tcg_temp_new_i64();
2241 TCGv_i64 temp64_3 = tcg_temp_new_i64();
2242 switch (mode) {
2243 case MODE_LL:
2244 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2245 break;
2246 case MODE_LU:
2247 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2248 break;
2249 case MODE_UL:
2250 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2251 break;
2252 case MODE_UU:
2253 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2254 break;
2255 }
2256 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
2257 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
2258 tcg_gen_ext32s_i64(temp64, temp64); /* low */
2259 tcg_gen_sub_i64(temp64, temp64_2, temp64);
2260 tcg_gen_shli_i64(temp64, temp64, 16);
2261
2262 gen_sub64_d(temp64_2, temp64_3, temp64);
2263 /* write back result */
2264 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
2265
2266 tcg_temp_free(temp);
2267 tcg_temp_free_i64(temp64);
2268 tcg_temp_free_i64(temp64_2);
2269 tcg_temp_free_i64(temp64_3);
2270 }
2271
2272 static inline void
2273 gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
2274 {
2275 TCGv temp = tcg_const_i32(n);
2276 TCGv temp2 = tcg_temp_new();
2277 TCGv_i64 temp64 = tcg_temp_new_i64();
2278 switch (mode) {
2279 case MODE_LL:
2280 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2281 break;
2282 case MODE_LU:
2283 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2284 break;
2285 case MODE_UL:
2286 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2287 break;
2288 case MODE_UU:
2289 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2290 break;
2291 }
2292 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
2293 tcg_gen_shli_tl(temp, r1, 16);
2294 gen_helper_subadr_h(ret, cpu_env, temp64, temp, temp2);
2295
2296 tcg_temp_free(temp);
2297 tcg_temp_free(temp2);
2298 tcg_temp_free_i64(temp64);
2299 }
2300
2301 static inline void
2302 gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2303 TCGv r3, uint32_t n, uint32_t mode)
2304 {
2305 TCGv temp = tcg_const_i32(n);
2306 TCGv temp2 = tcg_temp_new();
2307 TCGv temp3 = tcg_temp_new();
2308 TCGv_i64 temp64 = tcg_temp_new_i64();
2309
2310 switch (mode) {
2311 case MODE_LL:
2312 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2313 break;
2314 case MODE_LU:
2315 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2316 break;
2317 case MODE_UL:
2318 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2319 break;
2320 case MODE_UU:
2321 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2322 break;
2323 }
2324 tcg_gen_extr_i64_i32(temp, temp2, temp64);
2325 gen_adds(ret_low, r1_low, temp);
2326 tcg_gen_mov_tl(temp, cpu_PSW_V);
2327 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
2328 gen_subs(ret_high, r1_high, temp2);
2329 /* combine v bits */
2330 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
2331 /* combine av bits */
2332 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
2333
2334 tcg_temp_free(temp);
2335 tcg_temp_free(temp2);
2336 tcg_temp_free(temp3);
2337 tcg_temp_free_i64(temp64);
2338 }
2339
2340 static inline void
2341 gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2342 TCGv r3, uint32_t n, uint32_t mode)
2343 {
2344 TCGv temp = tcg_const_i32(n);
2345 TCGv_i64 temp64 = tcg_temp_new_i64();
2346 TCGv_i64 temp64_2 = tcg_temp_new_i64();
2347
2348 switch (mode) {
2349 case MODE_LL:
2350 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2351 break;
2352 case MODE_LU:
2353 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2354 break;
2355 case MODE_UL:
2356 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2357 break;
2358 case MODE_UU:
2359 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2360 break;
2361 }
2362 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
2363 tcg_gen_ext32s_i64(temp64, temp64); /* low */
2364 tcg_gen_sub_i64(temp64, temp64_2, temp64);
2365 tcg_gen_shli_i64(temp64, temp64, 16);
2366 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
2367
2368 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64);
2369 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2370
2371 tcg_temp_free(temp);
2372 tcg_temp_free_i64(temp64);
2373 tcg_temp_free_i64(temp64_2);
2374 }
2375
2376 static inline void
2377 gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
2378 {
2379 TCGv temp = tcg_const_i32(n);
2380 TCGv temp2 = tcg_temp_new();
2381 TCGv_i64 temp64 = tcg_temp_new_i64();
2382 switch (mode) {
2383 case MODE_LL:
2384 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2385 break;
2386 case MODE_LU:
2387 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2388 break;
2389 case MODE_UL:
2390 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2391 break;
2392 case MODE_UU:
2393 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2394 break;
2395 }
2396 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
2397 tcg_gen_shli_tl(temp, r1, 16);
2398 gen_helper_subadr_h_ssov(ret, cpu_env, temp64, temp, temp2);
2399
2400 tcg_temp_free(temp);
2401 tcg_temp_free(temp2);
2402 tcg_temp_free_i64(temp64);
2403 }
2404
2405 static inline void gen_abs(TCGv ret, TCGv r1)
2406 {
2407 TCGv temp = tcg_temp_new();
2408 TCGv t0 = tcg_const_i32(0);
2409
2410 tcg_gen_neg_tl(temp, r1);
2411 tcg_gen_movcond_tl(TCG_COND_GE, ret, r1, t0, r1, temp);
2412 /* overflow can only happen, if r1 = 0x80000000 */
2413 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000);
2414 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2415 /* calc SV bit */
2416 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2417 /* Calc AV bit */
2418 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2419 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2420 /* calc SAV bit */
2421 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2422
2423 tcg_temp_free(temp);
2424 tcg_temp_free(t0);
2425 }
2426
2427 static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
2428 {
2429 TCGv temp = tcg_temp_new_i32();
2430 TCGv result = tcg_temp_new_i32();
2431
2432 tcg_gen_sub_tl(result, r1, r2);
2433 tcg_gen_sub_tl(temp, r2, r1);
2434 tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp);
2435
2436 /* calc V bit */
2437 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
2438 tcg_gen_xor_tl(temp, result, r2);
2439 tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp);
2440 tcg_gen_xor_tl(temp, r1, r2);
2441 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
2442 /* calc SV bit */
2443 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2444 /* Calc AV bit */
2445 tcg_gen_add_tl(cpu_PSW_AV, result, result);
2446 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
2447 /* calc SAV bit */
2448 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2449 /* write back result */
2450 tcg_gen_mov_tl(ret, result);
2451
2452 tcg_temp_free(temp);
2453 tcg_temp_free(result);
2454 }
2455
2456 static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con)
2457 {
2458 TCGv temp = tcg_const_i32(con);
2459 gen_absdif(ret, r1, temp);
2460 tcg_temp_free(temp);
2461 }
2462
2463 static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con)
2464 {
2465 TCGv temp = tcg_const_i32(con);
2466 gen_helper_absdif_ssov(ret, cpu_env, r1, temp);
2467 tcg_temp_free(temp);
2468 }
2469
2470 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
2471 {
2472 TCGv high = tcg_temp_new();
2473 TCGv low = tcg_temp_new();
2474
2475 tcg_gen_muls2_tl(low, high, r1, r2);
2476 tcg_gen_mov_tl(ret, low);
2477 /* calc V bit */
2478 tcg_gen_sari_tl(low, low, 31);
2479 tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low);
2480 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2481 /* calc SV bit */
2482 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2483 /* Calc AV bit */
2484 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2485 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2486 /* calc SAV bit */
2487 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2488
2489 tcg_temp_free(high);
2490 tcg_temp_free(low);
2491 }
2492
2493 static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con)
2494 {
2495 TCGv temp = tcg_const_i32(con);
2496 gen_mul_i32s(ret, r1, temp);
2497 tcg_temp_free(temp);
2498 }
2499
2500 static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
2501 {
2502 tcg_gen_muls2_tl(ret_low, ret_high, r1, r2);
2503 /* clear V bit */
2504 tcg_gen_movi_tl(cpu_PSW_V, 0);
2505 /* calc SV bit */
2506 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2507 /* Calc AV bit */
2508 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
2509 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
2510 /* calc SAV bit */
2511 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2512 }
2513
2514 static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1,
2515 int32_t con)
2516 {
2517 TCGv temp = tcg_const_i32(con);
2518 gen_mul_i64s(ret_low, ret_high, r1, temp);
2519 tcg_temp_free(temp);
2520 }
2521
2522 static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
2523 {
2524 tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2);
2525 /* clear V bit */
2526 tcg_gen_movi_tl(cpu_PSW_V, 0);
2527 /* calc SV bit */
2528 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2529 /* Calc AV bit */
2530 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
2531 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
2532 /* calc SAV bit */
2533 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2534 }
2535
2536 static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1,
2537 int32_t con)
2538 {
2539 TCGv temp = tcg_const_i32(con);
2540 gen_mul_i64u(ret_low, ret_high, r1, temp);
2541 tcg_temp_free(temp);
2542 }
2543
2544 static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con)
2545 {
2546 TCGv temp = tcg_const_i32(con);
2547 gen_helper_mul_ssov(ret, cpu_env, r1, temp);
2548 tcg_temp_free(temp);
2549 }
2550
2551 static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con)
2552 {
2553 TCGv temp = tcg_const_i32(con);
2554 gen_helper_mul_suov(ret, cpu_env, r1, temp);
2555 tcg_temp_free(temp);
2556 }
2557 /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */
2558 static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2559 {
2560 TCGv temp = tcg_const_i32(con);
2561 gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp);
2562 tcg_temp_free(temp);
2563 }
2564
2565 static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2566 {
2567 TCGv temp = tcg_const_i32(con);
2568 gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp);
2569 tcg_temp_free(temp);
2570 }
2571
2572 static void
2573 gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift)
2574 {
2575 TCGv temp = tcg_temp_new();
2576 TCGv_i64 temp_64 = tcg_temp_new_i64();
2577 TCGv_i64 temp2_64 = tcg_temp_new_i64();
2578
2579 if (n == 0) {
2580 if (up_shift == 32) {
2581 tcg_gen_muls2_tl(rh, rl, arg1, arg2);
2582 } else if (up_shift == 16) {
2583 tcg_gen_ext_i32_i64(temp_64, arg1);
2584 tcg_gen_ext_i32_i64(temp2_64, arg2);
2585
2586 tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
2587 tcg_gen_shri_i64(temp_64, temp_64, up_shift);
2588 tcg_gen_extr_i64_i32(rl, rh, temp_64);
2589 } else {
2590 tcg_gen_muls2_tl(rl, rh, arg1, arg2);
2591 }
2592 /* reset v bit */
2593 tcg_gen_movi_tl(cpu_PSW_V, 0);
2594 } else { /* n is expected to be 1 */
2595 tcg_gen_ext_i32_i64(temp_64, arg1);
2596 tcg_gen_ext_i32_i64(temp2_64, arg2);
2597
2598 tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
2599
2600 if (up_shift == 0) {
2601 tcg_gen_shli_i64(temp_64, temp_64, 1);
2602 } else {
2603 tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1);
2604 }
2605 tcg_gen_extr_i64_i32(rl, rh, temp_64);
2606 /* overflow only occurs if r1 = r2 = 0x8000 */
2607 if (up_shift == 0) {/* result is 64 bit */
2608 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh,
2609 0x80000000);
2610 } else { /* result is 32 bit */
2611 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl,
2612 0x80000000);
2613 }
2614 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2615 /* calc sv overflow bit */
2616 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2617 }
2618 /* calc av overflow bit */
2619 if (up_shift == 0) {
2620 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
2621 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
2622 } else {
2623 tcg_gen_add_tl(cpu_PSW_AV, rl, rl);
2624 tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV);
2625 }
2626 /* calc sav overflow bit */
2627 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2628 tcg_temp_free(temp);
2629 tcg_temp_free_i64(temp_64);
2630 tcg_temp_free_i64(temp2_64);
2631 }
2632
2633 static void
2634 gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
2635 {
2636 TCGv temp = tcg_temp_new();
2637 if (n == 0) {
2638 tcg_gen_mul_tl(ret, arg1, arg2);
2639 } else { /* n is expected to be 1 */
2640 tcg_gen_mul_tl(ret, arg1, arg2);
2641 tcg_gen_shli_tl(ret, ret, 1);
2642 /* catch special case r1 = r2 = 0x8000 */
2643 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000);
2644 tcg_gen_sub_tl(ret, ret, temp);
2645 }
2646 /* reset v bit */
2647 tcg_gen_movi_tl(cpu_PSW_V, 0);
2648 /* calc av overflow bit */
2649 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2650 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2651 /* calc sav overflow bit */
2652 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2653
2654 tcg_temp_free(temp);
2655 }
2656
2657 static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
2658 {
2659 TCGv temp = tcg_temp_new();
2660 if (n == 0) {
2661 tcg_gen_mul_tl(ret, arg1, arg2);
2662 tcg_gen_addi_tl(ret, ret, 0x8000);
2663 } else {
2664 tcg_gen_mul_tl(ret, arg1, arg2);
2665 tcg_gen_shli_tl(ret, ret, 1);
2666 tcg_gen_addi_tl(ret, ret, 0x8000);
2667 /* catch special case r1 = r2 = 0x8000 */
2668 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000);
2669 tcg_gen_muli_tl(temp, temp, 0x8001);
2670 tcg_gen_sub_tl(ret, ret, temp);
2671 }
2672 /* reset v bit */
2673 tcg_gen_movi_tl(cpu_PSW_V, 0);
2674 /* calc av overflow bit */
2675 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2676 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2677 /* calc sav overflow bit */
2678 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2679 /* cut halfword off */
2680 tcg_gen_andi_tl(ret, ret, 0xffff0000);
2681
2682 tcg_temp_free(temp);
2683 }
2684
2685 static inline void
2686 gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2687 TCGv r3)
2688 {
2689 TCGv_i64 temp64 = tcg_temp_new_i64();
2690 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2691 gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3);
2692 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2693 tcg_temp_free_i64(temp64);
2694 }
2695
2696 static inline void
2697 gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2698 int32_t con)
2699 {
2700 TCGv temp = tcg_const_i32(con);
2701 gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2702 tcg_temp_free(temp);
2703 }
2704
2705 static inline void
2706 gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2707 TCGv r3)
2708 {
2709 TCGv_i64 temp64 = tcg_temp_new_i64();
2710 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2711 gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3);
2712 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2713 tcg_temp_free_i64(temp64);
2714 }
2715
2716 static inline void
2717 gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2718 int32_t con)
2719 {
2720 TCGv temp = tcg_const_i32(con);
2721 gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2722 tcg_temp_free(temp);
2723 }
2724
2725 static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2726 {
2727 TCGv temp = tcg_const_i32(con);
2728 gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp);
2729 tcg_temp_free(temp);
2730 }
2731
2732 static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2733 {
2734 TCGv temp = tcg_const_i32(con);
2735 gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp);
2736 tcg_temp_free(temp);
2737 }
2738
2739 static inline void
2740 gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2741 TCGv r3)
2742 {
2743 TCGv_i64 temp64 = tcg_temp_new_i64();
2744 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2745 gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3);
2746 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2747 tcg_temp_free_i64(temp64);
2748 }
2749
2750 static inline void
2751 gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2752 int32_t con)
2753 {
2754 TCGv temp = tcg_const_i32(con);
2755 gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2756 tcg_temp_free(temp);
2757 }
2758
2759 static inline void
2760 gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2761 TCGv r3)
2762 {
2763 TCGv_i64 temp64 = tcg_temp_new_i64();
2764 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2765 gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3);
2766 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2767 tcg_temp_free_i64(temp64);
2768 }
2769
2770 static inline void
2771 gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2772 int32_t con)
2773 {
2774 TCGv temp = tcg_const_i32(con);
2775 gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2776 tcg_temp_free(temp);
2777 }
2778
2779 static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
2780 {
2781 TCGv sat_neg = tcg_const_i32(low);
2782 TCGv temp = tcg_const_i32(up);
2783
2784 /* sat_neg = (arg < low ) ? low : arg; */
2785 tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, sat_neg, arg);
2786
2787 /* ret = (sat_neg > up ) ? up : sat_neg; */
2788 tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg);
2789
2790 tcg_temp_free(sat_neg);
2791 tcg_temp_free(temp);
2792 }
2793
2794 static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up)
2795 {
2796 TCGv temp = tcg_const_i32(up);
2797 /* sat_neg = (arg > up ) ? up : arg; */
2798 tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg);
2799 tcg_temp_free(temp);
2800 }
2801
2802 static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
2803 {
2804 if (shift_count == -32) {
2805 tcg_gen_movi_tl(ret, 0);
2806 } else if (shift_count >= 0) {
2807 tcg_gen_shli_tl(ret, r1, shift_count);
2808 } else {
2809 tcg_gen_shri_tl(ret, r1, -shift_count);
2810 }
2811 }
2812
2813 static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount)
2814 {
2815 TCGv temp_low, temp_high;
2816
2817 if (shiftcount == -16) {
2818 tcg_gen_movi_tl(ret, 0);
2819 } else {
2820 temp_high = tcg_temp_new();
2821 temp_low = tcg_temp_new();
2822
2823 tcg_gen_andi_tl(temp_low, r1, 0xffff);
2824 tcg_gen_andi_tl(temp_high, r1, 0xffff0000);
2825 gen_shi(temp_low, temp_low, shiftcount);
2826 gen_shi(ret, temp_high, shiftcount);
2827 tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16);
2828
2829 tcg_temp_free(temp_low);
2830 tcg_temp_free(temp_high);
2831 }
2832 }
2833
2834 static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
2835 {
2836 uint32_t msk, msk_start;
2837 TCGv temp = tcg_temp_new();
2838 TCGv temp2 = tcg_temp_new();
2839 TCGv t_0 = tcg_const_i32(0);
2840
2841 if (shift_count == 0) {
2842 /* Clear PSW.C and PSW.V */
2843 tcg_gen_movi_tl(cpu_PSW_C, 0);
2844 tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C);
2845 tcg_gen_mov_tl(ret, r1);
2846 } else if (shift_count == -32) {
2847 /* set PSW.C */
2848 tcg_gen_mov_tl(cpu_PSW_C, r1);
2849 /* fill ret completly with sign bit */
2850 tcg_gen_sari_tl(ret, r1, 31);
2851 /* clear PSW.V */
2852 tcg_gen_movi_tl(cpu_PSW_V, 0);
2853 } else if (shift_count > 0) {
2854 TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count);
2855 TCGv t_min = tcg_const_i32(((int32_t) -0x80000000) >> shift_count);
2856
2857 /* calc carry */
2858 msk_start = 32 - shift_count;
2859 msk = ((1 << shift_count) - 1) << msk_start;
2860 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
2861 /* calc v/sv bits */
2862 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max);
2863 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min);
2864 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
2865 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2866 /* calc sv */
2867 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV);
2868 /* do shift */
2869 tcg_gen_shli_tl(ret, r1, shift_count);
2870
2871 tcg_temp_free(t_max);
2872 tcg_temp_free(t_min);
2873 } else {
2874 /* clear PSW.V */
2875 tcg_gen_movi_tl(cpu_PSW_V, 0);
2876 /* calc carry */
2877 msk = (1 << -shift_count) - 1;
2878 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
2879 /* do shift */
2880 tcg_gen_sari_tl(ret, r1, -shift_count);
2881 }
2882 /* calc av overflow bit */
2883 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2884 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2885 /* calc sav overflow bit */
2886 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2887
2888 tcg_temp_free(temp);
2889 tcg_temp_free(temp2);
2890 tcg_temp_free(t_0);
2891 }
2892
2893 static void gen_shas(TCGv ret, TCGv r1, TCGv r2)
2894 {
2895 gen_helper_sha_ssov(ret, cpu_env, r1, r2);
2896 }
2897
2898 static void gen_shasi(TCGv ret, TCGv r1, int32_t con)
2899 {
2900 TCGv temp = tcg_const_i32(con);
2901 gen_shas(ret, r1, temp);
2902 tcg_temp_free(temp);
2903 }
2904
2905 static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count)
2906 {
2907 TCGv low, high;
2908
2909 if (shift_count == 0) {
2910 tcg_gen_mov_tl(ret, r1);
2911 } else if (shift_count > 0) {
2912 low = tcg_temp_new();
2913 high = tcg_temp_new();
2914
2915 tcg_gen_andi_tl(high, r1, 0xffff0000);
2916 tcg_gen_shli_tl(low, r1, shift_count);
2917 tcg_gen_shli_tl(ret, high, shift_count);
2918 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
2919
2920 tcg_temp_free(low);
2921 tcg_temp_free(high);
2922 } else {
2923 low = tcg_temp_new();
2924 high = tcg_temp_new();
2925
2926 tcg_gen_ext16s_tl(low, r1);
2927 tcg_gen_sari_tl(low, low, -shift_count);
2928 tcg_gen_sari_tl(ret, r1, -shift_count);
2929 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
2930
2931 tcg_temp_free(low);
2932 tcg_temp_free(high);
2933 }
2934
2935 }
2936
2937 /* ret = {ret[30:0], (r1 cond r2)}; */
2938 static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2)
2939 {
2940 TCGv temp = tcg_temp_new();
2941 TCGv temp2 = tcg_temp_new();
2942
2943 tcg_gen_shli_tl(temp, ret, 1);
2944 tcg_gen_setcond_tl(cond, temp2, r1, r2);
2945 tcg_gen_or_tl(ret, temp, temp2);
2946
2947 tcg_temp_free(temp);
2948 tcg_temp_free(temp2);
2949 }
2950
2951 static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con)
2952 {
2953 TCGv temp = tcg_const_i32(con);
2954 gen_sh_cond(cond, ret, r1, temp);
2955 tcg_temp_free(temp);
2956 }
2957
2958 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2)
2959 {
2960 gen_helper_add_ssov(ret, cpu_env, r1, r2);
2961 }
2962
2963 static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con)
2964 {
2965 TCGv temp = tcg_const_i32(con);
2966 gen_helper_add_ssov(ret, cpu_env, r1, temp);
2967 tcg_temp_free(temp);
2968 }
2969
2970 static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con)
2971 {
2972 TCGv temp = tcg_const_i32(con);
2973 gen_helper_add_suov(ret, cpu_env, r1, temp);
2974 tcg_temp_free(temp);
2975 }
2976
2977 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2)
2978 {
2979 gen_helper_sub_ssov(ret, cpu_env, r1, r2);
2980 }
2981
2982 static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2)
2983 {
2984 gen_helper_sub_suov(ret, cpu_env, r1, r2);
2985 }
2986
2987 static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2,
2988 int pos1, int pos2,
2989 void(*op1)(TCGv, TCGv, TCGv),
2990 void(*op2)(TCGv, TCGv, TCGv))
2991 {
2992 TCGv temp1, temp2;
2993
2994 temp1 = tcg_temp_new();
2995 temp2 = tcg_temp_new();
2996
2997 tcg_gen_shri_tl(temp2, r2, pos2);
2998 tcg_gen_shri_tl(temp1, r1, pos1);
2999
3000 (*op1)(temp1, temp1, temp2);
3001 (*op2)(temp1 , ret, temp1);
3002
3003 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1);
3004
3005 tcg_temp_free(temp1);
3006 tcg_temp_free(temp2);
3007 }
3008
3009 /* ret = r1[pos1] op1 r2[pos2]; */
3010 static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2,
3011 int pos1, int pos2,
3012 void(*op1)(TCGv, TCGv, TCGv))
3013 {
3014 TCGv temp1, temp2;
3015
3016 temp1 = tcg_temp_new();
3017 temp2 = tcg_temp_new();
3018
3019 tcg_gen_shri_tl(temp2, r2, pos2);
3020 tcg_gen_shri_tl(temp1, r1, pos1);
3021
3022 (*op1)(ret, temp1, temp2);
3023
3024 tcg_gen_andi_tl(ret, ret, 0x1);
3025
3026 tcg_temp_free(temp1);
3027 tcg_temp_free(temp2);
3028 }
3029
3030 static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2,
3031 void(*op)(TCGv, TCGv, TCGv))
3032 {
3033 TCGv temp = tcg_temp_new();
3034 TCGv temp2 = tcg_temp_new();
3035 /* temp = (arg1 cond arg2 )*/
3036 tcg_gen_setcond_tl(cond, temp, r1, r2);
3037 /* temp2 = ret[0]*/
3038 tcg_gen_andi_tl(temp2, ret, 0x1);
3039 /* temp = temp insn temp2 */
3040 (*op)(temp, temp, temp2);
3041 /* ret = {ret[31:1], temp} */
3042 tcg_gen_deposit_tl(ret, ret, temp, 0, 1);
3043
3044 tcg_temp_free(temp);
3045 tcg_temp_free(temp2);
3046 }
3047
3048 static inline void
3049 gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con,
3050 void(*op)(TCGv, TCGv, TCGv))
3051 {
3052 TCGv temp = tcg_const_i32(con);
3053 gen_accumulating_cond(cond, ret, r1, temp, op);
3054 tcg_temp_free(temp);
3055 }
3056
3057 /* ret = (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/
3058 static inline void gen_cond_w(TCGCond cond, TCGv ret, TCGv r1, TCGv r2)
3059 {
3060 tcg_gen_setcond_tl(cond, ret, r1, r2);
3061 tcg_gen_neg_tl(ret, ret);
3062 }
3063
3064 static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con)
3065 {
3066 TCGv b0 = tcg_temp_new();
3067 TCGv b1 = tcg_temp_new();
3068 TCGv b2 = tcg_temp_new();
3069 TCGv b3 = tcg_temp_new();
3070
3071 /* byte 0 */
3072 tcg_gen_andi_tl(b0, r1, 0xff);
3073 tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff);
3074
3075 /* byte 1 */
3076 tcg_gen_andi_tl(b1, r1, 0xff00);
3077 tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00);
3078
3079 /* byte 2 */
3080 tcg_gen_andi_tl(b2, r1, 0xff0000);
3081 tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000);
3082
3083 /* byte 3 */
3084 tcg_gen_andi_tl(b3, r1, 0xff000000);
3085 tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000);
3086
3087 /* combine them */
3088 tcg_gen_or_tl(ret, b0, b1);
3089 tcg_gen_or_tl(ret, ret, b2);
3090 tcg_gen_or_tl(ret, ret, b3);
3091
3092 tcg_temp_free(b0);
3093 tcg_temp_free(b1);
3094 tcg_temp_free(b2);
3095 tcg_temp_free(b3);
3096 }
3097
3098 static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con)
3099 {
3100 TCGv h0 = tcg_temp_new();
3101 TCGv h1 = tcg_temp_new();
3102
3103 /* halfword 0 */
3104 tcg_gen_andi_tl(h0, r1, 0xffff);
3105 tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff);
3106
3107 /* halfword 1 */
3108 tcg_gen_andi_tl(h1, r1, 0xffff0000);
3109 tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000);
3110
3111 /* combine them */
3112 tcg_gen_or_tl(ret, h0, h1);
3113
3114 tcg_temp_free(h0);
3115 tcg_temp_free(h1);
3116 }
3117 /* mask = ((1 << width) -1) << pos;
3118 ret = (r1 & ~mask) | (r2 << pos) & mask); */
3119 static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos)
3120 {
3121 TCGv mask = tcg_temp_new();
3122 TCGv temp = tcg_temp_new();
3123 TCGv temp2 = tcg_temp_new();
3124
3125 tcg_gen_movi_tl(mask, 1);
3126 tcg_gen_shl_tl(mask, mask, width);
3127 tcg_gen_subi_tl(mask, mask, 1);
3128 tcg_gen_shl_tl(mask, mask, pos);
3129
3130 tcg_gen_shl_tl(temp, r2, pos);
3131 tcg_gen_and_tl(temp, temp, mask);
3132 tcg_gen_andc_tl(temp2, r1, mask);
3133 tcg_gen_or_tl(ret, temp, temp2);
3134
3135 tcg_temp_free(mask);
3136 tcg_temp_free(temp);
3137 tcg_temp_free(temp2);
3138 }
3139
3140 static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1)
3141 {
3142 TCGv_i64 temp = tcg_temp_new_i64();
3143
3144 gen_helper_bsplit(temp, r1);
3145 tcg_gen_extr_i64_i32(rl, rh, temp);
3146
3147 tcg_temp_free_i64(temp);
3148 }
3149
3150 static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1)
3151 {
3152 TCGv_i64 temp = tcg_temp_new_i64();
3153
3154 gen_helper_unpack(temp, r1);
3155 tcg_gen_extr_i64_i32(rl, rh, temp);
3156
3157 tcg_temp_free_i64(temp);
3158 }
3159
3160 static inline void
3161 gen_dvinit_b(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
3162 {
3163 TCGv_i64 ret = tcg_temp_new_i64();
3164
3165 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
3166 gen_helper_dvinit_b_13(ret, cpu_env, r1, r2);
3167 } else {
3168 gen_helper_dvinit_b_131(ret, cpu_env, r1, r2);
3169 }
3170 tcg_gen_extr_i64_i32(rl, rh, ret);
3171
3172 tcg_temp_free_i64(ret);
3173 }
3174
3175 static inline void
3176 gen_dvinit_h(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
3177 {
3178 TCGv_i64 ret = tcg_temp_new_i64();
3179
3180 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
3181 gen_helper_dvinit_h_13(ret, cpu_env, r1, r2);
3182 } else {
3183 gen_helper_dvinit_h_131(ret, cpu_env, r1, r2);
3184 }
3185 tcg_gen_extr_i64_i32(rl, rh, ret);
3186
3187 tcg_temp_free_i64(ret);
3188 }
3189
3190 static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high)
3191 {
3192 TCGv temp = tcg_temp_new();
3193 /* calc AV bit */
3194 tcg_gen_add_tl(temp, arg_low, arg_low);
3195 tcg_gen_xor_tl(temp, temp, arg_low);
3196 tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high);
3197 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high);
3198 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
3199 /* calc SAV bit */
3200 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
3201 tcg_gen_movi_tl(cpu_PSW_V, 0);
3202 tcg_temp_free(temp);
3203 }
3204
3205 static void gen_calc_usb_mulr_h(TCGv arg)
3206 {
3207 TCGv temp = tcg_temp_new();
3208 /* calc AV bit */
3209 tcg_gen_add_tl(temp, arg, arg);
3210 tcg_gen_xor_tl(temp, temp, arg);
3211 tcg_gen_shli_tl(cpu_PSW_AV, temp, 16);
3212 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
3213 /* calc SAV bit */
3214 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
3215 /* clear V bit */
3216 tcg_gen_movi_tl(cpu_PSW_V, 0);
3217 tcg_temp_free(temp);
3218 }
3219
3220 /* helpers for generating program flow micro-ops */
3221
3222 static inline void gen_save_pc(target_ulong pc)
3223 {
3224 tcg_gen_movi_tl(cpu_PC, pc);
3225 }
3226
3227 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3228 {
3229 TranslationBlock *tb;
3230 tb = ctx->tb;
3231 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3232 likely(!ctx->singlestep_enabled)) {
3233 tcg_gen_goto_tb(n);
3234 gen_save_pc(dest);
3235 tcg_gen_exit_tb((uintptr_t)tb + n);
3236 } else {
3237 gen_save_pc(dest);
3238 if (ctx->singlestep_enabled) {
3239 /* raise exception debug */
3240 }
3241 tcg_gen_exit_tb(0);
3242 }
3243 }
3244
3245 static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
3246 TCGv r2, int16_t address)
3247 {
3248 TCGLabel *jumpLabel = gen_new_label();
3249 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel);
3250
3251 gen_goto_tb(ctx, 1, ctx->next_pc);
3252
3253 gen_set_label(jumpLabel);
3254 gen_goto_tb(ctx, 0, ctx->pc + address * 2);
3255 }
3256
3257 static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1,
3258 int r2, int16_t address)
3259 {
3260 TCGv temp = tcg_const_i32(r2);
3261 gen_branch_cond(ctx, cond, r1, temp, address);
3262 tcg_temp_free(temp);
3263 }
3264
3265 static void gen_loop(DisasContext *ctx, int r1, int32_t offset)
3266 {
3267 TCGLabel *l1 = gen_new_label();
3268
3269 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
3270 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1);
3271 gen_goto_tb(ctx, 1, ctx->pc + offset);
3272 gen_set_label(l1);
3273 gen_goto_tb(ctx, 0, ctx->next_pc);
3274 }
3275
3276 static void gen_fcall_save_ctx(DisasContext *ctx)
3277 {
3278 TCGv temp = tcg_temp_new();
3279
3280 tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4);
3281 tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL);
3282 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
3283 tcg_gen_mov_tl(cpu_gpr_a[10], temp);
3284
3285 tcg_temp_free(temp);
3286 }
3287
3288 static void gen_fret(DisasContext *ctx)
3289 {
3290 TCGv temp = tcg_temp_new();
3291
3292 tcg_gen_andi_tl(temp, cpu_gpr_a[11], ~0x1);
3293 tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL);
3294 tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4);
3295 tcg_gen_mov_tl(cpu_PC, temp);
3296 tcg_gen_exit_tb(0);
3297 ctx->bstate = BS_BRANCH;
3298
3299 tcg_temp_free(temp);
3300 }
3301
3302 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
3303 int r2 , int32_t constant , int32_t offset)
3304 {
3305 TCGv temp, temp2;
3306 int n;
3307
3308 switch (opc) {
3309 /* SB-format jumps */
3310 case OPC1_16_SB_J:
3311 case OPC1_32_B_J:
3312 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3313 break;
3314 case OPC1_32_B_CALL:
3315 case OPC1_16_SB_CALL:
3316 gen_helper_1arg(call, ctx->next_pc);
3317 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3318 break;
3319 case OPC1_16_SB_JZ:
3320 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset);
3321 break;
3322 case OPC1_16_SB_JNZ:
3323 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset);
3324 break;
3325 /* SBC-format jumps */
3326 case OPC1_16_SBC_JEQ:
3327 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);
3328 break;
3329 case OPC1_16_SBC_JNE:
3330 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
3331 break;
3332 /* SBRN-format jumps */
3333 case OPC1_16_SBRN_JZ_T:
3334 temp = tcg_temp_new();
3335 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
3336 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
3337 tcg_temp_free(temp);
3338 break;
3339 case OPC1_16_SBRN_JNZ_T:
3340 temp = tcg_temp_new();
3341 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
3342 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
3343 tcg_temp_free(temp);
3344 break;
3345 /* SBR-format jumps */
3346 case OPC1_16_SBR_JEQ:
3347 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
3348 offset);
3349 break;
3350 case OPC1_16_SBR_JNE:
3351 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
3352 offset);
3353 break;
3354 case OPC1_16_SBR_JNZ:
3355 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
3356 break;
3357 case OPC1_16_SBR_JNZ_A:
3358 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
3359 break;
3360 case OPC1_16_SBR_JGEZ:
3361 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset);
3362 break;
3363 case OPC1_16_SBR_JGTZ:
3364 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset);
3365 break;
3366 case OPC1_16_SBR_JLEZ:
3367 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset);
3368 break;
3369 case OPC1_16_SBR_JLTZ:
3370 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset);
3371 break;
3372 case OPC1_16_SBR_JZ:
3373 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset);
3374 break;
3375 case OPC1_16_SBR_JZ_A:
3376 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
3377 break;
3378 case OPC1_16_SBR_LOOP:
3379 gen_loop(ctx, r1, offset * 2 - 32);
3380 break;
3381 /* SR-format jumps */
3382 case OPC1_16_SR_JI:
3383 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe);
3384 tcg_gen_exit_tb(0);
3385 break;
3386 case OPC2_32_SYS_RET:
3387 case OPC2_16_SR_RET:
3388 gen_helper_ret(cpu_env);
3389 tcg_gen_exit_tb(0);
3390 break;
3391 /* B-format */
3392 case OPC1_32_B_CALLA:
3393 gen_helper_1arg(call, ctx->next_pc);
3394 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3395 break;
3396 case OPC1_32_B_FCALL:
3397 gen_fcall_save_ctx(ctx);
3398 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3399 break;
3400 case OPC1_32_B_FCALLA:
3401 gen_fcall_save_ctx(ctx);
3402 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3403 break;
3404 case OPC1_32_B_JLA:
3405 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
3406 /* fall through */
3407 case OPC1_32_B_JA:
3408 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3409 break;
3410 case OPC1_32_B_JL:
3411 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
3412 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3413 break;
3414 /* BOL format */
3415 case OPCM_32_BRC_EQ_NEQ:
3416 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) {
3417 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset);
3418 } else {
3419 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset);
3420 }
3421 break;
3422 case OPCM_32_BRC_GE:
3423 if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) {
3424 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset);
3425 } else {
3426 constant = MASK_OP_BRC_CONST4(ctx->opcode);
3427 gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant,
3428 offset);
3429 }
3430 break;
3431 case OPCM_32_BRC_JLT:
3432 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) {
3433 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset);
3434 } else {
3435 constant = MASK_OP_BRC_CONST4(ctx->opcode);
3436 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant,
3437 offset);
3438 }
3439 break;
3440 case OPCM_32_BRC_JNE:
3441 temp = tcg_temp_new();
3442 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) {
3443 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3444 /* subi is unconditional */
3445 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3446 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
3447 } else {
3448 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3449 /* addi is unconditional */
3450 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3451 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
3452 }
3453 tcg_temp_free(temp);
3454 break;
3455 /* BRN format */
3456 case OPCM_32_BRN_JTT:
3457 n = MASK_OP_BRN_N(ctx->opcode);
3458
3459 temp = tcg_temp_new();
3460 tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n));
3461
3462 if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) {
3463 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
3464 } else {
3465 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
3466 }
3467 tcg_temp_free(temp);
3468 break;
3469 /* BRR Format */
3470 case OPCM_32_BRR_EQ_NEQ:
3471 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) {
3472 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2],
3473 offset);
3474 } else {
3475 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
3476 offset);
3477 }
3478 break;
3479 case OPCM_32_BRR_ADDR_EQ_NEQ:
3480 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) {
3481 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2],
3482 offset);
3483 } else {
3484 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2],
3485 offset);
3486 }
3487 break;
3488 case OPCM_32_BRR_GE:
3489 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) {
3490 gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2],
3491 offset);
3492 } else {
3493 gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2],
3494 offset);
3495 }
3496 break;
3497 case OPCM_32_BRR_JLT:
3498 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) {
3499 gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2],
3500 offset);
3501 } else {
3502 gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2],
3503 offset);
3504 }
3505 break;
3506 case OPCM_32_BRR_LOOP:
3507 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) {
3508 gen_loop(ctx, r2, offset * 2);
3509 } else {
3510 /* OPC2_32_BRR_LOOPU */
3511 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3512 }
3513 break;
3514 case OPCM_32_BRR_JNE:
3515 temp = tcg_temp_new();
3516 temp2 = tcg_temp_new();
3517 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) {
3518 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3519 /* also save r2, in case of r1 == r2, so r2 is not decremented */
3520 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
3521 /* subi is unconditional */
3522 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3523 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
3524 } else {
3525 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3526 /* also save r2, in case of r1 == r2, so r2 is not decremented */
3527 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
3528 /* addi is unconditional */
3529 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3530 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
3531 }
3532 tcg_temp_free(temp);
3533 tcg_temp_free(temp2);
3534 break;
3535 case OPCM_32_BRR_JNZ:
3536 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) {
3537 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
3538 } else {
3539 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
3540 }
3541 break;
3542 default:
3543 printf("Branch Error at %x\n", ctx->pc);
3544 }
3545 ctx->bstate = BS_BRANCH;
3546 }
3547
3548
3549 /*
3550 * Functions for decoding instructions
3551 */
3552
3553 static void decode_src_opc(CPUTriCoreState *env, DisasContext *ctx, int op1)
3554 {
3555 int r1;
3556 int32_t const4;
3557 TCGv temp, temp2;
3558
3559 r1 = MASK_OP_SRC_S1D(ctx->opcode);
3560 const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode);
3561
3562 switch (op1) {
3563 case OPC1_16_SRC_ADD:
3564 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3565 break;
3566 case OPC1_16_SRC_ADD_A15:
3567 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4);
3568 break;
3569 case OPC1_16_SRC_ADD_15A:
3570 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4);
3571 break;
3572 case OPC1_16_SRC_ADD_A:
3573 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4);
3574 break;
3575 case OPC1_16_SRC_CADD:
3576 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
3577 cpu_gpr_d[15]);
3578 break;
3579 case OPC1_16_SRC_CADDN:
3580 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
3581 cpu_gpr_d[15]);
3582 break;
3583 case OPC1_16_SRC_CMOV:
3584 temp = tcg_const_tl(0);
3585 temp2 = tcg_const_tl(const4);
3586 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3587 temp2, cpu_gpr_d[r1]);
3588 tcg_temp_free(temp);
3589 tcg_temp_free(temp2);
3590 break;
3591 case OPC1_16_SRC_CMOVN:
3592 temp = tcg_const_tl(0);
3593 temp2 = tcg_const_tl(const4);
3594 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3595 temp2, cpu_gpr_d[r1]);
3596 tcg_temp_free(temp);
3597 tcg_temp_free(temp2);
3598 break;
3599 case OPC1_16_SRC_EQ:
3600 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
3601 const4);
3602 break;
3603 case OPC1_16_SRC_LT:
3604 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
3605 const4);
3606 break;
3607 case OPC1_16_SRC_MOV:
3608 tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
3609 break;
3610 case OPC1_16_SRC_MOV_A:
3611 const4 = MASK_OP_SRC_CONST4(ctx->opcode);
3612 tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
3613 break;
3614 case OPC1_16_SRC_MOV_E:
3615 if (tricore_feature(env, TRICORE_FEATURE_16)) {
3616 tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
3617 tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31);
3618 } /* TODO: else raise illegal opcode trap */
3619 break;
3620 case OPC1_16_SRC_SH:
3621 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3622 break;
3623 case OPC1_16_SRC_SHA:
3624 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3625 break;
3626 }
3627 }
3628
3629 static void decode_srr_opc(DisasContext *ctx, int op1)
3630 {
3631 int r1, r2;
3632 TCGv temp;
3633
3634 r1 = MASK_OP_SRR_S1D(ctx->opcode);
3635 r2 = MASK_OP_SRR_S2(ctx->opcode);
3636
3637 switch (op1) {
3638 case OPC1_16_SRR_ADD:
3639 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3640 break;
3641 case OPC1_16_SRR_ADD_A15:
3642 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
3643 break;
3644 case OPC1_16_SRR_ADD_15A:
3645 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3646 break;
3647 case OPC1_16_SRR_ADD_A:
3648 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
3649 break;
3650 case OPC1_16_SRR_ADDS:
3651 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3652 break;
3653 case OPC1_16_SRR_AND:
3654 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3655 break;
3656 case OPC1_16_SRR_CMOV:
3657 temp = tcg_const_tl(0);
3658 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3659 cpu_gpr_d[r2], cpu_gpr_d[r1]);
3660 tcg_temp_free(temp);
3661 break;
3662 case OPC1_16_SRR_CMOVN:
3663 temp = tcg_const_tl(0);
3664 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3665 cpu_gpr_d[r2], cpu_gpr_d[r1]);
3666 tcg_temp_free(temp);
3667 break;
3668 case OPC1_16_SRR_EQ:
3669 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
3670 cpu_gpr_d[r2]);
3671 break;
3672 case OPC1_16_SRR_LT:
3673 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
3674 cpu_gpr_d[r2]);
3675 break;
3676 case OPC1_16_SRR_MOV:
3677 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]);
3678 break;
3679 case OPC1_16_SRR_MOV_A:
3680 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]);
3681 break;
3682 case OPC1_16_SRR_MOV_AA:
3683 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]);
3684 break;
3685 case OPC1_16_SRR_MOV_D:
3686 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]);
3687 break;
3688 case OPC1_16_SRR_MUL:
3689 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3690 break;
3691 case OPC1_16_SRR_OR:
3692 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3693 break;
3694 case OPC1_16_SRR_SUB:
3695 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3696 break;
3697 case OPC1_16_SRR_SUB_A15B:
3698 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
3699 break;
3700 case OPC1_16_SRR_SUB_15AB:
3701 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3702 break;
3703 case OPC1_16_SRR_SUBS:
3704 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3705 break;
3706 case OPC1_16_SRR_XOR:
3707 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3708 break;
3709 }
3710 }
3711
3712 static void decode_ssr_opc(DisasContext *ctx, int op1)
3713 {
3714 int r1, r2;
3715
3716 r1 = MASK_OP_SSR_S1(ctx->opcode);
3717 r2 = MASK_OP_SSR_S2(ctx->opcode);
3718
3719 switch (op1) {
3720 case OPC1_16_SSR_ST_A:
3721 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3722 break;
3723 case OPC1_16_SSR_ST_A_POSTINC:
3724 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3725 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3726 break;
3727 case OPC1_16_SSR_ST_B:
3728 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3729 break;
3730 case OPC1_16_SSR_ST_B_POSTINC:
3731 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3732 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
3733 break;
3734 case OPC1_16_SSR_ST_H:
3735 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
3736 break;
3737 case OPC1_16_SSR_ST_H_POSTINC:
3738 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
3739 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
3740 break;
3741 case OPC1_16_SSR_ST_W:
3742 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3743 break;
3744 case OPC1_16_SSR_ST_W_POSTINC:
3745 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3746 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3747 break;
3748 }
3749 }
3750
3751 static void decode_sc_opc(DisasContext *ctx, int op1)
3752 {
3753 int32_t const16;
3754
3755 const16 = MASK_OP_SC_CONST8(ctx->opcode);
3756
3757 switch (op1) {
3758 case OPC1_16_SC_AND:
3759 tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
3760 break;
3761 case OPC1_16_SC_BISR:
3762 gen_helper_1arg(bisr, const16 & 0xff);
3763 break;
3764 case OPC1_16_SC_LD_A:
3765 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3766 break;
3767 case OPC1_16_SC_LD_W:
3768 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3769 break;
3770 case OPC1_16_SC_MOV:
3771 tcg_gen_movi_tl(cpu_gpr_d[15], const16);
3772 break;
3773 case OPC1_16_SC_OR:
3774 tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
3775 break;
3776 case OPC1_16_SC_ST_A:
3777 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3778 break;
3779 case OPC1_16_SC_ST_W:
3780 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3781 break;
3782 case OPC1_16_SC_SUB_A:
3783 tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
3784 break;
3785 }
3786 }
3787
3788 static void decode_slr_opc(DisasContext *ctx, int op1)
3789 {
3790 int r1, r2;
3791
3792 r1 = MASK_OP_SLR_D(ctx->opcode);
3793 r2 = MASK_OP_SLR_S2(ctx->opcode);
3794
3795 switch (op1) {
3796 /* SLR-format */
3797 case OPC1_16_SLR_LD_A:
3798 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3799 break;
3800 case OPC1_16_SLR_LD_A_POSTINC:
3801 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3802 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3803 break;
3804 case OPC1_16_SLR_LD_BU:
3805 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3806 break;
3807 case OPC1_16_SLR_LD_BU_POSTINC:
3808 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3809 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
3810 break;
3811 case OPC1_16_SLR_LD_H:
3812 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
3813 break;
3814 case OPC1_16_SLR_LD_H_POSTINC:
3815 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
3816 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
3817 break;
3818 case OPC1_16_SLR_LD_W:
3819 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3820 break;
3821 case OPC1_16_SLR_LD_W_POSTINC:
3822 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3823 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3824 break;
3825 }
3826 }
3827
3828 static void decode_sro_opc(DisasContext *ctx, int op1)
3829 {
3830 int r2;
3831 int32_t address;
3832
3833 r2 = MASK_OP_SRO_S2(ctx->opcode);
3834 address = MASK_OP_SRO_OFF4(ctx->opcode);
3835
3836 /* SRO-format */
3837 switch (op1) {
3838 case OPC1_16_SRO_LD_A:
3839 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3840 break;
3841 case OPC1_16_SRO_LD_BU:
3842 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
3843 break;
3844 case OPC1_16_SRO_LD_H:
3845 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW);
3846 break;
3847 case OPC1_16_SRO_LD_W:
3848 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3849 break;
3850 case OPC1_16_SRO_ST_A:
3851 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3852 break;
3853 case OPC1_16_SRO_ST_B:
3854 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
3855 break;
3856 case OPC1_16_SRO_ST_H:
3857 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
3858 break;
3859 case OPC1_16_SRO_ST_W:
3860 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3861 break;
3862 }
3863 }
3864
3865 static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx)
3866 {
3867 uint32_t op2;
3868 op2 = MASK_OP_SR_OP2(ctx->opcode);
3869
3870 switch (op2) {
3871 case OPC2_16_SR_NOP:
3872 break;
3873 case OPC2_16_SR_RET:
3874 gen_compute_branch(ctx, op2, 0, 0, 0, 0);
3875 break;
3876 case OPC2_16_SR_RFE:
3877 gen_helper_rfe(cpu_env);
3878 tcg_gen_exit_tb(0);
3879 ctx->bstate = BS_BRANCH;
3880 break;
3881 case OPC2_16_SR_DEBUG:
3882 /* raise EXCP_DEBUG */
3883 break;
3884 case OPC2_16_SR_FRET:
3885 gen_fret(ctx);
3886 }
3887 }
3888
3889 static void decode_sr_accu(CPUTriCoreState *env, DisasContext *ctx)
3890 {
3891 uint32_t op2;
3892 uint32_t r1;
3893 TCGv temp;
3894
3895 r1 = MASK_OP_SR_S1D(ctx->opcode);
3896 op2 = MASK_OP_SR_OP2(ctx->opcode);
3897
3898 switch (op2) {
3899 case OPC2_16_SR_RSUB:
3900 /* overflow only if r1 = -0x80000000 */
3901 temp = tcg_const_i32(-0x80000000);
3902 /* calc V bit */
3903 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp);
3904 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
3905 /* calc SV bit */
3906 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
3907 /* sub */
3908 tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
3909 /* calc av */
3910 tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]);
3911 tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV);
3912 /* calc sav */
3913 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
3914 tcg_temp_free(temp);
3915 break;
3916 case OPC2_16_SR_SAT_B:
3917 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80);
3918 break;
3919 case OPC2_16_SR_SAT_BU:
3920 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff);
3921 break;
3922 case OPC2_16_SR_SAT_H:
3923 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000);
3924 break;
3925 case OPC2_16_SR_SAT_HU:
3926 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff);
3927 break;
3928 }
3929 }
3930
3931 static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
3932 {
3933 int op1;
3934 int r1, r2;
3935 int32_t const16;
3936 int32_t address;
3937 TCGv temp;
3938
3939 op1 = MASK_OP_MAJOR(ctx->opcode);
3940
3941 /* handle ADDSC.A opcode only being 6 bit long */
3942 if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) {
3943 op1 = OPC1_16_SRRS_ADDSC_A;
3944 }
3945
3946 switch (op1) {
3947 case OPC1_16_SRC_ADD:
3948 case OPC1_16_SRC_ADD_A15:
3949 case OPC1_16_SRC_ADD_15A:
3950 case OPC1_16_SRC_ADD_A:
3951 case OPC1_16_SRC_CADD:
3952 case OPC1_16_SRC_CADDN:
3953 case OPC1_16_SRC_CMOV:
3954 case OPC1_16_SRC_CMOVN:
3955 case OPC1_16_SRC_EQ:
3956 case OPC1_16_SRC_LT:
3957 case OPC1_16_SRC_MOV:
3958 case OPC1_16_SRC_MOV_A:
3959 case OPC1_16_SRC_MOV_E:
3960 case OPC1_16_SRC_SH:
3961 case OPC1_16_SRC_SHA:
3962 decode_src_opc(env, ctx, op1);
3963 break;
3964 /* SRR-format */
3965 case OPC1_16_SRR_ADD:
3966 case OPC1_16_SRR_ADD_A15:
3967 case OPC1_16_SRR_ADD_15A:
3968 case OPC1_16_SRR_ADD_A:
3969 case OPC1_16_SRR_ADDS:
3970 case OPC1_16_SRR_AND:
3971 case OPC1_16_SRR_CMOV:
3972 case OPC1_16_SRR_CMOVN:
3973 case OPC1_16_SRR_EQ:
3974 case OPC1_16_SRR_LT:
3975 case OPC1_16_SRR_MOV:
3976 case OPC1_16_SRR_MOV_A:
3977 case OPC1_16_SRR_MOV_AA:
3978 case OPC1_16_SRR_MOV_D:
3979 case OPC1_16_SRR_MUL:
3980 case OPC1_16_SRR_OR:
3981 case OPC1_16_SRR_SUB:
3982 case OPC1_16_SRR_SUB_A15B:
3983 case OPC1_16_SRR_SUB_15AB:
3984 case OPC1_16_SRR_SUBS:
3985 case OPC1_16_SRR_XOR:
3986 decode_srr_opc(ctx, op1);
3987 break;
3988 /* SSR-format */
3989 case OPC1_16_SSR_ST_A:
3990 case OPC1_16_SSR_ST_A_POSTINC:
3991 case OPC1_16_SSR_ST_B:
3992 case OPC1_16_SSR_ST_B_POSTINC:
3993 case OPC1_16_SSR_ST_H:
3994 case OPC1_16_SSR_ST_H_POSTINC:
3995 case OPC1_16_SSR_ST_W:
3996 case OPC1_16_SSR_ST_W_POSTINC:
3997 decode_ssr_opc(ctx, op1);
3998 break;
3999 /* SRRS-format */
4000 case OPC1_16_SRRS_ADDSC_A:
4001 r2 = MASK_OP_SRRS_S2(ctx->opcode);
4002 r1 = MASK_OP_SRRS_S1D(ctx->opcode);
4003 const16 = MASK_OP_SRRS_N(ctx->opcode);
4004 temp = tcg_temp_new();
4005 tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16);
4006 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp);
4007 tcg_temp_free(temp);
4008 break;
4009 /* SLRO-format */
4010 case OPC1_16_SLRO_LD_A:
4011 r1 = MASK_OP_SLRO_D(ctx->opcode);
4012 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
4013 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
4014 break;
4015 case OPC1_16_SLRO_LD_BU:
4016 r1 = MASK_OP_SLRO_D(ctx->opcode);
4017 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
4018 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
4019 break;
4020 case OPC1_16_SLRO_LD_H:
4021 r1 = MASK_OP_SLRO_D(ctx->opcode);
4022 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
4023 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
4024 break;
4025 case OPC1_16_SLRO_LD_W:
4026 r1 = MASK_OP_SLRO_D(ctx->opcode);
4027 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
4028 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
4029 break;
4030 /* SB-format */
4031 case OPC1_16_SB_CALL:
4032 case OPC1_16_SB_J:
4033 case OPC1_16_SB_JNZ:
4034 case OPC1_16_SB_JZ:
4035 address = MASK_OP_SB_DISP8_SEXT(ctx->opcode);
4036 gen_compute_branch(ctx, op1, 0, 0, 0, address);
4037 break;
4038 /* SBC-format */
4039 case OPC1_16_SBC_JEQ:
4040 case OPC1_16_SBC_JNE:
4041 address = MASK_OP_SBC_DISP4(ctx->opcode);
4042 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
4043 gen_compute_branch(ctx, op1, 0, 0, const16, address);
4044 break;
4045 /* SBRN-format */
4046 case OPC1_16_SBRN_JNZ_T:
4047 case OPC1_16_SBRN_JZ_T:
4048 address = MASK_OP_SBRN_DISP4(ctx->opcode);
4049 const16 = MASK_OP_SBRN_N(ctx->opcode);
4050 gen_compute_branch(ctx, op1, 0, 0, const16, address);
4051 break;
4052 /* SBR-format */
4053 case OPC1_16_SBR_JEQ:
4054 case OPC1_16_SBR_JGEZ:
4055 case OPC1_16_SBR_JGTZ:
4056 case OPC1_16_SBR_JLEZ:
4057 case OPC1_16_SBR_JLTZ:
4058 case OPC1_16_SBR_JNE:
4059 case OPC1_16_SBR_JNZ:
4060 case OPC1_16_SBR_JNZ_A:
4061 case OPC1_16_SBR_JZ:
4062 case OPC1_16_SBR_JZ_A:
4063 case OPC1_16_SBR_LOOP:
4064 r1 = MASK_OP_SBR_S2(ctx->opcode);
4065 address = MASK_OP_SBR_DISP4(ctx->opcode);
4066 gen_compute_branch(ctx, op1, r1, 0, 0, address);
4067 break;
4068 /* SC-format */
4069 case OPC1_16_SC_AND:
4070 case OPC1_16_SC_BISR:
4071 case OPC1_16_SC_LD_A:
4072 case OPC1_16_SC_LD_W:
4073 case OPC1_16_SC_MOV:
4074 case OPC1_16_SC_OR:
4075 case OPC1_16_SC_ST_A:
4076 case OPC1_16_SC_ST_W:
4077 case OPC1_16_SC_SUB_A:
4078 decode_sc_opc(ctx, op1);
4079 break;
4080 /* SLR-format */
4081 case OPC1_16_SLR_LD_A:
4082 case OPC1_16_SLR_LD_A_POSTINC:
4083 case OPC1_16_SLR_LD_BU:
4084 case OPC1_16_SLR_LD_BU_POSTINC:
4085 case OPC1_16_SLR_LD_H:
4086 case OPC1_16_SLR_LD_H_POSTINC:
4087 case OPC1_16_SLR_LD_W:
4088 case OPC1_16_SLR_LD_W_POSTINC:
4089 decode_slr_opc(ctx, op1);
4090 break;
4091 /* SRO-format */
4092 case OPC1_16_SRO_LD_A:
4093 case OPC1_16_SRO_LD_BU:
4094 case OPC1_16_SRO_LD_H:
4095 case OPC1_16_SRO_LD_W:
4096 case OPC1_16_SRO_ST_A:
4097 case OPC1_16_SRO_ST_B:
4098 case OPC1_16_SRO_ST_H:
4099 case OPC1_16_SRO_ST_W:
4100 decode_sro_opc(ctx, op1);
4101 break;
4102 /* SSRO-format */
4103 case OPC1_16_SSRO_ST_A:
4104 r1 = MASK_OP_SSRO_S1(ctx->opcode);
4105 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
4106 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
4107 break;
4108 case OPC1_16_SSRO_ST_B:
4109 r1 = MASK_OP_SSRO_S1(ctx->opcode);
4110 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
4111 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
4112 break;
4113 case OPC1_16_SSRO_ST_H:
4114 r1 = MASK_OP_SSRO_S1(ctx->opcode);
4115 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
4116 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
4117 break;
4118 case OPC1_16_SSRO_ST_W:
4119 r1 = MASK_OP_SSRO_S1(ctx->opcode);
4120 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
4121 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
4122 break;
4123 /* SR-format */
4124 case OPCM_16_SR_SYSTEM:
4125 decode_sr_system(env, ctx);
4126 break;
4127 case OPCM_16_SR_ACCU:
4128 decode_sr_accu(env, ctx);
4129 break;
4130 case OPC1_16_SR_JI:
4131 r1 = MASK_OP_SR_S1D(ctx->opcode);
4132 gen_compute_branch(ctx, op1, r1, 0, 0, 0);
4133 break;
4134 case OPC1_16_SR_NOT:
4135 r1 = MASK_OP_SR_S1D(ctx->opcode);
4136 tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
4137 break;
4138 }
4139 }
4140
4141 /*
4142 * 32 bit instructions
4143 */
4144
4145 /* ABS-format */
4146 static void decode_abs_ldw(CPUTriCoreState *env, DisasContext *ctx)
4147 {
4148 int32_t op2;
4149 int32_t r1;
4150 uint32_t address;
4151 TCGv temp;
4152
4153 r1 = MASK_OP_ABS_S1D(ctx->opcode);
4154 address = MASK_OP_ABS_OFF18(ctx->opcode);
4155 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4156
4157 temp = tcg_const_i32(EA_ABS_FORMAT(address));
4158
4159 switch (op2) {
4160 case OPC2_32_ABS_LD_A:
4161 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
4162 break;
4163 case OPC2_32_ABS_LD_D:
4164 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4165 break;
4166 case OPC2_32_ABS_LD_DA:
4167 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4168 break;
4169 case OPC2_32_ABS_LD_W:
4170 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
4171 break;
4172 }
4173
4174 tcg_temp_free(temp);
4175 }
4176
4177 static void decode_abs_ldb(CPUTriCoreState *env, DisasContext *ctx)
4178 {
4179 int32_t op2;
4180 int32_t r1;
4181 uint32_t address;
4182 TCGv temp;
4183
4184 r1 = MASK_OP_ABS_S1D(ctx->opcode);
4185 address = MASK_OP_ABS_OFF18(ctx->opcode);
4186 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4187
4188 temp = tcg_const_i32(EA_ABS_FORMAT(address));
4189
4190 switch (op2) {
4191 case OPC2_32_ABS_LD_B:
4192 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB);
4193 break;
4194 case OPC2_32_ABS_LD_BU:
4195 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
4196 break;
4197 case OPC2_32_ABS_LD_H:
4198 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW);
4199 break;
4200 case OPC2_32_ABS_LD_HU:
4201 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
4202 break;
4203 }
4204
4205 tcg_temp_free(temp);
4206 }
4207
4208 static void decode_abs_ldst_swap(CPUTriCoreState *env, DisasContext *ctx)
4209 {
4210 int32_t op2;
4211 int32_t r1;
4212 uint32_t address;
4213 TCGv temp;
4214
4215 r1 = MASK_OP_ABS_S1D(ctx->opcode);
4216 address = MASK_OP_ABS_OFF18(ctx->opcode);
4217 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4218
4219 temp = tcg_const_i32(EA_ABS_FORMAT(address));
4220
4221 switch (op2) {
4222 case OPC2_32_ABS_LDMST:
4223 gen_ldmst(ctx, r1, temp);
4224 break;
4225 case OPC2_32_ABS_SWAP_W:
4226 gen_swap(ctx, r1, temp);
4227 break;
4228 }
4229
4230 tcg_temp_free(temp);
4231 }
4232
4233 static void decode_abs_ldst_context(CPUTriCoreState *env, DisasContext *ctx)
4234 {
4235 uint32_t op2;
4236 int32_t off18;
4237
4238 off18 = MASK_OP_ABS_OFF18(ctx->opcode);
4239 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4240
4241 switch (op2) {
4242 case OPC2_32_ABS_LDLCX:
4243 gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18));
4244 break;
4245 case OPC2_32_ABS_LDUCX:
4246 gen_helper_1arg(lducx, EA_ABS_FORMAT(off18));
4247 break;
4248 case OPC2_32_ABS_STLCX:
4249 gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18));
4250 break;
4251 case OPC2_32_ABS_STUCX:
4252 gen_helper_1arg(stucx, EA_ABS_FORMAT(off18));
4253 break;
4254 }
4255 }
4256
4257 static void decode_abs_store(CPUTriCoreState *env, DisasContext *ctx)
4258 {
4259 int32_t op2;
4260 int32_t r1;
4261 uint32_t address;
4262 TCGv temp;
4263
4264 r1 = MASK_OP_ABS_S1D(ctx->opcode);
4265 address = MASK_OP_ABS_OFF18(ctx->opcode);
4266 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4267
4268 temp = tcg_const_i32(EA_ABS_FORMAT(address));
4269
4270 switch (op2) {
4271 case OPC2_32_ABS_ST_A:
4272 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
4273 break;
4274 case OPC2_32_ABS_ST_D:
4275 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4276 break;
4277 case OPC2_32_ABS_ST_DA:
4278 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4279 break;
4280 case OPC2_32_ABS_ST_W:
4281 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
4282 break;
4283
4284 }
4285 tcg_temp_free(temp);
4286 }
4287
4288 static void decode_abs_storeb_h(CPUTriCoreState *env, DisasContext *ctx)
4289 {
4290 int32_t op2;
4291 int32_t r1;
4292 uint32_t address;
4293 TCGv temp;
4294
4295 r1 = MASK_OP_ABS_S1D(ctx->opcode);
4296 address = MASK_OP_ABS_OFF18(ctx->opcode);
4297 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4298
4299 temp = tcg_const_i32(EA_ABS_FORMAT(address));
4300
4301 switch (op2) {
4302 case OPC2_32_ABS_ST_B:
4303 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
4304 break;
4305 case OPC2_32_ABS_ST_H:
4306 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
4307 break;
4308 }
4309 tcg_temp_free(temp);
4310 }
4311
4312 /* Bit-format */
4313
4314 static void decode_bit_andacc(CPUTriCoreState *env, DisasContext *ctx)
4315 {
4316 uint32_t op2;
4317 int r1, r2, r3;
4318 int pos1, pos2;
4319
4320 r1 = MASK_OP_BIT_S1(ctx->opcode);
4321 r2 = MASK_OP_BIT_S2(ctx->opcode);
4322 r3 = MASK_OP_BIT_D(ctx->opcode);
4323 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4324 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4325 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4326
4327
4328 switch (op2) {
4329 case OPC2_32_BIT_AND_AND_T:
4330 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4331 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl);
4332 break;
4333 case OPC2_32_BIT_AND_ANDN_T:
4334 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4335 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl);
4336 break;
4337 case OPC2_32_BIT_AND_NOR_T:
4338 if (TCG_TARGET_HAS_andc_i32) {
4339 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4340 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl);
4341 } else {
4342 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4343 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl);
4344 }
4345 break;
4346 case OPC2_32_BIT_AND_OR_T:
4347 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4348 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl);
4349 break;
4350 }
4351 }
4352
4353 static void decode_bit_logical_t(CPUTriCoreState *env, DisasContext *ctx)
4354 {
4355 uint32_t op2;
4356 int r1, r2, r3;
4357 int pos1, pos2;
4358 r1 = MASK_OP_BIT_S1(ctx->opcode);
4359 r2 = MASK_OP_BIT_S2(ctx->opcode);
4360 r3 = MASK_OP_BIT_D(ctx->opcode);
4361 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4362 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4363 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4364
4365 switch (op2) {
4366 case OPC2_32_BIT_AND_T:
4367 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4368 pos1, pos2, &tcg_gen_and_tl);
4369 break;
4370 case OPC2_32_BIT_ANDN_T:
4371 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4372 pos1, pos2, &tcg_gen_andc_tl);
4373 break;
4374 case OPC2_32_BIT_NOR_T:
4375 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4376 pos1, pos2, &tcg_gen_nor_tl);
4377 break;
4378 case OPC2_32_BIT_OR_T:
4379 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4380 pos1, pos2, &tcg_gen_or_tl);
4381 break;
4382 }
4383 }
4384
4385 static void decode_bit_insert(CPUTriCoreState *env, DisasContext *ctx)
4386 {
4387 uint32_t op2;
4388 int r1, r2, r3;
4389 int pos1, pos2;
4390 TCGv temp;
4391 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4392 r1 = MASK_OP_BIT_S1(ctx->opcode);
4393 r2 = MASK_OP_BIT_S2(ctx->opcode);
4394 r3 = MASK_OP_BIT_D(ctx->opcode);
4395 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4396 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4397
4398 temp = tcg_temp_new();
4399
4400 tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2);
4401 if (op2 == OPC2_32_BIT_INSN_T) {
4402 tcg_gen_not_tl(temp, temp);
4403 }
4404 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1);
4405 tcg_temp_free(temp);
4406 }
4407
4408 static void decode_bit_logical_t2(CPUTriCoreState *env, DisasContext *ctx)
4409 {
4410 uint32_t op2;
4411
4412 int r1, r2, r3;
4413 int pos1, pos2;
4414
4415 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4416 r1 = MASK_OP_BIT_S1(ctx->opcode);
4417 r2 = MASK_OP_BIT_S2(ctx->opcode);
4418 r3 = MASK_OP_BIT_D(ctx->opcode);
4419 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4420 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4421
4422 switch (op2) {
4423 case OPC2_32_BIT_NAND_T:
4424 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4425 pos1, pos2, &tcg_gen_nand_tl);
4426 break;
4427 case OPC2_32_BIT_ORN_T:
4428 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4429 pos1, pos2, &tcg_gen_orc_tl);
4430 break;
4431 case OPC2_32_BIT_XNOR_T:
4432 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4433 pos1, pos2, &tcg_gen_eqv_tl);
4434 break;
4435 case OPC2_32_BIT_XOR_T:
4436 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4437 pos1, pos2, &tcg_gen_xor_tl);
4438 break;
4439 }
4440 }
4441
4442 static void decode_bit_orand(CPUTriCoreState *env, DisasContext *ctx)
4443 {
4444 uint32_t op2;
4445
4446 int r1, r2, r3;
4447 int pos1, pos2;
4448
4449 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4450 r1 = MASK_OP_BIT_S1(ctx->opcode);
4451 r2 = MASK_OP_BIT_S2(ctx->opcode);
4452 r3 = MASK_OP_BIT_D(ctx->opcode);
4453 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4454 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4455
4456 switch (op2) {
4457 case OPC2_32_BIT_OR_AND_T:
4458 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4459 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl);
4460 break;
4461 case OPC2_32_BIT_OR_ANDN_T:
4462 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4463 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl);
4464 break;
4465 case OPC2_32_BIT_OR_NOR_T:
4466 if (TCG_TARGET_HAS_orc_i32) {
4467 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4468 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl);
4469 } else {
4470 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4471 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl);
4472 }
4473 break;
4474 case OPC2_32_BIT_OR_OR_T:
4475 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4476 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl);
4477 break;
4478 }
4479 }
4480
4481 static void decode_bit_sh_logic1(CPUTriCoreState *env, DisasContext *ctx)
4482 {
4483 uint32_t op2;
4484 int r1, r2, r3;
4485 int pos1, pos2;
4486 TCGv temp;
4487
4488 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4489 r1 = MASK_OP_BIT_S1(ctx->opcode);
4490 r2 = MASK_OP_BIT_S2(ctx->opcode);
4491 r3 = MASK_OP_BIT_D(ctx->opcode);
4492 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4493 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4494
4495 temp = tcg_temp_new();
4496
4497 switch (op2) {
4498 case OPC2_32_BIT_SH_AND_T:
4499 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4500 pos1, pos2, &tcg_gen_and_tl);
4501 break;
4502 case OPC2_32_BIT_SH_ANDN_T:
4503 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4504 pos1, pos2, &tcg_gen_andc_tl);
4505 break;
4506 case OPC2_32_BIT_SH_NOR_T:
4507 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4508 pos1, pos2, &tcg_gen_nor_tl);
4509 break;
4510 case OPC2_32_BIT_SH_OR_T:
4511 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4512 pos1, pos2, &tcg_gen_or_tl);
4513 break;
4514 }
4515 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
4516 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
4517 tcg_temp_free(temp);
4518 }
4519
4520 static void decode_bit_sh_logic2(CPUTriCoreState *env, DisasContext *ctx)
4521 {
4522 uint32_t op2;
4523 int r1, r2, r3;
4524 int pos1, pos2;
4525 TCGv temp;
4526
4527 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4528 r1 = MASK_OP_BIT_S1(ctx->opcode);
4529 r2 = MASK_OP_BIT_S2(ctx->opcode);
4530 r3 = MASK_OP_BIT_D(ctx->opcode);
4531 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4532 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4533
4534 temp = tcg_temp_new();
4535
4536 switch (op2) {
4537 case OPC2_32_BIT_SH_NAND_T:
4538 gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] ,
4539 pos1, pos2, &tcg_gen_nand_tl);
4540 break;
4541 case OPC2_32_BIT_SH_ORN_T:
4542 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4543 pos1, pos2, &tcg_gen_orc_tl);
4544 break;
4545 case OPC2_32_BIT_SH_XNOR_T:
4546 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4547 pos1, pos2, &tcg_gen_eqv_tl);
4548 break;
4549 case OPC2_32_BIT_SH_XOR_T:
4550 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4551 pos1, pos2, &tcg_gen_xor_tl);
4552 break;
4553 }
4554 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
4555 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
4556 tcg_temp_free(temp);
4557 }
4558
4559 /* BO-format */
4560
4561
4562 static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env,
4563 DisasContext *ctx)
4564 {
4565 uint32_t op2;
4566 uint32_t off10;
4567 int32_t r1, r2;
4568 TCGv temp;
4569
4570 r1 = MASK_OP_BO_S1D(ctx->opcode);
4571 r2 = MASK_OP_BO_S2(ctx->opcode);
4572 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4573 op2 = MASK_OP_BO_OP2(ctx->opcode);
4574
4575 switch (op2) {
4576 case OPC2_32_BO_CACHEA_WI_SHORTOFF:
4577 case OPC2_32_BO_CACHEA_W_SHORTOFF:
4578 case OPC2_32_BO_CACHEA_I_SHORTOFF:
4579 /* instruction to access the cache */
4580 break;
4581 case OPC2_32_BO_CACHEA_WI_POSTINC:
4582 case OPC2_32_BO_CACHEA_W_POSTINC:
4583 case OPC2_32_BO_CACHEA_I_POSTINC:
4584 /* instruction to access the cache, but we still need to handle
4585 the addressing mode */
4586 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4587 break;
4588 case OPC2_32_BO_CACHEA_WI_PREINC:
4589 case OPC2_32_BO_CACHEA_W_PREINC:
4590 case OPC2_32_BO_CACHEA_I_PREINC:
4591 /* instruction to access the cache, but we still need to handle
4592 the addressing mode */
4593 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4594 break;
4595 case OPC2_32_BO_CACHEI_WI_SHORTOFF:
4596 case OPC2_32_BO_CACHEI_W_SHORTOFF:
4597 /* TODO: Raise illegal opcode trap,
4598 if !tricore_feature(TRICORE_FEATURE_131) */
4599 break;
4600 case OPC2_32_BO_CACHEI_W_POSTINC:
4601 case OPC2_32_BO_CACHEI_WI_POSTINC:
4602 if (tricore_feature(env, TRICORE_FEATURE_131)) {
4603 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4604 } /* TODO: else raise illegal opcode trap */
4605 break;
4606 case OPC2_32_BO_CACHEI_W_PREINC:
4607 case OPC2_32_BO_CACHEI_WI_PREINC:
4608 if (tricore_feature(env, TRICORE_FEATURE_131)) {
4609 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4610 } /* TODO: else raise illegal opcode trap */
4611 break;
4612 case OPC2_32_BO_ST_A_SHORTOFF:
4613 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
4614 break;
4615 case OPC2_32_BO_ST_A_POSTINC:
4616 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
4617 MO_LESL);
4618 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4619 break;
4620 case OPC2_32_BO_ST_A_PREINC:
4621 gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
4622 break;
4623 case OPC2_32_BO_ST_B_SHORTOFF:
4624 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4625 break;
4626 case OPC2_32_BO_ST_B_POSTINC:
4627 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4628 MO_UB);
4629 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4630 break;
4631 case OPC2_32_BO_ST_B_PREINC:
4632 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4633 break;
4634 case OPC2_32_BO_ST_D_SHORTOFF:
4635 gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
4636 off10, ctx);
4637 break;
4638 case OPC2_32_BO_ST_D_POSTINC:
4639 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
4640 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4641 break;
4642 case OPC2_32_BO_ST_D_PREINC:
4643 temp = tcg_temp_new();
4644 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4645 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4646 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4647 tcg_temp_free(temp);
4648 break;
4649 case OPC2_32_BO_ST_DA_SHORTOFF:
4650 gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
4651 off10, ctx);
4652 break;
4653 case OPC2_32_BO_ST_DA_POSTINC:
4654 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
4655 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4656 break;
4657 case OPC2_32_BO_ST_DA_PREINC:
4658 temp = tcg_temp_new();
4659 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4660 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4661 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4662 tcg_temp_free(temp);
4663 break;
4664 case OPC2_32_BO_ST_H_SHORTOFF:
4665 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4666 break;
4667 case OPC2_32_BO_ST_H_POSTINC:
4668 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4669 MO_LEUW);
4670 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4671 break;
4672 case OPC2_32_BO_ST_H_PREINC:
4673 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4674 break;
4675 case OPC2_32_BO_ST_Q_SHORTOFF:
4676 temp = tcg_temp_new();
4677 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4678 gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
4679 tcg_temp_free(temp);
4680 break;
4681 case OPC2_32_BO_ST_Q_POSTINC:
4682 temp = tcg_temp_new();
4683 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4684 tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx,
4685 MO_LEUW);
4686 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4687 tcg_temp_free(temp);
4688 break;
4689 case OPC2_32_BO_ST_Q_PREINC:
4690 temp = tcg_temp_new();
4691 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4692 gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
4693 tcg_temp_free(temp);
4694 break;
4695 case OPC2_32_BO_ST_W_SHORTOFF:
4696 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4697 break;
4698 case OPC2_32_BO_ST_W_POSTINC:
4699 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4700 MO_LEUL);
4701 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4702 break;
4703 case OPC2_32_BO_ST_W_PREINC:
4704 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4705 break;
4706 }
4707 }
4708
4709 static void decode_bo_addrmode_bitreverse_circular(CPUTriCoreState *env,
4710 DisasContext *ctx)
4711 {
4712 uint32_t op2;
4713 uint32_t off10;
4714 int32_t r1, r2;
4715 TCGv temp, temp2, temp3;
4716
4717 r1 = MASK_OP_BO_S1D(ctx->opcode);
4718 r2 = MASK_OP_BO_S2(ctx->opcode);
4719 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4720 op2 = MASK_OP_BO_OP2(ctx->opcode);
4721
4722 temp = tcg_temp_new();
4723 temp2 = tcg_temp_new();
4724 temp3 = tcg_const_i32(off10);
4725
4726 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
4727 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4728
4729 switch (op2) {
4730 case OPC2_32_BO_CACHEA_WI_BR:
4731 case OPC2_32_BO_CACHEA_W_BR:
4732 case OPC2_32_BO_CACHEA_I_BR:
4733 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4734 break;
4735 case OPC2_32_BO_CACHEA_WI_CIRC:
4736 case OPC2_32_BO_CACHEA_W_CIRC:
4737 case OPC2_32_BO_CACHEA_I_CIRC:
4738 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4739 break;
4740 case OPC2_32_BO_ST_A_BR:
4741 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4742 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4743 break;
4744 case OPC2_32_BO_ST_A_CIRC:
4745 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4746 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4747 break;
4748 case OPC2_32_BO_ST_B_BR:
4749 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4750 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4751 break;
4752 case OPC2_32_BO_ST_B_CIRC:
4753 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4754 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4755 break;
4756 case OPC2_32_BO_ST_D_BR:
4757 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
4758 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4759 break;
4760 case OPC2_32_BO_ST_D_CIRC:
4761 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4762 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4763 tcg_gen_addi_tl(temp, temp, 4);
4764 tcg_gen_rem_tl(temp, temp, temp2);
4765 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4766 tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4767 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4768 break;
4769 case OPC2_32_BO_ST_DA_BR:
4770 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
4771 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4772 break;
4773 case OPC2_32_BO_ST_DA_CIRC:
4774 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4775 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4776 tcg_gen_addi_tl(temp, temp, 4);
4777 tcg_gen_rem_tl(temp, temp, temp2);
4778 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4779 tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4780 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4781 break;
4782 case OPC2_32_BO_ST_H_BR:
4783 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4784 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4785 break;
4786 case OPC2_32_BO_ST_H_CIRC:
4787 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4788 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4789 break;
4790 case OPC2_32_BO_ST_Q_BR:
4791 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4792 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
4793 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4794 break;
4795 case OPC2_32_BO_ST_Q_CIRC:
4796 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4797 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
4798 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4799 break;
4800 case OPC2_32_BO_ST_W_BR:
4801 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4802 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4803 break;
4804 case OPC2_32_BO_ST_W_CIRC:
4805 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4806 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4807 break;
4808 }
4809 tcg_temp_free(temp);
4810 tcg_temp_free(temp2);
4811 tcg_temp_free(temp3);
4812 }
4813
4814 static void decode_bo_addrmode_ld_post_pre_base(CPUTriCoreState *env,
4815 DisasContext *ctx)
4816 {
4817 uint32_t op2;
4818 uint32_t off10;
4819 int32_t r1, r2;
4820 TCGv temp;
4821
4822 r1 = MASK_OP_BO_S1D(ctx->opcode);
4823 r2 = MASK_OP_BO_S2(ctx->opcode);
4824 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4825 op2 = MASK_OP_BO_OP2(ctx->opcode);
4826
4827 switch (op2) {
4828 case OPC2_32_BO_LD_A_SHORTOFF:
4829 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4830 break;
4831 case OPC2_32_BO_LD_A_POSTINC:
4832 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
4833 MO_LEUL);
4834 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4835 break;
4836 case OPC2_32_BO_LD_A_PREINC:
4837 gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4838 break;
4839 case OPC2_32_BO_LD_B_SHORTOFF:
4840 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4841 break;
4842 case OPC2_32_BO_LD_B_POSTINC:
4843 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4844 MO_SB);
4845 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4846 break;
4847 case OPC2_32_BO_LD_B_PREINC:
4848 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4849 break;
4850 case OPC2_32_BO_LD_BU_SHORTOFF:
4851 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4852 break;
4853 case OPC2_32_BO_LD_BU_POSTINC:
4854 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4855 MO_UB);
4856 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4857 break;
4858 case OPC2_32_BO_LD_BU_PREINC:
4859 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4860 break;
4861 case OPC2_32_BO_LD_D_SHORTOFF:
4862 gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
4863 off10, ctx);
4864 break;
4865 case OPC2_32_BO_LD_D_POSTINC:
4866 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
4867 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4868 break;
4869 case OPC2_32_BO_LD_D_PREINC:
4870 temp = tcg_temp_new();
4871 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4872 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4873 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4874 tcg_temp_free(temp);
4875 break;
4876 case OPC2_32_BO_LD_DA_SHORTOFF:
4877 gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
4878 off10, ctx);
4879 break;
4880 case OPC2_32_BO_LD_DA_POSTINC:
4881 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
4882 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4883 break;
4884 case OPC2_32_BO_LD_DA_PREINC:
4885 temp = tcg_temp_new();
4886 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4887 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4888 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4889 tcg_temp_free(temp);
4890 break;
4891 case OPC2_32_BO_LD_H_SHORTOFF:
4892 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
4893 break;
4894 case OPC2_32_BO_LD_H_POSTINC:
4895 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4896 MO_LESW);
4897 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4898 break;
4899 case OPC2_32_BO_LD_H_PREINC:
4900 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
4901 break;
4902 case OPC2_32_BO_LD_HU_SHORTOFF:
4903 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4904 break;
4905 case OPC2_32_BO_LD_HU_POSTINC:
4906 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4907 MO_LEUW);
4908 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4909 break;
4910 case OPC2_32_BO_LD_HU_PREINC:
4911 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4912 break;
4913 case OPC2_32_BO_LD_Q_SHORTOFF:
4914 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4915 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4916 break;
4917 case OPC2_32_BO_LD_Q_POSTINC:
4918 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4919 MO_LEUW);
4920 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4921 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4922 break;
4923 case OPC2_32_BO_LD_Q_PREINC:
4924 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4925 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4926 break;
4927 case OPC2_32_BO_LD_W_SHORTOFF:
4928 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4929 break;
4930 case OPC2_32_BO_LD_W_POSTINC:
4931 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4932 MO_LEUL);
4933 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4934 break;
4935 case OPC2_32_BO_LD_W_PREINC:
4936 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4937 break;
4938 }
4939 }
4940
4941 static void decode_bo_addrmode_ld_bitreverse_circular(CPUTriCoreState *env,
4942 DisasContext *ctx)
4943 {
4944 uint32_t op2;
4945 uint32_t off10;
4946 int r1, r2;
4947
4948 TCGv temp, temp2, temp3;
4949
4950 r1 = MASK_OP_BO_S1D(ctx->opcode);
4951 r2 = MASK_OP_BO_S2(ctx->opcode);
4952 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4953 op2 = MASK_OP_BO_OP2(ctx->opcode);
4954
4955 temp = tcg_temp_new();
4956 temp2 = tcg_temp_new();
4957 temp3 = tcg_const_i32(off10);
4958
4959 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
4960 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4961
4962
4963 switch (op2) {
4964 case OPC2_32_BO_LD_A_BR:
4965 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4966 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4967 break;
4968 case OPC2_32_BO_LD_A_CIRC:
4969 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4970 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4971 break;
4972 case OPC2_32_BO_LD_B_BR:
4973 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
4974 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4975 break;
4976 case OPC2_32_BO_LD_B_CIRC:
4977 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
4978 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4979 break;
4980 case OPC2_32_BO_LD_BU_BR:
4981 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4982 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4983 break;
4984 case OPC2_32_BO_LD_BU_CIRC:
4985 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4986 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4987 break;
4988 case OPC2_32_BO_LD_D_BR:
4989 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
4990 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4991 break;
4992 case OPC2_32_BO_LD_D_CIRC:
4993 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4994 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4995 tcg_gen_addi_tl(temp, temp, 4);
4996 tcg_gen_rem_tl(temp, temp, temp2);
4997 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4998 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4999 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5000 break;
5001 case OPC2_32_BO_LD_DA_BR:
5002 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
5003 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5004 break;
5005 case OPC2_32_BO_LD_DA_CIRC:
5006 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
5007 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
5008 tcg_gen_addi_tl(temp, temp, 4);
5009 tcg_gen_rem_tl(temp, temp, temp2);
5010 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
5011 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
5012 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5013 break;
5014 case OPC2_32_BO_LD_H_BR:
5015 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
5016 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5017 break;
5018 case OPC2_32_BO_LD_H_CIRC:
5019 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
5020 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5021 break;
5022 case OPC2_32_BO_LD_HU_BR:
5023 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
5024 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5025 break;
5026 case OPC2_32_BO_LD_HU_CIRC:
5027 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
5028 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5029 break;
5030 case OPC2_32_BO_LD_Q_BR:
5031 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
5032 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
5033 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5034 break;
5035 case OPC2_32_BO_LD_Q_CIRC:
5036 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
5037 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
5038 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5039 break;
5040 case OPC2_32_BO_LD_W_BR:
5041 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
5042 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5043 break;
5044 case OPC2_32_BO_LD_W_CIRC:
5045 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
5046 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5047 break;
5048 }
5049 tcg_temp_free(temp);
5050 tcg_temp_free(temp2);
5051 tcg_temp_free(temp3);
5052 }
5053
5054 static void decode_bo_addrmode_stctx_post_pre_base(CPUTriCoreState *env,
5055 DisasContext *ctx)
5056 {
5057 uint32_t op2;
5058 uint32_t off10;
5059 int r1, r2;
5060
5061 TCGv temp, temp2;
5062
5063 r1 = MASK_OP_BO_S1D(ctx->opcode);
5064 r2 = MASK_OP_BO_S2(ctx->opcode);
5065 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
5066 op2 = MASK_OP_BO_OP2(ctx->opcode);
5067
5068
5069 temp = tcg_temp_new();
5070 temp2 = tcg_temp_new();
5071
5072 switch (op2) {
5073 case OPC2_32_BO_LDLCX_SHORTOFF:
5074 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5075 gen_helper_ldlcx(cpu_env, temp);
5076 break;
5077 case OPC2_32_BO_LDMST_SHORTOFF:
5078 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5079 gen_ldmst(ctx, r1, temp);
5080 break;
5081 case OPC2_32_BO_LDMST_POSTINC:
5082 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
5083 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5084 break;
5085 case OPC2_32_BO_LDMST_PREINC:
5086 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5087 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
5088 break;
5089 case OPC2_32_BO_LDUCX_SHORTOFF:
5090 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5091 gen_helper_lducx(cpu_env, temp);
5092 break;
5093 case OPC2_32_BO_LEA_SHORTOFF:
5094 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10);
5095 break;
5096 case OPC2_32_BO_STLCX_SHORTOFF:
5097 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5098 gen_helper_stlcx(cpu_env, temp);
5099 break;
5100 case OPC2_32_BO_STUCX_SHORTOFF:
5101 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5102 gen_helper_stucx(cpu_env, temp);
5103 break;
5104 case OPC2_32_BO_SWAP_W_SHORTOFF:
5105 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5106 gen_swap(ctx, r1, temp);
5107 break;
5108 case OPC2_32_BO_SWAP_W_POSTINC:
5109 gen_swap(ctx, r1, cpu_gpr_a[r2]);
5110 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5111 break;
5112 case OPC2_32_BO_SWAP_W_PREINC:
5113 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5114 gen_swap(ctx, r1, cpu_gpr_a[r2]);
5115 break;
5116 case OPC2_32_BO_CMPSWAP_W_SHORTOFF:
5117 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5118 gen_cmpswap(ctx, r1, temp);
5119 break;
5120 case OPC2_32_BO_CMPSWAP_W_POSTINC:
5121 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]);
5122 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5123 break;
5124 case OPC2_32_BO_CMPSWAP_W_PREINC:
5125 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5126 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]);
5127 break;
5128 case OPC2_32_BO_SWAPMSK_W_SHORTOFF:
5129 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5130 gen_swapmsk(ctx, r1, temp);
5131 break;
5132 case OPC2_32_BO_SWAPMSK_W_POSTINC:
5133 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
5134 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5135 break;
5136 case OPC2_32_BO_SWAPMSK_W_PREINC:
5137 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5138 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
5139 break;
5140 }
5141 tcg_temp_free(temp);
5142 tcg_temp_free(temp2);
5143 }
5144
5145 static void decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState *env,
5146 DisasContext *ctx)
5147 {
5148 uint32_t op2;
5149 uint32_t off10;
5150 int r1, r2;
5151
5152 TCGv temp, temp2, temp3;
5153
5154 r1 = MASK_OP_BO_S1D(ctx->opcode);
5155 r2 = MASK_OP_BO_S2(ctx->opcode);
5156 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
5157 op2 = MASK_OP_BO_OP2(ctx->opcode);
5158
5159 temp = tcg_temp_new();
5160 temp2 = tcg_temp_new();
5161 temp3 = tcg_const_i32(off10);
5162
5163 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
5164 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
5165
5166 switch (op2) {
5167 case OPC2_32_BO_LDMST_BR:
5168 gen_ldmst(ctx, r1, temp2);
5169 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5170 break;
5171 case OPC2_32_BO_LDMST_CIRC:
5172 gen_ldmst(ctx, r1, temp2);
5173 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5174 break;
5175 case OPC2_32_BO_SWAP_W_BR:
5176 gen_swap(ctx, r1, temp2);
5177 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5178 break;
5179 case OPC2_32_BO_SWAP_W_CIRC:
5180 gen_swap(ctx, r1, temp2);
5181 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5182 break;
5183 case OPC2_32_BO_CMPSWAP_W_BR:
5184 gen_cmpswap(ctx, r1, temp2);
5185 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5186 break;
5187 case OPC2_32_BO_CMPSWAP_W_CIRC:
5188 gen_cmpswap(ctx, r1, temp2);
5189 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5190 break;
5191 case OPC2_32_BO_SWAPMSK_W_BR:
5192 gen_swapmsk(ctx, r1, temp2);
5193 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5194 break;
5195 case OPC2_32_BO_SWAPMSK_W_CIRC:
5196 gen_swapmsk(ctx, r1, temp2);
5197 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5198 break;
5199 }
5200
5201 tcg_temp_free(temp);
5202 tcg_temp_free(temp2);
5203 tcg_temp_free(temp3);
5204 }
5205
5206 static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1)
5207 {
5208 int r1, r2;
5209 int32_t address;
5210 TCGv temp;
5211
5212 r1 = MASK_OP_BOL_S1D(ctx->opcode);
5213 r2 = MASK_OP_BOL_S2(ctx->opcode);
5214 address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode);
5215
5216 switch (op1) {
5217 case OPC1_32_BOL_LD_A_LONGOFF:
5218 temp = tcg_temp_new();
5219 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
5220 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL);
5221 tcg_temp_free(temp);
5222 break;
5223 case OPC1_32_BOL_LD_W_LONGOFF:
5224 temp = tcg_temp_new();
5225 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
5226 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL);
5227 tcg_temp_free(temp);
5228 break;
5229 case OPC1_32_BOL_LEA_LONGOFF:
5230 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address);
5231 break;
5232 case OPC1_32_BOL_ST_A_LONGOFF:
5233 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5234 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL);
5235 } else {
5236 /* raise illegal opcode trap */
5237 }
5238 break;
5239 case OPC1_32_BOL_ST_W_LONGOFF:
5240 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL);
5241 break;
5242 case OPC1_32_BOL_LD_B_LONGOFF:
5243 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5244 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
5245 } else {
5246 /* raise illegal opcode trap */
5247 }
5248 break;
5249 case OPC1_32_BOL_LD_BU_LONGOFF:
5250 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5251 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB);
5252 } else {
5253 /* raise illegal opcode trap */
5254 }
5255 break;
5256 case OPC1_32_BOL_LD_H_LONGOFF:
5257 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5258 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
5259 } else {
5260 /* raise illegal opcode trap */
5261 }
5262 break;
5263 case OPC1_32_BOL_LD_HU_LONGOFF:
5264 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5265 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW);
5266 } else {
5267 /* raise illegal opcode trap */
5268 }
5269 break;
5270 case OPC1_32_BOL_ST_B_LONGOFF:
5271 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5272 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
5273 } else {
5274 /* raise illegal opcode trap */
5275 }
5276 break;
5277 case OPC1_32_BOL_ST_H_LONGOFF:
5278 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5279 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
5280 } else {
5281 /* raise illegal opcode trap */
5282 }
5283 break;
5284 }
5285 }
5286
5287 /* RC format */
5288 static void decode_rc_logical_shift(CPUTriCoreState *env, DisasContext *ctx)
5289 {
5290 uint32_t op2;
5291 int r1, r2;
5292 int32_t const9;
5293 TCGv temp;
5294
5295 r2 = MASK_OP_RC_D(ctx->opcode);
5296 r1 = MASK_OP_RC_S1(ctx->opcode);
5297 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5298 op2 = MASK_OP_RC_OP2(ctx->opcode);
5299
5300 temp = tcg_temp_new();
5301
5302 switch (op2) {
5303 case OPC2_32_RC_AND:
5304 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5305 break;
5306 case OPC2_32_RC_ANDN:
5307 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
5308 break;
5309 case OPC2_32_RC_NAND:
5310 tcg_gen_movi_tl(temp, const9);
5311 tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
5312 break;
5313 case OPC2_32_RC_NOR:
5314 tcg_gen_movi_tl(temp, const9);
5315 tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
5316 break;
5317 case OPC2_32_RC_OR:
5318 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5319 break;
5320 case OPC2_32_RC_ORN:
5321 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
5322 break;
5323 case OPC2_32_RC_SH:
5324 const9 = sextract32(const9, 0, 6);
5325 gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5326 break;
5327 case OPC2_32_RC_SH_H:
5328 const9 = sextract32(const9, 0, 5);
5329 gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5330 break;
5331 case OPC2_32_RC_SHA:
5332 const9 = sextract32(const9, 0, 6);
5333 gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5334 break;
5335 case OPC2_32_RC_SHA_H:
5336 const9 = sextract32(const9, 0, 5);
5337 gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5338 break;
5339 case OPC2_32_RC_SHAS:
5340 gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5341 break;
5342 case OPC2_32_RC_XNOR:
5343 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5344 tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]);
5345 break;
5346 case OPC2_32_RC_XOR:
5347 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5348 break;
5349 }
5350 tcg_temp_free(temp);
5351 }
5352
5353 static void decode_rc_accumulator(CPUTriCoreState *env, DisasContext *ctx)
5354 {
5355 uint32_t op2;
5356 int r1, r2;
5357 int16_t const9;
5358
5359 TCGv temp;
5360
5361 r2 = MASK_OP_RC_D(ctx->opcode);
5362 r1 = MASK_OP_RC_S1(ctx->opcode);
5363 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
5364
5365 op2 = MASK_OP_RC_OP2(ctx->opcode);
5366
5367 temp = tcg_temp_new();
5368
5369 switch (op2) {
5370 case OPC2_32_RC_ABSDIF:
5371 gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5372 break;
5373 case OPC2_32_RC_ABSDIFS:
5374 gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5375 break;
5376 case OPC2_32_RC_ADD:
5377 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5378 break;
5379 case OPC2_32_RC_ADDC:
5380 gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5381 break;
5382 case OPC2_32_RC_ADDS:
5383 gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5384 break;
5385 case OPC2_32_RC_ADDS_U:
5386 gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5387 break;
5388 case OPC2_32_RC_ADDX:
5389 gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5390 break;
5391 case OPC2_32_RC_AND_EQ:
5392 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5393 const9, &tcg_gen_and_tl);
5394 break;
5395 case OPC2_32_RC_AND_GE:
5396 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5397 const9, &tcg_gen_and_tl);
5398 break;
5399 case OPC2_32_RC_AND_GE_U:
5400 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5401 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5402 const9, &tcg_gen_and_tl);
5403 break;
5404 case OPC2_32_RC_AND_LT:
5405 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5406 const9, &tcg_gen_and_tl);
5407 break;
5408 case OPC2_32_RC_AND_LT_U:
5409 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5410 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5411 const9, &tcg_gen_and_tl);
5412 break;
5413 case OPC2_32_RC_AND_NE:
5414 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5415 const9, &tcg_gen_and_tl);
5416 break;
5417 case OPC2_32_RC_EQ:
5418 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5419 break;
5420 case OPC2_32_RC_EQANY_B:
5421 gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5422 break;
5423 case OPC2_32_RC_EQANY_H:
5424 gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5425 break;
5426 case OPC2_32_RC_GE:
5427 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5428 break;
5429 case OPC2_32_RC_GE_U:
5430 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5431 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5432 break;
5433 case OPC2_32_RC_LT:
5434 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5435 break;
5436 case OPC2_32_RC_LT_U:
5437 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5438 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5439 break;
5440 case OPC2_32_RC_MAX:
5441 tcg_gen_movi_tl(temp, const9);
5442 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5443 cpu_gpr_d[r1], temp);
5444 break;
5445 case OPC2_32_RC_MAX_U:
5446 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
5447 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5448 cpu_gpr_d[r1], temp);
5449 break;
5450 case OPC2_32_RC_MIN:
5451 tcg_gen_movi_tl(temp, const9);
5452 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5453 cpu_gpr_d[r1], temp);
5454 break;
5455 case OPC2_32_RC_MIN_U:
5456 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
5457 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5458 cpu_gpr_d[r1], temp);
5459 break;
5460 case OPC2_32_RC_NE:
5461 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5462 break;
5463 case OPC2_32_RC_OR_EQ:
5464 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5465 const9, &tcg_gen_or_tl);
5466 break;
5467 case OPC2_32_RC_OR_GE:
5468 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5469 const9, &tcg_gen_or_tl);
5470 break;
5471 case OPC2_32_RC_OR_GE_U:
5472 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5473 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5474 const9, &tcg_gen_or_tl);
5475 break;
5476 case OPC2_32_RC_OR_LT:
5477 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5478 const9, &tcg_gen_or_tl);
5479 break;
5480 case OPC2_32_RC_OR_LT_U:
5481 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5482 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5483 const9, &tcg_gen_or_tl);
5484 break;
5485 case OPC2_32_RC_OR_NE:
5486 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5487 const9, &tcg_gen_or_tl);
5488 break;
5489 case OPC2_32_RC_RSUB:
5490 tcg_gen_movi_tl(temp, const9);
5491 gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5492 break;
5493 case OPC2_32_RC_RSUBS:
5494 tcg_gen_movi_tl(temp, const9);
5495 gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5496 break;
5497 case OPC2_32_RC_RSUBS_U:
5498 tcg_gen_movi_tl(temp, const9);
5499 gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5500 break;
5501 case OPC2_32_RC_SH_EQ:
5502 gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5503 break;
5504 case OPC2_32_RC_SH_GE:
5505 gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5506 break;
5507 case OPC2_32_RC_SH_GE_U:
5508 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5509 gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5510 break;
5511 case OPC2_32_RC_SH_LT:
5512 gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5513 break;
5514 case OPC2_32_RC_SH_LT_U:
5515 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5516 gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5517 break;
5518 case OPC2_32_RC_SH_NE:
5519 gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5520 break;
5521 case OPC2_32_RC_XOR_EQ:
5522 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5523 const9, &tcg_gen_xor_tl);
5524 break;
5525 case OPC2_32_RC_XOR_GE:
5526 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5527 const9, &tcg_gen_xor_tl);
5528 break;
5529 case OPC2_32_RC_XOR_GE_U:
5530 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5531 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5532 const9, &tcg_gen_xor_tl);
5533 break;
5534 case OPC2_32_RC_XOR_LT:
5535 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5536 const9, &tcg_gen_xor_tl);
5537 break;
5538 case OPC2_32_RC_XOR_LT_U:
5539 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5540 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5541 const9, &tcg_gen_xor_tl);
5542 break;
5543 case OPC2_32_RC_XOR_NE:
5544 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5545 const9, &tcg_gen_xor_tl);
5546 break;
5547 }
5548 tcg_temp_free(temp);
5549 }
5550
5551 static void decode_rc_serviceroutine(CPUTriCoreState *env, DisasContext *ctx)
5552 {
5553 uint32_t op2;
5554 uint32_t const9;
5555
5556 op2 = MASK_OP_RC_OP2(ctx->opcode);
5557 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5558
5559 switch (op2) {
5560 case OPC2_32_RC_BISR:
5561 gen_helper_1arg(bisr, const9);
5562 break;
5563 case OPC2_32_RC_SYSCALL:
5564 /* TODO: Add exception generation */
5565 break;
5566 }
5567 }
5568
5569 static void decode_rc_mul(CPUTriCoreState *env, DisasContext *ctx)
5570 {
5571 uint32_t op2;
5572 int r1, r2;
5573 int16_t const9;
5574
5575 r2 = MASK_OP_RC_D(ctx->opcode);
5576 r1 = MASK_OP_RC_S1(ctx->opcode);
5577 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
5578
5579 op2 = MASK_OP_RC_OP2(ctx->opcode);
5580
5581 switch (op2) {
5582 case OPC2_32_RC_MUL_32:
5583 gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5584 break;
5585 case OPC2_32_RC_MUL_64:
5586 gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
5587 break;
5588 case OPC2_32_RC_MULS_32:
5589 gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5590 break;
5591 case OPC2_32_RC_MUL_U_64:
5592 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5593 gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
5594 break;
5595 case OPC2_32_RC_MULS_U_32:
5596 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5597 gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5598 break;
5599 }
5600 }
5601
5602 /* RCPW format */
5603 static void decode_rcpw_insert(CPUTriCoreState *env, DisasContext *ctx)
5604 {
5605 uint32_t op2;
5606 int r1, r2;
5607 int32_t pos, width, const4;
5608
5609 TCGv temp;
5610
5611 op2 = MASK_OP_RCPW_OP2(ctx->opcode);
5612 r1 = MASK_OP_RCPW_S1(ctx->opcode);
5613 r2 = MASK_OP_RCPW_D(ctx->opcode);
5614 const4 = MASK_OP_RCPW_CONST4(ctx->opcode);
5615 width = MASK_OP_RCPW_WIDTH(ctx->opcode);
5616 pos = MASK_OP_RCPW_POS(ctx->opcode);
5617
5618 switch (op2) {
5619 case OPC2_32_RCPW_IMASK:
5620 /* if pos + width > 31 undefined result */
5621 if (pos + width <= 31) {
5622 tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos);
5623 tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos));
5624 }
5625 break;
5626 case OPC2_32_RCPW_INSERT:
5627 /* if pos + width > 32 undefined result */
5628 if (pos + width <= 32) {
5629 temp = tcg_const_i32(const4);
5630 tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width);
5631 tcg_temp_free(temp);
5632 }
5633 break;
5634 }
5635 }
5636
5637 /* RCRW format */
5638
5639 static void decode_rcrw_insert(CPUTriCoreState *env, DisasContext *ctx)
5640 {
5641 uint32_t op2;
5642 int r1, r3, r4;
5643 int32_t width, const4;
5644
5645 TCGv temp, temp2, temp3;
5646
5647 op2 = MASK_OP_RCRW_OP2(ctx->opcode);
5648 r1 = MASK_OP_RCRW_S1(ctx->opcode);
5649 r3 = MASK_OP_RCRW_S3(ctx->opcode);
5650 r4 = MASK_OP_RCRW_D(ctx->opcode);
5651 width = MASK_OP_RCRW_WIDTH(ctx->opcode);
5652 const4 = MASK_OP_RCRW_CONST4(ctx->opcode);
5653
5654 temp = tcg_temp_new();
5655 temp2 = tcg_temp_new();
5656
5657 switch (op2) {
5658 case OPC2_32_RCRW_IMASK:
5659 tcg_gen_andi_tl(temp, cpu_gpr_d[r4], 0x1f);
5660 tcg_gen_movi_tl(temp2, (1 << width) - 1);
5661 tcg_gen_shl_tl(cpu_gpr_d[r3 + 1], temp2, temp);
5662 tcg_gen_movi_tl(temp2, const4);
5663 tcg_gen_shl_tl(cpu_gpr_d[r3], temp2, temp);
5664 break;
5665 case OPC2_32_RCRW_INSERT:
5666 temp3 = tcg_temp_new();
5667
5668 tcg_gen_movi_tl(temp, width);
5669 tcg_gen_movi_tl(temp2, const4);
5670 tcg_gen_andi_tl(temp3, cpu_gpr_d[r4], 0x1f);
5671 gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp2, temp, temp3);
5672
5673 tcg_temp_free(temp3);
5674 break;
5675 }
5676 tcg_temp_free(temp);
5677 tcg_temp_free(temp2);
5678 }
5679
5680 /* RCR format */
5681
5682 static void decode_rcr_cond_select(CPUTriCoreState *env, DisasContext *ctx)
5683 {
5684 uint32_t op2;
5685 int r1, r3, r4;
5686 int32_t const9;
5687
5688 TCGv temp, temp2;
5689
5690 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5691 r1 = MASK_OP_RCR_S1(ctx->opcode);
5692 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5693 r3 = MASK_OP_RCR_S3(ctx->opcode);
5694 r4 = MASK_OP_RCR_D(ctx->opcode);
5695
5696 switch (op2) {
5697 case OPC2_32_RCR_CADD:
5698 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const9, cpu_gpr_d[r3],
5699 cpu_gpr_d[r4]);
5700 break;
5701 case OPC2_32_RCR_CADDN:
5702 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const9, cpu_gpr_d[r3],
5703 cpu_gpr_d[r4]);
5704 break;
5705 case OPC2_32_RCR_SEL:
5706 temp = tcg_const_i32(0);
5707 temp2 = tcg_const_i32(const9);
5708 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
5709 cpu_gpr_d[r1], temp2);
5710 tcg_temp_free(temp);
5711 tcg_temp_free(temp2);
5712 break;
5713 case OPC2_32_RCR_SELN:
5714 temp = tcg_const_i32(0);
5715 temp2 = tcg_const_i32(const9);
5716 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
5717 cpu_gpr_d[r1], temp2);
5718 tcg_temp_free(temp);
5719 tcg_temp_free(temp2);
5720 break;
5721 }
5722 }
5723
5724 static void decode_rcr_madd(CPUTriCoreState *env, DisasContext *ctx)
5725 {
5726 uint32_t op2;
5727 int r1, r3, r4;
5728 int32_t const9;
5729
5730
5731 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5732 r1 = MASK_OP_RCR_S1(ctx->opcode);
5733 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5734 r3 = MASK_OP_RCR_S3(ctx->opcode);
5735 r4 = MASK_OP_RCR_D(ctx->opcode);
5736
5737 switch (op2) {
5738 case OPC2_32_RCR_MADD_32:
5739 gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5740 break;
5741 case OPC2_32_RCR_MADD_64:
5742 gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5743 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5744 break;
5745 case OPC2_32_RCR_MADDS_32:
5746 gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5747 break;
5748 case OPC2_32_RCR_MADDS_64:
5749 gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5750 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5751 break;
5752 case OPC2_32_RCR_MADD_U_64:
5753 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5754 gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5755 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5756 break;
5757 case OPC2_32_RCR_MADDS_U_32:
5758 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5759 gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5760 break;
5761 case OPC2_32_RCR_MADDS_U_64:
5762 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5763 gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5764 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5765 break;
5766 }
5767 }
5768
5769 static void decode_rcr_msub(CPUTriCoreState *env, DisasContext *ctx)
5770 {
5771 uint32_t op2;
5772 int r1, r3, r4;
5773 int32_t const9;
5774
5775
5776 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5777 r1 = MASK_OP_RCR_S1(ctx->opcode);
5778 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5779 r3 = MASK_OP_RCR_S3(ctx->opcode);
5780 r4 = MASK_OP_RCR_D(ctx->opcode);
5781
5782 switch (op2) {
5783 case OPC2_32_RCR_MSUB_32:
5784 gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5785 break;
5786 case OPC2_32_RCR_MSUB_64:
5787 gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5788 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5789 break;
5790 case OPC2_32_RCR_MSUBS_32:
5791 gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5792 break;
5793 case OPC2_32_RCR_MSUBS_64:
5794 gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5795 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5796 break;
5797 case OPC2_32_RCR_MSUB_U_64:
5798 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5799 gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5800 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5801 break;
5802 case OPC2_32_RCR_MSUBS_U_32:
5803 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5804 gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5805 break;
5806 case OPC2_32_RCR_MSUBS_U_64:
5807 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5808 gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5809 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5810 break;
5811 }
5812 }
5813
5814 /* RLC format */
5815
5816 static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx,
5817 uint32_t op1)
5818 {
5819 int32_t const16;
5820 int r1, r2;
5821
5822 const16 = MASK_OP_RLC_CONST16_SEXT(ctx->opcode);
5823 r1 = MASK_OP_RLC_S1(ctx->opcode);
5824 r2 = MASK_OP_RLC_D(ctx->opcode);
5825
5826 switch (op1) {
5827 case OPC1_32_RLC_ADDI:
5828 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16);
5829 break;
5830 case OPC1_32_RLC_ADDIH:
5831 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16);
5832 break;
5833 case OPC1_32_RLC_ADDIH_A:
5834 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16);
5835 break;
5836 case OPC1_32_RLC_MFCR:
5837 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
5838 gen_mfcr(env, cpu_gpr_d[r2], const16);
5839 break;
5840 case OPC1_32_RLC_MOV:
5841 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5842 break;
5843 case OPC1_32_RLC_MOV_64:
5844 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5845 if ((r2 & 0x1) != 0) {
5846 /* TODO: raise OPD trap */
5847 }
5848 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5849 tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15);
5850 } else {
5851 /* TODO: raise illegal opcode trap */
5852 }
5853 break;
5854 case OPC1_32_RLC_MOV_U:
5855 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
5856 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5857 break;
5858 case OPC1_32_RLC_MOV_H:
5859 tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16);
5860 break;
5861 case OPC1_32_RLC_MOVH_A:
5862 tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16);
5863 break;
5864 case OPC1_32_RLC_MTCR:
5865 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
5866 gen_mtcr(env, ctx, cpu_gpr_d[r1], const16);
5867 break;
5868 }
5869 }
5870
5871 /* RR format */
5872 static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx)
5873 {
5874 uint32_t op2;
5875 int r3, r2, r1;
5876
5877 r3 = MASK_OP_RR_D(ctx->opcode);
5878 r2 = MASK_OP_RR_S2(ctx->opcode);
5879 r1 = MASK_OP_RR_S1(ctx->opcode);
5880 op2 = MASK_OP_RR_OP2(ctx->opcode);
5881
5882 switch (op2) {
5883 case OPC2_32_RR_ABS:
5884 gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]);
5885 break;
5886 case OPC2_32_RR_ABS_B:
5887 gen_helper_abs_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5888 break;
5889 case OPC2_32_RR_ABS_H:
5890 gen_helper_abs_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5891 break;
5892 case OPC2_32_RR_ABSDIF:
5893 gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5894 break;
5895 case OPC2_32_RR_ABSDIF_B:
5896 gen_helper_absdif_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5897 cpu_gpr_d[r2]);
5898 break;
5899 case OPC2_32_RR_ABSDIF_H:
5900 gen_helper_absdif_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5901 cpu_gpr_d[r2]);
5902 break;
5903 case OPC2_32_RR_ABSDIFS:
5904 gen_helper_absdif_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5905 cpu_gpr_d[r2]);
5906 break;
5907 case OPC2_32_RR_ABSDIFS_H:
5908 gen_helper_absdif_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5909 cpu_gpr_d[r2]);
5910 break;
5911 case OPC2_32_RR_ABSS:
5912 gen_helper_abs_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5913 break;
5914 case OPC2_32_RR_ABSS_H:
5915 gen_helper_abs_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5916 break;
5917 case OPC2_32_RR_ADD:
5918 gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5919 break;
5920 case OPC2_32_RR_ADD_B:
5921 gen_helper_add_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5922 break;
5923 case OPC2_32_RR_ADD_H:
5924 gen_helper_add_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5925 break;
5926 case OPC2_32_RR_ADDC:
5927 gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5928 break;
5929 case OPC2_32_RR_ADDS:
5930 gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5931 break;
5932 case OPC2_32_RR_ADDS_H:
5933 gen_helper_add_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5934 cpu_gpr_d[r2]);
5935 break;
5936 case OPC2_32_RR_ADDS_HU:
5937 gen_helper_add_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5938 cpu_gpr_d[r2]);
5939 break;
5940 case OPC2_32_RR_ADDS_U:
5941 gen_helper_add_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5942 cpu_gpr_d[r2]);
5943 break;
5944 case OPC2_32_RR_ADDX:
5945 gen_add_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5946 break;
5947 case OPC2_32_RR_AND_EQ:
5948 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5949 cpu_gpr_d[r2], &tcg_gen_and_tl);
5950 break;
5951 case OPC2_32_RR_AND_GE:
5952 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5953 cpu_gpr_d[r2], &tcg_gen_and_tl);
5954 break;
5955 case OPC2_32_RR_AND_GE_U:
5956 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5957 cpu_gpr_d[r2], &tcg_gen_and_tl);
5958 break;
5959 case OPC2_32_RR_AND_LT:
5960 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5961 cpu_gpr_d[r2], &tcg_gen_and_tl);
5962 break;
5963 case OPC2_32_RR_AND_LT_U:
5964 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5965 cpu_gpr_d[r2], &tcg_gen_and_tl);
5966 break;
5967 case OPC2_32_RR_AND_NE:
5968 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5969 cpu_gpr_d[r2], &tcg_gen_and_tl);
5970 break;
5971 case OPC2_32_RR_EQ:
5972 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5973 cpu_gpr_d[r2]);
5974 break;
5975 case OPC2_32_RR_EQ_B:
5976 gen_helper_eq_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5977 break;
5978 case OPC2_32_RR_EQ_H:
5979 gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5980 break;
5981 case OPC2_32_RR_EQ_W:
5982 gen_cond_w(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5983 break;
5984 case OPC2_32_RR_EQANY_B:
5985 gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5986 break;
5987 case OPC2_32_RR_EQANY_H:
5988 gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5989 break;
5990 case OPC2_32_RR_GE:
5991 tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5992 cpu_gpr_d[r2]);
5993 break;
5994 case OPC2_32_RR_GE_U:
5995 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5996 cpu_gpr_d[r2]);
5997 break;
5998 case OPC2_32_RR_LT:
5999 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6000 cpu_gpr_d[r2]);
6001 break;
6002 case OPC2_32_RR_LT_U:
6003 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6004 cpu_gpr_d[r2]);
6005 break;
6006 case OPC2_32_RR_LT_B:
6007 gen_helper_lt_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6008 break;
6009 case OPC2_32_RR_LT_BU:
6010 gen_helper_lt_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6011 break;
6012 case OPC2_32_RR_LT_H:
6013 gen_helper_lt_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6014 break;
6015 case OPC2_32_RR_LT_HU:
6016 gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6017 break;
6018 case OPC2_32_RR_LT_W:
6019 gen_cond_w(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6020 break;
6021 case OPC2_32_RR_LT_WU:
6022 gen_cond_w(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6023 break;
6024 case OPC2_32_RR_MAX:
6025 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6026 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6027 break;
6028 case OPC2_32_RR_MAX_U:
6029 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6030 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6031 break;
6032 case OPC2_32_RR_MAX_B:
6033 gen_helper_max_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6034 break;
6035 case OPC2_32_RR_MAX_BU:
6036 gen_helper_max_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6037 break;
6038 case OPC2_32_RR_MAX_H:
6039 gen_helper_max_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6040 break;
6041 case OPC2_32_RR_MAX_HU:
6042 gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6043 break;
6044 case OPC2_32_RR_MIN:
6045 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6046 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6047 break;
6048 case OPC2_32_RR_MIN_U:
6049 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6050 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6051 break;
6052 case OPC2_32_RR_MIN_B:
6053 gen_helper_min_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6054 break;
6055 case OPC2_32_RR_MIN_BU:
6056 gen_helper_min_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6057 break;
6058 case OPC2_32_RR_MIN_H:
6059 gen_helper_min_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6060 break;
6061 case OPC2_32_RR_MIN_HU:
6062 gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6063 break;
6064 case OPC2_32_RR_MOV:
6065 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
6066 break;
6067 case OPC2_32_RR_NE:
6068 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6069 cpu_gpr_d[r2]);
6070 break;
6071 case OPC2_32_RR_OR_EQ:
6072 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
6073 cpu_gpr_d[r2], &tcg_gen_or_tl);
6074 break;
6075 case OPC2_32_RR_OR_GE:
6076 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6077 cpu_gpr_d[r2], &tcg_gen_or_tl);
6078 break;
6079 case OPC2_32_RR_OR_GE_U:
6080 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6081 cpu_gpr_d[r2], &tcg_gen_or_tl);
6082 break;
6083 case OPC2_32_RR_OR_LT:
6084 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6085 cpu_gpr_d[r2], &tcg_gen_or_tl);
6086 break;
6087 case OPC2_32_RR_OR_LT_U:
6088 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6089 cpu_gpr_d[r2], &tcg_gen_or_tl);
6090 break;
6091 case OPC2_32_RR_OR_NE:
6092 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6093 cpu_gpr_d[r2], &tcg_gen_or_tl);
6094 break;
6095 case OPC2_32_RR_SAT_B:
6096 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7f, -0x80);
6097 break;
6098 case OPC2_32_RR_SAT_BU:
6099 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xff);
6100 break;
6101 case OPC2_32_RR_SAT_H:
6102 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7fff, -0x8000);
6103 break;
6104 case OPC2_32_RR_SAT_HU:
6105 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xffff);
6106 break;
6107 case OPC2_32_RR_SH_EQ:
6108 gen_sh_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
6109 cpu_gpr_d[r2]);
6110 break;
6111 case OPC2_32_RR_SH_GE:
6112 gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6113 cpu_gpr_d[r2]);
6114 break;
6115 case OPC2_32_RR_SH_GE_U:
6116 gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6117 cpu_gpr_d[r2]);
6118 break;
6119 case OPC2_32_RR_SH_LT:
6120 gen_sh_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6121 cpu_gpr_d[r2]);
6122 break;
6123 case OPC2_32_RR_SH_LT_U:
6124 gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6125 cpu_gpr_d[r2]);
6126 break;
6127 case OPC2_32_RR_SH_NE:
6128 gen_sh_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6129 cpu_gpr_d[r2]);
6130 break;
6131 case OPC2_32_RR_SUB:
6132 gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6133 break;
6134 case OPC2_32_RR_SUB_B:
6135 gen_helper_sub_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6136 break;
6137 case OPC2_32_RR_SUB_H:
6138 gen_helper_sub_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6139 break;
6140 case OPC2_32_RR_SUBC:
6141 gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6142 break;
6143 case OPC2_32_RR_SUBS:
6144 gen_subs(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6145 break;
6146 case OPC2_32_RR_SUBS_U:
6147 gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6148 break;
6149 case OPC2_32_RR_SUBS_H:
6150 gen_helper_sub_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6151 cpu_gpr_d[r2]);
6152 break;
6153 case OPC2_32_RR_SUBS_HU:
6154 gen_helper_sub_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6155 cpu_gpr_d[r2]);
6156 break;
6157 case OPC2_32_RR_SUBX:
6158 gen_sub_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6159 break;
6160 case OPC2_32_RR_XOR_EQ:
6161 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
6162 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6163 break;
6164 case OPC2_32_RR_XOR_GE:
6165 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6166 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6167 break;
6168 case OPC2_32_RR_XOR_GE_U:
6169 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6170 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6171 break;
6172 case OPC2_32_RR_XOR_LT:
6173 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6174 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6175 break;
6176 case OPC2_32_RR_XOR_LT_U:
6177 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6178 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6179 break;
6180 case OPC2_32_RR_XOR_NE:
6181 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6182 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6183 break;
6184 }
6185 }
6186
6187 static void decode_rr_logical_shift(CPUTriCoreState *env, DisasContext *ctx)
6188 {
6189 uint32_t op2;
6190 int r3, r2, r1;
6191 TCGv temp;
6192
6193 r3 = MASK_OP_RR_D(ctx->opcode);
6194 r2 = MASK_OP_RR_S2(ctx->opcode);
6195 r1 = MASK_OP_RR_S1(ctx->opcode);
6196
6197 temp = tcg_temp_new();
6198 op2 = MASK_OP_RR_OP2(ctx->opcode);
6199
6200 switch (op2) {
6201 case OPC2_32_RR_AND:
6202 tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6203 break;
6204 case OPC2_32_RR_ANDN:
6205 tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6206 break;
6207 case OPC2_32_RR_CLO:
6208 gen_helper_clo(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6209 break;
6210 case OPC2_32_RR_CLO_H:
6211 gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6212 break;
6213 case OPC2_32_RR_CLS:
6214 gen_helper_cls(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6215 break;
6216 case OPC2_32_RR_CLS_H:
6217 gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6218 break;
6219 case OPC2_32_RR_CLZ:
6220 gen_helper_clz(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6221 break;
6222 case OPC2_32_RR_CLZ_H:
6223 gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6224 break;
6225 case OPC2_32_RR_NAND:
6226 tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6227 break;
6228 case OPC2_32_RR_NOR:
6229 tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6230 break;
6231 case OPC2_32_RR_OR:
6232 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6233 break;
6234 case OPC2_32_RR_ORN:
6235 tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6236 break;
6237 case OPC2_32_RR_SH:
6238 gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6239 break;
6240 case OPC2_32_RR_SH_H:
6241 gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6242 break;
6243 case OPC2_32_RR_SHA:
6244 gen_helper_sha(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6245 break;
6246 case OPC2_32_RR_SHA_H:
6247 gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6248 break;
6249 case OPC2_32_RR_SHAS:
6250 gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6251 break;
6252 case OPC2_32_RR_XNOR:
6253 tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6254 break;
6255 case OPC2_32_RR_XOR:
6256 tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6257 break;
6258 }
6259 tcg_temp_free(temp);
6260 }
6261
6262 static void decode_rr_address(CPUTriCoreState *env, DisasContext *ctx)
6263 {
6264 uint32_t op2, n;
6265 int r1, r2, r3;
6266 TCGv temp;
6267
6268 op2 = MASK_OP_RR_OP2(ctx->opcode);
6269 r3 = MASK_OP_RR_D(ctx->opcode);
6270 r2 = MASK_OP_RR_S2(ctx->opcode);
6271 r1 = MASK_OP_RR_S1(ctx->opcode);
6272 n = MASK_OP_RR_N(ctx->opcode);
6273
6274 switch (op2) {
6275 case OPC2_32_RR_ADD_A:
6276 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
6277 break;
6278 case OPC2_32_RR_ADDSC_A:
6279 temp = tcg_temp_new();
6280 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n);
6281 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp);
6282 tcg_temp_free(temp);
6283 break;
6284 case OPC2_32_RR_ADDSC_AT:
6285 temp = tcg_temp_new();
6286 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3);
6287 tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp);
6288 tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC);
6289 tcg_temp_free(temp);
6290 break;
6291 case OPC2_32_RR_EQ_A:
6292 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1],
6293 cpu_gpr_a[r2]);
6294 break;
6295 case OPC2_32_RR_EQZ:
6296 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
6297 break;
6298 case OPC2_32_RR_GE_A:
6299 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1],
6300 cpu_gpr_a[r2]);
6301 break;
6302 case OPC2_32_RR_LT_A:
6303 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1],
6304 cpu_gpr_a[r2]);
6305 break;
6306 case OPC2_32_RR_MOV_A:
6307 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_d[r2]);
6308 break;
6309 case OPC2_32_RR_MOV_AA:
6310 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_a[r2]);
6311 break;
6312 case OPC2_32_RR_MOV_D:
6313 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_a[r2]);
6314 break;
6315 case OPC2_32_RR_NE_A:
6316 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1],
6317 cpu_gpr_a[r2]);
6318 break;
6319 case OPC2_32_RR_NEZ_A:
6320 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
6321 break;
6322 case OPC2_32_RR_SUB_A:
6323 tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
6324 break;
6325 }
6326 }
6327
6328 static void decode_rr_idirect(CPUTriCoreState *env, DisasContext *ctx)
6329 {
6330 uint32_t op2;
6331 int r1;
6332
6333 op2 = MASK_OP_RR_OP2(ctx->opcode);
6334 r1 = MASK_OP_RR_S1(ctx->opcode);
6335
6336 switch (op2) {
6337 case OPC2_32_RR_JI:
6338 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6339 break;
6340 case OPC2_32_RR_JLI:
6341 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
6342 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6343 break;
6344 case OPC2_32_RR_CALLI:
6345 gen_helper_1arg(call, ctx->next_pc);
6346 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6347 break;
6348 case OPC2_32_RR_FCALLI:
6349 gen_fcall_save_ctx(ctx);
6350 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6351 break;
6352 }
6353 tcg_gen_exit_tb(0);
6354 ctx->bstate = BS_BRANCH;
6355 }
6356
6357 static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
6358 {
6359 uint32_t op2;
6360 int r1, r2, r3;
6361
6362 TCGv temp, temp2, temp3;
6363
6364 op2 = MASK_OP_RR_OP2(ctx->opcode);
6365 r3 = MASK_OP_RR_D(ctx->opcode);
6366 r2 = MASK_OP_RR_S2(ctx->opcode);
6367 r1 = MASK_OP_RR_S1(ctx->opcode);
6368
6369 switch (op2) {
6370 case OPC2_32_RR_BMERGE:
6371 gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6372 break;
6373 case OPC2_32_RR_BSPLIT:
6374 gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
6375 break;
6376 case OPC2_32_RR_DVINIT_B:
6377 gen_dvinit_b(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6378 cpu_gpr_d[r2]);
6379 break;
6380 case OPC2_32_RR_DVINIT_BU:
6381 temp = tcg_temp_new();
6382 temp2 = tcg_temp_new();
6383 temp3 = tcg_temp_new();
6384
6385 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8);
6386 /* reset av */
6387 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6388 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
6389 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
6390 tcg_gen_neg_tl(temp, temp3);
6391 /* use cpu_PSW_AV to compare against 0 */
6392 tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV,
6393 temp, temp3);
6394 tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
6395 tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
6396 temp2, cpu_gpr_d[r2]);
6397 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
6398 } else {
6399 /* overflow = (D[b] == 0) */
6400 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6401 }
6402 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6403 /* sv */
6404 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6405 /* write result */
6406 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24);
6407 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
6408
6409 tcg_temp_free(temp);
6410 tcg_temp_free(temp2);
6411 tcg_temp_free(temp3);
6412 break;
6413 case OPC2_32_RR_DVINIT_H:
6414 gen_dvinit_h(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6415 cpu_gpr_d[r2]);
6416 break;
6417 case OPC2_32_RR_DVINIT_HU:
6418 temp = tcg_temp_new();
6419 temp2 = tcg_temp_new();
6420 temp3 = tcg_temp_new();
6421
6422 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16);
6423 /* reset av */
6424 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6425 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
6426 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
6427 tcg_gen_neg_tl(temp, temp3);
6428 /* use cpu_PSW_AV to compare against 0 */
6429 tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV,
6430 temp, temp3);
6431 tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
6432 tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
6433 temp2, cpu_gpr_d[r2]);
6434 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
6435 } else {
6436 /* overflow = (D[b] == 0) */
6437 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6438 }
6439 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6440 /* sv */
6441 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6442 /* write result */
6443 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16);
6444 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
6445 tcg_temp_free(temp);
6446 tcg_temp_free(temp2);
6447 tcg_temp_free(temp3);
6448 break;
6449 case OPC2_32_RR_DVINIT:
6450 temp = tcg_temp_new();
6451 temp2 = tcg_temp_new();
6452 /* overflow = ((D[b] == 0) ||
6453 ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */
6454 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff);
6455 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000);
6456 tcg_gen_and_tl(temp, temp, temp2);
6457 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0);
6458 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
6459 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6460 /* sv */
6461 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6462 /* reset av */
6463 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6464 /* write result */
6465 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6466 /* sign extend to high reg */
6467 tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31);
6468 tcg_temp_free(temp);
6469 tcg_temp_free(temp2);
6470 break;
6471 case OPC2_32_RR_DVINIT_U:
6472 /* overflow = (D[b] == 0) */
6473 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6474 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6475 /* sv */
6476 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6477 /* reset av */
6478 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6479 /* write result */
6480 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6481 /* zero extend to high reg*/
6482 tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0);
6483 break;
6484 case OPC2_32_RR_PARITY:
6485 gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6486 break;
6487 case OPC2_32_RR_UNPACK:
6488 gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
6489 break;
6490 case OPC2_32_RR_CRC32:
6491 if (tricore_feature(env, TRICORE_FEATURE_161)) {
6492 gen_helper_crc32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6493 } /* TODO: else raise illegal opcode trap */
6494 break;
6495 case OPC2_32_RR_DIV:
6496 if (tricore_feature(env, TRICORE_FEATURE_16)) {
6497 GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6498 cpu_gpr_d[r2]);
6499 } /* TODO: else raise illegal opcode trap */
6500 break;
6501 case OPC2_32_RR_DIV_U:
6502 if (tricore_feature(env, TRICORE_FEATURE_16)) {
6503 GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1],
6504 cpu_gpr_d[r1], cpu_gpr_d[r2]);
6505 } /* TODO: else raise illegal opcode trap */
6506 break;
6507 }
6508 }
6509
6510 /* RR1 Format */
6511 static void decode_rr1_mul(CPUTriCoreState *env, DisasContext *ctx)
6512 {
6513 uint32_t op2;
6514
6515 int r1, r2, r3;
6516 TCGv n;
6517 TCGv_i64 temp64;
6518
6519 r1 = MASK_OP_RR1_S1(ctx->opcode);
6520 r2 = MASK_OP_RR1_S2(ctx->opcode);
6521 r3 = MASK_OP_RR1_D(ctx->opcode);
6522 n = tcg_const_i32(MASK_OP_RR1_N(ctx->opcode));
6523 op2 = MASK_OP_RR1_OP2(ctx->opcode);
6524
6525 switch (op2) {
6526 case OPC2_32_RR1_MUL_H_32_LL:
6527 temp64 = tcg_temp_new_i64();
6528 GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6529 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6530 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6531 tcg_temp_free_i64(temp64);
6532 break;
6533 case OPC2_32_RR1_MUL_H_32_LU:
6534 temp64 = tcg_temp_new_i64();
6535 GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6536 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6537 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6538 tcg_temp_free_i64(temp64);
6539 break;
6540 case OPC2_32_RR1_MUL_H_32_UL:
6541 temp64 = tcg_temp_new_i64();
6542 GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6543 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6544 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6545 tcg_temp_free_i64(temp64);
6546 break;
6547 case OPC2_32_RR1_MUL_H_32_UU:
6548 temp64 = tcg_temp_new_i64();
6549 GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6550 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6551 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6552 tcg_temp_free_i64(temp64);
6553 break;
6554 case OPC2_32_RR1_MULM_H_64_LL:
6555 temp64 = tcg_temp_new_i64();
6556 GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6557 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6558 /* reset V bit */
6559 tcg_gen_movi_tl(cpu_PSW_V, 0);
6560 /* reset AV bit */
6561 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6562 tcg_temp_free_i64(temp64);
6563 break;
6564 case OPC2_32_RR1_MULM_H_64_LU:
6565 temp64 = tcg_temp_new_i64();
6566 GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6567 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6568 /* reset V bit */
6569 tcg_gen_movi_tl(cpu_PSW_V, 0);
6570 /* reset AV bit */
6571 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6572 tcg_temp_free_i64(temp64);
6573 break;
6574 case OPC2_32_RR1_MULM_H_64_UL:
6575 temp64 = tcg_temp_new_i64();
6576 GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6577 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6578 /* reset V bit */
6579 tcg_gen_movi_tl(cpu_PSW_V, 0);
6580 /* reset AV bit */
6581 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6582 tcg_temp_free_i64(temp64);
6583 break;
6584 case OPC2_32_RR1_MULM_H_64_UU:
6585 temp64 = tcg_temp_new_i64();
6586 GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6587 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6588 /* reset V bit */
6589 tcg_gen_movi_tl(cpu_PSW_V, 0);
6590 /* reset AV bit */
6591 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6592 tcg_temp_free_i64(temp64);
6593
6594 break;
6595 case OPC2_32_RR1_MULR_H_16_LL:
6596 GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6597 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6598 break;
6599 case OPC2_32_RR1_MULR_H_16_LU:
6600 GEN_HELPER_LU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6601 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6602 break;
6603 case OPC2_32_RR1_MULR_H_16_UL:
6604 GEN_HELPER_UL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6605 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6606 break;
6607 case OPC2_32_RR1_MULR_H_16_UU:
6608 GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6609 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6610 break;
6611 }
6612 tcg_temp_free(n);
6613 }
6614
6615 static void decode_rr1_mulq(CPUTriCoreState *env, DisasContext *ctx)
6616 {
6617 uint32_t op2;
6618 int r1, r2, r3;
6619 uint32_t n;
6620
6621 TCGv temp, temp2;
6622
6623 r1 = MASK_OP_RR1_S1(ctx->opcode);
6624 r2 = MASK_OP_RR1_S2(ctx->opcode);
6625 r3 = MASK_OP_RR1_D(ctx->opcode);
6626 n = MASK_OP_RR1_N(ctx->opcode);
6627 op2 = MASK_OP_RR1_OP2(ctx->opcode);
6628
6629 temp = tcg_temp_new();
6630 temp2 = tcg_temp_new();
6631
6632 switch (op2) {
6633 case OPC2_32_RR1_MUL_Q_32:
6634 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32);
6635 break;
6636 case OPC2_32_RR1_MUL_Q_64:
6637 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6638 n, 0);
6639 break;
6640 case OPC2_32_RR1_MUL_Q_32_L:
6641 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6642 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
6643 break;
6644 case OPC2_32_RR1_MUL_Q_64_L:
6645 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6646 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
6647 break;
6648 case OPC2_32_RR1_MUL_Q_32_U:
6649 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6650 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
6651 break;
6652 case OPC2_32_RR1_MUL_Q_64_U:
6653 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6654 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
6655 break;
6656 case OPC2_32_RR1_MUL_Q_32_LL:
6657 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6658 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6659 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
6660 break;
6661 case OPC2_32_RR1_MUL_Q_32_UU:
6662 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6663 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6664 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
6665 break;
6666 case OPC2_32_RR1_MULR_Q_32_L:
6667 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6668 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6669 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
6670 break;
6671 case OPC2_32_RR1_MULR_Q_32_U:
6672 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6673 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6674 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
6675 break;
6676 }
6677 tcg_temp_free(temp);
6678 tcg_temp_free(temp2);
6679 }
6680
6681 /* RR2 format */
6682 static void decode_rr2_mul(CPUTriCoreState *env, DisasContext *ctx)
6683 {
6684 uint32_t op2;
6685 int r1, r2, r3;
6686
6687 op2 = MASK_OP_RR2_OP2(ctx->opcode);
6688 r1 = MASK_OP_RR2_S1(ctx->opcode);
6689 r2 = MASK_OP_RR2_S2(ctx->opcode);
6690 r3 = MASK_OP_RR2_D(ctx->opcode);
6691 switch (op2) {
6692 case OPC2_32_RR2_MUL_32:
6693 gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6694 break;
6695 case OPC2_32_RR2_MUL_64:
6696 gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6697 cpu_gpr_d[r2]);
6698 break;
6699 case OPC2_32_RR2_MULS_32:
6700 gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6701 cpu_gpr_d[r2]);
6702 break;
6703 case OPC2_32_RR2_MUL_U_64:
6704 gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6705 cpu_gpr_d[r2]);
6706 break;
6707 case OPC2_32_RR2_MULS_U_32:
6708 gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6709 cpu_gpr_d[r2]);
6710 break;
6711 }
6712 }
6713
6714 /* RRPW format */
6715 static void decode_rrpw_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
6716 {
6717 uint32_t op2;
6718 int r1, r2, r3;
6719 int32_t pos, width;
6720
6721 op2 = MASK_OP_RRPW_OP2(ctx->opcode);
6722 r1 = MASK_OP_RRPW_S1(ctx->opcode);
6723 r2 = MASK_OP_RRPW_S2(ctx->opcode);
6724 r3 = MASK_OP_RRPW_D(ctx->opcode);
6725 pos = MASK_OP_RRPW_POS(ctx->opcode);
6726 width = MASK_OP_RRPW_WIDTH(ctx->opcode);
6727
6728 switch (op2) {
6729 case OPC2_32_RRPW_EXTR:
6730 if (pos + width <= 31) {
6731 /* optimize special cases */
6732 if ((pos == 0) && (width == 8)) {
6733 tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6734 } else if ((pos == 0) && (width == 16)) {
6735 tcg_gen_ext16s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6736 } else {
6737 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32 - pos - width);
6738 tcg_gen_sari_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32 - width);
6739 }
6740 }
6741 break;
6742 case OPC2_32_RRPW_EXTR_U:
6743 if (width == 0) {
6744 tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
6745 } else {
6746 tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos);
6747 tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32-width));
6748 }
6749 break;
6750 case OPC2_32_RRPW_IMASK:
6751 if (pos + width <= 31) {
6752 tcg_gen_movi_tl(cpu_gpr_d[r3+1], ((1u << width) - 1) << pos);
6753 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos);
6754 }
6755 break;
6756 case OPC2_32_RRPW_INSERT:
6757 if (pos + width <= 31) {
6758 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
6759 width, pos);
6760 }
6761 break;
6762 }
6763 }
6764
6765 /* RRR format */
6766 static void decode_rrr_cond_select(CPUTriCoreState *env, DisasContext *ctx)
6767 {
6768 uint32_t op2;
6769 int r1, r2, r3, r4;
6770 TCGv temp;
6771
6772 op2 = MASK_OP_RRR_OP2(ctx->opcode);
6773 r1 = MASK_OP_RRR_S1(ctx->opcode);
6774 r2 = MASK_OP_RRR_S2(ctx->opcode);
6775 r3 = MASK_OP_RRR_S3(ctx->opcode);
6776 r4 = MASK_OP_RRR_D(ctx->opcode);
6777
6778 switch (op2) {
6779 case OPC2_32_RRR_CADD:
6780 gen_cond_add(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
6781 cpu_gpr_d[r4], cpu_gpr_d[r3]);
6782 break;
6783 case OPC2_32_RRR_CADDN:
6784 gen_cond_add(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
6785 cpu_gpr_d[r3]);
6786 break;
6787 case OPC2_32_RRR_CSUB:
6788 gen_cond_sub(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
6789 cpu_gpr_d[r3]);
6790 break;
6791 case OPC2_32_RRR_CSUBN:
6792 gen_cond_sub(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
6793 cpu_gpr_d[r3]);
6794 break;
6795 case OPC2_32_RRR_SEL:
6796 temp = tcg_const_i32(0);
6797 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
6798 cpu_gpr_d[r1], cpu_gpr_d[r2]);
6799 tcg_temp_free(temp);
6800 break;
6801 case OPC2_32_RRR_SELN:
6802 temp = tcg_const_i32(0);
6803 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
6804 cpu_gpr_d[r1], cpu_gpr_d[r2]);
6805 tcg_temp_free(temp);
6806 break;
6807 }
6808 }
6809
6810 static void decode_rrr_divide(CPUTriCoreState *env, DisasContext *ctx)
6811 {
6812 uint32_t op2;
6813
6814 int r1, r2, r3, r4;
6815
6816 op2 = MASK_OP_RRR_OP2(ctx->opcode);
6817 r1 = MASK_OP_RRR_S1(ctx->opcode);
6818 r2 = MASK_OP_RRR_S2(ctx->opcode);
6819 r3 = MASK_OP_RRR_S3(ctx->opcode);
6820 r4 = MASK_OP_RRR_D(ctx->opcode);
6821
6822 switch (op2) {
6823 case OPC2_32_RRR_DVADJ:
6824 GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6825 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6826 break;
6827 case OPC2_32_RRR_DVSTEP:
6828 GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6829 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6830 break;
6831 case OPC2_32_RRR_DVSTEP_U:
6832 GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6833 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6834 break;
6835 case OPC2_32_RRR_IXMAX:
6836 GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6837 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6838 break;
6839 case OPC2_32_RRR_IXMAX_U:
6840 GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6841 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6842 break;
6843 case OPC2_32_RRR_IXMIN:
6844 GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6845 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6846 break;
6847 case OPC2_32_RRR_IXMIN_U:
6848 GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6849 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6850 break;
6851 case OPC2_32_RRR_PACK:
6852 gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
6853 cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
6854 break;
6855 }
6856 }
6857
6858 /* RRR2 format */
6859 static void decode_rrr2_madd(CPUTriCoreState *env, DisasContext *ctx)
6860 {
6861 uint32_t op2;
6862 uint32_t r1, r2, r3, r4;
6863
6864 op2 = MASK_OP_RRR2_OP2(ctx->opcode);
6865 r1 = MASK_OP_RRR2_S1(ctx->opcode);
6866 r2 = MASK_OP_RRR2_S2(ctx->opcode);
6867 r3 = MASK_OP_RRR2_S3(ctx->opcode);
6868 r4 = MASK_OP_RRR2_D(ctx->opcode);
6869 switch (op2) {
6870 case OPC2_32_RRR2_MADD_32:
6871 gen_madd32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3],
6872 cpu_gpr_d[r2]);
6873 break;
6874 case OPC2_32_RRR2_MADD_64:
6875 gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6876 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6877 break;
6878 case OPC2_32_RRR2_MADDS_32:
6879 gen_helper_madd32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6880 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6881 break;
6882 case OPC2_32_RRR2_MADDS_64:
6883 gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6884 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6885 break;
6886 case OPC2_32_RRR2_MADD_U_64:
6887 gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6888 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6889 break;
6890 case OPC2_32_RRR2_MADDS_U_32:
6891 gen_helper_madd32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6892 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6893 break;
6894 case OPC2_32_RRR2_MADDS_U_64:
6895 gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6896 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6897 break;
6898 }
6899 }
6900
6901 static void decode_rrr2_msub(CPUTriCoreState *env, DisasContext *ctx)
6902 {
6903 uint32_t op2;
6904 uint32_t r1, r2, r3, r4;
6905
6906 op2 = MASK_OP_RRR2_OP2(ctx->opcode);
6907 r1 = MASK_OP_RRR2_S1(ctx->opcode);
6908 r2 = MASK_OP_RRR2_S2(ctx->opcode);
6909 r3 = MASK_OP_RRR2_S3(ctx->opcode);
6910 r4 = MASK_OP_RRR2_D(ctx->opcode);
6911
6912 switch (op2) {
6913 case OPC2_32_RRR2_MSUB_32:
6914 gen_msub32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3],
6915 cpu_gpr_d[r2]);
6916 break;
6917 case OPC2_32_RRR2_MSUB_64:
6918 gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6919 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6920 break;
6921 case OPC2_32_RRR2_MSUBS_32:
6922 gen_helper_msub32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6923 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6924 break;
6925 case OPC2_32_RRR2_MSUBS_64:
6926 gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6927 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6928 break;
6929 case OPC2_32_RRR2_MSUB_U_64:
6930 gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6931 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6932 break;
6933 case OPC2_32_RRR2_MSUBS_U_32:
6934 gen_helper_msub32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6935 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6936 break;
6937 case OPC2_32_RRR2_MSUBS_U_64:
6938 gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6939 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6940 break;
6941 }
6942 }
6943
6944 /* RRR1 format */
6945 static void decode_rrr1_madd(CPUTriCoreState *env, DisasContext *ctx)
6946 {
6947 uint32_t op2;
6948 uint32_t r1, r2, r3, r4, n;
6949
6950 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
6951 r1 = MASK_OP_RRR1_S1(ctx->opcode);
6952 r2 = MASK_OP_RRR1_S2(ctx->opcode);
6953 r3 = MASK_OP_RRR1_S3(ctx->opcode);
6954 r4 = MASK_OP_RRR1_D(ctx->opcode);
6955 n = MASK_OP_RRR1_N(ctx->opcode);
6956
6957 switch (op2) {
6958 case OPC2_32_RRR1_MADD_H_LL:
6959 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6960 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6961 break;
6962 case OPC2_32_RRR1_MADD_H_LU:
6963 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6964 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6965 break;
6966 case OPC2_32_RRR1_MADD_H_UL:
6967 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6968 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6969 break;
6970 case OPC2_32_RRR1_MADD_H_UU:
6971 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6972 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6973 break;
6974 case OPC2_32_RRR1_MADDS_H_LL:
6975 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6976 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6977 break;
6978 case OPC2_32_RRR1_MADDS_H_LU:
6979 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6980 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6981 break;
6982 case OPC2_32_RRR1_MADDS_H_UL:
6983 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6984 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6985 break;
6986 case OPC2_32_RRR1_MADDS_H_UU:
6987 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6988 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6989 break;
6990 case OPC2_32_RRR1_MADDM_H_LL:
6991 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6992 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6993 break;
6994 case OPC2_32_RRR1_MADDM_H_LU:
6995 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6996 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6997 break;
6998 case OPC2_32_RRR1_MADDM_H_UL:
6999 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7000 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7001 break;
7002 case OPC2_32_RRR1_MADDM_H_UU:
7003 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7004 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7005 break;
7006 case OPC2_32_RRR1_MADDMS_H_LL:
7007 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7008 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7009 break;
7010 case OPC2_32_RRR1_MADDMS_H_LU:
7011 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7012 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7013 break;
7014 case OPC2_32_RRR1_MADDMS_H_UL:
7015 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7016 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7017 break;
7018 case OPC2_32_RRR1_MADDMS_H_UU:
7019 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7020 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7021 break;
7022 case OPC2_32_RRR1_MADDR_H_LL:
7023 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7024 cpu_gpr_d[r2], n, MODE_LL);
7025 break;
7026 case OPC2_32_RRR1_MADDR_H_LU:
7027 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7028 cpu_gpr_d[r2], n, MODE_LU);
7029 break;
7030 case OPC2_32_RRR1_MADDR_H_UL:
7031 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7032 cpu_gpr_d[r2], n, MODE_UL);
7033 break;
7034 case OPC2_32_RRR1_MADDR_H_UU:
7035 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7036 cpu_gpr_d[r2], n, MODE_UU);
7037 break;
7038 case OPC2_32_RRR1_MADDRS_H_LL:
7039 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7040 cpu_gpr_d[r2], n, MODE_LL);
7041 break;
7042 case OPC2_32_RRR1_MADDRS_H_LU:
7043 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7044 cpu_gpr_d[r2], n, MODE_LU);
7045 break;
7046 case OPC2_32_RRR1_MADDRS_H_UL:
7047 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7048 cpu_gpr_d[r2], n, MODE_UL);
7049 break;
7050 case OPC2_32_RRR1_MADDRS_H_UU:
7051 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7052 cpu_gpr_d[r2], n, MODE_UU);
7053 break;
7054 }
7055 }
7056
7057 static void decode_rrr1_maddq_h(CPUTriCoreState *env, DisasContext *ctx)
7058 {
7059 uint32_t op2;
7060 uint32_t r1, r2, r3, r4, n;
7061 TCGv temp, temp2;
7062
7063 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7064 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7065 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7066 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7067 r4 = MASK_OP_RRR1_D(ctx->opcode);
7068 n = MASK_OP_RRR1_N(ctx->opcode);
7069
7070 temp = tcg_const_i32(n);
7071 temp2 = tcg_temp_new();
7072
7073 switch (op2) {
7074 case OPC2_32_RRR1_MADD_Q_32:
7075 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7076 cpu_gpr_d[r2], n, 32, env);
7077 break;
7078 case OPC2_32_RRR1_MADD_Q_64:
7079 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7080 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7081 n, env);
7082 break;
7083 case OPC2_32_RRR1_MADD_Q_32_L:
7084 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7085 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7086 temp, n, 16, env);
7087 break;
7088 case OPC2_32_RRR1_MADD_Q_64_L:
7089 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7090 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7091 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7092 n, env);
7093 break;
7094 case OPC2_32_RRR1_MADD_Q_32_U:
7095 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7096 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7097 temp, n, 16, env);
7098 break;
7099 case OPC2_32_RRR1_MADD_Q_64_U:
7100 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7101 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7102 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7103 n, env);
7104 break;
7105 case OPC2_32_RRR1_MADD_Q_32_LL:
7106 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7107 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7108 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7109 break;
7110 case OPC2_32_RRR1_MADD_Q_64_LL:
7111 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7112 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7113 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7114 cpu_gpr_d[r3+1], temp, temp2, n);
7115 break;
7116 case OPC2_32_RRR1_MADD_Q_32_UU:
7117 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7118 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7119 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7120 break;
7121 case OPC2_32_RRR1_MADD_Q_64_UU:
7122 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7123 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7124 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7125 cpu_gpr_d[r3+1], temp, temp2, n);
7126 break;
7127 case OPC2_32_RRR1_MADDS_Q_32:
7128 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7129 cpu_gpr_d[r2], n, 32);
7130 break;
7131 case OPC2_32_RRR1_MADDS_Q_64:
7132 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7133 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7134 n);
7135 break;
7136 case OPC2_32_RRR1_MADDS_Q_32_L:
7137 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7138 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7139 temp, n, 16);
7140 break;
7141 case OPC2_32_RRR1_MADDS_Q_64_L:
7142 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7143 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7144 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7145 n);
7146 break;
7147 case OPC2_32_RRR1_MADDS_Q_32_U:
7148 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7149 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7150 temp, n, 16);
7151 break;
7152 case OPC2_32_RRR1_MADDS_Q_64_U:
7153 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7154 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7155 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7156 n);
7157 break;
7158 case OPC2_32_RRR1_MADDS_Q_32_LL:
7159 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7160 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7161 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7162 break;
7163 case OPC2_32_RRR1_MADDS_Q_64_LL:
7164 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7165 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7166 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7167 cpu_gpr_d[r3+1], temp, temp2, n);
7168 break;
7169 case OPC2_32_RRR1_MADDS_Q_32_UU:
7170 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7171 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7172 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7173 break;
7174 case OPC2_32_RRR1_MADDS_Q_64_UU:
7175 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7176 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7177 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7178 cpu_gpr_d[r3+1], temp, temp2, n);
7179 break;
7180 case OPC2_32_RRR1_MADDR_H_64_UL:
7181 gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7182 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7183 break;
7184 case OPC2_32_RRR1_MADDRS_H_64_UL:
7185 gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7186 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7187 break;
7188 case OPC2_32_RRR1_MADDR_Q_32_LL:
7189 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7190 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7191 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7192 break;
7193 case OPC2_32_RRR1_MADDR_Q_32_UU:
7194 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7195 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7196 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7197 break;
7198 case OPC2_32_RRR1_MADDRS_Q_32_LL:
7199 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7200 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7201 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7202 break;
7203 case OPC2_32_RRR1_MADDRS_Q_32_UU:
7204 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7205 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7206 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7207 break;
7208 }
7209 tcg_temp_free(temp);
7210 tcg_temp_free(temp2);
7211 }
7212
7213 static void decode_rrr1_maddsu_h(CPUTriCoreState *env, DisasContext *ctx)
7214 {
7215 uint32_t op2;
7216 uint32_t r1, r2, r3, r4, n;
7217
7218 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7219 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7220 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7221 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7222 r4 = MASK_OP_RRR1_D(ctx->opcode);
7223 n = MASK_OP_RRR1_N(ctx->opcode);
7224
7225 switch (op2) {
7226 case OPC2_32_RRR1_MADDSU_H_32_LL:
7227 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7228 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7229 break;
7230 case OPC2_32_RRR1_MADDSU_H_32_LU:
7231 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7232 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7233 break;
7234 case OPC2_32_RRR1_MADDSU_H_32_UL:
7235 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7236 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7237 break;
7238 case OPC2_32_RRR1_MADDSU_H_32_UU:
7239 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7240 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7241 break;
7242 case OPC2_32_RRR1_MADDSUS_H_32_LL:
7243 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7244 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7245 n, MODE_LL);
7246 break;
7247 case OPC2_32_RRR1_MADDSUS_H_32_LU:
7248 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7249 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7250 n, MODE_LU);
7251 break;
7252 case OPC2_32_RRR1_MADDSUS_H_32_UL:
7253 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7254 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7255 n, MODE_UL);
7256 break;
7257 case OPC2_32_RRR1_MADDSUS_H_32_UU:
7258 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7259 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7260 n, MODE_UU);
7261 break;
7262 case OPC2_32_RRR1_MADDSUM_H_64_LL:
7263 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7264 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7265 n, MODE_LL);
7266 break;
7267 case OPC2_32_RRR1_MADDSUM_H_64_LU:
7268 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7269 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7270 n, MODE_LU);
7271 break;
7272 case OPC2_32_RRR1_MADDSUM_H_64_UL:
7273 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7274 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7275 n, MODE_UL);
7276 break;
7277 case OPC2_32_RRR1_MADDSUM_H_64_UU:
7278 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7279 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7280 n, MODE_UU);
7281 break;
7282 case OPC2_32_RRR1_MADDSUMS_H_64_LL:
7283 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7284 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7285 n, MODE_LL);
7286 break;
7287 case OPC2_32_RRR1_MADDSUMS_H_64_LU:
7288 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7289 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7290 n, MODE_LU);
7291 break;
7292 case OPC2_32_RRR1_MADDSUMS_H_64_UL:
7293 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7294 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7295 n, MODE_UL);
7296 break;
7297 case OPC2_32_RRR1_MADDSUMS_H_64_UU:
7298 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7299 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7300 n, MODE_UU);
7301 break;
7302 case OPC2_32_RRR1_MADDSUR_H_16_LL:
7303 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7304 cpu_gpr_d[r2], n, MODE_LL);
7305 break;
7306 case OPC2_32_RRR1_MADDSUR_H_16_LU:
7307 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7308 cpu_gpr_d[r2], n, MODE_LU);
7309 break;
7310 case OPC2_32_RRR1_MADDSUR_H_16_UL:
7311 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7312 cpu_gpr_d[r2], n, MODE_UL);
7313 break;
7314 case OPC2_32_RRR1_MADDSUR_H_16_UU:
7315 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7316 cpu_gpr_d[r2], n, MODE_UU);
7317 break;
7318 case OPC2_32_RRR1_MADDSURS_H_16_LL:
7319 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7320 cpu_gpr_d[r2], n, MODE_LL);
7321 break;
7322 case OPC2_32_RRR1_MADDSURS_H_16_LU:
7323 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7324 cpu_gpr_d[r2], n, MODE_LU);
7325 break;
7326 case OPC2_32_RRR1_MADDSURS_H_16_UL:
7327 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7328 cpu_gpr_d[r2], n, MODE_UL);
7329 break;
7330 case OPC2_32_RRR1_MADDSURS_H_16_UU:
7331 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7332 cpu_gpr_d[r2], n, MODE_UU);
7333 break;
7334 }
7335 }
7336
7337 static void decode_rrr1_msub(CPUTriCoreState *env, DisasContext *ctx)
7338 {
7339 uint32_t op2;
7340 uint32_t r1, r2, r3, r4, n;
7341
7342 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7343 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7344 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7345 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7346 r4 = MASK_OP_RRR1_D(ctx->opcode);
7347 n = MASK_OP_RRR1_N(ctx->opcode);
7348
7349 switch (op2) {
7350 case OPC2_32_RRR1_MSUB_H_LL:
7351 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7352 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7353 break;
7354 case OPC2_32_RRR1_MSUB_H_LU:
7355 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7356 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7357 break;
7358 case OPC2_32_RRR1_MSUB_H_UL:
7359 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7360 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7361 break;
7362 case OPC2_32_RRR1_MSUB_H_UU:
7363 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7364 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7365 break;
7366 case OPC2_32_RRR1_MSUBS_H_LL:
7367 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7368 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7369 break;
7370 case OPC2_32_RRR1_MSUBS_H_LU:
7371 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7372 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7373 break;
7374 case OPC2_32_RRR1_MSUBS_H_UL:
7375 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7376 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7377 break;
7378 case OPC2_32_RRR1_MSUBS_H_UU:
7379 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7380 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7381 break;
7382 case OPC2_32_RRR1_MSUBM_H_LL:
7383 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7384 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7385 break;
7386 case OPC2_32_RRR1_MSUBM_H_LU:
7387 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7388 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7389 break;
7390 case OPC2_32_RRR1_MSUBM_H_UL:
7391 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7392 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7393 break;
7394 case OPC2_32_RRR1_MSUBM_H_UU:
7395 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7396 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7397 break;
7398 case OPC2_32_RRR1_MSUBMS_H_LL:
7399 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7400 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7401 break;
7402 case OPC2_32_RRR1_MSUBMS_H_LU:
7403 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7404 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7405 break;
7406 case OPC2_32_RRR1_MSUBMS_H_UL:
7407 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7408 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7409 break;
7410 case OPC2_32_RRR1_MSUBMS_H_UU:
7411 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7412 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7413 break;
7414 case OPC2_32_RRR1_MSUBR_H_LL:
7415 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7416 cpu_gpr_d[r2], n, MODE_LL);
7417 break;
7418 case OPC2_32_RRR1_MSUBR_H_LU:
7419 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7420 cpu_gpr_d[r2], n, MODE_LU);
7421 break;
7422 case OPC2_32_RRR1_MSUBR_H_UL:
7423 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7424 cpu_gpr_d[r2], n, MODE_UL);
7425 break;
7426 case OPC2_32_RRR1_MSUBR_H_UU:
7427 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7428 cpu_gpr_d[r2], n, MODE_UU);
7429 break;
7430 case OPC2_32_RRR1_MSUBRS_H_LL:
7431 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7432 cpu_gpr_d[r2], n, MODE_LL);
7433 break;
7434 case OPC2_32_RRR1_MSUBRS_H_LU:
7435 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7436 cpu_gpr_d[r2], n, MODE_LU);
7437 break;
7438 case OPC2_32_RRR1_MSUBRS_H_UL:
7439 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7440 cpu_gpr_d[r2], n, MODE_UL);
7441 break;
7442 case OPC2_32_RRR1_MSUBRS_H_UU:
7443 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7444 cpu_gpr_d[r2], n, MODE_UU);
7445 break;
7446 }
7447 }
7448
7449 static void decode_rrr1_msubq_h(CPUTriCoreState *env, DisasContext *ctx)
7450 {
7451 uint32_t op2;
7452 uint32_t r1, r2, r3, r4, n;
7453 TCGv temp, temp2;
7454
7455 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7456 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7457 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7458 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7459 r4 = MASK_OP_RRR1_D(ctx->opcode);
7460 n = MASK_OP_RRR1_N(ctx->opcode);
7461
7462 temp = tcg_const_i32(n);
7463 temp2 = tcg_temp_new();
7464
7465 switch (op2) {
7466 case OPC2_32_RRR1_MSUB_Q_32:
7467 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7468 cpu_gpr_d[r2], n, 32, env);
7469 break;
7470 case OPC2_32_RRR1_MSUB_Q_64:
7471 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7472 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7473 n, env);
7474 break;
7475 case OPC2_32_RRR1_MSUB_Q_32_L:
7476 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7477 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7478 temp, n, 16, env);
7479 break;
7480 case OPC2_32_RRR1_MSUB_Q_64_L:
7481 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7482 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7483 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7484 n, env);
7485 break;
7486 case OPC2_32_RRR1_MSUB_Q_32_U:
7487 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7488 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7489 temp, n, 16, env);
7490 break;
7491 case OPC2_32_RRR1_MSUB_Q_64_U:
7492 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7493 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7494 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7495 n, env);
7496 break;
7497 case OPC2_32_RRR1_MSUB_Q_32_LL:
7498 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7499 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7500 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7501 break;
7502 case OPC2_32_RRR1_MSUB_Q_64_LL:
7503 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7504 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7505 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7506 cpu_gpr_d[r3+1], temp, temp2, n);
7507 break;
7508 case OPC2_32_RRR1_MSUB_Q_32_UU:
7509 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7510 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7511 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7512 break;
7513 case OPC2_32_RRR1_MSUB_Q_64_UU:
7514 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7515 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7516 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7517 cpu_gpr_d[r3+1], temp, temp2, n);
7518 break;
7519 case OPC2_32_RRR1_MSUBS_Q_32:
7520 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7521 cpu_gpr_d[r2], n, 32);
7522 break;
7523 case OPC2_32_RRR1_MSUBS_Q_64:
7524 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7525 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7526 n);
7527 break;
7528 case OPC2_32_RRR1_MSUBS_Q_32_L:
7529 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7530 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7531 temp, n, 16);
7532 break;
7533 case OPC2_32_RRR1_MSUBS_Q_64_L:
7534 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7535 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7536 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7537 n);
7538 break;
7539 case OPC2_32_RRR1_MSUBS_Q_32_U:
7540 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7541 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7542 temp, n, 16);
7543 break;
7544 case OPC2_32_RRR1_MSUBS_Q_64_U:
7545 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7546 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7547 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7548 n);
7549 break;
7550 case OPC2_32_RRR1_MSUBS_Q_32_LL:
7551 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7552 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7553 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7554 break;
7555 case OPC2_32_RRR1_MSUBS_Q_64_LL:
7556 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7557 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7558 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7559 cpu_gpr_d[r3+1], temp, temp2, n);
7560 break;
7561 case OPC2_32_RRR1_MSUBS_Q_32_UU:
7562 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7563 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7564 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7565 break;
7566 case OPC2_32_RRR1_MSUBS_Q_64_UU:
7567 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7568 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7569 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7570 cpu_gpr_d[r3+1], temp, temp2, n);
7571 break;
7572 case OPC2_32_RRR1_MSUBR_H_64_UL:
7573 gen_msubr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7574 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7575 break;
7576 case OPC2_32_RRR1_MSUBRS_H_64_UL:
7577 gen_msubr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7578 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7579 break;
7580 case OPC2_32_RRR1_MSUBR_Q_32_LL:
7581 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7582 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7583 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7584 break;
7585 case OPC2_32_RRR1_MSUBR_Q_32_UU:
7586 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7587 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7588 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7589 break;
7590 case OPC2_32_RRR1_MSUBRS_Q_32_LL:
7591 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7592 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7593 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7594 break;
7595 case OPC2_32_RRR1_MSUBRS_Q_32_UU:
7596 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7597 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7598 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7599 break;
7600 }
7601 tcg_temp_free(temp);
7602 tcg_temp_free(temp2);
7603 }
7604
7605 static void decode_rrr1_msubad_h(CPUTriCoreState *env, DisasContext *ctx)
7606 {
7607 uint32_t op2;
7608 uint32_t r1, r2, r3, r4, n;
7609
7610 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7611 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7612 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7613 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7614 r4 = MASK_OP_RRR1_D(ctx->opcode);
7615 n = MASK_OP_RRR1_N(ctx->opcode);
7616
7617 switch (op2) {
7618 case OPC2_32_RRR1_MSUBAD_H_32_LL:
7619 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7620 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7621 break;
7622 case OPC2_32_RRR1_MSUBAD_H_32_LU:
7623 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7624 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7625 break;
7626 case OPC2_32_RRR1_MSUBAD_H_32_UL:
7627 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7628 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7629 break;
7630 case OPC2_32_RRR1_MSUBAD_H_32_UU:
7631 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7632 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7633 break;
7634 case OPC2_32_RRR1_MSUBADS_H_32_LL:
7635 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7636 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7637 n, MODE_LL);
7638 break;
7639 case OPC2_32_RRR1_MSUBADS_H_32_LU:
7640 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7641 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7642 n, MODE_LU);
7643 break;
7644 case OPC2_32_RRR1_MSUBADS_H_32_UL:
7645 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7646 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7647 n, MODE_UL);
7648 break;
7649 case OPC2_32_RRR1_MSUBADS_H_32_UU:
7650 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7651 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7652 n, MODE_UU);
7653 break;
7654 case OPC2_32_RRR1_MSUBADM_H_64_LL:
7655 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7656 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7657 n, MODE_LL);
7658 break;
7659 case OPC2_32_RRR1_MSUBADM_H_64_LU:
7660 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7661 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7662 n, MODE_LU);
7663 break;
7664 case OPC2_32_RRR1_MSUBADM_H_64_UL:
7665 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7666 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7667 n, MODE_UL);
7668 break;
7669 case OPC2_32_RRR1_MSUBADM_H_64_UU:
7670 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7671 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7672 n, MODE_UU);
7673 break;
7674 case OPC2_32_RRR1_MSUBADMS_H_64_LL:
7675 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7676 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7677 n, MODE_LL);
7678 break;
7679 case OPC2_32_RRR1_MSUBADMS_H_64_LU:
7680 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7681 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7682 n, MODE_LU);
7683 break;
7684 case OPC2_32_RRR1_MSUBADMS_H_64_UL:
7685 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7686 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7687 n, MODE_UL);
7688 break;
7689 case OPC2_32_RRR1_MSUBADMS_H_64_UU:
7690 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7691 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7692 n, MODE_UU);
7693 break;
7694 case OPC2_32_RRR1_MSUBADR_H_16_LL:
7695 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7696 cpu_gpr_d[r2], n, MODE_LL);
7697 break;
7698 case OPC2_32_RRR1_MSUBADR_H_16_LU:
7699 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7700 cpu_gpr_d[r2], n, MODE_LU);
7701 break;
7702 case OPC2_32_RRR1_MSUBADR_H_16_UL:
7703 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7704 cpu_gpr_d[r2], n, MODE_UL);
7705 break;
7706 case OPC2_32_RRR1_MSUBADR_H_16_UU:
7707 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7708 cpu_gpr_d[r2], n, MODE_UU);
7709 break;
7710 case OPC2_32_RRR1_MSUBADRS_H_16_LL:
7711 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7712 cpu_gpr_d[r2], n, MODE_LL);
7713 break;
7714 case OPC2_32_RRR1_MSUBADRS_H_16_LU:
7715 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7716 cpu_gpr_d[r2], n, MODE_LU);
7717 break;
7718 case OPC2_32_RRR1_MSUBADRS_H_16_UL:
7719 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7720 cpu_gpr_d[r2], n, MODE_UL);
7721 break;
7722 case OPC2_32_RRR1_MSUBADRS_H_16_UU:
7723 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7724 cpu_gpr_d[r2], n, MODE_UU);
7725 break;
7726 }
7727 }
7728
7729 /* RRRR format */
7730 static void decode_rrrr_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
7731 {
7732 uint32_t op2;
7733 int r1, r2, r3, r4;
7734 TCGv tmp_width, tmp_pos;
7735
7736 r1 = MASK_OP_RRRR_S1(ctx->opcode);
7737 r2 = MASK_OP_RRRR_S2(ctx->opcode);
7738 r3 = MASK_OP_RRRR_S3(ctx->opcode);
7739 r4 = MASK_OP_RRRR_D(ctx->opcode);
7740 op2 = MASK_OP_RRRR_OP2(ctx->opcode);
7741
7742 tmp_pos = tcg_temp_new();
7743 tmp_width = tcg_temp_new();
7744
7745 switch (op2) {
7746 case OPC2_32_RRRR_DEXTR:
7747 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
7748 if (r1 == r2) {
7749 tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
7750 } else {
7751 tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos);
7752 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos);
7753 tcg_gen_shr_tl(tmp_pos, cpu_gpr_d[r2], tmp_pos);
7754 tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, tmp_pos);
7755 }
7756 break;
7757 case OPC2_32_RRRR_EXTR:
7758 case OPC2_32_RRRR_EXTR_U:
7759 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f);
7760 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
7761 tcg_gen_add_tl(tmp_pos, tmp_pos, tmp_width);
7762 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos);
7763 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
7764 tcg_gen_subfi_tl(tmp_width, 32, tmp_width);
7765 if (op2 == OPC2_32_RRRR_EXTR) {
7766 tcg_gen_sar_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width);
7767 } else {
7768 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width);
7769 }
7770 break;
7771 case OPC2_32_RRRR_INSERT:
7772 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f);
7773 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
7774 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], tmp_width,
7775 tmp_pos);
7776 break;
7777 }
7778 tcg_temp_free(tmp_pos);
7779 tcg_temp_free(tmp_width);
7780 }
7781
7782 /* RRRW format */
7783 static void decode_rrrw_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
7784 {
7785 uint32_t op2;
7786 int r1, r2, r3, r4;
7787 int32_t width;
7788
7789 TCGv temp, temp2;
7790
7791 op2 = MASK_OP_RRRW_OP2(ctx->opcode);
7792 r1 = MASK_OP_RRRW_S1(ctx->opcode);
7793 r2 = MASK_OP_RRRW_S2(ctx->opcode);
7794 r3 = MASK_OP_RRRW_S3(ctx->opcode);
7795 r4 = MASK_OP_RRRW_D(ctx->opcode);
7796 width = MASK_OP_RRRW_WIDTH(ctx->opcode);
7797
7798 temp = tcg_temp_new();
7799
7800 switch (op2) {
7801 case OPC2_32_RRRW_EXTR:
7802 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
7803 tcg_gen_addi_tl(temp, temp, width);
7804 tcg_gen_subfi_tl(temp, 32, temp);
7805 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
7806 tcg_gen_sari_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], 32 - width);
7807 break;
7808 case OPC2_32_RRRW_EXTR_U:
7809 if (width == 0) {
7810 tcg_gen_movi_tl(cpu_gpr_d[r4], 0);
7811 } else {
7812 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
7813 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
7814 tcg_gen_andi_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], ~0u >> (32-width));
7815 }
7816 break;
7817 case OPC2_32_RRRW_IMASK:
7818 temp2 = tcg_temp_new();
7819
7820 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
7821 tcg_gen_movi_tl(temp2, (1 << width) - 1);
7822 tcg_gen_shl_tl(temp2, temp2, temp);
7823 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r2], temp);
7824 tcg_gen_mov_tl(cpu_gpr_d[r4+1], temp2);
7825
7826 tcg_temp_free(temp2);
7827 break;
7828 case OPC2_32_RRRW_INSERT:
7829 temp2 = tcg_temp_new();
7830
7831 tcg_gen_movi_tl(temp, width);
7832 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3], 0x1f);
7833 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp2);
7834
7835 tcg_temp_free(temp2);
7836 break;
7837 }
7838 tcg_temp_free(temp);
7839 }
7840
7841 /* SYS Format*/
7842 static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx)
7843 {
7844 uint32_t op2;
7845 uint32_t r1;
7846 TCGLabel *l1;
7847 TCGv tmp;
7848
7849 op2 = MASK_OP_SYS_OP2(ctx->opcode);
7850 r1 = MASK_OP_SYS_S1D(ctx->opcode);
7851
7852 switch (op2) {
7853 case OPC2_32_SYS_DEBUG:
7854 /* raise EXCP_DEBUG */
7855 break;
7856 case OPC2_32_SYS_DISABLE:
7857 tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE);
7858 break;
7859 case OPC2_32_SYS_DSYNC:
7860 break;
7861 case OPC2_32_SYS_ENABLE:
7862 tcg_gen_ori_tl(cpu_ICR, cpu_ICR, MASK_ICR_IE);
7863 break;
7864 case OPC2_32_SYS_ISYNC:
7865 break;
7866 case OPC2_32_SYS_NOP:
7867 break;
7868 case OPC2_32_SYS_RET:
7869 gen_compute_branch(ctx, op2, 0, 0, 0, 0);
7870 break;
7871 case OPC2_32_SYS_FRET:
7872 gen_fret(ctx);
7873 break;
7874 case OPC2_32_SYS_RFE:
7875 gen_helper_rfe(cpu_env);
7876 tcg_gen_exit_tb(0);
7877 ctx->bstate = BS_BRANCH;
7878 break;
7879 case OPC2_32_SYS_RFM:
7880 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
7881 tmp = tcg_temp_new();
7882 l1 = gen_new_label();
7883
7884 tcg_gen_ld32u_tl(tmp, cpu_env, offsetof(CPUTriCoreState, DBGSR));
7885 tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE);
7886 tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1);
7887 gen_helper_rfm(cpu_env);
7888 gen_set_label(l1);
7889 tcg_gen_exit_tb(0);
7890 ctx->bstate = BS_BRANCH;
7891 tcg_temp_free(tmp);
7892 } else {
7893 /* generate privilege trap */
7894 }
7895 break;
7896 case OPC2_32_SYS_RSLCX:
7897 gen_helper_rslcx(cpu_env);
7898 break;
7899 case OPC2_32_SYS_SVLCX:
7900 gen_helper_svlcx(cpu_env);
7901 break;
7902 case OPC2_32_SYS_RESTORE:
7903 if (tricore_feature(env, TRICORE_FEATURE_16)) {
7904 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM ||
7905 (ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_UM1) {
7906 tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1);
7907 } /* else raise privilege trap */
7908 } /* else raise illegal opcode trap */
7909 break;
7910 case OPC2_32_SYS_TRAPSV:
7911 /* TODO: raise sticky overflow trap */
7912 break;
7913 case OPC2_32_SYS_TRAPV:
7914 /* TODO: raise overflow trap */
7915 break;
7916 }
7917 }
7918
7919 static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
7920 {
7921 int op1;
7922 int32_t r1, r2, r3;
7923 int32_t address, const16;
7924 int8_t b, const4;
7925 int32_t bpos;
7926 TCGv temp, temp2, temp3;
7927
7928 op1 = MASK_OP_MAJOR(ctx->opcode);
7929
7930 /* handle JNZ.T opcode only being 7 bit long */
7931 if (unlikely((op1 & 0x7f) == OPCM_32_BRN_JTT)) {
7932 op1 = OPCM_32_BRN_JTT;
7933 }
7934
7935 switch (op1) {
7936 /* ABS-format */
7937 case OPCM_32_ABS_LDW:
7938 decode_abs_ldw(env, ctx);
7939 break;
7940 case OPCM_32_ABS_LDB:
7941 decode_abs_ldb(env, ctx);
7942 break;
7943 case OPCM_32_ABS_LDMST_SWAP:
7944 decode_abs_ldst_swap(env, ctx);
7945 break;
7946 case OPCM_32_ABS_LDST_CONTEXT:
7947 decode_abs_ldst_context(env, ctx);
7948 break;
7949 case OPCM_32_ABS_STORE:
7950 decode_abs_store(env, ctx);
7951 break;
7952 case OPCM_32_ABS_STOREB_H:
7953 decode_abs_storeb_h(env, ctx);
7954 break;
7955 case OPC1_32_ABS_STOREQ:
7956 address = MASK_OP_ABS_OFF18(ctx->opcode);
7957 r1 = MASK_OP_ABS_S1D(ctx->opcode);
7958 temp = tcg_const_i32(EA_ABS_FORMAT(address));
7959 temp2 = tcg_temp_new();
7960
7961 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16);
7962 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW);
7963
7964 tcg_temp_free(temp2);
7965 tcg_temp_free(temp);
7966 break;
7967 case OPC1_32_ABS_LD_Q:
7968 address = MASK_OP_ABS_OFF18(ctx->opcode);
7969 r1 = MASK_OP_ABS_S1D(ctx->opcode);
7970 temp = tcg_const_i32(EA_ABS_FORMAT(address));
7971
7972 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
7973 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
7974
7975 tcg_temp_free(temp);
7976 break;
7977 case OPC1_32_ABS_LEA:
7978 address = MASK_OP_ABS_OFF18(ctx->opcode);
7979 r1 = MASK_OP_ABS_S1D(ctx->opcode);
7980 tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address));
7981 break;
7982 /* ABSB-format */
7983 case OPC1_32_ABSB_ST_T:
7984 address = MASK_OP_ABS_OFF18(ctx->opcode);
7985 b = MASK_OP_ABSB_B(ctx->opcode);
7986 bpos = MASK_OP_ABSB_BPOS(ctx->opcode);
7987
7988 temp = tcg_const_i32(EA_ABS_FORMAT(address));
7989 temp2 = tcg_temp_new();
7990
7991 tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB);
7992 tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos));
7993 tcg_gen_ori_tl(temp2, temp2, (b << bpos));
7994 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB);
7995
7996 tcg_temp_free(temp);
7997 tcg_temp_free(temp2);
7998 break;
7999 /* B-format */
8000 case OPC1_32_B_CALL:
8001 case OPC1_32_B_CALLA:
8002 case OPC1_32_B_FCALL:
8003 case OPC1_32_B_FCALLA:
8004 case OPC1_32_B_J:
8005 case OPC1_32_B_JA:
8006 case OPC1_32_B_JL:
8007 case OPC1_32_B_JLA:
8008 address = MASK_OP_B_DISP24_SEXT(ctx->opcode);
8009 gen_compute_branch(ctx, op1, 0, 0, 0, address);
8010 break;
8011 /* Bit-format */
8012 case OPCM_32_BIT_ANDACC:
8013 decode_bit_andacc(env, ctx);
8014 break;
8015 case OPCM_32_BIT_LOGICAL_T1:
8016 decode_bit_logical_t(env, ctx);
8017 break;
8018 case OPCM_32_BIT_INSERT:
8019 decode_bit_insert(env, ctx);
8020 break;
8021 case OPCM_32_BIT_LOGICAL_T2:
8022 decode_bit_logical_t2(env, ctx);
8023 break;
8024 case OPCM_32_BIT_ORAND:
8025 decode_bit_orand(env, ctx);
8026 break;
8027 case OPCM_32_BIT_SH_LOGIC1:
8028 decode_bit_sh_logic1(env, ctx);
8029 break;
8030 case OPCM_32_BIT_SH_LOGIC2:
8031 decode_bit_sh_logic2(env, ctx);
8032 break;
8033 /* BO Format */
8034 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE:
8035 decode_bo_addrmode_post_pre_base(env, ctx);
8036 break;
8037 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR:
8038 decode_bo_addrmode_bitreverse_circular(env, ctx);
8039 break;
8040 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE:
8041 decode_bo_addrmode_ld_post_pre_base(env, ctx);
8042 break;
8043 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR:
8044 decode_bo_addrmode_ld_bitreverse_circular(env, ctx);
8045 break;
8046 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE:
8047 decode_bo_addrmode_stctx_post_pre_base(env, ctx);
8048 break;
8049 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR:
8050 decode_bo_addrmode_ldmst_bitreverse_circular(env, ctx);
8051 break;
8052 /* BOL-format */
8053 case OPC1_32_BOL_LD_A_LONGOFF:
8054 case OPC1_32_BOL_LD_W_LONGOFF:
8055 case OPC1_32_BOL_LEA_LONGOFF:
8056 case OPC1_32_BOL_ST_W_LONGOFF:
8057 case OPC1_32_BOL_ST_A_LONGOFF:
8058 case OPC1_32_BOL_LD_B_LONGOFF:
8059 case OPC1_32_BOL_LD_BU_LONGOFF:
8060 case OPC1_32_BOL_LD_H_LONGOFF:
8061 case OPC1_32_BOL_LD_HU_LONGOFF:
8062 case OPC1_32_BOL_ST_B_LONGOFF:
8063 case OPC1_32_BOL_ST_H_LONGOFF:
8064 decode_bol_opc(env, ctx, op1);
8065 break;
8066 /* BRC Format */
8067 case OPCM_32_BRC_EQ_NEQ:
8068 case OPCM_32_BRC_GE:
8069 case OPCM_32_BRC_JLT:
8070 case OPCM_32_BRC_JNE:
8071 const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode);
8072 address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode);
8073 r1 = MASK_OP_BRC_S1(ctx->opcode);
8074 gen_compute_branch(ctx, op1, r1, 0, const4, address);
8075 break;
8076 /* BRN Format */
8077 case OPCM_32_BRN_JTT:
8078 address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode);
8079 r1 = MASK_OP_BRN_S1(ctx->opcode);
8080 gen_compute_branch(ctx, op1, r1, 0, 0, address);
8081 break;
8082 /* BRR Format */
8083 case OPCM_32_BRR_EQ_NEQ:
8084 case OPCM_32_BRR_ADDR_EQ_NEQ:
8085 case OPCM_32_BRR_GE:
8086 case OPCM_32_BRR_JLT:
8087 case OPCM_32_BRR_JNE:
8088 case OPCM_32_BRR_JNZ:
8089 case OPCM_32_BRR_LOOP:
8090 address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode);
8091 r2 = MASK_OP_BRR_S2(ctx->opcode);
8092 r1 = MASK_OP_BRR_S1(ctx->opcode);
8093 gen_compute_branch(ctx, op1, r1, r2, 0, address);
8094 break;
8095 /* RC Format */
8096 case OPCM_32_RC_LOGICAL_SHIFT:
8097 decode_rc_logical_shift(env, ctx);
8098 break;
8099 case OPCM_32_RC_ACCUMULATOR:
8100 decode_rc_accumulator(env, ctx);
8101 break;
8102 case OPCM_32_RC_SERVICEROUTINE:
8103 decode_rc_serviceroutine(env, ctx);
8104 break;
8105 case OPCM_32_RC_MUL:
8106 decode_rc_mul(env, ctx);
8107 break;
8108 /* RCPW Format */
8109 case OPCM_32_RCPW_MASK_INSERT:
8110 decode_rcpw_insert(env, ctx);
8111 break;
8112 /* RCRR Format */
8113 case OPC1_32_RCRR_INSERT:
8114 r1 = MASK_OP_RCRR_S1(ctx->opcode);
8115 r2 = MASK_OP_RCRR_S3(ctx->opcode);
8116 r3 = MASK_OP_RCRR_D(ctx->opcode);
8117 const16 = MASK_OP_RCRR_CONST4(ctx->opcode);
8118 temp = tcg_const_i32(const16);
8119 temp2 = tcg_temp_new(); /* width*/
8120 temp3 = tcg_temp_new(); /* pos */
8121
8122 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f);
8123 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
8124
8125 gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3);
8126
8127 tcg_temp_free(temp);
8128 tcg_temp_free(temp2);
8129 tcg_temp_free(temp3);
8130 break;
8131 /* RCRW Format */
8132 case OPCM_32_RCRW_MASK_INSERT:
8133 decode_rcrw_insert(env, ctx);
8134 break;
8135 /* RCR Format */
8136 case OPCM_32_RCR_COND_SELECT:
8137 decode_rcr_cond_select(env, ctx);
8138 break;
8139 case OPCM_32_RCR_MADD:
8140 decode_rcr_madd(env, ctx);
8141 break;
8142 case OPCM_32_RCR_MSUB:
8143 decode_rcr_msub(env, ctx);
8144 break;
8145 /* RLC Format */
8146 case OPC1_32_RLC_ADDI:
8147 case OPC1_32_RLC_ADDIH:
8148 case OPC1_32_RLC_ADDIH_A:
8149 case OPC1_32_RLC_MFCR:
8150 case OPC1_32_RLC_MOV:
8151 case OPC1_32_RLC_MOV_64:
8152 case OPC1_32_RLC_MOV_U:
8153 case OPC1_32_RLC_MOV_H:
8154 case OPC1_32_RLC_MOVH_A:
8155 case OPC1_32_RLC_MTCR:
8156 decode_rlc_opc(env, ctx, op1);
8157 break;
8158 /* RR Format */
8159 case OPCM_32_RR_ACCUMULATOR:
8160 decode_rr_accumulator(env, ctx);
8161 break;
8162 case OPCM_32_RR_LOGICAL_SHIFT:
8163 decode_rr_logical_shift(env, ctx);
8164 break;
8165 case OPCM_32_RR_ADDRESS:
8166 decode_rr_address(env, ctx);
8167 break;
8168 case OPCM_32_RR_IDIRECT:
8169 decode_rr_idirect(env, ctx);
8170 break;
8171 case OPCM_32_RR_DIVIDE:
8172 decode_rr_divide(env, ctx);
8173 break;
8174 /* RR1 Format */
8175 case OPCM_32_RR1_MUL:
8176 decode_rr1_mul(env, ctx);
8177 break;
8178 case OPCM_32_RR1_MULQ:
8179 decode_rr1_mulq(env, ctx);
8180 break;
8181 /* RR2 format */
8182 case OPCM_32_RR2_MUL:
8183 decode_rr2_mul(env, ctx);
8184 break;
8185 /* RRPW format */
8186 case OPCM_32_RRPW_EXTRACT_INSERT:
8187 decode_rrpw_extract_insert(env, ctx);
8188 break;
8189 case OPC1_32_RRPW_DEXTR:
8190 r1 = MASK_OP_RRPW_S1(ctx->opcode);
8191 r2 = MASK_OP_RRPW_S2(ctx->opcode);
8192 r3 = MASK_OP_RRPW_D(ctx->opcode);
8193 const16 = MASK_OP_RRPW_POS(ctx->opcode);
8194 if (r1 == r2) {
8195 tcg_gen_rotli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], const16);
8196 } else {
8197 temp = tcg_temp_new();
8198 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], const16);
8199 tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], 32 - const16);
8200 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
8201 tcg_temp_free(temp);
8202 }
8203 break;
8204 /* RRR Format */
8205 case OPCM_32_RRR_COND_SELECT:
8206 decode_rrr_cond_select(env, ctx);
8207 break;
8208 case OPCM_32_RRR_DIVIDE:
8209 decode_rrr_divide(env, ctx);
8210 /* RRR2 Format */
8211 case OPCM_32_RRR2_MADD:
8212 decode_rrr2_madd(env, ctx);
8213 break;
8214 case OPCM_32_RRR2_MSUB:
8215 decode_rrr2_msub(env, ctx);
8216 break;
8217 /* RRR1 format */
8218 case OPCM_32_RRR1_MADD:
8219 decode_rrr1_madd(env, ctx);
8220 break;
8221 case OPCM_32_RRR1_MADDQ_H:
8222 decode_rrr1_maddq_h(env, ctx);
8223 break;
8224 case OPCM_32_RRR1_MADDSU_H:
8225 decode_rrr1_maddsu_h(env, ctx);
8226 break;
8227 case OPCM_32_RRR1_MSUB_H:
8228 decode_rrr1_msub(env, ctx);
8229 break;
8230 case OPCM_32_RRR1_MSUB_Q:
8231 decode_rrr1_msubq_h(env, ctx);
8232 break;
8233 case OPCM_32_RRR1_MSUBAD_H:
8234 decode_rrr1_msubad_h(env, ctx);
8235 break;
8236 /* RRRR format */
8237 case OPCM_32_RRRR_EXTRACT_INSERT:
8238 decode_rrrr_extract_insert(env, ctx);
8239 /* RRRW format */
8240 case OPCM_32_RRRW_EXTRACT_INSERT:
8241 decode_rrrw_extract_insert(env, ctx);
8242 break;
8243 /* SYS format */
8244 case OPCM_32_SYS_INTERRUPTS:
8245 decode_sys_interrupts(env, ctx);
8246 break;
8247 case OPC1_32_SYS_RSTV:
8248 tcg_gen_movi_tl(cpu_PSW_V, 0);
8249 tcg_gen_mov_tl(cpu_PSW_SV, cpu_PSW_V);
8250 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
8251 tcg_gen_mov_tl(cpu_PSW_SAV, cpu_PSW_V);
8252 break;
8253 }
8254 }
8255
8256 static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
8257 {
8258 /* 16-Bit Instruction */
8259 if ((ctx->opcode & 0x1) == 0) {
8260 ctx->next_pc = ctx->pc + 2;
8261 decode_16Bit_opc(env, ctx);
8262 /* 32-Bit Instruction */
8263 } else {
8264 ctx->next_pc = ctx->pc + 4;
8265 decode_32Bit_opc(env, ctx);
8266 }
8267 }
8268
8269 static inline void
8270 gen_intermediate_code_internal(TriCoreCPU *cpu, struct TranslationBlock *tb,
8271 int search_pc)
8272 {
8273 CPUState *cs = CPU(cpu);
8274 CPUTriCoreState *env = &cpu->env;
8275 DisasContext ctx;
8276 target_ulong pc_start;
8277 int num_insns;
8278
8279 if (search_pc) {
8280 qemu_log("search pc %d\n", search_pc);
8281 }
8282
8283 num_insns = 0;
8284 pc_start = tb->pc;
8285 ctx.pc = pc_start;
8286 ctx.saved_pc = -1;
8287 ctx.tb = tb;
8288 ctx.singlestep_enabled = cs->singlestep_enabled;
8289 ctx.bstate = BS_NONE;
8290 ctx.mem_idx = cpu_mmu_index(env);
8291
8292 tcg_clear_temp_count();
8293 gen_tb_start(tb);
8294 while (ctx.bstate == BS_NONE) {
8295 ctx.opcode = cpu_ldl_code(env, ctx.pc);
8296 decode_opc(env, &ctx, 0);
8297
8298 num_insns++;
8299
8300 if (tcg_op_buf_full()) {
8301 gen_save_pc(ctx.next_pc);
8302 tcg_gen_exit_tb(0);
8303 break;
8304 }
8305 if (singlestep) {
8306 gen_save_pc(ctx.next_pc);
8307 tcg_gen_exit_tb(0);
8308 break;
8309 }
8310 ctx.pc = ctx.next_pc;
8311 }
8312
8313 gen_tb_end(tb, num_insns);
8314 if (search_pc) {
8315 printf("done_generating search pc\n");
8316 } else {
8317 tb->size = ctx.pc - pc_start;
8318 tb->icount = num_insns;
8319 }
8320 if (tcg_check_temp_count()) {
8321 printf("LEAK at %08x\n", env->PC);
8322 }
8323
8324 #ifdef DEBUG_DISAS
8325 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
8326 qemu_log("IN: %s\n", lookup_symbol(pc_start));
8327 log_target_disas(cs, pc_start, ctx.pc - pc_start, 0);
8328 qemu_log("\n");
8329 }
8330 #endif
8331 }
8332
8333 void
8334 gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
8335 {
8336 gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, false);
8337 }
8338
8339 void
8340 gen_intermediate_code_pc(CPUTriCoreState *env, struct TranslationBlock *tb)
8341 {
8342 gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, true);
8343 }
8344
8345 void
8346 restore_state_to_opc(CPUTriCoreState *env, TranslationBlock *tb, int pc_pos)
8347 {
8348 env->PC = tcg_ctx.gen_opc_pc[pc_pos];
8349 }
8350 /*
8351 *
8352 * Initialization
8353 *
8354 */
8355
8356 void cpu_state_reset(CPUTriCoreState *env)
8357 {
8358 /* Reset Regs to Default Value */
8359 env->PSW = 0xb80;
8360 }
8361
8362 static void tricore_tcg_init_csfr(void)
8363 {
8364 cpu_PCXI = tcg_global_mem_new(TCG_AREG0,
8365 offsetof(CPUTriCoreState, PCXI), "PCXI");
8366 cpu_PSW = tcg_global_mem_new(TCG_AREG0,
8367 offsetof(CPUTriCoreState, PSW), "PSW");
8368 cpu_PC = tcg_global_mem_new(TCG_AREG0,
8369 offsetof(CPUTriCoreState, PC), "PC");
8370 cpu_ICR = tcg_global_mem_new(TCG_AREG0,
8371 offsetof(CPUTriCoreState, ICR), "ICR");
8372 }
8373
8374 void tricore_tcg_init(void)
8375 {
8376 int i;
8377 static int inited;
8378 if (inited) {
8379 return;
8380 }
8381 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
8382 /* reg init */
8383 for (i = 0 ; i < 16 ; i++) {
8384 cpu_gpr_a[i] = tcg_global_mem_new(TCG_AREG0,
8385 offsetof(CPUTriCoreState, gpr_a[i]),
8386 regnames_a[i]);
8387 }
8388 for (i = 0 ; i < 16 ; i++) {
8389 cpu_gpr_d[i] = tcg_global_mem_new(TCG_AREG0,
8390 offsetof(CPUTriCoreState, gpr_d[i]),
8391 regnames_d[i]);
8392 }
8393 tricore_tcg_init_csfr();
8394 /* init PSW flag cache */
8395 cpu_PSW_C = tcg_global_mem_new(TCG_AREG0,
8396 offsetof(CPUTriCoreState, PSW_USB_C),
8397 "PSW_C");
8398 cpu_PSW_V = tcg_global_mem_new(TCG_AREG0,
8399 offsetof(CPUTriCoreState, PSW_USB_V),
8400 "PSW_V");
8401 cpu_PSW_SV = tcg_global_mem_new(TCG_AREG0,
8402 offsetof(CPUTriCoreState, PSW_USB_SV),
8403 "PSW_SV");
8404 cpu_PSW_AV = tcg_global_mem_new(TCG_AREG0,
8405 offsetof(CPUTriCoreState, PSW_USB_AV),
8406 "PSW_AV");
8407 cpu_PSW_SAV = tcg_global_mem_new(TCG_AREG0,
8408 offsetof(CPUTriCoreState, PSW_USB_SAV),
8409 "PSW_SAV");
8410 }
AR7 emulation for QEMU