target-cris/helper.c

   1 /*
   2  *  CRIS helper routines.
   3  *
   4  *  Copyright (c) 2007 AXIS Communications AB
   5  *  Written by Edgar E. Iglesias.
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "cpu.h"
  22 #include "mmu.h"
  23 #include "qemu/host-utils.h"
  24
  25
  26 //#define CRIS_HELPER_DEBUG
  27
  28
  29 #ifdef CRIS_HELPER_DEBUG
  30 #define D(x) x
  31 #define D_LOG(...) qemu_log(__VA_ARGS__)
  32 #else
  33 #define D(x)
  34 #define D_LOG(...) do { } while (0)
  35 #endif
  36
  37 #if defined(CONFIG_USER_ONLY)
  38
  39 void cris_cpu_do_interrupt(CPUState *cs)
  40 {
  41     CRISCPU *cpu = CRIS_CPU(cs);
  42     CPUCRISState *env = &cpu->env;
  43
  44     env->exception_index = -1;
  45     env->pregs[PR_ERP] = env->pc;
  46 }
  47
  48 void crisv10_cpu_do_interrupt(CPUState *cs)
  49 {
  50     cris_cpu_do_interrupt(cs);
  51 }
  52
  53 int cpu_cris_handle_mmu_fault(CPUCRISState * env, target_ulong address, int rw,
  54                               int mmu_idx)
  55 {
  56     CRISCPU *cpu = cris_env_get_cpu(env);
  57
  58     env->exception_index = 0xaa;
  59     env->pregs[PR_EDA] = address;
  60     cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
  61     return 1;
  62 }
  63
  64 #else /* !CONFIG_USER_ONLY */
  65
  66
  67 static void cris_shift_ccs(CPUCRISState *env)
  68 {
  69     uint32_t ccs;
  70     /* Apply the ccs shift.  */
  71     ccs = env->pregs[PR_CCS];
  72     ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff;
  73     env->pregs[PR_CCS] = ccs;
  74 }
  75
  76 int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw,
  77                               int mmu_idx)
  78 {
  79     D(CPUState *cpu = CPU(cris_env_get_cpu(env)));
  80     struct cris_mmu_result res;
  81     int prot, miss;
  82     int r = -1;
  83     target_ulong phy;
  84
  85     D(printf("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw));
  86     miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
  87                               rw, mmu_idx, 0);
  88     if (miss) {
  89         if (env->exception_index == EXCP_BUSFAULT) {
  90             cpu_abort(env,
  91                       "CRIS: Illegal recursive bus fault."
  92                       "addr=%x rw=%d\n",
  93                       address, rw);
  94         }
  95
  96         env->pregs[PR_EDA] = address;
  97         env->exception_index = EXCP_BUSFAULT;
  98         env->fault_vector = res.bf_vec;
  99         r = 1;
 100     } else {
 101         /*
 102          * Mask off the cache selection bit. The ETRAX busses do not
 103          * see the top bit.
 104          */
 105         phy = res.phy & ~0x80000000;
 106         prot = res.prot;
 107         tlb_set_page(env, address & TARGET_PAGE_MASK, phy,
 108                      prot, mmu_idx, TARGET_PAGE_SIZE);
 109         r = 0;
 110     }
 111     if (r > 0) {
 112         D_LOG("%s returns %d irqreq=%x addr=%x phy=%x vec=%x pc=%x\n",
 113               __func__, r, cpu->interrupt_request, address, res.phy,
 114               res.bf_vec, env->pc);
 115     }
 116     return r;
 117 }
 118
 119 void crisv10_cpu_do_interrupt(CPUState *cs)
 120 {
 121     CRISCPU *cpu = CRIS_CPU(cs);
 122     CPUCRISState *env = &cpu->env;
 123     int ex_vec = -1;
 124
 125     D_LOG("exception index=%d interrupt_req=%d\n",
 126           env->exception_index,
 127           cs->interrupt_request);
 128
 129     if (env->dslot) {
 130         /* CRISv10 never takes interrupts while in a delay-slot.  */
 131         cpu_abort(env, "CRIS: Interrupt on delay-slot\n");
 132     }
 133
 134     assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
 135     switch (env->exception_index) {
 136     case EXCP_BREAK:
 137         /* These exceptions are genereated by the core itself.
 138            ERP should point to the insn following the brk.  */
 139         ex_vec = env->trap_vector;
 140         env->pregs[PRV10_BRP] = env->pc;
 141         break;
 142
 143     case EXCP_NMI:
 144         /* NMI is hardwired to vector zero.  */
 145         ex_vec = 0;
 146         env->pregs[PR_CCS] &= ~M_FLAG_V10;
 147         env->pregs[PRV10_BRP] = env->pc;
 148         break;
 149
 150     case EXCP_BUSFAULT:
 151         cpu_abort(env, "Unhandled busfault");
 152         break;
 153
 154     default:
 155         /* The interrupt controller gives us the vector.  */
 156         ex_vec = env->interrupt_vector;
 157         /* Normal interrupts are taken between
 158            TB's.  env->pc is valid here.  */
 159         env->pregs[PR_ERP] = env->pc;
 160         break;
 161     }
 162
 163     if (env->pregs[PR_CCS] & U_FLAG) {
 164         /* Swap stack pointers.  */
 165         env->pregs[PR_USP] = env->regs[R_SP];
 166         env->regs[R_SP] = env->ksp;
 167     }
 168
 169     /* Now that we are in kernel mode, load the handlers address.  */
 170     env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
 171     env->locked_irq = 1;
 172     env->pregs[PR_CCS] |= F_FLAG_V10; /* set F.  */
 173
 174     qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
 175                   __func__, env->pc, ex_vec,
 176                   env->pregs[PR_CCS],
 177                   env->pregs[PR_PID],
 178                   env->pregs[PR_ERP]);
 179 }
 180
 181 void cris_cpu_do_interrupt(CPUState *cs)
 182 {
 183     CRISCPU *cpu = CRIS_CPU(cs);
 184     CPUCRISState *env = &cpu->env;
 185     int ex_vec = -1;
 186
 187     D_LOG("exception index=%d interrupt_req=%d\n",
 188           env->exception_index,
 189           cs->interrupt_request);
 190
 191     switch (env->exception_index) {
 192     case EXCP_BREAK:
 193         /* These exceptions are genereated by the core itself.
 194            ERP should point to the insn following the brk.  */
 195         ex_vec = env->trap_vector;
 196         env->pregs[PR_ERP] = env->pc;
 197         break;
 198
 199     case EXCP_NMI:
 200         /* NMI is hardwired to vector zero.  */
 201         ex_vec = 0;
 202         env->pregs[PR_CCS] &= ~M_FLAG_V32;
 203         env->pregs[PR_NRP] = env->pc;
 204         break;
 205
 206     case EXCP_BUSFAULT:
 207         ex_vec = env->fault_vector;
 208         env->pregs[PR_ERP] = env->pc;
 209         break;
 210
 211     default:
 212         /* The interrupt controller gives us the vector.  */
 213         ex_vec = env->interrupt_vector;
 214         /* Normal interrupts are taken between
 215            TB's.  env->pc is valid here.  */
 216         env->pregs[PR_ERP] = env->pc;
 217         break;
 218     }
 219
 220     /* Fill in the IDX field.  */
 221     env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;
 222
 223     if (env->dslot) {
 224         D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
 225               " ERP=%x pid=%x ccs=%x cc=%d %x\n",
 226               ex_vec, env->pc, env->dslot,
 227               env->regs[R_SP],
 228               env->pregs[PR_ERP], env->pregs[PR_PID],
 229               env->pregs[PR_CCS],
 230               env->cc_op, env->cc_mask);
 231         /* We loose the btarget, btaken state here so rexec the
 232            branch.  */
 233         env->pregs[PR_ERP] -= env->dslot;
 234         /* Exception starts with dslot cleared.  */
 235         env->dslot = 0;
 236     }
 237
 238     if (env->pregs[PR_CCS] & U_FLAG) {
 239         /* Swap stack pointers.  */
 240         env->pregs[PR_USP] = env->regs[R_SP];
 241         env->regs[R_SP] = env->ksp;
 242     }
 243
 244     /* Apply the CRIS CCS shift. Clears U if set.  */
 245     cris_shift_ccs(env);
 246
 247     /* Now that we are in kernel mode, load the handlers address.
 248        This load may not fault, real hw leaves that behaviour as
 249        undefined.  */
 250     env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
 251
 252     /* Clear the excption_index to avoid spurios hw_aborts for recursive
 253        bus faults.  */
 254     env->exception_index = -1;
 255
 256     D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
 257           __func__, env->pc, ex_vec,
 258           env->pregs[PR_CCS],
 259           env->pregs[PR_PID],
 260           env->pregs[PR_ERP]);
 261 }
 262
 263 hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 264 {
 265     CRISCPU *cpu = CRIS_CPU(cs);
 266     uint32_t phy = addr;
 267     struct cris_mmu_result res;
 268     int miss;
 269
 270     miss = cris_mmu_translate(&res, &cpu->env, addr, 0, 0, 1);
 271     /* If D TLB misses, try I TLB.  */
 272     if (miss) {
 273         miss = cris_mmu_translate(&res, &cpu->env, addr, 2, 0, 1);
 274     }
 275
 276     if (!miss) {
 277         phy = res.phy;
 278     }
 279     D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
 280     return phy;
 281 }
 282 #endif