include/hw/pci-host/xilinx-pcie.h

   1 /*
   2  * Xilinx PCIe host controller emulation.
   3  *
   4  * Copyright (c) 2016 Imagination Technologies
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef HW_XILINX_PCIE_H
  21 #define HW_XILINX_PCIE_H
  22
  23 #include "hw/sysbus.h"
  24 #include "hw/pci/pci.h"
  25 #include "hw/pci/pci_bridge.h"
  26 #include "hw/pci/pcie_host.h"
  27 #include "qom/object.h"
  28
  29 #define TYPE_XILINX_PCIE_HOST "xilinx-pcie-host"
  30 OBJECT_DECLARE_SIMPLE_TYPE(XilinxPCIEHost, XILINX_PCIE_HOST)
  31
  32 #define TYPE_XILINX_PCIE_ROOT "xilinx-pcie-root"
  33 OBJECT_DECLARE_SIMPLE_TYPE(XilinxPCIERoot, XILINX_PCIE_ROOT)
  34
  35 struct XilinxPCIERoot {
  36     PCIBridge parent_obj;
  37 };
  38
  39 typedef struct XilinxPCIEInt {
  40     uint32_t fifo_reg1;
  41     uint32_t fifo_reg2;
  42 } XilinxPCIEInt;
  43
  44 struct XilinxPCIEHost {
  45     PCIExpressHost parent_obj;
  46
  47     char name[16];
  48
  49     uint32_t bus_nr;
  50     uint64_t cfg_base, cfg_size;
  51     uint64_t mmio_base, mmio_size;
  52     bool link_up;
  53     qemu_irq irq;
  54
  55     MemoryRegion mmio, io;
  56
  57     XilinxPCIERoot root;
  58
  59     uint32_t intr;
  60     uint32_t intr_mask;
  61     XilinxPCIEInt intr_fifo[16];
  62     unsigned int intr_fifo_r, intr_fifo_w;
  63     uint32_t rpscr;
  64 };
  65
  66 #endif /* HW_XILINX_PCIE_H */