target/arm: Factor out FWB=0 specific part of combine_cacheattrs()
[qemu/ar7.git] / target / ppc / tcg-stub.c
blobaadcf59d261a63a5651bb8f8d24d2702c5f5674d
1 /*
2 * PowerPC CPU initialization for qemu.
4 * Copyright (C) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "cpu.h"
21 #include "internal.h"
22 #include "hw/ppc/spapr.h"
24 void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
28 void destroy_ppc_opcodes(PowerPCCPU *cpu)
32 target_ulong softmmu_resize_hpt_prepare(PowerPCCPU *cpu,
33 SpaprMachineState *spapr,
34 target_ulong shift)
36 g_assert_not_reached();
39 target_ulong softmmu_resize_hpt_commit(PowerPCCPU *cpu,
40 SpaprMachineState *spapr,
41 target_ulong flags,
42 target_ulong shift)
44 g_assert_not_reached();