hw/net/ath5k.h

   1 /*
   2  * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
   3  * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
   4  *
   5  * Permission to use, copy, modify, and distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  *
  17  * $Id$
  18  */
  19
  20 /*
  21  * HAL interface for Atheros Wireless LAN devices.
  22  *
  23  * ar5k is a free replacement of the binary-only HAL used by some drivers
  24  * for Atheros chipsets. While using a different ABI, it tries to be
  25  * source-compatible with the original (non-free) HAL interface.
  26  *
  27  * Many thanks to various contributors who supported the development of
  28  * ar5k with hard work and useful information. And, of course, for all the
  29  * people who encouraged me to continue this work which has been based
  30  * on my initial approach found on http://team.vantronix.net/ar5k/.
  31  */
  32
  33 #ifndef _AR5K_H
  34 #define _AR5K_H
  35
  36 /*
  37  * Device tracing
  38  */
  39
  40 #define AR5K_TRACE_PRINTF(_trace)   AR5K_PRINTF(_trace)
  41
  42 /****************************\
  43   GENERIC DRIVER DEFINITIONS
  44 \****************************/
  45
  46 /*
  47  * C doesn't support boolean ;-(
  48  * TODO: See if there is a bool definition somewere else
  49  * in the kernel, we shouldn't redefine it if it does...
  50  */
  51 #ifndef TRUE
  52 #define TRUE    1
  53 #endif
  54 #ifndef FALSE
  55 #define FALSE   0
  56 #endif
  57
  58 /*
  59  * Error codes reported from HAL to the driver
  60  */
  61 typedef enum {
  62     AR5K_OK     = 0,    /* Everything went O.K.*/
  63     AR5K_ENOMEM = 1,    /* Unable to allocate memory for ath_hal*/
  64     AR5K_EIO    = 2,    /* Hardware I/O Error*/
  65     AR5K_EELOCKED   = 3,    /* Unable to access EEPROM*/
  66     AR5K_EEBADSUM   = 4,    /* Invalid EEPROM checksum*/
  67     AR5K_EEREAD = 5,    /* Unable to get device caps from EEPROM */
  68     AR5K_EEBADMAC   = 6,    /* Unable to read MAC address from EEPROM */
  69     AR5K_EINVAL = 7,    /* Invalid parameter to function */
  70     AR5K_ENOTSUPP   = 8,    /* Hardware revision not supported */
  71     AR5K_EINPROGRESS = 9,   /* Unexpected error ocured during process */
  72 } AR5K_STATUS;
  73
  74 /*
  75  * Some tuneable values (these should be changeable by the user)
  76  */
  77 #define AR5K_TUNE_DMA_BEACON_RESP       2
  78 #define AR5K_TUNE_SW_BEACON_RESP        10
  79 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF   0
  80 #define AR5K_TUNE_RADAR_ALERT           FALSE
  81 #define AR5K_TUNE_MIN_TX_FIFO_THRES     1
  82 #define AR5K_TUNE_MAX_TX_FIFO_THRES     ((MAX_PDU_LENGTH / 64) + 1)
  83 #define AR5K_TUNE_RSSI_THRES            1792
  84 #define AR5K_TUNE_REGISTER_TIMEOUT      20000
  85 #define AR5K_TUNE_REGISTER_DWELL_TIME       20000
  86 #define AR5K_TUNE_BEACON_INTERVAL       100
  87 #define AR5K_TUNE_AIFS              2
  88 #define AR5K_TUNE_AIFS_11B          2
  89 #define AR5K_TUNE_AIFS_XR           0
  90 #define AR5K_TUNE_CWMIN             15
  91 #define AR5K_TUNE_CWMIN_11B         31
  92 #define AR5K_TUNE_CWMIN_XR          3
  93 #define AR5K_TUNE_CWMAX             1023
  94 #define AR5K_TUNE_CWMAX_11B         1023
  95 #define AR5K_TUNE_CWMAX_XR          7
  96 #define AR5K_TUNE_NOISE_FLOOR           -72
  97 #define AR5K_TUNE_MAX_TXPOWER           60
  98 #define AR5K_TUNE_DEFAULT_TXPOWER       30
  99 #define AR5K_TUNE_TPC_TXPOWER           TRUE
 100 #define AR5K_TUNE_ANT_DIVERSITY         TRUE
 101 #define AR5K_TUNE_HWTXTRIES         4
 102
 103 /* token to use for aifs, cwmin, cwmax in MadWiFi */
 104 #define AR5K_TXQ_USEDEFAULT ((uint32_t) -1)
 105
 106 #define IEEE80211_ADDR_LEN      6       /* size of 802.11 address */
 107 #define ETHER_ADDR_LEN          6       /* length of an Ethernet address */
 108 static const u_char etherbroadcastaddr[ETHER_ADDR_LEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 109 //#define etherbroadcastaddr 0xff
 110
 111
 112
 113
 114 /*****************************\
 115   GENERIC CHIPSET DEFINITIONS
 116 \*****************************/
 117
 118 /* MAC Chips*/
 119 enum ath5k_version {
 120     AR5K_AR5210 = 0,
 121     AR5K_AR5211 = 1,
 122     AR5K_AR5212 = 2,
 123 };
 124
 125 /*PHY Chips*/
 126 enum ath5k_radio {
 127     AR5K_AR5110 = 0,
 128     AR5K_AR5111 = 1,
 129     AR5K_AR5112 = 2,
 130 };
 131
 132 /*
 133  * Common silicon revision/version values
 134  */
 135 enum ath5k_srev_type {
 136     AR5K_VERSION_VER,
 137     AR5K_VERSION_REV,
 138     AR5K_VERSION_RAD,
 139     AR5K_VERSION_DEV
 140 };
 141
 142 struct ath5k_srev_name {
 143     const char      *sr_name;
 144     enum ath5k_srev_type    sr_type;
 145     u_int           sr_val;
 146 };
 147
 148 #define AR5K_SREV_NAME  {                       \
 149     { "5210",   AR5K_VERSION_VER,   AR5K_SREV_VER_AR5210 }, \
 150     { "5311",   AR5K_VERSION_VER,   AR5K_SREV_VER_AR5311 }, \
 151     { "5311a",  AR5K_VERSION_VER,   AR5K_SREV_VER_AR5311A },\
 152     { "5311b",  AR5K_VERSION_VER,   AR5K_SREV_VER_AR5311B },\
 153     { "5211",   AR5K_VERSION_VER,   AR5K_SREV_VER_AR5211 }, \
 154     { "5212",   AR5K_VERSION_VER,   AR5K_SREV_VER_AR5212 }, \
 155     { "5213",   AR5K_VERSION_VER,   AR5K_SREV_VER_AR5213 }, \
 156     { "xxxx",   AR5K_VERSION_VER,   AR5K_SREV_UNKNOWN },    \
 157     { "5110",   AR5K_VERSION_RAD,   AR5K_SREV_RAD_5110 },   \
 158     { "5111",   AR5K_VERSION_RAD,   AR5K_SREV_RAD_5111 },   \
 159     { "2111",   AR5K_VERSION_RAD,   AR5K_SREV_RAD_2111 },   \
 160     { "5112",   AR5K_VERSION_RAD,   AR5K_SREV_RAD_5112 },   \
 161     { "5112a",  AR5K_VERSION_RAD,   AR5K_SREV_RAD_5112A },  \
 162     { "2112",   AR5K_VERSION_RAD,   AR5K_SREV_RAD_2112 },   \
 163     { "2112a",  AR5K_VERSION_RAD,   AR5K_SREV_RAD_2112A },  \
 164     { "xxxx",   AR5K_VERSION_RAD,   AR5K_SREV_UNKNOWN },    \
 165     { "2413",   AR5K_VERSION_DEV,   AR5K_DEVID_AR2413 },    \
 166     { "5413",   AR5K_VERSION_DEV,   AR5K_DEVID_AR5413 },    \
 167     { "5424",   AR5K_VERSION_DEV,   AR5K_DEVID_AR5424 },    \
 168     { "xxxx",   AR5K_VERSION_DEV,   AR5K_SREV_UNKNOWN } \
 169 }
 170
 171 #define AR5K_SREV_UNKNOWN   0xffff
 172
 173 #define AR5K_SREV_VER_AR5210    0x00
 174 #define AR5K_SREV_VER_AR5311    0x10
 175 #define AR5K_SREV_VER_AR5311A   0x20
 176 #define AR5K_SREV_VER_AR5311B   0x30
 177 #define AR5K_SREV_VER_AR5211    0x40
 178 #define AR5K_SREV_VER_AR5212    0x50
 179 #define AR5K_SREV_VER_AR5213    0x55
 180 #define AR5K_SREV_VER_UNSUPP    0x60
 181
 182 #define AR5K_SREV_RAD_5110  0x00
 183 #define AR5K_SREV_RAD_5111  0x10
 184 #define AR5K_SREV_RAD_5111A 0x15
 185 #define AR5K_SREV_RAD_2111  0x20
 186 #define AR5K_SREV_RAD_5112  0x30
 187 #define AR5K_SREV_RAD_5112A 0x35
 188 #define AR5K_SREV_RAD_2112  0x40
 189 #define AR5K_SREV_RAD_2112A 0x45
 190 #define AR5K_SREV_RAD_UNSUPP    0x50
 191
 192
 193
 194
 195 /****************\
 196   TX DEFINITIONS
 197 \****************/
 198
 199 /*
 200  * Tx Descriptor
 201  */
 202 struct ath_tx_status {
 203     uint16_t   ts_seqnum;
 204     uint16_t   ts_tstamp;
 205     uint8_t    ts_status;
 206     uint8_t    ts_rate;
 207     int8_t      ts_rssi;
 208     uint8_t    ts_shortretry;
 209     uint8_t    ts_longretry;
 210     uint8_t    ts_virtcol;
 211     uint8_t    ts_antenna;
 212 };
 213
 214 #define AR5K_TXSTAT_ALTRATE 0x80
 215 #define AR5K_TXERR_XRETRY   0x01
 216 #define AR5K_TXERR_FILT     0x02
 217 #define AR5K_TXERR_FIFO     0x04
 218
 219 /*
 220  * Queue types used to classify tx queues.
 221  */
 222 typedef enum {
 223     AR5K_TX_QUEUE_INACTIVE = 0, /* This queue is not used -
 224                                    see ath_hal_releasetxqueue */
 225     AR5K_TX_QUEUE_DATA,   /*A normal data queue*/
 226     AR5K_TX_QUEUE_XR_DATA,    /*An XR-data queue*/
 227     AR5K_TX_QUEUE_BEACON,     /*The beacon queue*/
 228     AR5K_TX_QUEUE_CAB,    /*The ater-beacon queue*/
 229     AR5K_TX_QUEUE_UAPSD,  /*Unscheduled Automatic Power Save Delivery queue*/
 230 } AR5K_TX_QUEUE;
 231
 232 #define AR5K_NUM_TX_QUEUES  10
 233
 234 /*
 235  * Queue syb-types to classify normal data queues.
 236  * These are the 4 Access Categories as defined in
 237  * WME spec. 0 is the lowest priority and 4 is the
 238  * highest. Normal data that hasn't been classified
 239  * goes to the Best Effort AC.
 240  */
 241 typedef enum {
 242     AR5K_WME_AC_BK = 0, /*Background traffic*/
 243     AR5K_WME_AC_BE,     /*Best-effort (normal) traffic)*/
 244     AR5K_WME_AC_VI,     /*Video traffic*/
 245     AR5K_WME_AC_VO,     /*Voice traffic*/
 246 } AR5K_TX_QUEUE_SUBTYPE;
 247
 248 /*
 249  * Queue ID numbers as returned by the HAL, each number
 250  * represents a hw queue. If hw does not support hw queues
 251  * (eg 5210/5211) all data goes in one queue. These match
 252  * d80211 definitions (net80211/MadWiFi don't use them).
 253  */
 254 typedef enum {
 255     AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/
 256     AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/
 257     AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP -
 258                                      Spectralink Voice Protocol*/
 259     AR5K_TX_QUEUE_ID_CAB      = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
 260     AR5K_TX_QUEUE_ID_BEACON   = 7, /*IEEE80211_TX_QUEUE_BEACON*/
 261     AR5K_TX_QUEUE_ID_UAPSD    = 8,
 262     AR5K_TX_QUEUE_ID_XR_DATA  = 9,
 263 } AR5K_TX_QUEUE_ID;
 264
 265
 266 /*
 267  * Flags to set hw queue's parameters...
 268  */
 269 /* Enable TXOK and TXERR interrupts -not used- */
 270 #define AR5K_TXQ_FLAG_TXINT_ENABLE      0x0001
 271 /* Enable TXDESC interrupt -not implemented- */
 272 #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE      0x0002
 273 /* Disable random post-backoff */
 274 #define AR5K_TXQ_FLAG_BACKOFF_DISABLE       0x0004
 275 /* Enable hw compression -not implemented-*/
 276 #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE    0x0008
 277 /* Enable ready time expiry policy (?)*/
 278 #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0010
 279 /* Enable backoff while bursting */
 280 #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0020
 281 /* Disable backoff while bursting */
 282 #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS     0x0040
 283 /* Enable TXEOL interrupt -not implemented-*/
 284 #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE       0x0080
 285
 286 /*
 287  * A struct to hold tx queue's parameters
 288  */
 289 typedef struct {
 290     AR5K_TX_QUEUE           tqi_type;   /* See AR5K_TX_QUEUE */
 291     AR5K_TX_QUEUE_SUBTYPE       tqi_subtype;    /* See AR5K_TX_QUEUE_SUBTYPE */
 292     uint16_t           tqi_flags;  /* Tx queue flags (see above) */
 293     uint32_t           tqi_aifs;   /* Arbitrated Interframe Space */
 294     int32_t             tqi_cw_min; /* Minimum Contention Window */
 295     int32_t             tqi_cw_max; /* Maximum Contention Window */
 296     uint32_t           tqi_cbr_period; /* Constant bit rate period */
 297     uint32_t           tqi_cbr_overflow_limit;
 298     uint32_t           tqi_burst_time;
 299     uint32_t           tqi_ready_time; /* Not used */
 300     uint32_t           tqi_comp_buffer;/* Compression Buffer's phys addr */
 301 } AR5K_TXQ_INFO;
 302
 303 /*
 304  * Transmit packet types.
 305  * These are not fully used inside OpenHAL yet
 306  */
 307 typedef enum {
 308     AR5K_PKT_TYPE_NORMAL        = 0,
 309     AR5K_PKT_TYPE_ATIM      = 1,
 310     AR5K_PKT_TYPE_PSPOLL        = 2,
 311     AR5K_PKT_TYPE_BEACON        = 3,
 312     AR5K_PKT_TYPE_PROBE_RESP    = 4,
 313     AR5K_PKT_TYPE_PIFS      = 5,
 314 } AR5K_PKT_TYPE;
 315
 316 /*
 317  * TX power and TPC settings
 318  */
 319 #define AR5K_TXPOWER_OFDM(_r, _v)   (           \
 320     ((0 & 1) << ((_v) + 6)) |               \
 321     (((hal->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v))    \
 322 )
 323
 324 #define AR5K_TXPOWER_CCK(_r, _v)    (           \
 325     (hal->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v)    \
 326 )
 327
 328 /*
 329  * Used to compute TX times
 330  */
 331 #define AR5K_CCK_SIFS_TIME      10
 332 #define AR5K_CCK_PREAMBLE_BITS      144
 333 #define AR5K_CCK_PLCP_BITS      48
 334
 335 #define AR5K_OFDM_SIFS_TIME     16
 336 #define AR5K_OFDM_PREAMBLE_TIME     20
 337 #define AR5K_OFDM_PLCP_BITS     22
 338 #define AR5K_OFDM_SYMBOL_TIME       4
 339
 340 #define AR5K_TURBO_SIFS_TIME        8
 341 #define AR5K_TURBO_PREAMBLE_TIME    14
 342 #define AR5K_TURBO_PLCP_BITS        22
 343 #define AR5K_TURBO_SYMBOL_TIME      4
 344
 345 #define AR5K_XR_SIFS_TIME       16
 346 #define AR5K_XR_PLCP_BITS       22
 347 #define AR5K_XR_SYMBOL_TIME     4
 348
 349 /* CCK */
 350 #define AR5K_CCK_NUM_BITS(_frmlen) (_frmlen << 3)
 351
 352 #define AR5K_CCK_PHY_TIME(_sp) (_sp ?                   \
 353     ((AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS) >> 1) :      \
 354     (AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS))
 355
 356 #define AR5K_CCK_TX_TIME(_kbps, _frmlen, _sp) \
 357     AR5K_CCK_PHY_TIME(_sp) +                  \
 358     ((AR5K_CCK_NUM_BITS(_frmlen) * 1000) / _kbps) +     \
 359     AR5K_CCK_SIFS_TIME
 360
 361 /* OFDM */
 362 #define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3))
 363
 364 #define AR5K_OFDM_NUM_BITS_PER_SYM(_kbps) ((_kbps *         \
 365     AR5K_OFDM_SYMBOL_TIME) / 1000)
 366
 367 #define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3))
 368
 369 #define AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen)               \
 370     howmany(AR5K_OFDM_NUM_BITS(_frmlen), AR5K_OFDM_NUM_BITS_PER_SYM(_kbps))
 371
 372 #define AR5K_OFDM_TX_TIME(_kbps, _frmlen)               \
 373     AR5K_OFDM_PREAMBLE_TIME + AR5K_OFDM_SIFS_TIME +         \
 374     (AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_OFDM_SYMBOL_TIME)
 375
 376 /* TURBO */
 377 #define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3))
 378
 379 #define AR5K_TURBO_NUM_BITS_PER_SYM(_kbps) (((_kbps << 1) *     \
 380     AR5K_TURBO_SYMBOL_TIME) / 1000)
 381
 382 #define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3))
 383
 384 #define AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen)              \
 385     howmany(AR5K_TURBO_NUM_BITS(_frmlen),               \
 386     AR5K_TURBO_NUM_BITS_PER_SYM(_kbps))
 387
 388 #define AR5K_TURBO_TX_TIME(_kbps, _frmlen)              \
 389     AR5K_TURBO_PREAMBLE_TIME + AR5K_TURBO_SIFS_TIME +       \
 390     (AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_TURBO_SYMBOL_TIME)
 391
 392 /* eXtendent Range (?)*/
 393 #define AR5K_XR_PREAMBLE_TIME(_kbps) (((_kbps) < 1000) ? 173 : 76)
 394
 395 #define AR5K_XR_NUM_BITS_PER_SYM(_kbps) ((_kbps *           \
 396     AR5K_XR_SYMBOL_TIME) / 1000)
 397
 398 #define AR5K_XR_NUM_BITS(_frmlen) (AR5K_XR_PLCP_BITS + (_frmlen << 3))
 399
 400 #define AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen)             \
 401     howmany(AR5K_XR_NUM_BITS(_frmlen), AR5K_XR_NUM_BITS_PER_SYM(_kbps))
 402
 403 #define AR5K_XR_TX_TIME(_kbps, _frmlen)             \
 404     AR5K_XR_PREAMBLE_TIME(_kbps) + AR5K_XR_SIFS_TIME +      \
 405     (AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_XR_SYMBOL_TIME)
 406
 407 /*
 408  * DMA size definitions (2^n+2)
 409  */
 410 typedef enum {
 411     AR5K_DMASIZE_4B = 0,
 412     AR5K_DMASIZE_8B,
 413     AR5K_DMASIZE_16B,
 414     AR5K_DMASIZE_32B,
 415     AR5K_DMASIZE_64B,
 416     AR5K_DMASIZE_128B,
 417     AR5K_DMASIZE_256B,
 418     AR5K_DMASIZE_512B
 419 } ath5k_dmasize_t;
 420
 421
 422
 423 /****************\
 424   RX DEFINITIONS
 425 \****************/
 426
 427 /*
 428  * Rx Descriptor
 429  */
 430 struct ath_rx_status {
 431     uint16_t   rs_datalen;
 432     uint16_t   rs_tstamp;
 433     uint8_t    rs_status;
 434     uint8_t    rs_phyerr;
 435     int8_t      rs_rssi;
 436     uint8_t    rs_keyix;
 437     uint8_t    rs_rate;
 438     uint8_t    rs_antenna;
 439     uint8_t    rs_more;
 440 };
 441
 442 #define AR5K_RXERR_CRC      0x01
 443 #define AR5K_RXERR_PHY      0x02
 444 #define AR5K_RXERR_FIFO     0x04
 445 #define AR5K_RXERR_DECRYPT  0x08
 446 #define AR5K_RXERR_MIC      0x10
 447 #define AR5K_RXKEYIX_INVALID    ((uint8_t) -1)
 448 #define AR5K_TXKEYIX_INVALID    ((uint32_t) -1)
 449
 450 /*
 451  * RX filters
 452  * Most of them are not yet used inside OpenHAL
 453  */
 454 /* Don't filter unicast frames */
 455 #define AR5K_RX_FILTER_UCAST        0x00000001
 456 /* Don't filter multicast frames */
 457 #define AR5K_RX_FILTER_MCAST        0x00000002
 458 /* Don't filter broadcast frames */
 459 #define AR5K_RX_FILTER_BCAST        0x00000004
 460 /* Don't filter control frames */
 461 #define AR5K_RX_FILTER_CONTROL      0x00000008
 462 /* Don't filter beacon frames */
 463 #define AR5K_RX_FILTER_BEACON       0x00000010
 464 /* Set promiscuous mode */
 465 #define AR5K_RX_FILTER_PROM         0x00000020
 466 /* Don't filter XR poll frame */
 467 #define AR5K_RX_FILTER_XRPOLL       0x00000040
 468 /* Don't filter probe requests */
 469 #define AR5K_RX_FILTER_PROBEREQ     0x00000080
 470 /* Don't filter phy errors */
 471 #define AR5K_RX_FILTER_PHYERROR     0x00000100
 472 /* Don't filter phy radar errors*/
 473 #define AR5K_RX_FILTER_PHYRADAR     0x00000200
 474
 475 typedef struct {
 476     uint32_t   ackrcv_bad;
 477     uint32_t   rts_bad;
 478     uint32_t   rts_good;
 479     uint32_t   fcs_bad;
 480     uint32_t   beacons;
 481 } AR5K_MIB_STATS;
 482
 483
 484
 485
 486 /**************************\
 487  BEACON TIMERS DEFINITIONS
 488 \**************************/
 489
 490 #define AR5K_BEACON_PERIOD  0x0000ffff
 491 #define AR5K_BEACON_ENA     0x00800000 /*enable beacon xmit*/
 492 #define AR5K_BEACON_RESET_TSF   0x01000000 /*force a TSF reset*/
 493
 494 /*
 495  * Per-station beacon timer state.
 496  */
 497 typedef struct {
 498     uint32_t   bs_next_beacon;
 499     uint32_t   bs_next_dtim;
 500     uint32_t   bs_interval;        /*in TU's -see net80211/ieee80211_var.h-
 501                         can also include the above flags*/
 502     uint8_t    bs_dtim_period;
 503     uint8_t    bs_cfp_period;
 504     uint16_t   bs_cfp_max_duration; /*if non-zero hw is setup to coexist with
 505                         a Point Coordination Function capable AP*/
 506     uint16_t   bs_cfp_du_remain;
 507     uint16_t   bs_tim_offset;
 508     uint16_t   bs_sleep_duration;
 509     uint16_t   bs_bmiss_threshold;
 510     uint32_t   bs_cfp_next;
 511 } AR5K_BEACON_STATE;
 512
 513
 514
 515
 516 /********************\
 517   COMMON DEFINITIONS
 518 \********************/
 519
 520 /*
 521  * Atheros descriptor
 522  */
 523 struct __attribute__((__packed__)) ath_desc {
 524     uint32_t   ds_link;
 525     uint32_t   ds_data;
 526     uint32_t   ds_ctl0;
 527     uint32_t   ds_ctl1;
 528     uint32_t   ds_hw[4];
 529
 530     union {
 531         struct ath_rx_status rx;
 532         struct ath_tx_status tx;
 533     } ds_us;
 534
 535 #define ds_rxstat ds_us.rx
 536 #define ds_txstat ds_us.tx
 537
 538 };
 539
 540 #define AR5K_RXDESC_INTREQ  0x0020
 541
 542 #define AR5K_TXDESC_CLRDMASK    0x0001
 543 #define AR5K_TXDESC_NOACK   0x0002
 544 #define AR5K_TXDESC_RTSENA  0x0004
 545 #define AR5K_TXDESC_CTSENA  0x0008
 546 #define AR5K_TXDESC_INTREQ  0x0010
 547 #define AR5K_TXDESC_VEOL    0x0020
 548
 549 /*
 550  * 802.11 operating modes...
 551  */
 552 #define AR5K_MODE_11A   0x01
 553 #define AR5K_MODE_11B   0x02
 554 #define AR5K_MODE_11G   0x04
 555 #define AR5K_MODE_TURBO 0x08
 556 #define AR5K_MODE_108G  0x16
 557 #define AR5K_MODE_XR    0x32
 558 #define AR5K_MODE_ALL   (AR5K_MODE_11A| \
 559             AR5K_MODE_11B|  \
 560             AR5K_MODE_11G|  \
 561             AR5K_MODE_TURBO|\
 562             AR5K_MODE_108G| \
 563             AR5K_MODE_XR)
 564
 565 /*
 566  * Channel definitions
 567  */
 568 typedef struct {
 569     uint16_t   freq;       /* setting in Mhz */
 570     uint16_t   channel_flags;
 571     uint8_t    private_flags;  /* not used in OpenHAL yet*/
 572 } AR5K_CHANNEL;
 573
 574 #define AR5K_SLOT_TIME_9    396
 575 #define AR5K_SLOT_TIME_20   880
 576 #define AR5K_SLOT_TIME_MAX  0xffff
 577
 578 /* channel_flags */
 579 #define CHANNEL_CW_INT  0x0008  /* Contention Window interference detected */
 580 #define CHANNEL_TURBO   0x0010  /* Turbo Channel */
 581 #define CHANNEL_CCK 0x0020  /* CCK channel */
 582 #define CHANNEL_OFDM    0x0040  /* OFDM channel */
 583 #define CHANNEL_2GHZ    0x0080  /* 2GHz channel. */
 584 #define CHANNEL_5GHZ    0x0100  /* 5GHz channel */
 585 #define CHANNEL_PASSIVE 0x0200  /* Only passive scan allowed */
 586 #define CHANNEL_DYN 0x0400  /* Dynamic CCK-OFDM channel (for g operation)*/
 587 #define CHANNEL_XR  0x0800  /* XR channel */
 588
 589 #define CHANNEL_A   (CHANNEL_5GHZ|CHANNEL_OFDM)
 590 #define CHANNEL_B   (CHANNEL_2GHZ|CHANNEL_CCK)
 591 #define CHANNEL_PUREG   (CHANNEL_2GHZ|CHANNEL_OFDM)
 592 //#ifdef notdef
 593 #define CHANNEL_G   (CHANNEL_2GHZ|CHANNEL_DYN)
 594 //#else
 595 //#define   CHANNEL_G   (CHANNEL_2GHZ|CHANNEL_OFDM)
 596 //#endif
 597 #define CHANNEL_T   (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
 598 #define CHANNEL_TG  (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
 599 #define CHANNEL_108A    CHANNEL_T
 600 #define CHANNEL_108G    CHANNEL_TG
 601 #define CHANNEL_X   (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
 602
 603 #define CHANNEL_ALL (CHANNEL_OFDM | CHANNEL_CCK | CHANNEL_2GHZ | \
 604                      CHANNEL_5GHZ | CHANNEL_TURBO)
 605
 606 #define CHANNEL_ALL_NOTURBO     (CHANNEL_ALL & ~CHANNEL_TURBO)
 607 #define CHANNEL_MODES   CHANNEL_ALL
 608
 609 /*
 610  * Used internaly in OpenHAL (ar5211.c/ar5212.c
 611  * for reset_tx_queue). Also see struct AR5K_CHANNEL.
 612  */
 613 #define IS_CHAN_XR(_c) \
 614         ((_c.channel_flags & CHANNEL_XR) != 0)
 615
 616 #define IS_CHAN_B(_c) \
 617         ((_c.channel_flags & CHANNEL_B) != 0)
 618
 619 typedef enum {
 620     AR5K_CHIP_5GHZ = CHANNEL_5GHZ,
 621     AR5K_CHIP_2GHZ = CHANNEL_2GHZ,
 622 } AR5K_CHIP;
 623
 624 /*
 625  * The following structure will be used to map 2GHz channels to
 626  * 5GHz Atheros channels.
 627  */
 628 struct ath5k_athchan_2ghz {
 629     uint32_t   a2_flags;
 630     uint16_t   a2_athchan;
 631 };
 632
 633 /*
 634  * Rate definitions
 635  */
 636
 637 #define AR5K_MAX_RATES  32 /*max number of rates on the rate table*/
 638
 639 typedef struct {
 640     uint8_t    valid;      /* Valid for rate control */
 641     uint32_t   modulation;
 642     uint16_t   rate_kbps;
 643     uint8_t    rate_code;  /* Rate mapping for h/w descriptors */
 644     uint8_t    dot11_rate;
 645     uint8_t    control_rate;
 646     uint16_t   lp_ack_duration;/* long preamble ACK duration */
 647     uint16_t   sp_ack_duration;/* short preamble ACK duration*/
 648 } AR5K_RATE;
 649
 650 typedef struct {
 651     uint16_t   rate_count;
 652     uint8_t    rate_code_to_index[AR5K_MAX_RATES]; /* Back-mapping */
 653     AR5K_RATE   rates[AR5K_MAX_RATES];
 654 } AR5K_RATE_TABLE;
 655
 656 /*
 657  * Rate tables...
 658  */
 659 #define AR5K_RATES_11A { 8, {                   \
 660     255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \
 661     7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \
 662     255, 255, 255, 255, 255, 255, 255, 255 }, {     \
 663     { 1, MODULATION_OFDM, 6000, 11, 140, 0 },       \
 664     { 1, MODULATION_OFDM, 9000, 15, 18, 0 },        \
 665     { 1, MODULATION_OFDM, 12000, 10, 152, 2 },      \
 666     { 1, MODULATION_OFDM, 18000, 14, 36, 2 },       \
 667     { 1, MODULATION_OFDM, 24000, 9, 176, 4 },       \
 668     { 1, MODULATION_OFDM, 36000, 13, 72, 4 },       \
 669     { 1, MODULATION_OFDM, 48000, 8, 96, 4 },        \
 670     { 1, MODULATION_OFDM, 54000, 12, 108, 4 } }     \
 671 }
 672
 673 #define AR5K_RATES_11B { 4, {                       \
 674     255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \
 675     255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \
 676     3, 2, 1, 0, 255, 255, 255, 255 }, {             \
 677     { 1, MODULATION_CCK, 1000, 27, 130, 0 },    \
 678     { 1, MODULATION_CCK, 2000, 26, 132, 1 },    \
 679     { 1, MODULATION_CCK, 5500, 25, 139, 1 },    \
 680     { 1, MODULATION_CCK, 11000, 24, 150, 1 } }  \
 681 }
 682
 683 #define AR5K_RATES_11G { 12, {                  \
 684     255, 255, 255, 255, 255, 255, 255, 255, 10, 8, 6, 4,    \
 685     11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255,    \
 686     3, 2, 1, 0, 255, 255, 255, 255 }, {         \
 687     { 1, MODULATION_CCK, 1000, 27, 2, 0 },      \
 688     { 1, MODULATION_CCK, 2000, 26, 4, 1 },      \
 689     { 1, MODULATION_CCK, 5500, 25, 11, 1 },     \
 690     { 1, MODULATION_CCK, 11000, 24, 22, 1 },    \
 691     { 0, MODULATION_OFDM, 6000, 11, 12, 4 },    \
 692     { 0, MODULATION_OFDM, 9000, 15, 18, 4 },    \
 693     { 1, MODULATION_OFDM, 12000, 10, 24, 6 },   \
 694     { 1, MODULATION_OFDM, 18000, 14, 36, 6 },   \
 695     { 1, MODULATION_OFDM, 24000, 9, 48, 8 },    \
 696     { 1, MODULATION_OFDM, 36000, 13, 72, 8 },   \
 697     { 1, MODULATION_OFDM, 48000, 8, 96, 8 },    \
 698     { 1, MODULATION_OFDM, 54000, 12, 108, 8 } } \
 699 }
 700
 701 #define AR5K_RATES_TURBO { 8, {                 \
 702     255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \
 703     7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \
 704     255, 255, 255, 255, 255, 255, 255, 255 }, {     \
 705     { 1, MODULATION_TURBO, 6000, 11, 140, 0 },  \
 706     { 1, MODULATION_TURBO, 9000, 15, 18, 0 },   \
 707     { 1, MODULATION_TURBO, 12000, 10, 152, 2 }, \
 708     { 1, MODULATION_TURBO, 18000, 14, 36, 2 },  \
 709     { 1, MODULATION_TURBO, 24000, 9, 176, 4 },  \
 710     { 1, MODULATION_TURBO, 36000, 13, 72, 4 },  \
 711     { 1, MODULATION_TURBO, 48000, 8, 96, 4 },   \
 712     { 1, MODULATION_TURBO, 54000, 12, 108, 4 } }    \
 713 }
 714
 715 #define AR5K_RATES_XR { 12, {                   \
 716     255, 3, 1, 255, 255, 255, 2, 0, 10, 8, 6, 4,        \
 717     11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255,    \
 718     255, 255, 255, 255, 255, 255, 255, 255 }, {     \
 719     { 1, MODULATION_XR, 500, 7, 129, 0 },       \
 720     { 1, MODULATION_XR, 1000, 2, 139, 1 },      \
 721     { 1, MODULATION_XR, 2000, 6, 150, 2 },      \
 722     { 1, MODULATION_XR, 3000, 1, 150, 3 },      \
 723     { 1, MODULATION_OFDM, 6000, 11, 140, 4 },   \
 724     { 1, MODULATION_OFDM, 9000, 15, 18, 4 },    \
 725     { 1, MODULATION_OFDM, 12000, 10, 152, 6 },  \
 726     { 1, MODULATION_OFDM, 18000, 14, 36, 6 },   \
 727     { 1, MODULATION_OFDM, 24000, 9, 176, 8 },   \
 728     { 1, MODULATION_OFDM, 36000, 13, 72, 8 },   \
 729     { 1, MODULATION_OFDM, 48000, 8, 96, 8 },    \
 730     { 1, MODULATION_OFDM, 54000, 12, 108, 8 } } \
 731 }
 732
 733 /*
 734  * Crypto definitions
 735  */
 736
 737 /* key types */
 738 typedef enum {
 739     AR5K_CIPHER_WEP     = 0,
 740     AR5K_CIPHER_AES_OCB = 1,
 741     AR5K_CIPHER_AES_CCM = 2,
 742     AR5K_CIPHER_CKIP    = 3,
 743     AR5K_CIPHER_TKIP    = 4,
 744     AR5K_CIPHER_CLR     = 5,    /* no encryption */
 745     AR5K_CIPHER_MIC     = 127   /* used for Message
 746                        Integrity Code */
 747 } AR5K_CIPHER;
 748
 749 #define AR5K_KEYVAL_LENGTH_40   5
 750 #define AR5K_KEYVAL_LENGTH_104  13
 751 #define AR5K_KEYVAL_LENGTH_128  16
 752 #define AR5K_KEYVAL_LENGTH_MAX  AR5K_KEYVAL_LENGTH_128
 753
 754 typedef struct {
 755     int     wk_len;     /* key's length */
 756     uint8_t    wk_key[AR5K_KEYVAL_LENGTH_MAX];
 757     uint8_t    wk_type;    /* see above */
 758     uint8_t    wk_mic[8];  /* TKIP MIC key */
 759 } AR5K_KEYVAL;
 760
 761
 762
 763 /***********************\
 764  HW RELATED DEFINITIONS
 765 \***********************/
 766
 767 /*
 768  * Misc definitions
 769  */
 770 #define AR5K_RSSI_EP_MULTIPLIER (1<<7)
 771
 772 #define AR5K_ASSERT_ENTRY(_e, _s) do {      \
 773     if (_e >= _s) {   \
 774         return FALSE; \
 775     }                 \
 776 } while (0)
 777
 778
 779 typedef struct {
 780     uint32_t   ns_avgbrssi;    /* average beacon rssi */
 781     uint32_t   ns_avgrssi; /* average data rssi */
 782     uint32_t   ns_avgtxrssi;   /* average tx rssi */
 783 } AR5K_NODE_STATS;
 784
 785 typedef enum {
 786     AR5K_ANT_VARIABLE   = 0,    /* variable by programming */
 787     AR5K_ANT_FIXED_A    = 1,    /* fixed to 11a frequencies */
 788     AR5K_ANT_FIXED_B    = 2,    /* fixed to 11b frequencies */
 789     AR5K_ANT_MAX        = 3,
 790 } AR5K_ANT_SETTING;
 791
 792 /*
 793  * HAL interrupt abstraction
 794  */
 795
 796 /*
 797  * These are maped to take advantage of some common bits
 798  * between the MAC chips, to be able to set intr properties
 799  * easier. Some of them are not used yet inside OpenHAL.
 800  */
 801 typedef enum {
 802     AR5K_INT_RX = 0x00000001,
 803     AR5K_INT_RXDESC = 0x00000002,
 804     AR5K_INT_RXNOFRM = 0x00000008,
 805     AR5K_INT_RXEOL  = 0x00000010,
 806     AR5K_INT_RXORN  = 0x00000020,
 807     AR5K_INT_TX = 0x00000040,
 808     AR5K_INT_TXDESC = 0x00000080,
 809     AR5K_INT_TXURN  = 0x00000800,
 810     AR5K_INT_MIB    = 0x00001000,
 811     AR5K_INT_RXPHY  = 0x00004000,
 812     AR5K_INT_RXKCM  = 0x00008000,
 813     AR5K_INT_SWBA   = 0x00010000,
 814     AR5K_INT_BMISS  = 0x00040000,
 815     AR5K_INT_BNR    = 0x00100000,
 816     AR5K_INT_GPIO   = 0x01000000,
 817     AR5K_INT_FATAL  = 0x40000000,
 818     AR5K_INT_GLOBAL = 0x80000000,
 819
 820     /*A sum of all the common bits*/
 821     AR5K_INT_COMMON  = AR5K_INT_RXNOFRM
 822     | AR5K_INT_RXDESC
 823     | AR5K_INT_RXEOL
 824     | AR5K_INT_RXORN
 825     | AR5K_INT_TXURN
 826     | AR5K_INT_TXDESC
 827     | AR5K_INT_MIB
 828     | AR5K_INT_RXPHY
 829     | AR5K_INT_RXKCM
 830     | AR5K_INT_SWBA
 831     | AR5K_INT_BMISS
 832     | AR5K_INT_GPIO,
 833     AR5K_INT_NOCARD = 0xffffffff /*Declare that the card
 834                        has been removed*/
 835 } AR5K_INT;
 836
 837 /*
 838  * Power management
 839  */
 840 typedef enum {
 841     AR5K_PM_UNDEFINED = 0,
 842     AR5K_PM_AUTO,
 843     AR5K_PM_AWAKE,
 844     AR5K_PM_FULL_SLEEP,
 845     AR5K_PM_NETWORK_SLEEP,
 846 } AR5K_POWER_MODE;
 847
 848
 849 /*
 850  * LED states
 851  */
 852 typedef int AR5K_LED_STATE;
 853
 854 /*
 855  * These match net80211 definitions (not used in
 856  * d80211).
 857  */
 858 #define AR5K_LED_INIT   0 /*IEEE80211_S_INIT*/
 859 #define AR5K_LED_SCAN   1 /*IEEE80211_S_SCAN*/
 860 #define AR5K_LED_AUTH   2 /*IEEE80211_S_AUTH*/
 861 #define AR5K_LED_ASSOC  3 /*IEEE80211_S_ASSOC*/
 862 #define AR5K_LED_RUN    4 /*IEEE80211_S_RUN*/
 863
 864 /* GPIO-controlled software LED */
 865 #define AR5K_SOFTLED_PIN    0
 866 #define AR5K_SOFTLED_ON     0
 867 #define AR5K_SOFTLED_OFF    1
 868
 869 /*
 870  * Chipset capabilities -see ath_hal_getcapability-
 871  * get_capability function is not yet fully implemented
 872  * in OpenHAL so most of these don't work yet...
 873  */
 874 typedef enum {
 875     AR5K_CAP_REG_DMN        = 0,    /* Used to get current reg. domain id */
 876     AR5K_CAP_CIPHER         = 1,    /* Can handle encryption */
 877     AR5K_CAP_TKIP_MIC       = 2,    /* Can handle TKIP MIC in hardware */
 878     AR5K_CAP_TKIP_SPLIT     = 3,    /* TKIP uses split keys */
 879     AR5K_CAP_PHYCOUNTERS    = 4,    /* PHY error counters */
 880     AR5K_CAP_DIVERSITY      = 5,    /* Supports fast diversity */
 881     AR5K_CAP_NUM_TXQUEUES   = 6,    /* Used to get max number of hw txqueues */
 882     AR5K_CAP_VEOL           = 7,    /* Supports virtual EOL */
 883     AR5K_CAP_COMPRESSION    = 8,    /* Supports compression */
 884     AR5K_CAP_BURST          = 9,    /* Supports packet bursting */
 885     AR5K_CAP_FASTFRAME      = 10,   /* Supports fast frames */
 886     AR5K_CAP_TXPOW          = 11,   /* Used to get global tx power limit */
 887     AR5K_CAP_TPC            = 12,   /* Can do per-packet tx power control
 888                                        (needed for 802.11a) */
 889     AR5K_CAP_BSSIDMASK      = 13,   /* Supports bssid mask */
 890     AR5K_CAP_MCAST_KEYSRCH  = 14,   /* Supports multicast key search */
 891     AR5K_CAP_TSF_ADJUST     = 15,   /* Supports beacon tsf adjust */
 892     AR5K_CAP_XR             = 16,   /* Supports XR mode */
 893     AR5K_CAP_WME_TKIPMIC    = 17,   /* Supports TKIP MIC when using WMM */
 894     AR5K_CAP_CHAN_HALFRATE  = 18,   /* Supports half rate channels */
 895     AR5K_CAP_CHAN_QUARTERRATE = 19,   /* Supports quarter rate channels */
 896     AR5K_CAP_RFSILENT       = 20,   /* Supports RFsilent */
 897 } AR5K_CAPABILITY_TYPE;
 898
 899 #endif /* _AR5K_H */