?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
target-*: dfilter support for in_asm
[qemu/ar7.git] / target-ppc / translate.c
blob123e42fe6b6f5fb758f2a77e7b4cb1b9a4908cc1
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
43
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46 #else
47 # define LOG_DISAS(...) do { } while (0)
48 #endif
49 /*****************************************************************************/
50 /* Code translation helpers */
51
52 /* global register indexes */
53 static TCGv_env cpu_env;
54 static char cpu_reg_names[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
59 + 8*5 /* CRF */];
60 static TCGv cpu_gpr[32];
61 static TCGv cpu_gprh[32];
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i64 cpu_vsr[32];
65 static TCGv_i32 cpu_crf[8];
66 static TCGv cpu_nip;
67 static TCGv cpu_msr;
68 static TCGv cpu_ctr;
69 static TCGv cpu_lr;
70 #if defined(TARGET_PPC64)
71 static TCGv cpu_cfar;
72 #endif
73 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
74 static TCGv cpu_reserve;
75 static TCGv cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "exec/gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 size_t cpu_reg_names_size;
85 static int done_init = 0;
86
87 if (done_init)
88 return;
89
90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
91
92 p = cpu_reg_names;
93 cpu_reg_names_size = sizeof(cpu_reg_names);
94
95 for (i = 0; i < 8; i++) {
96 snprintf(p, cpu_reg_names_size, "crf%d", i);
97 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
98 offsetof(CPUPPCState, crf[i]), p);
99 p += 5;
100 cpu_reg_names_size -= 5;
101 }
102
103 for (i = 0; i < 32; i++) {
104 snprintf(p, cpu_reg_names_size, "r%d", i);
105 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
106 offsetof(CPUPPCState, gpr[i]), p);
107 p += (i < 10) ? 3 : 4;
108 cpu_reg_names_size -= (i < 10) ? 3 : 4;
109 snprintf(p, cpu_reg_names_size, "r%dH", i);
110 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
111 offsetof(CPUPPCState, gprh[i]), p);
112 p += (i < 10) ? 4 : 5;
113 cpu_reg_names_size -= (i < 10) ? 4 : 5;
114
115 snprintf(p, cpu_reg_names_size, "fp%d", i);
116 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
117 offsetof(CPUPPCState, fpr[i]), p);
118 p += (i < 10) ? 4 : 5;
119 cpu_reg_names_size -= (i < 10) ? 4 : 5;
120
121 snprintf(p, cpu_reg_names_size, "avr%dH", i);
122 #ifdef HOST_WORDS_BIGENDIAN
123 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
124 offsetof(CPUPPCState, avr[i].u64[0]), p);
125 #else
126 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
127 offsetof(CPUPPCState, avr[i].u64[1]), p);
128 #endif
129 p += (i < 10) ? 6 : 7;
130 cpu_reg_names_size -= (i < 10) ? 6 : 7;
131
132 snprintf(p, cpu_reg_names_size, "avr%dL", i);
133 #ifdef HOST_WORDS_BIGENDIAN
134 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
135 offsetof(CPUPPCState, avr[i].u64[1]), p);
136 #else
137 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
138 offsetof(CPUPPCState, avr[i].u64[0]), p);
139 #endif
140 p += (i < 10) ? 6 : 7;
141 cpu_reg_names_size -= (i < 10) ? 6 : 7;
142 snprintf(p, cpu_reg_names_size, "vsr%d", i);
143 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
144 offsetof(CPUPPCState, vsr[i]), p);
145 p += (i < 10) ? 5 : 6;
146 cpu_reg_names_size -= (i < 10) ? 5 : 6;
147 }
148
149 cpu_nip = tcg_global_mem_new(cpu_env,
150 offsetof(CPUPPCState, nip), "nip");
151
152 cpu_msr = tcg_global_mem_new(cpu_env,
153 offsetof(CPUPPCState, msr), "msr");
154
155 cpu_ctr = tcg_global_mem_new(cpu_env,
156 offsetof(CPUPPCState, ctr), "ctr");
157
158 cpu_lr = tcg_global_mem_new(cpu_env,
159 offsetof(CPUPPCState, lr), "lr");
160
161 #if defined(TARGET_PPC64)
162 cpu_cfar = tcg_global_mem_new(cpu_env,
163 offsetof(CPUPPCState, cfar), "cfar");
164 #endif
165
166 cpu_xer = tcg_global_mem_new(cpu_env,
167 offsetof(CPUPPCState, xer), "xer");
168 cpu_so = tcg_global_mem_new(cpu_env,
169 offsetof(CPUPPCState, so), "SO");
170 cpu_ov = tcg_global_mem_new(cpu_env,
171 offsetof(CPUPPCState, ov), "OV");
172 cpu_ca = tcg_global_mem_new(cpu_env,
173 offsetof(CPUPPCState, ca), "CA");
174
175 cpu_reserve = tcg_global_mem_new(cpu_env,
176 offsetof(CPUPPCState, reserve_addr),
177 "reserve_addr");
178
179 cpu_fpscr = tcg_global_mem_new(cpu_env,
180 offsetof(CPUPPCState, fpscr), "fpscr");
181
182 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
183 offsetof(CPUPPCState, access_type), "access_type");
184
185 done_init = 1;
186 }
187
188 /* internal defines */
189 struct DisasContext {
190 struct TranslationBlock *tb;
191 target_ulong nip;
192 uint32_t opcode;
193 uint32_t exception;
194 /* Routine used to access memory */
195 bool pr, hv;
196 int mem_idx;
197 int access_type;
198 /* Translation flags */
199 int le_mode;
200 TCGMemOp default_tcg_memop_mask;
201 #if defined(TARGET_PPC64)
202 int sf_mode;
203 int has_cfar;
204 #endif
205 int fpu_enabled;
206 int altivec_enabled;
207 int vsx_enabled;
208 int spe_enabled;
209 int tm_enabled;
210 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
211 int singlestep_enabled;
212 uint64_t insns_flags;
213 uint64_t insns_flags2;
214 };
215
216 /* Return true iff byteswap is needed in a scalar memop */
217 static inline bool need_byteswap(const DisasContext *ctx)
218 {
219 #if defined(TARGET_WORDS_BIGENDIAN)
220 return ctx->le_mode;
221 #else
222 return !ctx->le_mode;
223 #endif
224 }
225
226 /* True when active word size < size of target_long. */
227 #ifdef TARGET_PPC64
228 # define NARROW_MODE(C) (!(C)->sf_mode)
229 #else
230 # define NARROW_MODE(C) 0
231 #endif
232
233 struct opc_handler_t {
234 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
235 uint32_t inval1;
236 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
237 uint32_t inval2;
238 /* instruction type */
239 uint64_t type;
240 /* extended instruction type */
241 uint64_t type2;
242 /* handler */
243 void (*handler)(DisasContext *ctx);
244 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
245 const char *oname;
246 #endif
247 #if defined(DO_PPC_STATISTICS)
248 uint64_t count;
249 #endif
250 };
251
252 static inline void gen_reset_fpstatus(void)
253 {
254 gen_helper_reset_fpstatus(cpu_env);
255 }
256
257 static inline void gen_compute_fprf(TCGv_i64 arg)
258 {
259 gen_helper_compute_fprf(cpu_env, arg);
260 gen_helper_float_check_status(cpu_env);
261 }
262
263 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
264 {
265 if (ctx->access_type != access_type) {
266 tcg_gen_movi_i32(cpu_access_type, access_type);
267 ctx->access_type = access_type;
268 }
269 }
270
271 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
272 {
273 if (NARROW_MODE(ctx)) {
274 nip = (uint32_t)nip;
275 }
276 tcg_gen_movi_tl(cpu_nip, nip);
277 }
278
279 void gen_update_current_nip(void *opaque)
280 {
281 DisasContext *ctx = opaque;
282
283 tcg_gen_movi_tl(cpu_nip, ctx->nip);
284 }
285
286 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
287 {
288 TCGv_i32 t0, t1;
289 if (ctx->exception == POWERPC_EXCP_NONE) {
290 gen_update_nip(ctx, ctx->nip);
291 }
292 t0 = tcg_const_i32(excp);
293 t1 = tcg_const_i32(error);
294 gen_helper_raise_exception_err(cpu_env, t0, t1);
295 tcg_temp_free_i32(t0);
296 tcg_temp_free_i32(t1);
297 ctx->exception = (excp);
298 }
299
300 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
301 {
302 TCGv_i32 t0;
303 if (ctx->exception == POWERPC_EXCP_NONE) {
304 gen_update_nip(ctx, ctx->nip);
305 }
306 t0 = tcg_const_i32(excp);
307 gen_helper_raise_exception(cpu_env, t0);
308 tcg_temp_free_i32(t0);
309 ctx->exception = (excp);
310 }
311
312 static inline void gen_debug_exception(DisasContext *ctx)
313 {
314 TCGv_i32 t0;
315
316 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
317 (ctx->exception != POWERPC_EXCP_SYNC)) {
318 gen_update_nip(ctx, ctx->nip);
319 }
320 t0 = tcg_const_i32(EXCP_DEBUG);
321 gen_helper_raise_exception(cpu_env, t0);
322 tcg_temp_free_i32(t0);
323 }
324
325 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
326 {
327 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
328 }
329
330 /* Stop translation */
331 static inline void gen_stop_exception(DisasContext *ctx)
332 {
333 gen_update_nip(ctx, ctx->nip);
334 ctx->exception = POWERPC_EXCP_STOP;
335 }
336
337 #ifndef CONFIG_USER_ONLY
338 /* No need to update nip here, as execution flow will change */
339 static inline void gen_sync_exception(DisasContext *ctx)
340 {
341 ctx->exception = POWERPC_EXCP_SYNC;
342 }
343 #endif
344
345 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
346 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
347
348 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
349 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
350
351 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
352 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
353
354 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
355 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
356
357 typedef struct opcode_t {
358 unsigned char opc1, opc2, opc3;
359 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
360 unsigned char pad[5];
361 #else
362 unsigned char pad[1];
363 #endif
364 opc_handler_t handler;
365 const char *oname;
366 } opcode_t;
367
368 /*****************************************************************************/
369 /*** Instruction decoding ***/
370 #define EXTRACT_HELPER(name, shift, nb) \
371 static inline uint32_t name(uint32_t opcode) \
372 { \
373 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
374 }
375
376 #define EXTRACT_SHELPER(name, shift, nb) \
377 static inline int32_t name(uint32_t opcode) \
378 { \
379 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
380 }
381
382 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
383 static inline uint32_t name(uint32_t opcode) \
384 { \
385 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
386 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
387 }
388 /* Opcode part 1 */
389 EXTRACT_HELPER(opc1, 26, 6);
390 /* Opcode part 2 */
391 EXTRACT_HELPER(opc2, 1, 5);
392 /* Opcode part 3 */
393 EXTRACT_HELPER(opc3, 6, 5);
394 /* Update Cr0 flags */
395 EXTRACT_HELPER(Rc, 0, 1);
396 /* Update Cr6 flags (Altivec) */
397 EXTRACT_HELPER(Rc21, 10, 1);
398 /* Destination */
399 EXTRACT_HELPER(rD, 21, 5);
400 /* Source */
401 EXTRACT_HELPER(rS, 21, 5);
402 /* First operand */
403 EXTRACT_HELPER(rA, 16, 5);
404 /* Second operand */
405 EXTRACT_HELPER(rB, 11, 5);
406 /* Third operand */
407 EXTRACT_HELPER(rC, 6, 5);
408 /*** Get CRn ***/
409 EXTRACT_HELPER(crfD, 23, 3);
410 EXTRACT_HELPER(crfS, 18, 3);
411 EXTRACT_HELPER(crbD, 21, 5);
412 EXTRACT_HELPER(crbA, 16, 5);
413 EXTRACT_HELPER(crbB, 11, 5);
414 /* SPR / TBL */
415 EXTRACT_HELPER(_SPR, 11, 10);
416 static inline uint32_t SPR(uint32_t opcode)
417 {
418 uint32_t sprn = _SPR(opcode);
419
420 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
421 }
422 /*** Get constants ***/
423 /* 16 bits signed immediate value */
424 EXTRACT_SHELPER(SIMM, 0, 16);
425 /* 16 bits unsigned immediate value */
426 EXTRACT_HELPER(UIMM, 0, 16);
427 /* 5 bits signed immediate value */
428 EXTRACT_HELPER(SIMM5, 16, 5);
429 /* 5 bits signed immediate value */
430 EXTRACT_HELPER(UIMM5, 16, 5);
431 /* Bit count */
432 EXTRACT_HELPER(NB, 11, 5);
433 /* Shift count */
434 EXTRACT_HELPER(SH, 11, 5);
435 /* Vector shift count */
436 EXTRACT_HELPER(VSH, 6, 4);
437 /* Mask start */
438 EXTRACT_HELPER(MB, 6, 5);
439 /* Mask end */
440 EXTRACT_HELPER(ME, 1, 5);
441 /* Trap operand */
442 EXTRACT_HELPER(TO, 21, 5);
443
444 EXTRACT_HELPER(CRM, 12, 8);
445
446 #ifndef CONFIG_USER_ONLY
447 EXTRACT_HELPER(SR, 16, 4);
448 #endif
449
450 /* mtfsf/mtfsfi */
451 EXTRACT_HELPER(FPBF, 23, 3);
452 EXTRACT_HELPER(FPIMM, 12, 4);
453 EXTRACT_HELPER(FPL, 25, 1);
454 EXTRACT_HELPER(FPFLM, 17, 8);
455 EXTRACT_HELPER(FPW, 16, 1);
456
457 /*** Jump target decoding ***/
458 /* Immediate address */
459 static inline target_ulong LI(uint32_t opcode)
460 {
461 return (opcode >> 0) & 0x03FFFFFC;
462 }
463
464 static inline uint32_t BD(uint32_t opcode)
465 {
466 return (opcode >> 0) & 0xFFFC;
467 }
468
469 EXTRACT_HELPER(BO, 21, 5);
470 EXTRACT_HELPER(BI, 16, 5);
471 /* Absolute/relative address */
472 EXTRACT_HELPER(AA, 1, 1);
473 /* Link */
474 EXTRACT_HELPER(LK, 0, 1);
475
476 /* DFP Z22-form */
477 EXTRACT_HELPER(DCM, 10, 6)
478
479 /* DFP Z23-form */
480 EXTRACT_HELPER(RMC, 9, 2)
481
482 /* Create a mask between <start> and <end> bits */
483 static inline target_ulong MASK(uint32_t start, uint32_t end)
484 {
485 target_ulong ret;
486
487 #if defined(TARGET_PPC64)
488 if (likely(start == 0)) {
489 ret = UINT64_MAX << (63 - end);
490 } else if (likely(end == 63)) {
491 ret = UINT64_MAX >> start;
492 }
493 #else
494 if (likely(start == 0)) {
495 ret = UINT32_MAX << (31 - end);
496 } else if (likely(end == 31)) {
497 ret = UINT32_MAX >> start;
498 }
499 #endif
500 else {
501 ret = (((target_ulong)(-1ULL)) >> (start)) ^
502 (((target_ulong)(-1ULL) >> (end)) >> 1);
503 if (unlikely(start > end))
504 return ~ret;
505 }
506
507 return ret;
508 }
509
510 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
511 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
512 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
513 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
514 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
515 EXTRACT_HELPER(DM, 8, 2);
516 EXTRACT_HELPER(UIM, 16, 2);
517 EXTRACT_HELPER(SHW, 8, 2);
518 EXTRACT_HELPER(SP, 19, 2);
519 /*****************************************************************************/
520 /* PowerPC instructions table */
521
522 #if defined(DO_PPC_STATISTICS)
523 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
524 { \
525 .opc1 = op1, \
526 .opc2 = op2, \
527 .opc3 = op3, \
528 .pad = { 0, }, \
529 .handler = { \
530 .inval1 = invl, \
531 .type = _typ, \
532 .type2 = _typ2, \
533 .handler = &gen_##name, \
534 .oname = stringify(name), \
535 }, \
536 .oname = stringify(name), \
537 }
538 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
539 { \
540 .opc1 = op1, \
541 .opc2 = op2, \
542 .opc3 = op3, \
543 .pad = { 0, }, \
544 .handler = { \
545 .inval1 = invl1, \
546 .inval2 = invl2, \
547 .type = _typ, \
548 .type2 = _typ2, \
549 .handler = &gen_##name, \
550 .oname = stringify(name), \
551 }, \
552 .oname = stringify(name), \
553 }
554 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
555 { \
556 .opc1 = op1, \
557 .opc2 = op2, \
558 .opc3 = op3, \
559 .pad = { 0, }, \
560 .handler = { \
561 .inval1 = invl, \
562 .type = _typ, \
563 .type2 = _typ2, \
564 .handler = &gen_##name, \
565 .oname = onam, \
566 }, \
567 .oname = onam, \
568 }
569 #else
570 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
571 { \
572 .opc1 = op1, \
573 .opc2 = op2, \
574 .opc3 = op3, \
575 .pad = { 0, }, \
576 .handler = { \
577 .inval1 = invl, \
578 .type = _typ, \
579 .type2 = _typ2, \
580 .handler = &gen_##name, \
581 }, \
582 .oname = stringify(name), \
583 }
584 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
585 { \
586 .opc1 = op1, \
587 .opc2 = op2, \
588 .opc3 = op3, \
589 .pad = { 0, }, \
590 .handler = { \
591 .inval1 = invl1, \
592 .inval2 = invl2, \
593 .type = _typ, \
594 .type2 = _typ2, \
595 .handler = &gen_##name, \
596 }, \
597 .oname = stringify(name), \
598 }
599 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
600 { \
601 .opc1 = op1, \
602 .opc2 = op2, \
603 .opc3 = op3, \
604 .pad = { 0, }, \
605 .handler = { \
606 .inval1 = invl, \
607 .type = _typ, \
608 .type2 = _typ2, \
609 .handler = &gen_##name, \
610 }, \
611 .oname = onam, \
612 }
613 #endif
614
615 /* SPR load/store helpers */
616 static inline void gen_load_spr(TCGv t, int reg)
617 {
618 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
619 }
620
621 static inline void gen_store_spr(int reg, TCGv t)
622 {
623 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
624 }
625
626 /* Invalid instruction */
627 static void gen_invalid(DisasContext *ctx)
628 {
629 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
630 }
631
632 static opc_handler_t invalid_handler = {
633 .inval1 = 0xFFFFFFFF,
634 .inval2 = 0xFFFFFFFF,
635 .type = PPC_NONE,
636 .type2 = PPC_NONE,
637 .handler = gen_invalid,
638 };
639
640 /*** Integer comparison ***/
641
642 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
643 {
644 TCGv t0 = tcg_temp_new();
645 TCGv_i32 t1 = tcg_temp_new_i32();
646
647 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
648
649 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
650 tcg_gen_trunc_tl_i32(t1, t0);
651 tcg_gen_shli_i32(t1, t1, CRF_LT);
652 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
653
654 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
655 tcg_gen_trunc_tl_i32(t1, t0);
656 tcg_gen_shli_i32(t1, t1, CRF_GT);
657 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
658
659 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
660 tcg_gen_trunc_tl_i32(t1, t0);
661 tcg_gen_shli_i32(t1, t1, CRF_EQ);
662 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
663
664 tcg_temp_free(t0);
665 tcg_temp_free_i32(t1);
666 }
667
668 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
669 {
670 TCGv t0 = tcg_const_tl(arg1);
671 gen_op_cmp(arg0, t0, s, crf);
672 tcg_temp_free(t0);
673 }
674
675 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
676 {
677 TCGv t0, t1;
678 t0 = tcg_temp_new();
679 t1 = tcg_temp_new();
680 if (s) {
681 tcg_gen_ext32s_tl(t0, arg0);
682 tcg_gen_ext32s_tl(t1, arg1);
683 } else {
684 tcg_gen_ext32u_tl(t0, arg0);
685 tcg_gen_ext32u_tl(t1, arg1);
686 }
687 gen_op_cmp(t0, t1, s, crf);
688 tcg_temp_free(t1);
689 tcg_temp_free(t0);
690 }
691
692 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
693 {
694 TCGv t0 = tcg_const_tl(arg1);
695 gen_op_cmp32(arg0, t0, s, crf);
696 tcg_temp_free(t0);
697 }
698
699 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
700 {
701 if (NARROW_MODE(ctx)) {
702 gen_op_cmpi32(reg, 0, 1, 0);
703 } else {
704 gen_op_cmpi(reg, 0, 1, 0);
705 }
706 }
707
708 /* cmp */
709 static void gen_cmp(DisasContext *ctx)
710 {
711 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
712 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
713 1, crfD(ctx->opcode));
714 } else {
715 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
716 1, crfD(ctx->opcode));
717 }
718 }
719
720 /* cmpi */
721 static void gen_cmpi(DisasContext *ctx)
722 {
723 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
724 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
725 1, crfD(ctx->opcode));
726 } else {
727 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
728 1, crfD(ctx->opcode));
729 }
730 }
731
732 /* cmpl */
733 static void gen_cmpl(DisasContext *ctx)
734 {
735 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
736 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
737 0, crfD(ctx->opcode));
738 } else {
739 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
740 0, crfD(ctx->opcode));
741 }
742 }
743
744 /* cmpli */
745 static void gen_cmpli(DisasContext *ctx)
746 {
747 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
748 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
749 0, crfD(ctx->opcode));
750 } else {
751 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
752 0, crfD(ctx->opcode));
753 }
754 }
755
756 /* isel (PowerPC 2.03 specification) */
757 static void gen_isel(DisasContext *ctx)
758 {
759 uint32_t bi = rC(ctx->opcode);
760 uint32_t mask = 0x08 >> (bi & 0x03);
761 TCGv t0 = tcg_temp_new();
762 TCGv zr;
763
764 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
765 tcg_gen_andi_tl(t0, t0, mask);
766
767 zr = tcg_const_tl(0);
768 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
769 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
770 cpu_gpr[rB(ctx->opcode)]);
771 tcg_temp_free(zr);
772 tcg_temp_free(t0);
773 }
774
775 /* cmpb: PowerPC 2.05 specification */
776 static void gen_cmpb(DisasContext *ctx)
777 {
778 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
779 cpu_gpr[rB(ctx->opcode)]);
780 }
781
782 /*** Integer arithmetic ***/
783
784 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
785 TCGv arg1, TCGv arg2, int sub)
786 {
787 TCGv t0 = tcg_temp_new();
788
789 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
790 tcg_gen_xor_tl(t0, arg1, arg2);
791 if (sub) {
792 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
793 } else {
794 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
795 }
796 tcg_temp_free(t0);
797 if (NARROW_MODE(ctx)) {
798 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
799 }
800 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
801 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
802 }
803
804 /* Common add function */
805 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
806 TCGv arg2, bool add_ca, bool compute_ca,
807 bool compute_ov, bool compute_rc0)
808 {
809 TCGv t0 = ret;
810
811 if (compute_ca || compute_ov) {
812 t0 = tcg_temp_new();
813 }
814
815 if (compute_ca) {
816 if (NARROW_MODE(ctx)) {
817 /* Caution: a non-obvious corner case of the spec is that we
818 must produce the *entire* 64-bit addition, but produce the
819 carry into bit 32. */
820 TCGv t1 = tcg_temp_new();
821 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
822 tcg_gen_add_tl(t0, arg1, arg2);
823 if (add_ca) {
824 tcg_gen_add_tl(t0, t0, cpu_ca);
825 }
826 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
827 tcg_temp_free(t1);
828 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
829 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
830 } else {
831 TCGv zero = tcg_const_tl(0);
832 if (add_ca) {
833 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
834 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
835 } else {
836 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
837 }
838 tcg_temp_free(zero);
839 }
840 } else {
841 tcg_gen_add_tl(t0, arg1, arg2);
842 if (add_ca) {
843 tcg_gen_add_tl(t0, t0, cpu_ca);
844 }
845 }
846
847 if (compute_ov) {
848 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
849 }
850 if (unlikely(compute_rc0)) {
851 gen_set_Rc0(ctx, t0);
852 }
853
854 if (!TCGV_EQUAL(t0, ret)) {
855 tcg_gen_mov_tl(ret, t0);
856 tcg_temp_free(t0);
857 }
858 }
859 /* Add functions with two operands */
860 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
861 static void glue(gen_, name)(DisasContext *ctx) \
862 { \
863 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
864 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
865 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
866 }
867 /* Add functions with one operand and one immediate */
868 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
869 add_ca, compute_ca, compute_ov) \
870 static void glue(gen_, name)(DisasContext *ctx) \
871 { \
872 TCGv t0 = tcg_const_tl(const_val); \
873 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
874 cpu_gpr[rA(ctx->opcode)], t0, \
875 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
876 tcg_temp_free(t0); \
877 }
878
879 /* add add. addo addo. */
880 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
881 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
882 /* addc addc. addco addco. */
883 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
884 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
885 /* adde adde. addeo addeo. */
886 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
887 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
888 /* addme addme. addmeo addmeo. */
889 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
890 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
891 /* addze addze. addzeo addzeo.*/
892 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
893 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
894 /* addi */
895 static void gen_addi(DisasContext *ctx)
896 {
897 target_long simm = SIMM(ctx->opcode);
898
899 if (rA(ctx->opcode) == 0) {
900 /* li case */
901 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
902 } else {
903 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
904 cpu_gpr[rA(ctx->opcode)], simm);
905 }
906 }
907 /* addic addic.*/
908 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
909 {
910 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
911 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
912 c, 0, 1, 0, compute_rc0);
913 tcg_temp_free(c);
914 }
915
916 static void gen_addic(DisasContext *ctx)
917 {
918 gen_op_addic(ctx, 0);
919 }
920
921 static void gen_addic_(DisasContext *ctx)
922 {
923 gen_op_addic(ctx, 1);
924 }
925
926 /* addis */
927 static void gen_addis(DisasContext *ctx)
928 {
929 target_long simm = SIMM(ctx->opcode);
930
931 if (rA(ctx->opcode) == 0) {
932 /* lis case */
933 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
934 } else {
935 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
936 cpu_gpr[rA(ctx->opcode)], simm << 16);
937 }
938 }
939
940 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
941 TCGv arg2, int sign, int compute_ov)
942 {
943 TCGLabel *l1 = gen_new_label();
944 TCGLabel *l2 = gen_new_label();
945 TCGv_i32 t0 = tcg_temp_local_new_i32();
946 TCGv_i32 t1 = tcg_temp_local_new_i32();
947
948 tcg_gen_trunc_tl_i32(t0, arg1);
949 tcg_gen_trunc_tl_i32(t1, arg2);
950 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
951 if (sign) {
952 TCGLabel *l3 = gen_new_label();
953 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
954 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
955 gen_set_label(l3);
956 tcg_gen_div_i32(t0, t0, t1);
957 } else {
958 tcg_gen_divu_i32(t0, t0, t1);
959 }
960 if (compute_ov) {
961 tcg_gen_movi_tl(cpu_ov, 0);
962 }
963 tcg_gen_br(l2);
964 gen_set_label(l1);
965 if (sign) {
966 tcg_gen_sari_i32(t0, t0, 31);
967 } else {
968 tcg_gen_movi_i32(t0, 0);
969 }
970 if (compute_ov) {
971 tcg_gen_movi_tl(cpu_ov, 1);
972 tcg_gen_movi_tl(cpu_so, 1);
973 }
974 gen_set_label(l2);
975 tcg_gen_extu_i32_tl(ret, t0);
976 tcg_temp_free_i32(t0);
977 tcg_temp_free_i32(t1);
978 if (unlikely(Rc(ctx->opcode) != 0))
979 gen_set_Rc0(ctx, ret);
980 }
981 /* Div functions */
982 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
983 static void glue(gen_, name)(DisasContext *ctx) \
984 { \
985 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
986 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
987 sign, compute_ov); \
988 }
989 /* divwu divwu. divwuo divwuo. */
990 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
991 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
992 /* divw divw. divwo divwo. */
993 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
994 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
995
996 /* div[wd]eu[o][.] */
997 #define GEN_DIVE(name, hlpr, compute_ov) \
998 static void gen_##name(DisasContext *ctx) \
999 { \
1000 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1001 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1002 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1003 tcg_temp_free_i32(t0); \
1004 if (unlikely(Rc(ctx->opcode) != 0)) { \
1005 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1006 } \
1007 }
1008
1009 GEN_DIVE(divweu, divweu, 0);
1010 GEN_DIVE(divweuo, divweu, 1);
1011 GEN_DIVE(divwe, divwe, 0);
1012 GEN_DIVE(divweo, divwe, 1);
1013
1014 #if defined(TARGET_PPC64)
1015 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1016 TCGv arg2, int sign, int compute_ov)
1017 {
1018 TCGLabel *l1 = gen_new_label();
1019 TCGLabel *l2 = gen_new_label();
1020
1021 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1022 if (sign) {
1023 TCGLabel *l3 = gen_new_label();
1024 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1025 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1026 gen_set_label(l3);
1027 tcg_gen_div_i64(ret, arg1, arg2);
1028 } else {
1029 tcg_gen_divu_i64(ret, arg1, arg2);
1030 }
1031 if (compute_ov) {
1032 tcg_gen_movi_tl(cpu_ov, 0);
1033 }
1034 tcg_gen_br(l2);
1035 gen_set_label(l1);
1036 if (sign) {
1037 tcg_gen_sari_i64(ret, arg1, 63);
1038 } else {
1039 tcg_gen_movi_i64(ret, 0);
1040 }
1041 if (compute_ov) {
1042 tcg_gen_movi_tl(cpu_ov, 1);
1043 tcg_gen_movi_tl(cpu_so, 1);
1044 }
1045 gen_set_label(l2);
1046 if (unlikely(Rc(ctx->opcode) != 0))
1047 gen_set_Rc0(ctx, ret);
1048 }
1049 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1050 static void glue(gen_, name)(DisasContext *ctx) \
1051 { \
1052 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1053 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1054 sign, compute_ov); \
1055 }
1056 /* divwu divwu. divwuo divwuo. */
1057 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1058 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1059 /* divw divw. divwo divwo. */
1060 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1061 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1062
1063 GEN_DIVE(divdeu, divdeu, 0);
1064 GEN_DIVE(divdeuo, divdeu, 1);
1065 GEN_DIVE(divde, divde, 0);
1066 GEN_DIVE(divdeo, divde, 1);
1067 #endif
1068
1069 /* mulhw mulhw. */
1070 static void gen_mulhw(DisasContext *ctx)
1071 {
1072 TCGv_i32 t0 = tcg_temp_new_i32();
1073 TCGv_i32 t1 = tcg_temp_new_i32();
1074
1075 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1076 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1077 tcg_gen_muls2_i32(t0, t1, t0, t1);
1078 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1079 tcg_temp_free_i32(t0);
1080 tcg_temp_free_i32(t1);
1081 if (unlikely(Rc(ctx->opcode) != 0))
1082 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1083 }
1084
1085 /* mulhwu mulhwu. */
1086 static void gen_mulhwu(DisasContext *ctx)
1087 {
1088 TCGv_i32 t0 = tcg_temp_new_i32();
1089 TCGv_i32 t1 = tcg_temp_new_i32();
1090
1091 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1092 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1093 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1094 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1095 tcg_temp_free_i32(t0);
1096 tcg_temp_free_i32(t1);
1097 if (unlikely(Rc(ctx->opcode) != 0))
1098 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1099 }
1100
1101 /* mullw mullw. */
1102 static void gen_mullw(DisasContext *ctx)
1103 {
1104 #if defined(TARGET_PPC64)
1105 TCGv_i64 t0, t1;
1106 t0 = tcg_temp_new_i64();
1107 t1 = tcg_temp_new_i64();
1108 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1109 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1110 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1111 tcg_temp_free(t0);
1112 tcg_temp_free(t1);
1113 #else
1114 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1115 cpu_gpr[rB(ctx->opcode)]);
1116 #endif
1117 if (unlikely(Rc(ctx->opcode) != 0))
1118 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1119 }
1120
1121 /* mullwo mullwo. */
1122 static void gen_mullwo(DisasContext *ctx)
1123 {
1124 TCGv_i32 t0 = tcg_temp_new_i32();
1125 TCGv_i32 t1 = tcg_temp_new_i32();
1126
1127 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1128 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1129 tcg_gen_muls2_i32(t0, t1, t0, t1);
1130 #if defined(TARGET_PPC64)
1131 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1132 #else
1133 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1134 #endif
1135
1136 tcg_gen_sari_i32(t0, t0, 31);
1137 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1138 tcg_gen_extu_i32_tl(cpu_ov, t0);
1139 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1140
1141 tcg_temp_free_i32(t0);
1142 tcg_temp_free_i32(t1);
1143 if (unlikely(Rc(ctx->opcode) != 0))
1144 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1145 }
1146
1147 /* mulli */
1148 static void gen_mulli(DisasContext *ctx)
1149 {
1150 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1151 SIMM(ctx->opcode));
1152 }
1153
1154 #if defined(TARGET_PPC64)
1155 /* mulhd mulhd. */
1156 static void gen_mulhd(DisasContext *ctx)
1157 {
1158 TCGv lo = tcg_temp_new();
1159 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1160 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1161 tcg_temp_free(lo);
1162 if (unlikely(Rc(ctx->opcode) != 0)) {
1163 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1164 }
1165 }
1166
1167 /* mulhdu mulhdu. */
1168 static void gen_mulhdu(DisasContext *ctx)
1169 {
1170 TCGv lo = tcg_temp_new();
1171 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1172 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1173 tcg_temp_free(lo);
1174 if (unlikely(Rc(ctx->opcode) != 0)) {
1175 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1176 }
1177 }
1178
1179 /* mulld mulld. */
1180 static void gen_mulld(DisasContext *ctx)
1181 {
1182 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1183 cpu_gpr[rB(ctx->opcode)]);
1184 if (unlikely(Rc(ctx->opcode) != 0))
1185 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1186 }
1187
1188 /* mulldo mulldo. */
1189 static void gen_mulldo(DisasContext *ctx)
1190 {
1191 TCGv_i64 t0 = tcg_temp_new_i64();
1192 TCGv_i64 t1 = tcg_temp_new_i64();
1193
1194 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1195 cpu_gpr[rB(ctx->opcode)]);
1196 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1197
1198 tcg_gen_sari_i64(t0, t0, 63);
1199 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1200 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1201
1202 tcg_temp_free_i64(t0);
1203 tcg_temp_free_i64(t1);
1204
1205 if (unlikely(Rc(ctx->opcode) != 0)) {
1206 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1207 }
1208 }
1209 #endif
1210
1211 /* Common subf function */
1212 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1213 TCGv arg2, bool add_ca, bool compute_ca,
1214 bool compute_ov, bool compute_rc0)
1215 {
1216 TCGv t0 = ret;
1217
1218 if (compute_ca || compute_ov) {
1219 t0 = tcg_temp_new();
1220 }
1221
1222 if (compute_ca) {
1223 /* dest = ~arg1 + arg2 [+ ca]. */
1224 if (NARROW_MODE(ctx)) {
1225 /* Caution: a non-obvious corner case of the spec is that we
1226 must produce the *entire* 64-bit addition, but produce the
1227 carry into bit 32. */
1228 TCGv inv1 = tcg_temp_new();
1229 TCGv t1 = tcg_temp_new();
1230 tcg_gen_not_tl(inv1, arg1);
1231 if (add_ca) {
1232 tcg_gen_add_tl(t0, arg2, cpu_ca);
1233 } else {
1234 tcg_gen_addi_tl(t0, arg2, 1);
1235 }
1236 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1237 tcg_gen_add_tl(t0, t0, inv1);
1238 tcg_temp_free(inv1);
1239 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1240 tcg_temp_free(t1);
1241 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1242 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1243 } else if (add_ca) {
1244 TCGv zero, inv1 = tcg_temp_new();
1245 tcg_gen_not_tl(inv1, arg1);
1246 zero = tcg_const_tl(0);
1247 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1248 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1249 tcg_temp_free(zero);
1250 tcg_temp_free(inv1);
1251 } else {
1252 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1253 tcg_gen_sub_tl(t0, arg2, arg1);
1254 }
1255 } else if (add_ca) {
1256 /* Since we're ignoring carry-out, we can simplify the
1257 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1258 tcg_gen_sub_tl(t0, arg2, arg1);
1259 tcg_gen_add_tl(t0, t0, cpu_ca);
1260 tcg_gen_subi_tl(t0, t0, 1);
1261 } else {
1262 tcg_gen_sub_tl(t0, arg2, arg1);
1263 }
1264
1265 if (compute_ov) {
1266 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1267 }
1268 if (unlikely(compute_rc0)) {
1269 gen_set_Rc0(ctx, t0);
1270 }
1271
1272 if (!TCGV_EQUAL(t0, ret)) {
1273 tcg_gen_mov_tl(ret, t0);
1274 tcg_temp_free(t0);
1275 }
1276 }
1277 /* Sub functions with Two operands functions */
1278 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1279 static void glue(gen_, name)(DisasContext *ctx) \
1280 { \
1281 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1282 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1283 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1284 }
1285 /* Sub functions with one operand and one immediate */
1286 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1287 add_ca, compute_ca, compute_ov) \
1288 static void glue(gen_, name)(DisasContext *ctx) \
1289 { \
1290 TCGv t0 = tcg_const_tl(const_val); \
1291 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1292 cpu_gpr[rA(ctx->opcode)], t0, \
1293 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1294 tcg_temp_free(t0); \
1295 }
1296 /* subf subf. subfo subfo. */
1297 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1298 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1299 /* subfc subfc. subfco subfco. */
1300 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1301 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1302 /* subfe subfe. subfeo subfo. */
1303 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1304 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1305 /* subfme subfme. subfmeo subfmeo. */
1306 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1307 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1308 /* subfze subfze. subfzeo subfzeo.*/
1309 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1310 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1311
1312 /* subfic */
1313 static void gen_subfic(DisasContext *ctx)
1314 {
1315 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1316 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1317 c, 0, 1, 0, 0);
1318 tcg_temp_free(c);
1319 }
1320
1321 /* neg neg. nego nego. */
1322 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1323 {
1324 TCGv zero = tcg_const_tl(0);
1325 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1326 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1327 tcg_temp_free(zero);
1328 }
1329
1330 static void gen_neg(DisasContext *ctx)
1331 {
1332 gen_op_arith_neg(ctx, 0);
1333 }
1334
1335 static void gen_nego(DisasContext *ctx)
1336 {
1337 gen_op_arith_neg(ctx, 1);
1338 }
1339
1340 /*** Integer logical ***/
1341 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1342 static void glue(gen_, name)(DisasContext *ctx) \
1343 { \
1344 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1345 cpu_gpr[rB(ctx->opcode)]); \
1346 if (unlikely(Rc(ctx->opcode) != 0)) \
1347 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1348 }
1349
1350 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1351 static void glue(gen_, name)(DisasContext *ctx) \
1352 { \
1353 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1354 if (unlikely(Rc(ctx->opcode) != 0)) \
1355 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1356 }
1357
1358 /* and & and. */
1359 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1360 /* andc & andc. */
1361 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1362
1363 /* andi. */
1364 static void gen_andi_(DisasContext *ctx)
1365 {
1366 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1367 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1368 }
1369
1370 /* andis. */
1371 static void gen_andis_(DisasContext *ctx)
1372 {
1373 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1374 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1375 }
1376
1377 /* cntlzw */
1378 static void gen_cntlzw(DisasContext *ctx)
1379 {
1380 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1381 if (unlikely(Rc(ctx->opcode) != 0))
1382 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1383 }
1384 /* eqv & eqv. */
1385 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1386 /* extsb & extsb. */
1387 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1388 /* extsh & extsh. */
1389 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1390 /* nand & nand. */
1391 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1392 /* nor & nor. */
1393 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1394
1395 #if defined(TARGET_PPC64)
1396 static void gen_pause(DisasContext *ctx)
1397 {
1398 TCGv_i32 t0 = tcg_const_i32(0);
1399 tcg_gen_st_i32(t0, cpu_env,
1400 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1401 tcg_temp_free_i32(t0);
1402
1403 /* Stop translation, this gives other CPUs a chance to run */
1404 gen_exception_err(ctx, EXCP_HLT, 1);
1405 }
1406 #endif /* defined(TARGET_PPC64) */
1407
1408 /* or & or. */
1409 static void gen_or(DisasContext *ctx)
1410 {
1411 int rs, ra, rb;
1412
1413 rs = rS(ctx->opcode);
1414 ra = rA(ctx->opcode);
1415 rb = rB(ctx->opcode);
1416 /* Optimisation for mr. ri case */
1417 if (rs != ra || rs != rb) {
1418 if (rs != rb)
1419 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1420 else
1421 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1422 if (unlikely(Rc(ctx->opcode) != 0))
1423 gen_set_Rc0(ctx, cpu_gpr[ra]);
1424 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1425 gen_set_Rc0(ctx, cpu_gpr[rs]);
1426 #if defined(TARGET_PPC64)
1427 } else {
1428 int prio = 0;
1429
1430 switch (rs) {
1431 case 1:
1432 /* Set process priority to low */
1433 prio = 2;
1434 break;
1435 case 6:
1436 /* Set process priority to medium-low */
1437 prio = 3;
1438 break;
1439 case 2:
1440 /* Set process priority to normal */
1441 prio = 4;
1442 break;
1443 #if !defined(CONFIG_USER_ONLY)
1444 case 31:
1445 if (!ctx->pr) {
1446 /* Set process priority to very low */
1447 prio = 1;
1448 }
1449 break;
1450 case 5:
1451 if (!ctx->pr) {
1452 /* Set process priority to medium-hight */
1453 prio = 5;
1454 }
1455 break;
1456 case 3:
1457 if (!ctx->pr) {
1458 /* Set process priority to high */
1459 prio = 6;
1460 }
1461 break;
1462 case 7:
1463 if (ctx->hv && !ctx->pr) {
1464 /* Set process priority to very high */
1465 prio = 7;
1466 }
1467 break;
1468 #endif
1469 default:
1470 /* nop */
1471 break;
1472 }
1473 if (prio) {
1474 TCGv t0 = tcg_temp_new();
1475 gen_load_spr(t0, SPR_PPR);
1476 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1477 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1478 gen_store_spr(SPR_PPR, t0);
1479 tcg_temp_free(t0);
1480 /* Pause us out of TCG otherwise spin loops with smt_low
1481 * eat too much CPU and the kernel hangs
1482 */
1483 gen_pause(ctx);
1484 }
1485 #endif
1486 }
1487 }
1488 /* orc & orc. */
1489 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1490
1491 /* xor & xor. */
1492 static void gen_xor(DisasContext *ctx)
1493 {
1494 /* Optimisation for "set to zero" case */
1495 if (rS(ctx->opcode) != rB(ctx->opcode))
1496 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1497 else
1498 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1499 if (unlikely(Rc(ctx->opcode) != 0))
1500 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1501 }
1502
1503 /* ori */
1504 static void gen_ori(DisasContext *ctx)
1505 {
1506 target_ulong uimm = UIMM(ctx->opcode);
1507
1508 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1509 return;
1510 }
1511 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1512 }
1513
1514 /* oris */
1515 static void gen_oris(DisasContext *ctx)
1516 {
1517 target_ulong uimm = UIMM(ctx->opcode);
1518
1519 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1520 /* NOP */
1521 return;
1522 }
1523 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1524 }
1525
1526 /* xori */
1527 static void gen_xori(DisasContext *ctx)
1528 {
1529 target_ulong uimm = UIMM(ctx->opcode);
1530
1531 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1532 /* NOP */
1533 return;
1534 }
1535 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1536 }
1537
1538 /* xoris */
1539 static void gen_xoris(DisasContext *ctx)
1540 {
1541 target_ulong uimm = UIMM(ctx->opcode);
1542
1543 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1544 /* NOP */
1545 return;
1546 }
1547 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1548 }
1549
1550 /* popcntb : PowerPC 2.03 specification */
1551 static void gen_popcntb(DisasContext *ctx)
1552 {
1553 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1554 }
1555
1556 static void gen_popcntw(DisasContext *ctx)
1557 {
1558 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1559 }
1560
1561 #if defined(TARGET_PPC64)
1562 /* popcntd: PowerPC 2.06 specification */
1563 static void gen_popcntd(DisasContext *ctx)
1564 {
1565 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1566 }
1567 #endif
1568
1569 /* prtyw: PowerPC 2.05 specification */
1570 static void gen_prtyw(DisasContext *ctx)
1571 {
1572 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1573 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1574 TCGv t0 = tcg_temp_new();
1575 tcg_gen_shri_tl(t0, rs, 16);
1576 tcg_gen_xor_tl(ra, rs, t0);
1577 tcg_gen_shri_tl(t0, ra, 8);
1578 tcg_gen_xor_tl(ra, ra, t0);
1579 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1580 tcg_temp_free(t0);
1581 }
1582
1583 #if defined(TARGET_PPC64)
1584 /* prtyd: PowerPC 2.05 specification */
1585 static void gen_prtyd(DisasContext *ctx)
1586 {
1587 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1588 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1589 TCGv t0 = tcg_temp_new();
1590 tcg_gen_shri_tl(t0, rs, 32);
1591 tcg_gen_xor_tl(ra, rs, t0);
1592 tcg_gen_shri_tl(t0, ra, 16);
1593 tcg_gen_xor_tl(ra, ra, t0);
1594 tcg_gen_shri_tl(t0, ra, 8);
1595 tcg_gen_xor_tl(ra, ra, t0);
1596 tcg_gen_andi_tl(ra, ra, 1);
1597 tcg_temp_free(t0);
1598 }
1599 #endif
1600
1601 #if defined(TARGET_PPC64)
1602 /* bpermd */
1603 static void gen_bpermd(DisasContext *ctx)
1604 {
1605 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1606 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1607 }
1608 #endif
1609
1610 #if defined(TARGET_PPC64)
1611 /* extsw & extsw. */
1612 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1613
1614 /* cntlzd */
1615 static void gen_cntlzd(DisasContext *ctx)
1616 {
1617 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1618 if (unlikely(Rc(ctx->opcode) != 0))
1619 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1620 }
1621 #endif
1622
1623 /*** Integer rotate ***/
1624
1625 /* rlwimi & rlwimi. */
1626 static void gen_rlwimi(DisasContext *ctx)
1627 {
1628 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1629 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1630 uint32_t sh = SH(ctx->opcode);
1631 uint32_t mb = MB(ctx->opcode);
1632 uint32_t me = ME(ctx->opcode);
1633
1634 if (sh == (31-me) && mb <= me) {
1635 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1636 } else {
1637 target_ulong mask;
1638 TCGv_i32 t0;
1639 TCGv t1;
1640
1641 #if defined(TARGET_PPC64)
1642 mb += 32;
1643 me += 32;
1644 #endif
1645 mask = MASK(mb, me);
1646
1647 t0 = tcg_temp_new_i32();
1648 t1 = tcg_temp_new();
1649 tcg_gen_trunc_tl_i32(t0, t_rs);
1650 tcg_gen_rotli_i32(t0, t0, sh);
1651 tcg_gen_extu_i32_tl(t1, t0);
1652 tcg_temp_free_i32(t0);
1653
1654 tcg_gen_andi_tl(t1, t1, mask);
1655 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1656 tcg_gen_or_tl(t_ra, t_ra, t1);
1657 tcg_temp_free(t1);
1658 }
1659 if (unlikely(Rc(ctx->opcode) != 0)) {
1660 gen_set_Rc0(ctx, t_ra);
1661 }
1662 }
1663
1664 /* rlwinm & rlwinm. */
1665 static void gen_rlwinm(DisasContext *ctx)
1666 {
1667 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1668 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1669 uint32_t sh = SH(ctx->opcode);
1670 uint32_t mb = MB(ctx->opcode);
1671 uint32_t me = ME(ctx->opcode);
1672
1673 if (mb == 0 && me == (31 - sh)) {
1674 tcg_gen_shli_tl(t_ra, t_rs, sh);
1675 tcg_gen_ext32u_tl(t_ra, t_ra);
1676 } else if (sh != 0 && me == 31 && sh == (32 - mb)) {
1677 tcg_gen_ext32u_tl(t_ra, t_rs);
1678 tcg_gen_shri_tl(t_ra, t_ra, mb);
1679 } else {
1680 #if defined(TARGET_PPC64)
1681 mb += 32;
1682 me += 32;
1683 #endif
1684 if (sh == 0) {
1685 tcg_gen_andi_tl(t_ra, t_rs, MASK(mb, me));
1686 } else {
1687 TCGv_i32 t0 = tcg_temp_new_i32();
1688
1689 tcg_gen_trunc_tl_i32(t0, t_rs);
1690 tcg_gen_rotli_i32(t0, t0, sh);
1691 tcg_gen_andi_i32(t0, t0, MASK(mb, me));
1692 tcg_gen_extu_i32_tl(t_ra, t0);
1693 tcg_temp_free_i32(t0);
1694 }
1695 }
1696 if (unlikely(Rc(ctx->opcode) != 0)) {
1697 gen_set_Rc0(ctx, t_ra);
1698 }
1699 }
1700
1701 /* rlwnm & rlwnm. */
1702 static void gen_rlwnm(DisasContext *ctx)
1703 {
1704 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1705 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1706 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1707 uint32_t mb = MB(ctx->opcode);
1708 uint32_t me = ME(ctx->opcode);
1709 TCGv_i32 t0, t1;
1710
1711 #if defined(TARGET_PPC64)
1712 mb += 32;
1713 me += 32;
1714 #endif
1715
1716 t0 = tcg_temp_new_i32();
1717 t1 = tcg_temp_new_i32();
1718 tcg_gen_trunc_tl_i32(t0, t_rb);
1719 tcg_gen_trunc_tl_i32(t1, t_rs);
1720 tcg_gen_andi_i32(t0, t0, 0x1f);
1721 tcg_gen_rotl_i32(t1, t1, t0);
1722 tcg_temp_free_i32(t0);
1723
1724 tcg_gen_andi_i32(t1, t1, MASK(mb, me));
1725 tcg_gen_extu_i32_tl(t_ra, t1);
1726 tcg_temp_free_i32(t1);
1727
1728 if (unlikely(Rc(ctx->opcode) != 0)) {
1729 gen_set_Rc0(ctx, t_ra);
1730 }
1731 }
1732
1733 #if defined(TARGET_PPC64)
1734 #define GEN_PPC64_R2(name, opc1, opc2) \
1735 static void glue(gen_, name##0)(DisasContext *ctx) \
1736 { \
1737 gen_##name(ctx, 0); \
1738 } \
1739 \
1740 static void glue(gen_, name##1)(DisasContext *ctx) \
1741 { \
1742 gen_##name(ctx, 1); \
1743 }
1744 #define GEN_PPC64_R4(name, opc1, opc2) \
1745 static void glue(gen_, name##0)(DisasContext *ctx) \
1746 { \
1747 gen_##name(ctx, 0, 0); \
1748 } \
1749 \
1750 static void glue(gen_, name##1)(DisasContext *ctx) \
1751 { \
1752 gen_##name(ctx, 0, 1); \
1753 } \
1754 \
1755 static void glue(gen_, name##2)(DisasContext *ctx) \
1756 { \
1757 gen_##name(ctx, 1, 0); \
1758 } \
1759 \
1760 static void glue(gen_, name##3)(DisasContext *ctx) \
1761 { \
1762 gen_##name(ctx, 1, 1); \
1763 }
1764
1765 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
1766 {
1767 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1768 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1769
1770 if (sh != 0 && mb == 0 && me == (63 - sh)) {
1771 tcg_gen_shli_tl(t_ra, t_rs, sh);
1772 } else if (sh != 0 && me == 63 && sh == (64 - mb)) {
1773 tcg_gen_shri_tl(t_ra, t_rs, mb);
1774 } else {
1775 tcg_gen_rotli_tl(t_ra, t_rs, sh);
1776 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
1777 }
1778 if (unlikely(Rc(ctx->opcode) != 0)) {
1779 gen_set_Rc0(ctx, t_ra);
1780 }
1781 }
1782
1783 /* rldicl - rldicl. */
1784 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1785 {
1786 uint32_t sh, mb;
1787
1788 sh = SH(ctx->opcode) | (shn << 5);
1789 mb = MB(ctx->opcode) | (mbn << 5);
1790 gen_rldinm(ctx, mb, 63, sh);
1791 }
1792 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1793
1794 /* rldicr - rldicr. */
1795 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1796 {
1797 uint32_t sh, me;
1798
1799 sh = SH(ctx->opcode) | (shn << 5);
1800 me = MB(ctx->opcode) | (men << 5);
1801 gen_rldinm(ctx, 0, me, sh);
1802 }
1803 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1804
1805 /* rldic - rldic. */
1806 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1807 {
1808 uint32_t sh, mb;
1809
1810 sh = SH(ctx->opcode) | (shn << 5);
1811 mb = MB(ctx->opcode) | (mbn << 5);
1812 gen_rldinm(ctx, mb, 63 - sh, sh);
1813 }
1814 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1815
1816 static void gen_rldnm(DisasContext *ctx, int mb, int me)
1817 {
1818 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1819 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1820 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1821 TCGv t0;
1822
1823 t0 = tcg_temp_new();
1824 tcg_gen_andi_tl(t0, t_rb, 0x3f);
1825 tcg_gen_rotl_tl(t_ra, t_rs, t0);
1826 tcg_temp_free(t0);
1827
1828 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
1829 if (unlikely(Rc(ctx->opcode) != 0)) {
1830 gen_set_Rc0(ctx, t_ra);
1831 }
1832 }
1833
1834 /* rldcl - rldcl. */
1835 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1836 {
1837 uint32_t mb;
1838
1839 mb = MB(ctx->opcode) | (mbn << 5);
1840 gen_rldnm(ctx, mb, 63);
1841 }
1842 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1843
1844 /* rldcr - rldcr. */
1845 static inline void gen_rldcr(DisasContext *ctx, int men)
1846 {
1847 uint32_t me;
1848
1849 me = MB(ctx->opcode) | (men << 5);
1850 gen_rldnm(ctx, 0, me);
1851 }
1852 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1853
1854 /* rldimi - rldimi. */
1855 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1856 {
1857 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1858 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1859 uint32_t sh = SH(ctx->opcode) | (shn << 5);
1860 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
1861 uint32_t me = 63 - sh;
1862
1863 if (mb <= me) {
1864 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1865 } else {
1866 target_ulong mask = MASK(mb, me);
1867 TCGv t1 = tcg_temp_new();
1868
1869 tcg_gen_rotli_tl(t1, t_rs, sh);
1870 tcg_gen_andi_tl(t1, t1, mask);
1871 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1872 tcg_gen_or_tl(t_ra, t_ra, t1);
1873 tcg_temp_free(t1);
1874 }
1875 if (unlikely(Rc(ctx->opcode) != 0)) {
1876 gen_set_Rc0(ctx, t_ra);
1877 }
1878 }
1879 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1880 #endif
1881
1882 /*** Integer shift ***/
1883
1884 /* slw & slw. */
1885 static void gen_slw(DisasContext *ctx)
1886 {
1887 TCGv t0, t1;
1888
1889 t0 = tcg_temp_new();
1890 /* AND rS with a mask that is 0 when rB >= 0x20 */
1891 #if defined(TARGET_PPC64)
1892 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1893 tcg_gen_sari_tl(t0, t0, 0x3f);
1894 #else
1895 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1896 tcg_gen_sari_tl(t0, t0, 0x1f);
1897 #endif
1898 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1899 t1 = tcg_temp_new();
1900 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1901 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1902 tcg_temp_free(t1);
1903 tcg_temp_free(t0);
1904 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1905 if (unlikely(Rc(ctx->opcode) != 0))
1906 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1907 }
1908
1909 /* sraw & sraw. */
1910 static void gen_sraw(DisasContext *ctx)
1911 {
1912 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1913 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1914 if (unlikely(Rc(ctx->opcode) != 0))
1915 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1916 }
1917
1918 /* srawi & srawi. */
1919 static void gen_srawi(DisasContext *ctx)
1920 {
1921 int sh = SH(ctx->opcode);
1922 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1923 TCGv src = cpu_gpr[rS(ctx->opcode)];
1924 if (sh == 0) {
1925 tcg_gen_ext32s_tl(dst, src);
1926 tcg_gen_movi_tl(cpu_ca, 0);
1927 } else {
1928 TCGv t0;
1929 tcg_gen_ext32s_tl(dst, src);
1930 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1931 t0 = tcg_temp_new();
1932 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1933 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1934 tcg_temp_free(t0);
1935 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1936 tcg_gen_sari_tl(dst, dst, sh);
1937 }
1938 if (unlikely(Rc(ctx->opcode) != 0)) {
1939 gen_set_Rc0(ctx, dst);
1940 }
1941 }
1942
1943 /* srw & srw. */
1944 static void gen_srw(DisasContext *ctx)
1945 {
1946 TCGv t0, t1;
1947
1948 t0 = tcg_temp_new();
1949 /* AND rS with a mask that is 0 when rB >= 0x20 */
1950 #if defined(TARGET_PPC64)
1951 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1952 tcg_gen_sari_tl(t0, t0, 0x3f);
1953 #else
1954 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1955 tcg_gen_sari_tl(t0, t0, 0x1f);
1956 #endif
1957 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1958 tcg_gen_ext32u_tl(t0, t0);
1959 t1 = tcg_temp_new();
1960 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1961 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1962 tcg_temp_free(t1);
1963 tcg_temp_free(t0);
1964 if (unlikely(Rc(ctx->opcode) != 0))
1965 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1966 }
1967
1968 #if defined(TARGET_PPC64)
1969 /* sld & sld. */
1970 static void gen_sld(DisasContext *ctx)
1971 {
1972 TCGv t0, t1;
1973
1974 t0 = tcg_temp_new();
1975 /* AND rS with a mask that is 0 when rB >= 0x40 */
1976 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1977 tcg_gen_sari_tl(t0, t0, 0x3f);
1978 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1979 t1 = tcg_temp_new();
1980 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1981 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1982 tcg_temp_free(t1);
1983 tcg_temp_free(t0);
1984 if (unlikely(Rc(ctx->opcode) != 0))
1985 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1986 }
1987
1988 /* srad & srad. */
1989 static void gen_srad(DisasContext *ctx)
1990 {
1991 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1992 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1993 if (unlikely(Rc(ctx->opcode) != 0))
1994 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1995 }
1996 /* sradi & sradi. */
1997 static inline void gen_sradi(DisasContext *ctx, int n)
1998 {
1999 int sh = SH(ctx->opcode) + (n << 5);
2000 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2001 TCGv src = cpu_gpr[rS(ctx->opcode)];
2002 if (sh == 0) {
2003 tcg_gen_mov_tl(dst, src);
2004 tcg_gen_movi_tl(cpu_ca, 0);
2005 } else {
2006 TCGv t0;
2007 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2008 t0 = tcg_temp_new();
2009 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2010 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2011 tcg_temp_free(t0);
2012 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2013 tcg_gen_sari_tl(dst, src, sh);
2014 }
2015 if (unlikely(Rc(ctx->opcode) != 0)) {
2016 gen_set_Rc0(ctx, dst);
2017 }
2018 }
2019
2020 static void gen_sradi0(DisasContext *ctx)
2021 {
2022 gen_sradi(ctx, 0);
2023 }
2024
2025 static void gen_sradi1(DisasContext *ctx)
2026 {
2027 gen_sradi(ctx, 1);
2028 }
2029
2030 /* srd & srd. */
2031 static void gen_srd(DisasContext *ctx)
2032 {
2033 TCGv t0, t1;
2034
2035 t0 = tcg_temp_new();
2036 /* AND rS with a mask that is 0 when rB >= 0x40 */
2037 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2038 tcg_gen_sari_tl(t0, t0, 0x3f);
2039 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2040 t1 = tcg_temp_new();
2041 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2042 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2043 tcg_temp_free(t1);
2044 tcg_temp_free(t0);
2045 if (unlikely(Rc(ctx->opcode) != 0))
2046 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2047 }
2048 #endif
2049
2050 #if defined(TARGET_PPC64)
2051 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2052 {
2053 TCGv_i32 tmp = tcg_temp_new_i32();
2054 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
2055 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
2056 tcg_temp_free_i32(tmp);
2057 }
2058 #else
2059 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2060 {
2061 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
2062 }
2063 #endif
2064
2065 /*** Floating-Point arithmetic ***/
2066 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2067 static void gen_f##name(DisasContext *ctx) \
2068 { \
2069 if (unlikely(!ctx->fpu_enabled)) { \
2070 gen_exception(ctx, POWERPC_EXCP_FPU); \
2071 return; \
2072 } \
2073 /* NIP cannot be restored if the memory exception comes from an helper */ \
2074 gen_update_nip(ctx, ctx->nip - 4); \
2075 gen_reset_fpstatus(); \
2076 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2077 cpu_fpr[rA(ctx->opcode)], \
2078 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2079 if (isfloat) { \
2080 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2081 cpu_fpr[rD(ctx->opcode)]); \
2082 } \
2083 if (set_fprf) { \
2084 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2085 } \
2086 if (unlikely(Rc(ctx->opcode) != 0)) { \
2087 gen_set_cr1_from_fpscr(ctx); \
2088 } \
2089 }
2090
2091 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2092 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2093 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2094
2095 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2096 static void gen_f##name(DisasContext *ctx) \
2097 { \
2098 if (unlikely(!ctx->fpu_enabled)) { \
2099 gen_exception(ctx, POWERPC_EXCP_FPU); \
2100 return; \
2101 } \
2102 /* NIP cannot be restored if the memory exception comes from an helper */ \
2103 gen_update_nip(ctx, ctx->nip - 4); \
2104 gen_reset_fpstatus(); \
2105 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2106 cpu_fpr[rA(ctx->opcode)], \
2107 cpu_fpr[rB(ctx->opcode)]); \
2108 if (isfloat) { \
2109 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2110 cpu_fpr[rD(ctx->opcode)]); \
2111 } \
2112 if (set_fprf) { \
2113 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2114 } \
2115 if (unlikely(Rc(ctx->opcode) != 0)) { \
2116 gen_set_cr1_from_fpscr(ctx); \
2117 } \
2118 }
2119 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2120 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2121 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2122
2123 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2124 static void gen_f##name(DisasContext *ctx) \
2125 { \
2126 if (unlikely(!ctx->fpu_enabled)) { \
2127 gen_exception(ctx, POWERPC_EXCP_FPU); \
2128 return; \
2129 } \
2130 /* NIP cannot be restored if the memory exception comes from an helper */ \
2131 gen_update_nip(ctx, ctx->nip - 4); \
2132 gen_reset_fpstatus(); \
2133 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2134 cpu_fpr[rA(ctx->opcode)], \
2135 cpu_fpr[rC(ctx->opcode)]); \
2136 if (isfloat) { \
2137 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2138 cpu_fpr[rD(ctx->opcode)]); \
2139 } \
2140 if (set_fprf) { \
2141 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2142 } \
2143 if (unlikely(Rc(ctx->opcode) != 0)) { \
2144 gen_set_cr1_from_fpscr(ctx); \
2145 } \
2146 }
2147 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2148 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2149 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2150
2151 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2152 static void gen_f##name(DisasContext *ctx) \
2153 { \
2154 if (unlikely(!ctx->fpu_enabled)) { \
2155 gen_exception(ctx, POWERPC_EXCP_FPU); \
2156 return; \
2157 } \
2158 /* NIP cannot be restored if the memory exception comes from an helper */ \
2159 gen_update_nip(ctx, ctx->nip - 4); \
2160 gen_reset_fpstatus(); \
2161 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2162 cpu_fpr[rB(ctx->opcode)]); \
2163 if (set_fprf) { \
2164 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2165 } \
2166 if (unlikely(Rc(ctx->opcode) != 0)) { \
2167 gen_set_cr1_from_fpscr(ctx); \
2168 } \
2169 }
2170
2171 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2172 static void gen_f##name(DisasContext *ctx) \
2173 { \
2174 if (unlikely(!ctx->fpu_enabled)) { \
2175 gen_exception(ctx, POWERPC_EXCP_FPU); \
2176 return; \
2177 } \
2178 /* NIP cannot be restored if the memory exception comes from an helper */ \
2179 gen_update_nip(ctx, ctx->nip - 4); \
2180 gen_reset_fpstatus(); \
2181 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2182 cpu_fpr[rB(ctx->opcode)]); \
2183 if (set_fprf) { \
2184 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2185 } \
2186 if (unlikely(Rc(ctx->opcode) != 0)) { \
2187 gen_set_cr1_from_fpscr(ctx); \
2188 } \
2189 }
2190
2191 /* fadd - fadds */
2192 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2193 /* fdiv - fdivs */
2194 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2195 /* fmul - fmuls */
2196 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2197
2198 /* fre */
2199 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2200
2201 /* fres */
2202 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2203
2204 /* frsqrte */
2205 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2206
2207 /* frsqrtes */
2208 static void gen_frsqrtes(DisasContext *ctx)
2209 {
2210 if (unlikely(!ctx->fpu_enabled)) {
2211 gen_exception(ctx, POWERPC_EXCP_FPU);
2212 return;
2213 }
2214 /* NIP cannot be restored if the memory exception comes from an helper */
2215 gen_update_nip(ctx, ctx->nip - 4);
2216 gen_reset_fpstatus();
2217 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2218 cpu_fpr[rB(ctx->opcode)]);
2219 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2220 cpu_fpr[rD(ctx->opcode)]);
2221 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2222 if (unlikely(Rc(ctx->opcode) != 0)) {
2223 gen_set_cr1_from_fpscr(ctx);
2224 }
2225 }
2226
2227 /* fsel */
2228 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2229 /* fsub - fsubs */
2230 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2231 /* Optional: */
2232
2233 /* fsqrt */
2234 static void gen_fsqrt(DisasContext *ctx)
2235 {
2236 if (unlikely(!ctx->fpu_enabled)) {
2237 gen_exception(ctx, POWERPC_EXCP_FPU);
2238 return;
2239 }
2240 /* NIP cannot be restored if the memory exception comes from an helper */
2241 gen_update_nip(ctx, ctx->nip - 4);
2242 gen_reset_fpstatus();
2243 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2244 cpu_fpr[rB(ctx->opcode)]);
2245 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2246 if (unlikely(Rc(ctx->opcode) != 0)) {
2247 gen_set_cr1_from_fpscr(ctx);
2248 }
2249 }
2250
2251 static void gen_fsqrts(DisasContext *ctx)
2252 {
2253 if (unlikely(!ctx->fpu_enabled)) {
2254 gen_exception(ctx, POWERPC_EXCP_FPU);
2255 return;
2256 }
2257 /* NIP cannot be restored if the memory exception comes from an helper */
2258 gen_update_nip(ctx, ctx->nip - 4);
2259 gen_reset_fpstatus();
2260 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2261 cpu_fpr[rB(ctx->opcode)]);
2262 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2263 cpu_fpr[rD(ctx->opcode)]);
2264 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2265 if (unlikely(Rc(ctx->opcode) != 0)) {
2266 gen_set_cr1_from_fpscr(ctx);
2267 }
2268 }
2269
2270 /*** Floating-Point multiply-and-add ***/
2271 /* fmadd - fmadds */
2272 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2273 /* fmsub - fmsubs */
2274 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2275 /* fnmadd - fnmadds */
2276 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2277 /* fnmsub - fnmsubs */
2278 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2279
2280 /*** Floating-Point round & convert ***/
2281 /* fctiw */
2282 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2283 /* fctiwu */
2284 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2285 /* fctiwz */
2286 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2287 /* fctiwuz */
2288 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2289 /* frsp */
2290 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2291 /* fcfid */
2292 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
2293 /* fcfids */
2294 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2295 /* fcfidu */
2296 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2297 /* fcfidus */
2298 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2299 /* fctid */
2300 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
2301 /* fctidu */
2302 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2303 /* fctidz */
2304 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
2305 /* fctidu */
2306 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2307
2308 /* frin */
2309 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2310 /* friz */
2311 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2312 /* frip */
2313 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2314 /* frim */
2315 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2316
2317 static void gen_ftdiv(DisasContext *ctx)
2318 {
2319 if (unlikely(!ctx->fpu_enabled)) {
2320 gen_exception(ctx, POWERPC_EXCP_FPU);
2321 return;
2322 }
2323 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2324 cpu_fpr[rB(ctx->opcode)]);
2325 }
2326
2327 static void gen_ftsqrt(DisasContext *ctx)
2328 {
2329 if (unlikely(!ctx->fpu_enabled)) {
2330 gen_exception(ctx, POWERPC_EXCP_FPU);
2331 return;
2332 }
2333 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2334 }
2335
2336
2337
2338 /*** Floating-Point compare ***/
2339
2340 /* fcmpo */
2341 static void gen_fcmpo(DisasContext *ctx)
2342 {
2343 TCGv_i32 crf;
2344 if (unlikely(!ctx->fpu_enabled)) {
2345 gen_exception(ctx, POWERPC_EXCP_FPU);
2346 return;
2347 }
2348 /* NIP cannot be restored if the memory exception comes from an helper */
2349 gen_update_nip(ctx, ctx->nip - 4);
2350 gen_reset_fpstatus();
2351 crf = tcg_const_i32(crfD(ctx->opcode));
2352 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2353 cpu_fpr[rB(ctx->opcode)], crf);
2354 tcg_temp_free_i32(crf);
2355 gen_helper_float_check_status(cpu_env);
2356 }
2357
2358 /* fcmpu */
2359 static void gen_fcmpu(DisasContext *ctx)
2360 {
2361 TCGv_i32 crf;
2362 if (unlikely(!ctx->fpu_enabled)) {
2363 gen_exception(ctx, POWERPC_EXCP_FPU);
2364 return;
2365 }
2366 /* NIP cannot be restored if the memory exception comes from an helper */
2367 gen_update_nip(ctx, ctx->nip - 4);
2368 gen_reset_fpstatus();
2369 crf = tcg_const_i32(crfD(ctx->opcode));
2370 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2371 cpu_fpr[rB(ctx->opcode)], crf);
2372 tcg_temp_free_i32(crf);
2373 gen_helper_float_check_status(cpu_env);
2374 }
2375
2376 /*** Floating-point move ***/
2377 /* fabs */
2378 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2379 static void gen_fabs(DisasContext *ctx)
2380 {
2381 if (unlikely(!ctx->fpu_enabled)) {
2382 gen_exception(ctx, POWERPC_EXCP_FPU);
2383 return;
2384 }
2385 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2386 ~(1ULL << 63));
2387 if (unlikely(Rc(ctx->opcode))) {
2388 gen_set_cr1_from_fpscr(ctx);
2389 }
2390 }
2391
2392 /* fmr - fmr. */
2393 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2394 static void gen_fmr(DisasContext *ctx)
2395 {
2396 if (unlikely(!ctx->fpu_enabled)) {
2397 gen_exception(ctx, POWERPC_EXCP_FPU);
2398 return;
2399 }
2400 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2401 if (unlikely(Rc(ctx->opcode))) {
2402 gen_set_cr1_from_fpscr(ctx);
2403 }
2404 }
2405
2406 /* fnabs */
2407 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2408 static void gen_fnabs(DisasContext *ctx)
2409 {
2410 if (unlikely(!ctx->fpu_enabled)) {
2411 gen_exception(ctx, POWERPC_EXCP_FPU);
2412 return;
2413 }
2414 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2415 1ULL << 63);
2416 if (unlikely(Rc(ctx->opcode))) {
2417 gen_set_cr1_from_fpscr(ctx);
2418 }
2419 }
2420
2421 /* fneg */
2422 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2423 static void gen_fneg(DisasContext *ctx)
2424 {
2425 if (unlikely(!ctx->fpu_enabled)) {
2426 gen_exception(ctx, POWERPC_EXCP_FPU);
2427 return;
2428 }
2429 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2430 1ULL << 63);
2431 if (unlikely(Rc(ctx->opcode))) {
2432 gen_set_cr1_from_fpscr(ctx);
2433 }
2434 }
2435
2436 /* fcpsgn: PowerPC 2.05 specification */
2437 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2438 static void gen_fcpsgn(DisasContext *ctx)
2439 {
2440 if (unlikely(!ctx->fpu_enabled)) {
2441 gen_exception(ctx, POWERPC_EXCP_FPU);
2442 return;
2443 }
2444 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2445 cpu_fpr[rB(ctx->opcode)], 0, 63);
2446 if (unlikely(Rc(ctx->opcode))) {
2447 gen_set_cr1_from_fpscr(ctx);
2448 }
2449 }
2450
2451 static void gen_fmrgew(DisasContext *ctx)
2452 {
2453 TCGv_i64 b0;
2454 if (unlikely(!ctx->fpu_enabled)) {
2455 gen_exception(ctx, POWERPC_EXCP_FPU);
2456 return;
2457 }
2458 b0 = tcg_temp_new_i64();
2459 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2460 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2461 b0, 0, 32);
2462 tcg_temp_free_i64(b0);
2463 }
2464
2465 static void gen_fmrgow(DisasContext *ctx)
2466 {
2467 if (unlikely(!ctx->fpu_enabled)) {
2468 gen_exception(ctx, POWERPC_EXCP_FPU);
2469 return;
2470 }
2471 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2472 cpu_fpr[rB(ctx->opcode)],
2473 cpu_fpr[rA(ctx->opcode)],
2474 32, 32);
2475 }
2476
2477 /*** Floating-Point status & ctrl register ***/
2478
2479 /* mcrfs */
2480 static void gen_mcrfs(DisasContext *ctx)
2481 {
2482 TCGv tmp = tcg_temp_new();
2483 TCGv_i32 tmask;
2484 TCGv_i64 tnew_fpscr = tcg_temp_new_i64();
2485 int bfa;
2486 int nibble;
2487 int shift;
2488
2489 if (unlikely(!ctx->fpu_enabled)) {
2490 gen_exception(ctx, POWERPC_EXCP_FPU);
2491 return;
2492 }
2493 bfa = crfS(ctx->opcode);
2494 nibble = 7 - bfa;
2495 shift = 4 * nibble;
2496 tcg_gen_shri_tl(tmp, cpu_fpscr, shift);
2497 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2498 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2499 tcg_temp_free(tmp);
2500 tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr);
2501 /* Only the exception bits (including FX) should be cleared if read */
2502 tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, ~((0xF << shift) & FP_EX_CLEAR_BITS));
2503 /* FEX and VX need to be updated, so don't set fpscr directly */
2504 tmask = tcg_const_i32(1 << nibble);
2505 gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
2506 tcg_temp_free_i32(tmask);
2507 tcg_temp_free_i64(tnew_fpscr);
2508 }
2509
2510 /* mffs */
2511 static void gen_mffs(DisasContext *ctx)
2512 {
2513 if (unlikely(!ctx->fpu_enabled)) {
2514 gen_exception(ctx, POWERPC_EXCP_FPU);
2515 return;
2516 }
2517 gen_reset_fpstatus();
2518 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2519 if (unlikely(Rc(ctx->opcode))) {
2520 gen_set_cr1_from_fpscr(ctx);
2521 }
2522 }
2523
2524 /* mtfsb0 */
2525 static void gen_mtfsb0(DisasContext *ctx)
2526 {
2527 uint8_t crb;
2528
2529 if (unlikely(!ctx->fpu_enabled)) {
2530 gen_exception(ctx, POWERPC_EXCP_FPU);
2531 return;
2532 }
2533 crb = 31 - crbD(ctx->opcode);
2534 gen_reset_fpstatus();
2535 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2536 TCGv_i32 t0;
2537 /* NIP cannot be restored if the memory exception comes from an helper */
2538 gen_update_nip(ctx, ctx->nip - 4);
2539 t0 = tcg_const_i32(crb);
2540 gen_helper_fpscr_clrbit(cpu_env, t0);
2541 tcg_temp_free_i32(t0);
2542 }
2543 if (unlikely(Rc(ctx->opcode) != 0)) {
2544 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2545 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2546 }
2547 }
2548
2549 /* mtfsb1 */
2550 static void gen_mtfsb1(DisasContext *ctx)
2551 {
2552 uint8_t crb;
2553
2554 if (unlikely(!ctx->fpu_enabled)) {
2555 gen_exception(ctx, POWERPC_EXCP_FPU);
2556 return;
2557 }
2558 crb = 31 - crbD(ctx->opcode);
2559 gen_reset_fpstatus();
2560 /* XXX: we pretend we can only do IEEE floating-point computations */
2561 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2562 TCGv_i32 t0;
2563 /* NIP cannot be restored if the memory exception comes from an helper */
2564 gen_update_nip(ctx, ctx->nip - 4);
2565 t0 = tcg_const_i32(crb);
2566 gen_helper_fpscr_setbit(cpu_env, t0);
2567 tcg_temp_free_i32(t0);
2568 }
2569 if (unlikely(Rc(ctx->opcode) != 0)) {
2570 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2571 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2572 }
2573 /* We can raise a differed exception */
2574 gen_helper_float_check_status(cpu_env);
2575 }
2576
2577 /* mtfsf */
2578 static void gen_mtfsf(DisasContext *ctx)
2579 {
2580 TCGv_i32 t0;
2581 int flm, l, w;
2582
2583 if (unlikely(!ctx->fpu_enabled)) {
2584 gen_exception(ctx, POWERPC_EXCP_FPU);
2585 return;
2586 }
2587 flm = FPFLM(ctx->opcode);
2588 l = FPL(ctx->opcode);
2589 w = FPW(ctx->opcode);
2590 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2591 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2592 return;
2593 }
2594 /* NIP cannot be restored if the memory exception comes from an helper */
2595 gen_update_nip(ctx, ctx->nip - 4);
2596 gen_reset_fpstatus();
2597 if (l) {
2598 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2599 } else {
2600 t0 = tcg_const_i32(flm << (w * 8));
2601 }
2602 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2603 tcg_temp_free_i32(t0);
2604 if (unlikely(Rc(ctx->opcode) != 0)) {
2605 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2606 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2607 }
2608 /* We can raise a differed exception */
2609 gen_helper_float_check_status(cpu_env);
2610 }
2611
2612 /* mtfsfi */
2613 static void gen_mtfsfi(DisasContext *ctx)
2614 {
2615 int bf, sh, w;
2616 TCGv_i64 t0;
2617 TCGv_i32 t1;
2618
2619 if (unlikely(!ctx->fpu_enabled)) {
2620 gen_exception(ctx, POWERPC_EXCP_FPU);
2621 return;
2622 }
2623 w = FPW(ctx->opcode);
2624 bf = FPBF(ctx->opcode);
2625 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2626 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2627 return;
2628 }
2629 sh = (8 * w) + 7 - bf;
2630 /* NIP cannot be restored if the memory exception comes from an helper */
2631 gen_update_nip(ctx, ctx->nip - 4);
2632 gen_reset_fpstatus();
2633 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2634 t1 = tcg_const_i32(1 << sh);
2635 gen_helper_store_fpscr(cpu_env, t0, t1);
2636 tcg_temp_free_i64(t0);
2637 tcg_temp_free_i32(t1);
2638 if (unlikely(Rc(ctx->opcode) != 0)) {
2639 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2640 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2641 }
2642 /* We can raise a differed exception */
2643 gen_helper_float_check_status(cpu_env);
2644 }
2645
2646 /*** Addressing modes ***/
2647 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2648 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2649 target_long maskl)
2650 {
2651 target_long simm = SIMM(ctx->opcode);
2652
2653 simm &= ~maskl;
2654 if (rA(ctx->opcode) == 0) {
2655 if (NARROW_MODE(ctx)) {
2656 simm = (uint32_t)simm;
2657 }
2658 tcg_gen_movi_tl(EA, simm);
2659 } else if (likely(simm != 0)) {
2660 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2661 if (NARROW_MODE(ctx)) {
2662 tcg_gen_ext32u_tl(EA, EA);
2663 }
2664 } else {
2665 if (NARROW_MODE(ctx)) {
2666 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2667 } else {
2668 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2669 }
2670 }
2671 }
2672
2673 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2674 {
2675 if (rA(ctx->opcode) == 0) {
2676 if (NARROW_MODE(ctx)) {
2677 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2678 } else {
2679 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2680 }
2681 } else {
2682 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2683 if (NARROW_MODE(ctx)) {
2684 tcg_gen_ext32u_tl(EA, EA);
2685 }
2686 }
2687 }
2688
2689 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2690 {
2691 if (rA(ctx->opcode) == 0) {
2692 tcg_gen_movi_tl(EA, 0);
2693 } else if (NARROW_MODE(ctx)) {
2694 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2695 } else {
2696 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2697 }
2698 }
2699
2700 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2701 target_long val)
2702 {
2703 tcg_gen_addi_tl(ret, arg1, val);
2704 if (NARROW_MODE(ctx)) {
2705 tcg_gen_ext32u_tl(ret, ret);
2706 }
2707 }
2708
2709 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2710 {
2711 TCGLabel *l1 = gen_new_label();
2712 TCGv t0 = tcg_temp_new();
2713 TCGv_i32 t1, t2;
2714 /* NIP cannot be restored if the memory exception comes from an helper */
2715 gen_update_nip(ctx, ctx->nip - 4);
2716 tcg_gen_andi_tl(t0, EA, mask);
2717 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2718 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2719 t2 = tcg_const_i32(0);
2720 gen_helper_raise_exception_err(cpu_env, t1, t2);
2721 tcg_temp_free_i32(t1);
2722 tcg_temp_free_i32(t2);
2723 gen_set_label(l1);
2724 tcg_temp_free(t0);
2725 }
2726
2727 /*** Integer load ***/
2728 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2729 {
2730 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2731 }
2732
2733 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2734 {
2735 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2736 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2737 }
2738
2739 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2740 {
2741 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2742 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2743 }
2744
2745 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2746 {
2747 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2748 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2749 }
2750
2751 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2752 {
2753 TCGv tmp = tcg_temp_new();
2754 gen_qemu_ld32u(ctx, tmp, addr);
2755 tcg_gen_extu_tl_i64(val, tmp);
2756 tcg_temp_free(tmp);
2757 }
2758
2759 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2760 {
2761 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2762 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2763 }
2764
2765 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2766 {
2767 TCGv tmp = tcg_temp_new();
2768 gen_qemu_ld32s(ctx, tmp, addr);
2769 tcg_gen_ext_tl_i64(val, tmp);
2770 tcg_temp_free(tmp);
2771 }
2772
2773 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2774 {
2775 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2776 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2777 }
2778
2779 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2780 {
2781 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2782 }
2783
2784 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2785 {
2786 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2787 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2788 }
2789
2790 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2791 {
2792 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2793 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2794 }
2795
2796 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2797 {
2798 TCGv tmp = tcg_temp_new();
2799 tcg_gen_trunc_i64_tl(tmp, val);
2800 gen_qemu_st32(ctx, tmp, addr);
2801 tcg_temp_free(tmp);
2802 }
2803
2804 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2805 {
2806 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2807 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2808 }
2809
2810 #define GEN_LD(name, ldop, opc, type) \
2811 static void glue(gen_, name)(DisasContext *ctx) \
2812 { \
2813 TCGv EA; \
2814 gen_set_access_type(ctx, ACCESS_INT); \
2815 EA = tcg_temp_new(); \
2816 gen_addr_imm_index(ctx, EA, 0); \
2817 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2818 tcg_temp_free(EA); \
2819 }
2820
2821 #define GEN_LDU(name, ldop, opc, type) \
2822 static void glue(gen_, name##u)(DisasContext *ctx) \
2823 { \
2824 TCGv EA; \
2825 if (unlikely(rA(ctx->opcode) == 0 || \
2826 rA(ctx->opcode) == rD(ctx->opcode))) { \
2827 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2828 return; \
2829 } \
2830 gen_set_access_type(ctx, ACCESS_INT); \
2831 EA = tcg_temp_new(); \
2832 if (type == PPC_64B) \
2833 gen_addr_imm_index(ctx, EA, 0x03); \
2834 else \
2835 gen_addr_imm_index(ctx, EA, 0); \
2836 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2837 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2838 tcg_temp_free(EA); \
2839 }
2840
2841 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2842 static void glue(gen_, name##ux)(DisasContext *ctx) \
2843 { \
2844 TCGv EA; \
2845 if (unlikely(rA(ctx->opcode) == 0 || \
2846 rA(ctx->opcode) == rD(ctx->opcode))) { \
2847 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2848 return; \
2849 } \
2850 gen_set_access_type(ctx, ACCESS_INT); \
2851 EA = tcg_temp_new(); \
2852 gen_addr_reg_index(ctx, EA); \
2853 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2854 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2855 tcg_temp_free(EA); \
2856 }
2857
2858 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2859 static void glue(gen_, name##x)(DisasContext *ctx) \
2860 { \
2861 TCGv EA; \
2862 gen_set_access_type(ctx, ACCESS_INT); \
2863 EA = tcg_temp_new(); \
2864 gen_addr_reg_index(ctx, EA); \
2865 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2866 tcg_temp_free(EA); \
2867 }
2868 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2869 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2870
2871 #define GEN_LDS(name, ldop, op, type) \
2872 GEN_LD(name, ldop, op | 0x20, type); \
2873 GEN_LDU(name, ldop, op | 0x21, type); \
2874 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2875 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2876
2877 /* lbz lbzu lbzux lbzx */
2878 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2879 /* lha lhau lhaux lhax */
2880 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2881 /* lhz lhzu lhzux lhzx */
2882 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2883 /* lwz lwzu lwzux lwzx */
2884 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2885 #if defined(TARGET_PPC64)
2886 /* lwaux */
2887 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2888 /* lwax */
2889 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2890 /* ldux */
2891 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2892 /* ldx */
2893 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2894
2895 static void gen_ld(DisasContext *ctx)
2896 {
2897 TCGv EA;
2898 if (Rc(ctx->opcode)) {
2899 if (unlikely(rA(ctx->opcode) == 0 ||
2900 rA(ctx->opcode) == rD(ctx->opcode))) {
2901 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2902 return;
2903 }
2904 }
2905 gen_set_access_type(ctx, ACCESS_INT);
2906 EA = tcg_temp_new();
2907 gen_addr_imm_index(ctx, EA, 0x03);
2908 if (ctx->opcode & 0x02) {
2909 /* lwa (lwau is undefined) */
2910 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2911 } else {
2912 /* ld - ldu */
2913 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2914 }
2915 if (Rc(ctx->opcode))
2916 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2917 tcg_temp_free(EA);
2918 }
2919
2920 /* lq */
2921 static void gen_lq(DisasContext *ctx)
2922 {
2923 int ra, rd;
2924 TCGv EA;
2925
2926 /* lq is a legal user mode instruction starting in ISA 2.07 */
2927 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2928 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2929
2930 if (!legal_in_user_mode && ctx->pr) {
2931 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2932 return;
2933 }
2934
2935 if (!le_is_supported && ctx->le_mode) {
2936 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2937 return;
2938 }
2939
2940 ra = rA(ctx->opcode);
2941 rd = rD(ctx->opcode);
2942 if (unlikely((rd & 1) || rd == ra)) {
2943 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2944 return;
2945 }
2946
2947 gen_set_access_type(ctx, ACCESS_INT);
2948 EA = tcg_temp_new();
2949 gen_addr_imm_index(ctx, EA, 0x0F);
2950
2951 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2952 64-bit byteswap already. */
2953 if (unlikely(ctx->le_mode)) {
2954 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2955 gen_addr_add(ctx, EA, EA, 8);
2956 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2957 } else {
2958 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2959 gen_addr_add(ctx, EA, EA, 8);
2960 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2961 }
2962 tcg_temp_free(EA);
2963 }
2964 #endif
2965
2966 /*** Integer store ***/
2967 #define GEN_ST(name, stop, opc, type) \
2968 static void glue(gen_, name)(DisasContext *ctx) \
2969 { \
2970 TCGv EA; \
2971 gen_set_access_type(ctx, ACCESS_INT); \
2972 EA = tcg_temp_new(); \
2973 gen_addr_imm_index(ctx, EA, 0); \
2974 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2975 tcg_temp_free(EA); \
2976 }
2977
2978 #define GEN_STU(name, stop, opc, type) \
2979 static void glue(gen_, stop##u)(DisasContext *ctx) \
2980 { \
2981 TCGv EA; \
2982 if (unlikely(rA(ctx->opcode) == 0)) { \
2983 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2984 return; \
2985 } \
2986 gen_set_access_type(ctx, ACCESS_INT); \
2987 EA = tcg_temp_new(); \
2988 if (type == PPC_64B) \
2989 gen_addr_imm_index(ctx, EA, 0x03); \
2990 else \
2991 gen_addr_imm_index(ctx, EA, 0); \
2992 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2993 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2994 tcg_temp_free(EA); \
2995 }
2996
2997 #define GEN_STUX(name, stop, opc2, opc3, type) \
2998 static void glue(gen_, name##ux)(DisasContext *ctx) \
2999 { \
3000 TCGv EA; \
3001 if (unlikely(rA(ctx->opcode) == 0)) { \
3002 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3003 return; \
3004 } \
3005 gen_set_access_type(ctx, ACCESS_INT); \
3006 EA = tcg_temp_new(); \
3007 gen_addr_reg_index(ctx, EA); \
3008 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3009 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3010 tcg_temp_free(EA); \
3011 }
3012
3013 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
3014 static void glue(gen_, name##x)(DisasContext *ctx) \
3015 { \
3016 TCGv EA; \
3017 gen_set_access_type(ctx, ACCESS_INT); \
3018 EA = tcg_temp_new(); \
3019 gen_addr_reg_index(ctx, EA); \
3020 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3021 tcg_temp_free(EA); \
3022 }
3023 #define GEN_STX(name, stop, opc2, opc3, type) \
3024 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
3025
3026 #define GEN_STS(name, stop, op, type) \
3027 GEN_ST(name, stop, op | 0x20, type); \
3028 GEN_STU(name, stop, op | 0x21, type); \
3029 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3030 GEN_STX(name, stop, 0x17, op | 0x00, type)
3031
3032 /* stb stbu stbux stbx */
3033 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
3034 /* sth sthu sthux sthx */
3035 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
3036 /* stw stwu stwux stwx */
3037 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
3038 #if defined(TARGET_PPC64)
3039 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3040 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
3041
3042 static void gen_std(DisasContext *ctx)
3043 {
3044 int rs;
3045 TCGv EA;
3046
3047 rs = rS(ctx->opcode);
3048 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3049
3050 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3051 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3052
3053 if (!legal_in_user_mode && ctx->pr) {
3054 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3055 return;
3056 }
3057
3058 if (!le_is_supported && ctx->le_mode) {
3059 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3060 return;
3061 }
3062
3063 if (unlikely(rs & 1)) {
3064 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3065 return;
3066 }
3067 gen_set_access_type(ctx, ACCESS_INT);
3068 EA = tcg_temp_new();
3069 gen_addr_imm_index(ctx, EA, 0x03);
3070
3071 /* We only need to swap high and low halves. gen_qemu_st64 does
3072 necessary 64-bit byteswap already. */
3073 if (unlikely(ctx->le_mode)) {
3074 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3075 gen_addr_add(ctx, EA, EA, 8);
3076 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3077 } else {
3078 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3079 gen_addr_add(ctx, EA, EA, 8);
3080 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3081 }
3082 tcg_temp_free(EA);
3083 } else {
3084 /* std / stdu*/
3085 if (Rc(ctx->opcode)) {
3086 if (unlikely(rA(ctx->opcode) == 0)) {
3087 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3088 return;
3089 }
3090 }
3091 gen_set_access_type(ctx, ACCESS_INT);
3092 EA = tcg_temp_new();
3093 gen_addr_imm_index(ctx, EA, 0x03);
3094 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3095 if (Rc(ctx->opcode))
3096 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3097 tcg_temp_free(EA);
3098 }
3099 }
3100 #endif
3101 /*** Integer load and store with byte reverse ***/
3102
3103 /* lhbrx */
3104 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3105 {
3106 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3107 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3108 }
3109 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3110
3111 /* lwbrx */
3112 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3113 {
3114 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3115 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3116 }
3117 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3118
3119 #if defined(TARGET_PPC64)
3120 /* ldbrx */
3121 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3122 {
3123 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3124 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3125 }
3126 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3127 #endif /* TARGET_PPC64 */
3128
3129 /* sthbrx */
3130 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3131 {
3132 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3133 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3134 }
3135 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3136
3137 /* stwbrx */
3138 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3139 {
3140 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3141 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3142 }
3143 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3144
3145 #if defined(TARGET_PPC64)
3146 /* stdbrx */
3147 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3148 {
3149 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3150 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3151 }
3152 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3153 #endif /* TARGET_PPC64 */
3154
3155 /*** Integer load and store multiple ***/
3156
3157 /* lmw */
3158 static void gen_lmw(DisasContext *ctx)
3159 {
3160 TCGv t0;
3161 TCGv_i32 t1;
3162 gen_set_access_type(ctx, ACCESS_INT);
3163 /* NIP cannot be restored if the memory exception comes from an helper */
3164 gen_update_nip(ctx, ctx->nip - 4);
3165 t0 = tcg_temp_new();
3166 t1 = tcg_const_i32(rD(ctx->opcode));
3167 gen_addr_imm_index(ctx, t0, 0);
3168 gen_helper_lmw(cpu_env, t0, t1);
3169 tcg_temp_free(t0);
3170 tcg_temp_free_i32(t1);
3171 }
3172
3173 /* stmw */
3174 static void gen_stmw(DisasContext *ctx)
3175 {
3176 TCGv t0;
3177 TCGv_i32 t1;
3178 gen_set_access_type(ctx, ACCESS_INT);
3179 /* NIP cannot be restored if the memory exception comes from an helper */
3180 gen_update_nip(ctx, ctx->nip - 4);
3181 t0 = tcg_temp_new();
3182 t1 = tcg_const_i32(rS(ctx->opcode));
3183 gen_addr_imm_index(ctx, t0, 0);
3184 gen_helper_stmw(cpu_env, t0, t1);
3185 tcg_temp_free(t0);
3186 tcg_temp_free_i32(t1);
3187 }
3188
3189 /*** Integer load and store strings ***/
3190
3191 /* lswi */
3192 /* PowerPC32 specification says we must generate an exception if
3193 * rA is in the range of registers to be loaded.
3194 * In an other hand, IBM says this is valid, but rA won't be loaded.
3195 * For now, I'll follow the spec...
3196 */
3197 static void gen_lswi(DisasContext *ctx)
3198 {
3199 TCGv t0;
3200 TCGv_i32 t1, t2;
3201 int nb = NB(ctx->opcode);
3202 int start = rD(ctx->opcode);
3203 int ra = rA(ctx->opcode);
3204 int nr;
3205
3206 if (nb == 0)
3207 nb = 32;
3208 nr = (nb + 3) / 4;
3209 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
3210 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3211 return;
3212 }
3213 gen_set_access_type(ctx, ACCESS_INT);
3214 /* NIP cannot be restored if the memory exception comes from an helper */
3215 gen_update_nip(ctx, ctx->nip - 4);
3216 t0 = tcg_temp_new();
3217 gen_addr_register(ctx, t0);
3218 t1 = tcg_const_i32(nb);
3219 t2 = tcg_const_i32(start);
3220 gen_helper_lsw(cpu_env, t0, t1, t2);
3221 tcg_temp_free(t0);
3222 tcg_temp_free_i32(t1);
3223 tcg_temp_free_i32(t2);
3224 }
3225
3226 /* lswx */
3227 static void gen_lswx(DisasContext *ctx)
3228 {
3229 TCGv t0;
3230 TCGv_i32 t1, t2, t3;
3231 gen_set_access_type(ctx, ACCESS_INT);
3232 /* NIP cannot be restored if the memory exception comes from an helper */
3233 gen_update_nip(ctx, ctx->nip - 4);
3234 t0 = tcg_temp_new();
3235 gen_addr_reg_index(ctx, t0);
3236 t1 = tcg_const_i32(rD(ctx->opcode));
3237 t2 = tcg_const_i32(rA(ctx->opcode));
3238 t3 = tcg_const_i32(rB(ctx->opcode));
3239 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3240 tcg_temp_free(t0);
3241 tcg_temp_free_i32(t1);
3242 tcg_temp_free_i32(t2);
3243 tcg_temp_free_i32(t3);
3244 }
3245
3246 /* stswi */
3247 static void gen_stswi(DisasContext *ctx)
3248 {
3249 TCGv t0;
3250 TCGv_i32 t1, t2;
3251 int nb = NB(ctx->opcode);
3252 gen_set_access_type(ctx, ACCESS_INT);
3253 /* NIP cannot be restored if the memory exception comes from an helper */
3254 gen_update_nip(ctx, ctx->nip - 4);
3255 t0 = tcg_temp_new();
3256 gen_addr_register(ctx, t0);
3257 if (nb == 0)
3258 nb = 32;
3259 t1 = tcg_const_i32(nb);
3260 t2 = tcg_const_i32(rS(ctx->opcode));
3261 gen_helper_stsw(cpu_env, t0, t1, t2);
3262 tcg_temp_free(t0);
3263 tcg_temp_free_i32(t1);
3264 tcg_temp_free_i32(t2);
3265 }
3266
3267 /* stswx */
3268 static void gen_stswx(DisasContext *ctx)
3269 {
3270 TCGv t0;
3271 TCGv_i32 t1, t2;
3272 gen_set_access_type(ctx, ACCESS_INT);
3273 /* NIP cannot be restored if the memory exception comes from an helper */
3274 gen_update_nip(ctx, ctx->nip - 4);
3275 t0 = tcg_temp_new();
3276 gen_addr_reg_index(ctx, t0);
3277 t1 = tcg_temp_new_i32();
3278 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3279 tcg_gen_andi_i32(t1, t1, 0x7F);
3280 t2 = tcg_const_i32(rS(ctx->opcode));
3281 gen_helper_stsw(cpu_env, t0, t1, t2);
3282 tcg_temp_free(t0);
3283 tcg_temp_free_i32(t1);
3284 tcg_temp_free_i32(t2);
3285 }
3286
3287 /*** Memory synchronisation ***/
3288 /* eieio */
3289 static void gen_eieio(DisasContext *ctx)
3290 {
3291 }
3292
3293 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
3294 static inline void gen_check_tlb_flush(DisasContext *ctx)
3295 {
3296 TCGv_i32 t = tcg_temp_new_i32();
3297 TCGLabel *l = gen_new_label();
3298
3299 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3300 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3301 gen_helper_check_tlb_flush(cpu_env);
3302 gen_set_label(l);
3303 tcg_temp_free_i32(t);
3304 }
3305 #else
3306 static inline void gen_check_tlb_flush(DisasContext *ctx) { }
3307 #endif
3308
3309 /* isync */
3310 static void gen_isync(DisasContext *ctx)
3311 {
3312 /*
3313 * We need to check for a pending TLB flush. This can only happen in
3314 * kernel mode however so check MSR_PR
3315 */
3316 if (!ctx->pr) {
3317 gen_check_tlb_flush(ctx);
3318 }
3319 gen_stop_exception(ctx);
3320 }
3321
3322 #define LARX(name, len, loadop) \
3323 static void gen_##name(DisasContext *ctx) \
3324 { \
3325 TCGv t0; \
3326 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3327 gen_set_access_type(ctx, ACCESS_RES); \
3328 t0 = tcg_temp_local_new(); \
3329 gen_addr_reg_index(ctx, t0); \
3330 if ((len) > 1) { \
3331 gen_check_align(ctx, t0, (len)-1); \
3332 } \
3333 gen_qemu_##loadop(ctx, gpr, t0); \
3334 tcg_gen_mov_tl(cpu_reserve, t0); \
3335 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3336 tcg_temp_free(t0); \
3337 }
3338
3339 /* lwarx */
3340 LARX(lbarx, 1, ld8u);
3341 LARX(lharx, 2, ld16u);
3342 LARX(lwarx, 4, ld32u);
3343
3344
3345 #if defined(CONFIG_USER_ONLY)
3346 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3347 int reg, int size)
3348 {
3349 TCGv t0 = tcg_temp_new();
3350 uint32_t save_exception = ctx->exception;
3351
3352 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3353 tcg_gen_movi_tl(t0, (size << 5) | reg);
3354 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3355 tcg_temp_free(t0);
3356 gen_update_nip(ctx, ctx->nip-4);
3357 ctx->exception = POWERPC_EXCP_BRANCH;
3358 gen_exception(ctx, POWERPC_EXCP_STCX);
3359 ctx->exception = save_exception;
3360 }
3361 #else
3362 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3363 int reg, int size)
3364 {
3365 TCGLabel *l1;
3366
3367 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3368 l1 = gen_new_label();
3369 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3370 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3371 #if defined(TARGET_PPC64)
3372 if (size == 8) {
3373 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3374 } else
3375 #endif
3376 if (size == 4) {
3377 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3378 } else if (size == 2) {
3379 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3380 #if defined(TARGET_PPC64)
3381 } else if (size == 16) {
3382 TCGv gpr1, gpr2 , EA8;
3383 if (unlikely(ctx->le_mode)) {
3384 gpr1 = cpu_gpr[reg+1];
3385 gpr2 = cpu_gpr[reg];
3386 } else {
3387 gpr1 = cpu_gpr[reg];
3388 gpr2 = cpu_gpr[reg+1];
3389 }
3390 gen_qemu_st64(ctx, gpr1, EA);
3391 EA8 = tcg_temp_local_new();
3392 gen_addr_add(ctx, EA8, EA, 8);
3393 gen_qemu_st64(ctx, gpr2, EA8);
3394 tcg_temp_free(EA8);
3395 #endif
3396 } else {
3397 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3398 }
3399 gen_set_label(l1);
3400 tcg_gen_movi_tl(cpu_reserve, -1);
3401 }
3402 #endif
3403
3404 #define STCX(name, len) \
3405 static void gen_##name(DisasContext *ctx) \
3406 { \
3407 TCGv t0; \
3408 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3409 gen_inval_exception(ctx, \
3410 POWERPC_EXCP_INVAL_INVAL); \
3411 return; \
3412 } \
3413 gen_set_access_type(ctx, ACCESS_RES); \
3414 t0 = tcg_temp_local_new(); \
3415 gen_addr_reg_index(ctx, t0); \
3416 if (len > 1) { \
3417 gen_check_align(ctx, t0, (len)-1); \
3418 } \
3419 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3420 tcg_temp_free(t0); \
3421 }
3422
3423 STCX(stbcx_, 1);
3424 STCX(sthcx_, 2);
3425 STCX(stwcx_, 4);
3426
3427 #if defined(TARGET_PPC64)
3428 /* ldarx */
3429 LARX(ldarx, 8, ld64);
3430
3431 /* lqarx */
3432 static void gen_lqarx(DisasContext *ctx)
3433 {
3434 TCGv EA;
3435 int rd = rD(ctx->opcode);
3436 TCGv gpr1, gpr2;
3437
3438 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3439 (rd == rB(ctx->opcode)))) {
3440 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3441 return;
3442 }
3443
3444 gen_set_access_type(ctx, ACCESS_RES);
3445 EA = tcg_temp_local_new();
3446 gen_addr_reg_index(ctx, EA);
3447 gen_check_align(ctx, EA, 15);
3448 if (unlikely(ctx->le_mode)) {
3449 gpr1 = cpu_gpr[rd+1];
3450 gpr2 = cpu_gpr[rd];
3451 } else {
3452 gpr1 = cpu_gpr[rd];
3453 gpr2 = cpu_gpr[rd+1];
3454 }
3455 gen_qemu_ld64(ctx, gpr1, EA);
3456 tcg_gen_mov_tl(cpu_reserve, EA);
3457
3458 gen_addr_add(ctx, EA, EA, 8);
3459 gen_qemu_ld64(ctx, gpr2, EA);
3460
3461 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3462 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3463
3464 tcg_temp_free(EA);
3465 }
3466
3467 /* stdcx. */
3468 STCX(stdcx_, 8);
3469 STCX(stqcx_, 16);
3470 #endif /* defined(TARGET_PPC64) */
3471
3472 /* sync */
3473 static void gen_sync(DisasContext *ctx)
3474 {
3475 uint32_t l = (ctx->opcode >> 21) & 3;
3476
3477 /*
3478 * For l == 2, it's a ptesync, We need to check for a pending TLB flush.
3479 * This can only happen in kernel mode however so check MSR_PR as well.
3480 */
3481 if (l == 2 && !ctx->pr) {
3482 gen_check_tlb_flush(ctx);
3483 }
3484 }
3485
3486 /* wait */
3487 static void gen_wait(DisasContext *ctx)
3488 {
3489 TCGv_i32 t0 = tcg_temp_new_i32();
3490 tcg_gen_st_i32(t0, cpu_env,
3491 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3492 tcg_temp_free_i32(t0);
3493 /* Stop translation, as the CPU is supposed to sleep from now */
3494 gen_exception_err(ctx, EXCP_HLT, 1);
3495 }
3496
3497 /*** Floating-point load ***/
3498 #define GEN_LDF(name, ldop, opc, type) \
3499 static void glue(gen_, name)(DisasContext *ctx) \
3500 { \
3501 TCGv EA; \
3502 if (unlikely(!ctx->fpu_enabled)) { \
3503 gen_exception(ctx, POWERPC_EXCP_FPU); \
3504 return; \
3505 } \
3506 gen_set_access_type(ctx, ACCESS_FLOAT); \
3507 EA = tcg_temp_new(); \
3508 gen_addr_imm_index(ctx, EA, 0); \
3509 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3510 tcg_temp_free(EA); \
3511 }
3512
3513 #define GEN_LDUF(name, ldop, opc, type) \
3514 static void glue(gen_, name##u)(DisasContext *ctx) \
3515 { \
3516 TCGv EA; \
3517 if (unlikely(!ctx->fpu_enabled)) { \
3518 gen_exception(ctx, POWERPC_EXCP_FPU); \
3519 return; \
3520 } \
3521 if (unlikely(rA(ctx->opcode) == 0)) { \
3522 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3523 return; \
3524 } \
3525 gen_set_access_type(ctx, ACCESS_FLOAT); \
3526 EA = tcg_temp_new(); \
3527 gen_addr_imm_index(ctx, EA, 0); \
3528 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3529 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3530 tcg_temp_free(EA); \
3531 }
3532
3533 #define GEN_LDUXF(name, ldop, opc, type) \
3534 static void glue(gen_, name##ux)(DisasContext *ctx) \
3535 { \
3536 TCGv EA; \
3537 if (unlikely(!ctx->fpu_enabled)) { \
3538 gen_exception(ctx, POWERPC_EXCP_FPU); \
3539 return; \
3540 } \
3541 if (unlikely(rA(ctx->opcode) == 0)) { \
3542 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3543 return; \
3544 } \
3545 gen_set_access_type(ctx, ACCESS_FLOAT); \
3546 EA = tcg_temp_new(); \
3547 gen_addr_reg_index(ctx, EA); \
3548 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3549 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3550 tcg_temp_free(EA); \
3551 }
3552
3553 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3554 static void glue(gen_, name##x)(DisasContext *ctx) \
3555 { \
3556 TCGv EA; \
3557 if (unlikely(!ctx->fpu_enabled)) { \
3558 gen_exception(ctx, POWERPC_EXCP_FPU); \
3559 return; \
3560 } \
3561 gen_set_access_type(ctx, ACCESS_FLOAT); \
3562 EA = tcg_temp_new(); \
3563 gen_addr_reg_index(ctx, EA); \
3564 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3565 tcg_temp_free(EA); \
3566 }
3567
3568 #define GEN_LDFS(name, ldop, op, type) \
3569 GEN_LDF(name, ldop, op | 0x20, type); \
3570 GEN_LDUF(name, ldop, op | 0x21, type); \
3571 GEN_LDUXF(name, ldop, op | 0x01, type); \
3572 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3573
3574 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3575 {
3576 TCGv t0 = tcg_temp_new();
3577 TCGv_i32 t1 = tcg_temp_new_i32();
3578 gen_qemu_ld32u(ctx, t0, arg2);
3579 tcg_gen_trunc_tl_i32(t1, t0);
3580 tcg_temp_free(t0);
3581 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3582 tcg_temp_free_i32(t1);
3583 }
3584
3585 /* lfd lfdu lfdux lfdx */
3586 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3587 /* lfs lfsu lfsux lfsx */
3588 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3589
3590 /* lfdp */
3591 static void gen_lfdp(DisasContext *ctx)
3592 {
3593 TCGv EA;
3594 if (unlikely(!ctx->fpu_enabled)) {
3595 gen_exception(ctx, POWERPC_EXCP_FPU);
3596 return;
3597 }
3598 gen_set_access_type(ctx, ACCESS_FLOAT);
3599 EA = tcg_temp_new();
3600 gen_addr_imm_index(ctx, EA, 0);
3601 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3602 64-bit byteswap already. */
3603 if (unlikely(ctx->le_mode)) {
3604 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3605 tcg_gen_addi_tl(EA, EA, 8);
3606 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3607 } else {
3608 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3609 tcg_gen_addi_tl(EA, EA, 8);
3610 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3611 }
3612 tcg_temp_free(EA);
3613 }
3614
3615 /* lfdpx */
3616 static void gen_lfdpx(DisasContext *ctx)
3617 {
3618 TCGv EA;
3619 if (unlikely(!ctx->fpu_enabled)) {
3620 gen_exception(ctx, POWERPC_EXCP_FPU);
3621 return;
3622 }
3623 gen_set_access_type(ctx, ACCESS_FLOAT);
3624 EA = tcg_temp_new();
3625 gen_addr_reg_index(ctx, EA);
3626 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3627 64-bit byteswap already. */
3628 if (unlikely(ctx->le_mode)) {
3629 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3630 tcg_gen_addi_tl(EA, EA, 8);
3631 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3632 } else {
3633 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3634 tcg_gen_addi_tl(EA, EA, 8);
3635 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3636 }
3637 tcg_temp_free(EA);
3638 }
3639
3640 /* lfiwax */
3641 static void gen_lfiwax(DisasContext *ctx)
3642 {
3643 TCGv EA;
3644 TCGv t0;
3645 if (unlikely(!ctx->fpu_enabled)) {
3646 gen_exception(ctx, POWERPC_EXCP_FPU);
3647 return;
3648 }
3649 gen_set_access_type(ctx, ACCESS_FLOAT);
3650 EA = tcg_temp_new();
3651 t0 = tcg_temp_new();
3652 gen_addr_reg_index(ctx, EA);
3653 gen_qemu_ld32s(ctx, t0, EA);
3654 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3655 tcg_temp_free(EA);
3656 tcg_temp_free(t0);
3657 }
3658
3659 /* lfiwzx */
3660 static void gen_lfiwzx(DisasContext *ctx)
3661 {
3662 TCGv EA;
3663 if (unlikely(!ctx->fpu_enabled)) {
3664 gen_exception(ctx, POWERPC_EXCP_FPU);
3665 return;
3666 }
3667 gen_set_access_type(ctx, ACCESS_FLOAT);
3668 EA = tcg_temp_new();
3669 gen_addr_reg_index(ctx, EA);
3670 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3671 tcg_temp_free(EA);
3672 }
3673 /*** Floating-point store ***/
3674 #define GEN_STF(name, stop, opc, type) \
3675 static void glue(gen_, name)(DisasContext *ctx) \
3676 { \
3677 TCGv EA; \
3678 if (unlikely(!ctx->fpu_enabled)) { \
3679 gen_exception(ctx, POWERPC_EXCP_FPU); \
3680 return; \
3681 } \
3682 gen_set_access_type(ctx, ACCESS_FLOAT); \
3683 EA = tcg_temp_new(); \
3684 gen_addr_imm_index(ctx, EA, 0); \
3685 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3686 tcg_temp_free(EA); \
3687 }
3688
3689 #define GEN_STUF(name, stop, opc, type) \
3690 static void glue(gen_, name##u)(DisasContext *ctx) \
3691 { \
3692 TCGv EA; \
3693 if (unlikely(!ctx->fpu_enabled)) { \
3694 gen_exception(ctx, POWERPC_EXCP_FPU); \
3695 return; \
3696 } \
3697 if (unlikely(rA(ctx->opcode) == 0)) { \
3698 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3699 return; \
3700 } \
3701 gen_set_access_type(ctx, ACCESS_FLOAT); \
3702 EA = tcg_temp_new(); \
3703 gen_addr_imm_index(ctx, EA, 0); \
3704 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3705 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3706 tcg_temp_free(EA); \
3707 }
3708
3709 #define GEN_STUXF(name, stop, opc, type) \
3710 static void glue(gen_, name##ux)(DisasContext *ctx) \
3711 { \
3712 TCGv EA; \
3713 if (unlikely(!ctx->fpu_enabled)) { \
3714 gen_exception(ctx, POWERPC_EXCP_FPU); \
3715 return; \
3716 } \
3717 if (unlikely(rA(ctx->opcode) == 0)) { \
3718 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3719 return; \
3720 } \
3721 gen_set_access_type(ctx, ACCESS_FLOAT); \
3722 EA = tcg_temp_new(); \
3723 gen_addr_reg_index(ctx, EA); \
3724 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3725 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3726 tcg_temp_free(EA); \
3727 }
3728
3729 #define GEN_STXF(name, stop, opc2, opc3, type) \
3730 static void glue(gen_, name##x)(DisasContext *ctx) \
3731 { \
3732 TCGv EA; \
3733 if (unlikely(!ctx->fpu_enabled)) { \
3734 gen_exception(ctx, POWERPC_EXCP_FPU); \
3735 return; \
3736 } \
3737 gen_set_access_type(ctx, ACCESS_FLOAT); \
3738 EA = tcg_temp_new(); \
3739 gen_addr_reg_index(ctx, EA); \
3740 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3741 tcg_temp_free(EA); \
3742 }
3743
3744 #define GEN_STFS(name, stop, op, type) \
3745 GEN_STF(name, stop, op | 0x20, type); \
3746 GEN_STUF(name, stop, op | 0x21, type); \
3747 GEN_STUXF(name, stop, op | 0x01, type); \
3748 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3749
3750 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3751 {
3752 TCGv_i32 t0 = tcg_temp_new_i32();
3753 TCGv t1 = tcg_temp_new();
3754 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3755 tcg_gen_extu_i32_tl(t1, t0);
3756 tcg_temp_free_i32(t0);
3757 gen_qemu_st32(ctx, t1, arg2);
3758 tcg_temp_free(t1);
3759 }
3760
3761 /* stfd stfdu stfdux stfdx */
3762 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3763 /* stfs stfsu stfsux stfsx */
3764 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3765
3766 /* stfdp */
3767 static void gen_stfdp(DisasContext *ctx)
3768 {
3769 TCGv EA;
3770 if (unlikely(!ctx->fpu_enabled)) {
3771 gen_exception(ctx, POWERPC_EXCP_FPU);
3772 return;
3773 }
3774 gen_set_access_type(ctx, ACCESS_FLOAT);
3775 EA = tcg_temp_new();
3776 gen_addr_imm_index(ctx, EA, 0);
3777 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3778 64-bit byteswap already. */
3779 if (unlikely(ctx->le_mode)) {
3780 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3781 tcg_gen_addi_tl(EA, EA, 8);
3782 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3783 } else {
3784 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3785 tcg_gen_addi_tl(EA, EA, 8);
3786 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3787 }
3788 tcg_temp_free(EA);
3789 }
3790
3791 /* stfdpx */
3792 static void gen_stfdpx(DisasContext *ctx)
3793 {
3794 TCGv EA;
3795 if (unlikely(!ctx->fpu_enabled)) {
3796 gen_exception(ctx, POWERPC_EXCP_FPU);
3797 return;
3798 }
3799 gen_set_access_type(ctx, ACCESS_FLOAT);
3800 EA = tcg_temp_new();
3801 gen_addr_reg_index(ctx, EA);
3802 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3803 64-bit byteswap already. */
3804 if (unlikely(ctx->le_mode)) {
3805 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3806 tcg_gen_addi_tl(EA, EA, 8);
3807 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3808 } else {
3809 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3810 tcg_gen_addi_tl(EA, EA, 8);
3811 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3812 }
3813 tcg_temp_free(EA);
3814 }
3815
3816 /* Optional: */
3817 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3818 {
3819 TCGv t0 = tcg_temp_new();
3820 tcg_gen_trunc_i64_tl(t0, arg1),
3821 gen_qemu_st32(ctx, t0, arg2);
3822 tcg_temp_free(t0);
3823 }
3824 /* stfiwx */
3825 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3826
3827 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3828 {
3829 #if defined(TARGET_PPC64)
3830 if (ctx->has_cfar)
3831 tcg_gen_movi_tl(cpu_cfar, nip);
3832 #endif
3833 }
3834
3835 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3836 {
3837 if (unlikely(ctx->singlestep_enabled)) {
3838 return false;
3839 }
3840
3841 #ifndef CONFIG_USER_ONLY
3842 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3843 #else
3844 return true;
3845 #endif
3846 }
3847
3848 /*** Branch ***/
3849 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3850 {
3851 if (NARROW_MODE(ctx)) {
3852 dest = (uint32_t) dest;
3853 }
3854 if (use_goto_tb(ctx, dest)) {
3855 tcg_gen_goto_tb(n);
3856 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3857 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3858 } else {
3859 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3860 if (unlikely(ctx->singlestep_enabled)) {
3861 if ((ctx->singlestep_enabled &
3862 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3863 (ctx->exception == POWERPC_EXCP_BRANCH ||
3864 ctx->exception == POWERPC_EXCP_TRACE)) {
3865 target_ulong tmp = ctx->nip;
3866 ctx->nip = dest;
3867 gen_exception(ctx, POWERPC_EXCP_TRACE);
3868 ctx->nip = tmp;
3869 }
3870 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3871 gen_debug_exception(ctx);
3872 }
3873 }
3874 tcg_gen_exit_tb(0);
3875 }
3876 }
3877
3878 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3879 {
3880 if (NARROW_MODE(ctx)) {
3881 nip = (uint32_t)nip;
3882 }
3883 tcg_gen_movi_tl(cpu_lr, nip);
3884 }
3885
3886 /* b ba bl bla */
3887 static void gen_b(DisasContext *ctx)
3888 {
3889 target_ulong li, target;
3890
3891 ctx->exception = POWERPC_EXCP_BRANCH;
3892 /* sign extend LI */
3893 li = LI(ctx->opcode);
3894 li = (li ^ 0x02000000) - 0x02000000;
3895 if (likely(AA(ctx->opcode) == 0)) {
3896 target = ctx->nip + li - 4;
3897 } else {
3898 target = li;
3899 }
3900 if (LK(ctx->opcode)) {
3901 gen_setlr(ctx, ctx->nip);
3902 }
3903 gen_update_cfar(ctx, ctx->nip);
3904 gen_goto_tb(ctx, 0, target);
3905 }
3906
3907 #define BCOND_IM 0
3908 #define BCOND_LR 1
3909 #define BCOND_CTR 2
3910 #define BCOND_TAR 3
3911
3912 static inline void gen_bcond(DisasContext *ctx, int type)
3913 {
3914 uint32_t bo = BO(ctx->opcode);
3915 TCGLabel *l1;
3916 TCGv target;
3917
3918 ctx->exception = POWERPC_EXCP_BRANCH;
3919 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3920 target = tcg_temp_local_new();
3921 if (type == BCOND_CTR)
3922 tcg_gen_mov_tl(target, cpu_ctr);
3923 else if (type == BCOND_TAR)
3924 gen_load_spr(target, SPR_TAR);
3925 else
3926 tcg_gen_mov_tl(target, cpu_lr);
3927 } else {
3928 TCGV_UNUSED(target);
3929 }
3930 if (LK(ctx->opcode))
3931 gen_setlr(ctx, ctx->nip);
3932 l1 = gen_new_label();
3933 if ((bo & 0x4) == 0) {
3934 /* Decrement and test CTR */
3935 TCGv temp = tcg_temp_new();
3936 if (unlikely(type == BCOND_CTR)) {
3937 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3938 return;
3939 }
3940 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3941 if (NARROW_MODE(ctx)) {
3942 tcg_gen_ext32u_tl(temp, cpu_ctr);
3943 } else {
3944 tcg_gen_mov_tl(temp, cpu_ctr);
3945 }
3946 if (bo & 0x2) {
3947 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3948 } else {
3949 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3950 }
3951 tcg_temp_free(temp);
3952 }
3953 if ((bo & 0x10) == 0) {
3954 /* Test CR */
3955 uint32_t bi = BI(ctx->opcode);
3956 uint32_t mask = 0x08 >> (bi & 0x03);
3957 TCGv_i32 temp = tcg_temp_new_i32();
3958
3959 if (bo & 0x8) {
3960 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3961 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3962 } else {
3963 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3964 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3965 }
3966 tcg_temp_free_i32(temp);
3967 }
3968 gen_update_cfar(ctx, ctx->nip);
3969 if (type == BCOND_IM) {
3970 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3971 if (likely(AA(ctx->opcode) == 0)) {
3972 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3973 } else {
3974 gen_goto_tb(ctx, 0, li);
3975 }
3976 gen_set_label(l1);
3977 gen_goto_tb(ctx, 1, ctx->nip);
3978 } else {
3979 if (NARROW_MODE(ctx)) {
3980 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3981 } else {
3982 tcg_gen_andi_tl(cpu_nip, target, ~3);
3983 }
3984 tcg_gen_exit_tb(0);
3985 gen_set_label(l1);
3986 gen_update_nip(ctx, ctx->nip);
3987 tcg_gen_exit_tb(0);
3988 }
3989 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3990 tcg_temp_free(target);
3991 }
3992 }
3993
3994 static void gen_bc(DisasContext *ctx)
3995 {
3996 gen_bcond(ctx, BCOND_IM);
3997 }
3998
3999 static void gen_bcctr(DisasContext *ctx)
4000 {
4001 gen_bcond(ctx, BCOND_CTR);
4002 }
4003
4004 static void gen_bclr(DisasContext *ctx)
4005 {
4006 gen_bcond(ctx, BCOND_LR);
4007 }
4008
4009 static void gen_bctar(DisasContext *ctx)
4010 {
4011 gen_bcond(ctx, BCOND_TAR);
4012 }
4013
4014 /*** Condition register logical ***/
4015 #define GEN_CRLOGIC(name, tcg_op, opc) \
4016 static void glue(gen_, name)(DisasContext *ctx) \
4017 { \
4018 uint8_t bitmask; \
4019 int sh; \
4020 TCGv_i32 t0, t1; \
4021 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
4022 t0 = tcg_temp_new_i32(); \
4023 if (sh > 0) \
4024 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
4025 else if (sh < 0) \
4026 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
4027 else \
4028 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
4029 t1 = tcg_temp_new_i32(); \
4030 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
4031 if (sh > 0) \
4032 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
4033 else if (sh < 0) \
4034 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
4035 else \
4036 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4037 tcg_op(t0, t0, t1); \
4038 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
4039 tcg_gen_andi_i32(t0, t0, bitmask); \
4040 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4041 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
4042 tcg_temp_free_i32(t0); \
4043 tcg_temp_free_i32(t1); \
4044 }
4045
4046 /* crand */
4047 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
4048 /* crandc */
4049 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
4050 /* creqv */
4051 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
4052 /* crnand */
4053 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
4054 /* crnor */
4055 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
4056 /* cror */
4057 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
4058 /* crorc */
4059 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
4060 /* crxor */
4061 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
4062
4063 /* mcrf */
4064 static void gen_mcrf(DisasContext *ctx)
4065 {
4066 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
4067 }
4068
4069 /*** System linkage ***/
4070
4071 /* rfi (supervisor only) */
4072 static void gen_rfi(DisasContext *ctx)
4073 {
4074 #if defined(CONFIG_USER_ONLY)
4075 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4076 #else
4077 /* Restore CPU state */
4078 if (unlikely(ctx->pr)) {
4079 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4080 return;
4081 }
4082 gen_update_cfar(ctx, ctx->nip);
4083 gen_helper_rfi(cpu_env);
4084 gen_sync_exception(ctx);
4085 #endif
4086 }
4087
4088 #if defined(TARGET_PPC64)
4089 static void gen_rfid(DisasContext *ctx)
4090 {
4091 #if defined(CONFIG_USER_ONLY)
4092 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4093 #else
4094 /* Restore CPU state */
4095 if (unlikely(ctx->pr)) {
4096 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4097 return;
4098 }
4099 gen_update_cfar(ctx, ctx->nip);
4100 gen_helper_rfid(cpu_env);
4101 gen_sync_exception(ctx);
4102 #endif
4103 }
4104
4105 static void gen_hrfid(DisasContext *ctx)
4106 {
4107 #if defined(CONFIG_USER_ONLY)
4108 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4109 #else
4110 /* Restore CPU state */
4111 if (unlikely(!ctx->hv)) {
4112 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4113 return;
4114 }
4115 gen_helper_hrfid(cpu_env);
4116 gen_sync_exception(ctx);
4117 #endif
4118 }
4119 #endif
4120
4121 /* sc */
4122 #if defined(CONFIG_USER_ONLY)
4123 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4124 #else
4125 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4126 #endif
4127 static void gen_sc(DisasContext *ctx)
4128 {
4129 uint32_t lev;
4130
4131 lev = (ctx->opcode >> 5) & 0x7F;
4132 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4133 }
4134
4135 /*** Trap ***/
4136
4137 /* tw */
4138 static void gen_tw(DisasContext *ctx)
4139 {
4140 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4141 /* Update the nip since this might generate a trap exception */
4142 gen_update_nip(ctx, ctx->nip);
4143 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4144 t0);
4145 tcg_temp_free_i32(t0);
4146 }
4147
4148 /* twi */
4149 static void gen_twi(DisasContext *ctx)
4150 {
4151 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4152 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4153 /* Update the nip since this might generate a trap exception */
4154 gen_update_nip(ctx, ctx->nip);
4155 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4156 tcg_temp_free(t0);
4157 tcg_temp_free_i32(t1);
4158 }
4159
4160 #if defined(TARGET_PPC64)
4161 /* td */
4162 static void gen_td(DisasContext *ctx)
4163 {
4164 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4165 /* Update the nip since this might generate a trap exception */
4166 gen_update_nip(ctx, ctx->nip);
4167 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4168 t0);
4169 tcg_temp_free_i32(t0);
4170 }
4171
4172 /* tdi */
4173 static void gen_tdi(DisasContext *ctx)
4174 {
4175 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4176 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4177 /* Update the nip since this might generate a trap exception */
4178 gen_update_nip(ctx, ctx->nip);
4179 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4180 tcg_temp_free(t0);
4181 tcg_temp_free_i32(t1);
4182 }
4183 #endif
4184
4185 /*** Processor control ***/
4186
4187 static void gen_read_xer(TCGv dst)
4188 {
4189 TCGv t0 = tcg_temp_new();
4190 TCGv t1 = tcg_temp_new();
4191 TCGv t2 = tcg_temp_new();
4192 tcg_gen_mov_tl(dst, cpu_xer);
4193 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4194 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4195 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4196 tcg_gen_or_tl(t0, t0, t1);
4197 tcg_gen_or_tl(dst, dst, t2);
4198 tcg_gen_or_tl(dst, dst, t0);
4199 tcg_temp_free(t0);
4200 tcg_temp_free(t1);
4201 tcg_temp_free(t2);
4202 }
4203
4204 static void gen_write_xer(TCGv src)
4205 {
4206 tcg_gen_andi_tl(cpu_xer, src,
4207 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4208 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4209 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4210 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4211 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4212 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4213 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4214 }
4215
4216 /* mcrxr */
4217 static void gen_mcrxr(DisasContext *ctx)
4218 {
4219 TCGv_i32 t0 = tcg_temp_new_i32();
4220 TCGv_i32 t1 = tcg_temp_new_i32();
4221 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4222
4223 tcg_gen_trunc_tl_i32(t0, cpu_so);
4224 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4225 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4226 tcg_gen_shli_i32(t0, t0, 3);
4227 tcg_gen_shli_i32(t1, t1, 2);
4228 tcg_gen_shli_i32(dst, dst, 1);
4229 tcg_gen_or_i32(dst, dst, t0);
4230 tcg_gen_or_i32(dst, dst, t1);
4231 tcg_temp_free_i32(t0);
4232 tcg_temp_free_i32(t1);
4233
4234 tcg_gen_movi_tl(cpu_so, 0);
4235 tcg_gen_movi_tl(cpu_ov, 0);
4236 tcg_gen_movi_tl(cpu_ca, 0);
4237 }
4238
4239 /* mfcr mfocrf */
4240 static void gen_mfcr(DisasContext *ctx)
4241 {
4242 uint32_t crm, crn;
4243
4244 if (likely(ctx->opcode & 0x00100000)) {
4245 crm = CRM(ctx->opcode);
4246 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4247 crn = ctz32 (crm);
4248 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4249 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4250 cpu_gpr[rD(ctx->opcode)], crn * 4);
4251 }
4252 } else {
4253 TCGv_i32 t0 = tcg_temp_new_i32();
4254 tcg_gen_mov_i32(t0, cpu_crf[0]);
4255 tcg_gen_shli_i32(t0, t0, 4);
4256 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4257 tcg_gen_shli_i32(t0, t0, 4);
4258 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4259 tcg_gen_shli_i32(t0, t0, 4);
4260 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4261 tcg_gen_shli_i32(t0, t0, 4);
4262 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4263 tcg_gen_shli_i32(t0, t0, 4);
4264 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4265 tcg_gen_shli_i32(t0, t0, 4);
4266 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4267 tcg_gen_shli_i32(t0, t0, 4);
4268 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4269 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4270 tcg_temp_free_i32(t0);
4271 }
4272 }
4273
4274 /* mfmsr */
4275 static void gen_mfmsr(DisasContext *ctx)
4276 {
4277 #if defined(CONFIG_USER_ONLY)
4278 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4279 #else
4280 if (unlikely(ctx->pr)) {
4281 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4282 return;
4283 }
4284 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4285 #endif
4286 }
4287
4288 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
4289 {
4290 #if 0
4291 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4292 printf("ERROR: try to access SPR %d !\n", sprn);
4293 #endif
4294 }
4295 #define SPR_NOACCESS (&spr_noaccess)
4296
4297 /* mfspr */
4298 static inline void gen_op_mfspr(DisasContext *ctx)
4299 {
4300 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4301 uint32_t sprn = SPR(ctx->opcode);
4302
4303 #if defined(CONFIG_USER_ONLY)
4304 read_cb = ctx->spr_cb[sprn].uea_read;
4305 #else
4306 if (ctx->pr) {
4307 read_cb = ctx->spr_cb[sprn].uea_read;
4308 } else if (ctx->hv) {
4309 read_cb = ctx->spr_cb[sprn].hea_read;
4310 } else {
4311 read_cb = ctx->spr_cb[sprn].oea_read;
4312 }
4313 #endif
4314 if (likely(read_cb != NULL)) {
4315 if (likely(read_cb != SPR_NOACCESS)) {
4316 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4317 } else {
4318 /* Privilege exception */
4319 /* This is a hack to avoid warnings when running Linux:
4320 * this OS breaks the PowerPC virtualisation model,
4321 * allowing userland application to read the PVR
4322 */
4323 if (sprn != SPR_PVR) {
4324 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
4325 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4326 if (qemu_log_separate()) {
4327 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4328 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4329 }
4330 }
4331 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4332 }
4333 } else {
4334 /* Not defined */
4335 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
4336 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4337 if (qemu_log_separate()) {
4338 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4339 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4340 }
4341 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4342 }
4343 }
4344
4345 static void gen_mfspr(DisasContext *ctx)
4346 {
4347 gen_op_mfspr(ctx);
4348 }
4349
4350 /* mftb */
4351 static void gen_mftb(DisasContext *ctx)
4352 {
4353 gen_op_mfspr(ctx);
4354 }
4355
4356 /* mtcrf mtocrf*/
4357 static void gen_mtcrf(DisasContext *ctx)
4358 {
4359 uint32_t crm, crn;
4360
4361 crm = CRM(ctx->opcode);
4362 if (likely((ctx->opcode & 0x00100000))) {
4363 if (crm && ((crm & (crm - 1)) == 0)) {
4364 TCGv_i32 temp = tcg_temp_new_i32();
4365 crn = ctz32 (crm);
4366 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4367 tcg_gen_shri_i32(temp, temp, crn * 4);
4368 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4369 tcg_temp_free_i32(temp);
4370 }
4371 } else {
4372 TCGv_i32 temp = tcg_temp_new_i32();
4373 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4374 for (crn = 0 ; crn < 8 ; crn++) {
4375 if (crm & (1 << crn)) {
4376 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4377 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4378 }
4379 }
4380 tcg_temp_free_i32(temp);
4381 }
4382 }
4383
4384 /* mtmsr */
4385 #if defined(TARGET_PPC64)
4386 static void gen_mtmsrd(DisasContext *ctx)
4387 {
4388 #if defined(CONFIG_USER_ONLY)
4389 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4390 #else
4391 if (unlikely(ctx->pr)) {
4392 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4393 return;
4394 }
4395 if (ctx->opcode & 0x00010000) {
4396 /* Special form that does not need any synchronisation */
4397 TCGv t0 = tcg_temp_new();
4398 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4399 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4400 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4401 tcg_temp_free(t0);
4402 } else {
4403 /* XXX: we need to update nip before the store
4404 * if we enter power saving mode, we will exit the loop
4405 * directly from ppc_store_msr
4406 */
4407 gen_update_nip(ctx, ctx->nip);
4408 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4409 /* Must stop the translation as machine state (may have) changed */
4410 /* Note that mtmsr is not always defined as context-synchronizing */
4411 gen_stop_exception(ctx);
4412 }
4413 #endif
4414 }
4415 #endif
4416
4417 static void gen_mtmsr(DisasContext *ctx)
4418 {
4419 #if defined(CONFIG_USER_ONLY)
4420 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4421 #else
4422 if (unlikely(ctx->pr)) {
4423 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4424 return;
4425 }
4426 if (ctx->opcode & 0x00010000) {
4427 /* Special form that does not need any synchronisation */
4428 TCGv t0 = tcg_temp_new();
4429 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4430 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4431 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4432 tcg_temp_free(t0);
4433 } else {
4434 TCGv msr = tcg_temp_new();
4435
4436 /* XXX: we need to update nip before the store
4437 * if we enter power saving mode, we will exit the loop
4438 * directly from ppc_store_msr
4439 */
4440 gen_update_nip(ctx, ctx->nip);
4441 #if defined(TARGET_PPC64)
4442 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4443 #else
4444 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4445 #endif
4446 gen_helper_store_msr(cpu_env, msr);
4447 tcg_temp_free(msr);
4448 /* Must stop the translation as machine state (may have) changed */
4449 /* Note that mtmsr is not always defined as context-synchronizing */
4450 gen_stop_exception(ctx);
4451 }
4452 #endif
4453 }
4454
4455 /* mtspr */
4456 static void gen_mtspr(DisasContext *ctx)
4457 {
4458 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4459 uint32_t sprn = SPR(ctx->opcode);
4460
4461 #if defined(CONFIG_USER_ONLY)
4462 write_cb = ctx->spr_cb[sprn].uea_write;
4463 #else
4464 if (ctx->pr) {
4465 write_cb = ctx->spr_cb[sprn].uea_write;
4466 } else if (ctx->hv) {
4467 write_cb = ctx->spr_cb[sprn].hea_write;
4468 } else {
4469 write_cb = ctx->spr_cb[sprn].oea_write;
4470 }
4471 #endif
4472 if (likely(write_cb != NULL)) {
4473 if (likely(write_cb != SPR_NOACCESS)) {
4474 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4475 } else {
4476 /* Privilege exception */
4477 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4478 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4479 if (qemu_log_separate()) {
4480 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4481 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4482 }
4483 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4484 }
4485 } else {
4486 /* Not defined */
4487 if (qemu_log_separate()) {
4488 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4489 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4490 }
4491 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4492 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4493 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4494 }
4495 }
4496
4497 /*** Cache management ***/
4498
4499 /* dcbf */
4500 static void gen_dcbf(DisasContext *ctx)
4501 {
4502 /* XXX: specification says this is treated as a load by the MMU */
4503 TCGv t0;
4504 gen_set_access_type(ctx, ACCESS_CACHE);
4505 t0 = tcg_temp_new();
4506 gen_addr_reg_index(ctx, t0);
4507 gen_qemu_ld8u(ctx, t0, t0);
4508 tcg_temp_free(t0);
4509 }
4510
4511 /* dcbi (Supervisor only) */
4512 static void gen_dcbi(DisasContext *ctx)
4513 {
4514 #if defined(CONFIG_USER_ONLY)
4515 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4516 #else
4517 TCGv EA, val;
4518 if (unlikely(ctx->pr)) {
4519 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4520 return;
4521 }
4522 EA = tcg_temp_new();
4523 gen_set_access_type(ctx, ACCESS_CACHE);
4524 gen_addr_reg_index(ctx, EA);
4525 val = tcg_temp_new();
4526 /* XXX: specification says this should be treated as a store by the MMU */
4527 gen_qemu_ld8u(ctx, val, EA);
4528 gen_qemu_st8(ctx, val, EA);
4529 tcg_temp_free(val);
4530 tcg_temp_free(EA);
4531 #endif
4532 }
4533
4534 /* dcdst */
4535 static void gen_dcbst(DisasContext *ctx)
4536 {
4537 /* XXX: specification say this is treated as a load by the MMU */
4538 TCGv t0;
4539 gen_set_access_type(ctx, ACCESS_CACHE);
4540 t0 = tcg_temp_new();
4541 gen_addr_reg_index(ctx, t0);
4542 gen_qemu_ld8u(ctx, t0, t0);
4543 tcg_temp_free(t0);
4544 }
4545
4546 /* dcbt */
4547 static void gen_dcbt(DisasContext *ctx)
4548 {
4549 /* interpreted as no-op */
4550 /* XXX: specification say this is treated as a load by the MMU
4551 * but does not generate any exception
4552 */
4553 }
4554
4555 /* dcbtst */
4556 static void gen_dcbtst(DisasContext *ctx)
4557 {
4558 /* interpreted as no-op */
4559 /* XXX: specification say this is treated as a load by the MMU
4560 * but does not generate any exception
4561 */
4562 }
4563
4564 /* dcbtls */
4565 static void gen_dcbtls(DisasContext *ctx)
4566 {
4567 /* Always fails locking the cache */
4568 TCGv t0 = tcg_temp_new();
4569 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4570 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4571 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4572 tcg_temp_free(t0);
4573 }
4574
4575 /* dcbz */
4576 static void gen_dcbz(DisasContext *ctx)
4577 {
4578 TCGv tcgv_addr;
4579 TCGv_i32 tcgv_is_dcbzl;
4580 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4581
4582 gen_set_access_type(ctx, ACCESS_CACHE);
4583 /* NIP cannot be restored if the memory exception comes from an helper */
4584 gen_update_nip(ctx, ctx->nip - 4);
4585 tcgv_addr = tcg_temp_new();
4586 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4587
4588 gen_addr_reg_index(ctx, tcgv_addr);
4589 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4590
4591 tcg_temp_free(tcgv_addr);
4592 tcg_temp_free_i32(tcgv_is_dcbzl);
4593 }
4594
4595 /* dst / dstt */
4596 static void gen_dst(DisasContext *ctx)
4597 {
4598 if (rA(ctx->opcode) == 0) {
4599 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4600 } else {
4601 /* interpreted as no-op */
4602 }
4603 }
4604
4605 /* dstst /dststt */
4606 static void gen_dstst(DisasContext *ctx)
4607 {
4608 if (rA(ctx->opcode) == 0) {
4609 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4610 } else {
4611 /* interpreted as no-op */
4612 }
4613
4614 }
4615
4616 /* dss / dssall */
4617 static void gen_dss(DisasContext *ctx)
4618 {
4619 /* interpreted as no-op */
4620 }
4621
4622 /* icbi */
4623 static void gen_icbi(DisasContext *ctx)
4624 {
4625 TCGv t0;
4626 gen_set_access_type(ctx, ACCESS_CACHE);
4627 /* NIP cannot be restored if the memory exception comes from an helper */
4628 gen_update_nip(ctx, ctx->nip - 4);
4629 t0 = tcg_temp_new();
4630 gen_addr_reg_index(ctx, t0);
4631 gen_helper_icbi(cpu_env, t0);
4632 tcg_temp_free(t0);
4633 }
4634
4635 /* Optional: */
4636 /* dcba */
4637 static void gen_dcba(DisasContext *ctx)
4638 {
4639 /* interpreted as no-op */
4640 /* XXX: specification say this is treated as a store by the MMU
4641 * but does not generate any exception
4642 */
4643 }
4644
4645 /*** Segment register manipulation ***/
4646 /* Supervisor only: */
4647
4648 /* mfsr */
4649 static void gen_mfsr(DisasContext *ctx)
4650 {
4651 #if defined(CONFIG_USER_ONLY)
4652 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4653 #else
4654 TCGv t0;
4655 if (unlikely(ctx->pr)) {
4656 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4657 return;
4658 }
4659 t0 = tcg_const_tl(SR(ctx->opcode));
4660 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4661 tcg_temp_free(t0);
4662 #endif
4663 }
4664
4665 /* mfsrin */
4666 static void gen_mfsrin(DisasContext *ctx)
4667 {
4668 #if defined(CONFIG_USER_ONLY)
4669 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4670 #else
4671 TCGv t0;
4672 if (unlikely(ctx->pr)) {
4673 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4674 return;
4675 }
4676 t0 = tcg_temp_new();
4677 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4678 tcg_gen_andi_tl(t0, t0, 0xF);
4679 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4680 tcg_temp_free(t0);
4681 #endif
4682 }
4683
4684 /* mtsr */
4685 static void gen_mtsr(DisasContext *ctx)
4686 {
4687 #if defined(CONFIG_USER_ONLY)
4688 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4689 #else
4690 TCGv t0;
4691 if (unlikely(ctx->pr)) {
4692 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4693 return;
4694 }
4695 t0 = tcg_const_tl(SR(ctx->opcode));
4696 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4697 tcg_temp_free(t0);
4698 #endif
4699 }
4700
4701 /* mtsrin */
4702 static void gen_mtsrin(DisasContext *ctx)
4703 {
4704 #if defined(CONFIG_USER_ONLY)
4705 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4706 #else
4707 TCGv t0;
4708 if (unlikely(ctx->pr)) {
4709 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4710 return;
4711 }
4712 t0 = tcg_temp_new();
4713 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4714 tcg_gen_andi_tl(t0, t0, 0xF);
4715 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4716 tcg_temp_free(t0);
4717 #endif
4718 }
4719
4720 #if defined(TARGET_PPC64)
4721 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4722
4723 /* mfsr */
4724 static void gen_mfsr_64b(DisasContext *ctx)
4725 {
4726 #if defined(CONFIG_USER_ONLY)
4727 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4728 #else
4729 TCGv t0;
4730 if (unlikely(ctx->pr)) {
4731 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4732 return;
4733 }
4734 t0 = tcg_const_tl(SR(ctx->opcode));
4735 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4736 tcg_temp_free(t0);
4737 #endif
4738 }
4739
4740 /* mfsrin */
4741 static void gen_mfsrin_64b(DisasContext *ctx)
4742 {
4743 #if defined(CONFIG_USER_ONLY)
4744 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4745 #else
4746 TCGv t0;
4747 if (unlikely(ctx->pr)) {
4748 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4749 return;
4750 }
4751 t0 = tcg_temp_new();
4752 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4753 tcg_gen_andi_tl(t0, t0, 0xF);
4754 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4755 tcg_temp_free(t0);
4756 #endif
4757 }
4758
4759 /* mtsr */
4760 static void gen_mtsr_64b(DisasContext *ctx)
4761 {
4762 #if defined(CONFIG_USER_ONLY)
4763 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4764 #else
4765 TCGv t0;
4766 if (unlikely(ctx->pr)) {
4767 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4768 return;
4769 }
4770 t0 = tcg_const_tl(SR(ctx->opcode));
4771 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4772 tcg_temp_free(t0);
4773 #endif
4774 }
4775
4776 /* mtsrin */
4777 static void gen_mtsrin_64b(DisasContext *ctx)
4778 {
4779 #if defined(CONFIG_USER_ONLY)
4780 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4781 #else
4782 TCGv t0;
4783 if (unlikely(ctx->pr)) {
4784 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4785 return;
4786 }
4787 t0 = tcg_temp_new();
4788 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4789 tcg_gen_andi_tl(t0, t0, 0xF);
4790 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4791 tcg_temp_free(t0);
4792 #endif
4793 }
4794
4795 /* slbmte */
4796 static void gen_slbmte(DisasContext *ctx)
4797 {
4798 #if defined(CONFIG_USER_ONLY)
4799 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4800 #else
4801 if (unlikely(ctx->pr)) {
4802 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4803 return;
4804 }
4805 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4806 cpu_gpr[rS(ctx->opcode)]);
4807 #endif
4808 }
4809
4810 static void gen_slbmfee(DisasContext *ctx)
4811 {
4812 #if defined(CONFIG_USER_ONLY)
4813 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4814 #else
4815 if (unlikely(ctx->pr)) {
4816 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4817 return;
4818 }
4819 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4820 cpu_gpr[rB(ctx->opcode)]);
4821 #endif
4822 }
4823
4824 static void gen_slbmfev(DisasContext *ctx)
4825 {
4826 #if defined(CONFIG_USER_ONLY)
4827 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4828 #else
4829 if (unlikely(ctx->pr)) {
4830 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4831 return;
4832 }
4833 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4834 cpu_gpr[rB(ctx->opcode)]);
4835 #endif
4836 }
4837 #endif /* defined(TARGET_PPC64) */
4838
4839 /*** Lookaside buffer management ***/
4840 /* Optional & supervisor only: */
4841
4842 /* tlbia */
4843 static void gen_tlbia(DisasContext *ctx)
4844 {
4845 #if defined(CONFIG_USER_ONLY)
4846 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4847 #else
4848 if (unlikely(ctx->pr)) {
4849 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4850 return;
4851 }
4852 gen_helper_tlbia(cpu_env);
4853 #endif
4854 }
4855
4856 /* tlbiel */
4857 static void gen_tlbiel(DisasContext *ctx)
4858 {
4859 #if defined(CONFIG_USER_ONLY)
4860 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4861 #else
4862 if (unlikely(ctx->pr)) {
4863 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4864 return;
4865 }
4866 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4867 #endif
4868 }
4869
4870 /* tlbie */
4871 static void gen_tlbie(DisasContext *ctx)
4872 {
4873 #if defined(CONFIG_USER_ONLY)
4874 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4875 #else
4876 if (unlikely(ctx->pr || !ctx->hv)) {
4877 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4878 return;
4879 }
4880 if (NARROW_MODE(ctx)) {
4881 TCGv t0 = tcg_temp_new();
4882 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4883 gen_helper_tlbie(cpu_env, t0);
4884 tcg_temp_free(t0);
4885 } else {
4886 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4887 }
4888 #endif
4889 }
4890
4891 /* tlbsync */
4892 static void gen_tlbsync(DisasContext *ctx)
4893 {
4894 #if defined(CONFIG_USER_ONLY)
4895 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4896 #else
4897 if (unlikely(ctx->pr || !ctx->hv)) {
4898 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4899 return;
4900 }
4901 /* tlbsync is a nop for server, ptesync handles delayed tlb flush,
4902 * embedded however needs to deal with tlbsync. We don't try to be
4903 * fancy and swallow the overhead of checking for both.
4904 */
4905 gen_check_tlb_flush(ctx);
4906 #endif
4907 }
4908
4909 #if defined(TARGET_PPC64)
4910 /* slbia */
4911 static void gen_slbia(DisasContext *ctx)
4912 {
4913 #if defined(CONFIG_USER_ONLY)
4914 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4915 #else
4916 if (unlikely(ctx->pr || !ctx->hv)) {
4917 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4918 return;
4919 }
4920 gen_helper_slbia(cpu_env);
4921 #endif
4922 }
4923
4924 /* slbie */
4925 static void gen_slbie(DisasContext *ctx)
4926 {
4927 #if defined(CONFIG_USER_ONLY)
4928 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4929 #else
4930 if (unlikely(ctx->pr)) {
4931 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4932 return;
4933 }
4934 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4935 #endif
4936 }
4937 #endif
4938
4939 /*** External control ***/
4940 /* Optional: */
4941
4942 /* eciwx */
4943 static void gen_eciwx(DisasContext *ctx)
4944 {
4945 TCGv t0;
4946 /* Should check EAR[E] ! */
4947 gen_set_access_type(ctx, ACCESS_EXT);
4948 t0 = tcg_temp_new();
4949 gen_addr_reg_index(ctx, t0);
4950 gen_check_align(ctx, t0, 0x03);
4951 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4952 tcg_temp_free(t0);
4953 }
4954
4955 /* ecowx */
4956 static void gen_ecowx(DisasContext *ctx)
4957 {
4958 TCGv t0;
4959 /* Should check EAR[E] ! */
4960 gen_set_access_type(ctx, ACCESS_EXT);
4961 t0 = tcg_temp_new();
4962 gen_addr_reg_index(ctx, t0);
4963 gen_check_align(ctx, t0, 0x03);
4964 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4965 tcg_temp_free(t0);
4966 }
4967
4968 /* PowerPC 601 specific instructions */
4969
4970 /* abs - abs. */
4971 static void gen_abs(DisasContext *ctx)
4972 {
4973 TCGLabel *l1 = gen_new_label();
4974 TCGLabel *l2 = gen_new_label();
4975 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4976 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4977 tcg_gen_br(l2);
4978 gen_set_label(l1);
4979 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4980 gen_set_label(l2);
4981 if (unlikely(Rc(ctx->opcode) != 0))
4982 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4983 }
4984
4985 /* abso - abso. */
4986 static void gen_abso(DisasContext *ctx)
4987 {
4988 TCGLabel *l1 = gen_new_label();
4989 TCGLabel *l2 = gen_new_label();
4990 TCGLabel *l3 = gen_new_label();
4991 /* Start with XER OV disabled, the most likely case */
4992 tcg_gen_movi_tl(cpu_ov, 0);
4993 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4994 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4995 tcg_gen_movi_tl(cpu_ov, 1);
4996 tcg_gen_movi_tl(cpu_so, 1);
4997 tcg_gen_br(l2);
4998 gen_set_label(l1);
4999 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5000 tcg_gen_br(l3);
5001 gen_set_label(l2);
5002 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5003 gen_set_label(l3);
5004 if (unlikely(Rc(ctx->opcode) != 0))
5005 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5006 }
5007
5008 /* clcs */
5009 static void gen_clcs(DisasContext *ctx)
5010 {
5011 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
5012 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5013 tcg_temp_free_i32(t0);
5014 /* Rc=1 sets CR0 to an undefined state */
5015 }
5016
5017 /* div - div. */
5018 static void gen_div(DisasContext *ctx)
5019 {
5020 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5021 cpu_gpr[rB(ctx->opcode)]);
5022 if (unlikely(Rc(ctx->opcode) != 0))
5023 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5024 }
5025
5026 /* divo - divo. */
5027 static void gen_divo(DisasContext *ctx)
5028 {
5029 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5030 cpu_gpr[rB(ctx->opcode)]);
5031 if (unlikely(Rc(ctx->opcode) != 0))
5032 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5033 }
5034
5035 /* divs - divs. */
5036 static void gen_divs(DisasContext *ctx)
5037 {
5038 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5039 cpu_gpr[rB(ctx->opcode)]);
5040 if (unlikely(Rc(ctx->opcode) != 0))
5041 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5042 }
5043
5044 /* divso - divso. */
5045 static void gen_divso(DisasContext *ctx)
5046 {
5047 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
5048 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5049 if (unlikely(Rc(ctx->opcode) != 0))
5050 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5051 }
5052
5053 /* doz - doz. */
5054 static void gen_doz(DisasContext *ctx)
5055 {
5056 TCGLabel *l1 = gen_new_label();
5057 TCGLabel *l2 = gen_new_label();
5058 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5059 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5060 tcg_gen_br(l2);
5061 gen_set_label(l1);
5062 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5063 gen_set_label(l2);
5064 if (unlikely(Rc(ctx->opcode) != 0))
5065 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5066 }
5067
5068 /* dozo - dozo. */
5069 static void gen_dozo(DisasContext *ctx)
5070 {
5071 TCGLabel *l1 = gen_new_label();
5072 TCGLabel *l2 = gen_new_label();
5073 TCGv t0 = tcg_temp_new();
5074 TCGv t1 = tcg_temp_new();
5075 TCGv t2 = tcg_temp_new();
5076 /* Start with XER OV disabled, the most likely case */
5077 tcg_gen_movi_tl(cpu_ov, 0);
5078 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5079 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5080 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5081 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5082 tcg_gen_andc_tl(t1, t1, t2);
5083 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5084 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5085 tcg_gen_movi_tl(cpu_ov, 1);
5086 tcg_gen_movi_tl(cpu_so, 1);
5087 tcg_gen_br(l2);
5088 gen_set_label(l1);
5089 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5090 gen_set_label(l2);
5091 tcg_temp_free(t0);
5092 tcg_temp_free(t1);
5093 tcg_temp_free(t2);
5094 if (unlikely(Rc(ctx->opcode) != 0))
5095 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5096 }
5097
5098 /* dozi */
5099 static void gen_dozi(DisasContext *ctx)
5100 {
5101 target_long simm = SIMM(ctx->opcode);
5102 TCGLabel *l1 = gen_new_label();
5103 TCGLabel *l2 = gen_new_label();
5104 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5105 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5106 tcg_gen_br(l2);
5107 gen_set_label(l1);
5108 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5109 gen_set_label(l2);
5110 if (unlikely(Rc(ctx->opcode) != 0))
5111 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5112 }
5113
5114 /* lscbx - lscbx. */
5115 static void gen_lscbx(DisasContext *ctx)
5116 {
5117 TCGv t0 = tcg_temp_new();
5118 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5119 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5120 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5121
5122 gen_addr_reg_index(ctx, t0);
5123 /* NIP cannot be restored if the memory exception comes from an helper */
5124 gen_update_nip(ctx, ctx->nip - 4);
5125 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5126 tcg_temp_free_i32(t1);
5127 tcg_temp_free_i32(t2);
5128 tcg_temp_free_i32(t3);
5129 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5130 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5131 if (unlikely(Rc(ctx->opcode) != 0))
5132 gen_set_Rc0(ctx, t0);
5133 tcg_temp_free(t0);
5134 }
5135
5136 /* maskg - maskg. */
5137 static void gen_maskg(DisasContext *ctx)
5138 {
5139 TCGLabel *l1 = gen_new_label();
5140 TCGv t0 = tcg_temp_new();
5141 TCGv t1 = tcg_temp_new();
5142 TCGv t2 = tcg_temp_new();
5143 TCGv t3 = tcg_temp_new();
5144 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5145 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5146 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5147 tcg_gen_addi_tl(t2, t0, 1);
5148 tcg_gen_shr_tl(t2, t3, t2);
5149 tcg_gen_shr_tl(t3, t3, t1);
5150 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5151 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5152 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5153 gen_set_label(l1);
5154 tcg_temp_free(t0);
5155 tcg_temp_free(t1);
5156 tcg_temp_free(t2);
5157 tcg_temp_free(t3);
5158 if (unlikely(Rc(ctx->opcode) != 0))
5159 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5160 }
5161
5162 /* maskir - maskir. */
5163 static void gen_maskir(DisasContext *ctx)
5164 {
5165 TCGv t0 = tcg_temp_new();
5166 TCGv t1 = tcg_temp_new();
5167 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5168 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5169 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5170 tcg_temp_free(t0);
5171 tcg_temp_free(t1);
5172 if (unlikely(Rc(ctx->opcode) != 0))
5173 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5174 }
5175
5176 /* mul - mul. */
5177 static void gen_mul(DisasContext *ctx)
5178 {
5179 TCGv_i64 t0 = tcg_temp_new_i64();
5180 TCGv_i64 t1 = tcg_temp_new_i64();
5181 TCGv t2 = tcg_temp_new();
5182 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5183 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5184 tcg_gen_mul_i64(t0, t0, t1);
5185 tcg_gen_trunc_i64_tl(t2, t0);
5186 gen_store_spr(SPR_MQ, t2);
5187 tcg_gen_shri_i64(t1, t0, 32);
5188 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5189 tcg_temp_free_i64(t0);
5190 tcg_temp_free_i64(t1);
5191 tcg_temp_free(t2);
5192 if (unlikely(Rc(ctx->opcode) != 0))
5193 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5194 }
5195
5196 /* mulo - mulo. */
5197 static void gen_mulo(DisasContext *ctx)
5198 {
5199 TCGLabel *l1 = gen_new_label();
5200 TCGv_i64 t0 = tcg_temp_new_i64();
5201 TCGv_i64 t1 = tcg_temp_new_i64();
5202 TCGv t2 = tcg_temp_new();
5203 /* Start with XER OV disabled, the most likely case */
5204 tcg_gen_movi_tl(cpu_ov, 0);
5205 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5206 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5207 tcg_gen_mul_i64(t0, t0, t1);
5208 tcg_gen_trunc_i64_tl(t2, t0);
5209 gen_store_spr(SPR_MQ, t2);
5210 tcg_gen_shri_i64(t1, t0, 32);
5211 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5212 tcg_gen_ext32s_i64(t1, t0);
5213 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5214 tcg_gen_movi_tl(cpu_ov, 1);
5215 tcg_gen_movi_tl(cpu_so, 1);
5216 gen_set_label(l1);
5217 tcg_temp_free_i64(t0);
5218 tcg_temp_free_i64(t1);
5219 tcg_temp_free(t2);
5220 if (unlikely(Rc(ctx->opcode) != 0))
5221 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5222 }
5223
5224 /* nabs - nabs. */
5225 static void gen_nabs(DisasContext *ctx)
5226 {
5227 TCGLabel *l1 = gen_new_label();
5228 TCGLabel *l2 = gen_new_label();
5229 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5230 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5231 tcg_gen_br(l2);
5232 gen_set_label(l1);
5233 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5234 gen_set_label(l2);
5235 if (unlikely(Rc(ctx->opcode) != 0))
5236 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5237 }
5238
5239 /* nabso - nabso. */
5240 static void gen_nabso(DisasContext *ctx)
5241 {
5242 TCGLabel *l1 = gen_new_label();
5243 TCGLabel *l2 = gen_new_label();
5244 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5245 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5246 tcg_gen_br(l2);
5247 gen_set_label(l1);
5248 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5249 gen_set_label(l2);
5250 /* nabs never overflows */
5251 tcg_gen_movi_tl(cpu_ov, 0);
5252 if (unlikely(Rc(ctx->opcode) != 0))
5253 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5254 }
5255
5256 /* rlmi - rlmi. */
5257 static void gen_rlmi(DisasContext *ctx)
5258 {
5259 uint32_t mb = MB(ctx->opcode);
5260 uint32_t me = ME(ctx->opcode);
5261 TCGv t0 = tcg_temp_new();
5262 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5263 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5264 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5265 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5266 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5267 tcg_temp_free(t0);
5268 if (unlikely(Rc(ctx->opcode) != 0))
5269 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5270 }
5271
5272 /* rrib - rrib. */
5273 static void gen_rrib(DisasContext *ctx)
5274 {
5275 TCGv t0 = tcg_temp_new();
5276 TCGv t1 = tcg_temp_new();
5277 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5278 tcg_gen_movi_tl(t1, 0x80000000);
5279 tcg_gen_shr_tl(t1, t1, t0);
5280 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5281 tcg_gen_and_tl(t0, t0, t1);
5282 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5283 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5284 tcg_temp_free(t0);
5285 tcg_temp_free(t1);
5286 if (unlikely(Rc(ctx->opcode) != 0))
5287 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5288 }
5289
5290 /* sle - sle. */
5291 static void gen_sle(DisasContext *ctx)
5292 {
5293 TCGv t0 = tcg_temp_new();
5294 TCGv t1 = tcg_temp_new();
5295 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5296 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5297 tcg_gen_subfi_tl(t1, 32, t1);
5298 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5299 tcg_gen_or_tl(t1, t0, t1);
5300 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5301 gen_store_spr(SPR_MQ, t1);
5302 tcg_temp_free(t0);
5303 tcg_temp_free(t1);
5304 if (unlikely(Rc(ctx->opcode) != 0))
5305 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5306 }
5307
5308 /* sleq - sleq. */
5309 static void gen_sleq(DisasContext *ctx)
5310 {
5311 TCGv t0 = tcg_temp_new();
5312 TCGv t1 = tcg_temp_new();
5313 TCGv t2 = tcg_temp_new();
5314 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5315 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5316 tcg_gen_shl_tl(t2, t2, t0);
5317 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5318 gen_load_spr(t1, SPR_MQ);
5319 gen_store_spr(SPR_MQ, t0);
5320 tcg_gen_and_tl(t0, t0, t2);
5321 tcg_gen_andc_tl(t1, t1, t2);
5322 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5323 tcg_temp_free(t0);
5324 tcg_temp_free(t1);
5325 tcg_temp_free(t2);
5326 if (unlikely(Rc(ctx->opcode) != 0))
5327 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5328 }
5329
5330 /* sliq - sliq. */
5331 static void gen_sliq(DisasContext *ctx)
5332 {
5333 int sh = SH(ctx->opcode);
5334 TCGv t0 = tcg_temp_new();
5335 TCGv t1 = tcg_temp_new();
5336 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5337 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5338 tcg_gen_or_tl(t1, t0, t1);
5339 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5340 gen_store_spr(SPR_MQ, t1);
5341 tcg_temp_free(t0);
5342 tcg_temp_free(t1);
5343 if (unlikely(Rc(ctx->opcode) != 0))
5344 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5345 }
5346
5347 /* slliq - slliq. */
5348 static void gen_slliq(DisasContext *ctx)
5349 {
5350 int sh = SH(ctx->opcode);
5351 TCGv t0 = tcg_temp_new();
5352 TCGv t1 = tcg_temp_new();
5353 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5354 gen_load_spr(t1, SPR_MQ);
5355 gen_store_spr(SPR_MQ, t0);
5356 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5357 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5358 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5359 tcg_temp_free(t0);
5360 tcg_temp_free(t1);
5361 if (unlikely(Rc(ctx->opcode) != 0))
5362 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5363 }
5364
5365 /* sllq - sllq. */
5366 static void gen_sllq(DisasContext *ctx)
5367 {
5368 TCGLabel *l1 = gen_new_label();
5369 TCGLabel *l2 = gen_new_label();
5370 TCGv t0 = tcg_temp_local_new();
5371 TCGv t1 = tcg_temp_local_new();
5372 TCGv t2 = tcg_temp_local_new();
5373 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5374 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5375 tcg_gen_shl_tl(t1, t1, t2);
5376 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5377 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5378 gen_load_spr(t0, SPR_MQ);
5379 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5380 tcg_gen_br(l2);
5381 gen_set_label(l1);
5382 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5383 gen_load_spr(t2, SPR_MQ);
5384 tcg_gen_andc_tl(t1, t2, t1);
5385 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5386 gen_set_label(l2);
5387 tcg_temp_free(t0);
5388 tcg_temp_free(t1);
5389 tcg_temp_free(t2);
5390 if (unlikely(Rc(ctx->opcode) != 0))
5391 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5392 }
5393
5394 /* slq - slq. */
5395 static void gen_slq(DisasContext *ctx)
5396 {
5397 TCGLabel *l1 = gen_new_label();
5398 TCGv t0 = tcg_temp_new();
5399 TCGv t1 = tcg_temp_new();
5400 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5401 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5402 tcg_gen_subfi_tl(t1, 32, t1);
5403 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5404 tcg_gen_or_tl(t1, t0, t1);
5405 gen_store_spr(SPR_MQ, t1);
5406 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5407 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5408 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5409 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5410 gen_set_label(l1);
5411 tcg_temp_free(t0);
5412 tcg_temp_free(t1);
5413 if (unlikely(Rc(ctx->opcode) != 0))
5414 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5415 }
5416
5417 /* sraiq - sraiq. */
5418 static void gen_sraiq(DisasContext *ctx)
5419 {
5420 int sh = SH(ctx->opcode);
5421 TCGLabel *l1 = gen_new_label();
5422 TCGv t0 = tcg_temp_new();
5423 TCGv t1 = tcg_temp_new();
5424 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5425 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5426 tcg_gen_or_tl(t0, t0, t1);
5427 gen_store_spr(SPR_MQ, t0);
5428 tcg_gen_movi_tl(cpu_ca, 0);
5429 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5430 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5431 tcg_gen_movi_tl(cpu_ca, 1);
5432 gen_set_label(l1);
5433 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5434 tcg_temp_free(t0);
5435 tcg_temp_free(t1);
5436 if (unlikely(Rc(ctx->opcode) != 0))
5437 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5438 }
5439
5440 /* sraq - sraq. */
5441 static void gen_sraq(DisasContext *ctx)
5442 {
5443 TCGLabel *l1 = gen_new_label();
5444 TCGLabel *l2 = gen_new_label();
5445 TCGv t0 = tcg_temp_new();
5446 TCGv t1 = tcg_temp_local_new();
5447 TCGv t2 = tcg_temp_local_new();
5448 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5449 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5450 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5451 tcg_gen_subfi_tl(t2, 32, t2);
5452 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5453 tcg_gen_or_tl(t0, t0, t2);
5454 gen_store_spr(SPR_MQ, t0);
5455 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5456 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5457 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5458 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5459 gen_set_label(l1);
5460 tcg_temp_free(t0);
5461 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5462 tcg_gen_movi_tl(cpu_ca, 0);
5463 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5464 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5465 tcg_gen_movi_tl(cpu_ca, 1);
5466 gen_set_label(l2);
5467 tcg_temp_free(t1);
5468 tcg_temp_free(t2);
5469 if (unlikely(Rc(ctx->opcode) != 0))
5470 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5471 }
5472
5473 /* sre - sre. */
5474 static void gen_sre(DisasContext *ctx)
5475 {
5476 TCGv t0 = tcg_temp_new();
5477 TCGv t1 = tcg_temp_new();
5478 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5479 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5480 tcg_gen_subfi_tl(t1, 32, t1);
5481 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5482 tcg_gen_or_tl(t1, t0, t1);
5483 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5484 gen_store_spr(SPR_MQ, t1);
5485 tcg_temp_free(t0);
5486 tcg_temp_free(t1);
5487 if (unlikely(Rc(ctx->opcode) != 0))
5488 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5489 }
5490
5491 /* srea - srea. */
5492 static void gen_srea(DisasContext *ctx)
5493 {
5494 TCGv t0 = tcg_temp_new();
5495 TCGv t1 = tcg_temp_new();
5496 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5497 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5498 gen_store_spr(SPR_MQ, t0);
5499 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5500 tcg_temp_free(t0);
5501 tcg_temp_free(t1);
5502 if (unlikely(Rc(ctx->opcode) != 0))
5503 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5504 }
5505
5506 /* sreq */
5507 static void gen_sreq(DisasContext *ctx)
5508 {
5509 TCGv t0 = tcg_temp_new();
5510 TCGv t1 = tcg_temp_new();
5511 TCGv t2 = tcg_temp_new();
5512 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5513 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5514 tcg_gen_shr_tl(t1, t1, t0);
5515 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5516 gen_load_spr(t2, SPR_MQ);
5517 gen_store_spr(SPR_MQ, t0);
5518 tcg_gen_and_tl(t0, t0, t1);
5519 tcg_gen_andc_tl(t2, t2, t1);
5520 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5521 tcg_temp_free(t0);
5522 tcg_temp_free(t1);
5523 tcg_temp_free(t2);
5524 if (unlikely(Rc(ctx->opcode) != 0))
5525 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5526 }
5527
5528 /* sriq */
5529 static void gen_sriq(DisasContext *ctx)
5530 {
5531 int sh = SH(ctx->opcode);
5532 TCGv t0 = tcg_temp_new();
5533 TCGv t1 = tcg_temp_new();
5534 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5535 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5536 tcg_gen_or_tl(t1, t0, t1);
5537 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5538 gen_store_spr(SPR_MQ, t1);
5539 tcg_temp_free(t0);
5540 tcg_temp_free(t1);
5541 if (unlikely(Rc(ctx->opcode) != 0))
5542 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5543 }
5544
5545 /* srliq */
5546 static void gen_srliq(DisasContext *ctx)
5547 {
5548 int sh = SH(ctx->opcode);
5549 TCGv t0 = tcg_temp_new();
5550 TCGv t1 = tcg_temp_new();
5551 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5552 gen_load_spr(t1, SPR_MQ);
5553 gen_store_spr(SPR_MQ, t0);
5554 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5555 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5556 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5557 tcg_temp_free(t0);
5558 tcg_temp_free(t1);
5559 if (unlikely(Rc(ctx->opcode) != 0))
5560 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5561 }
5562
5563 /* srlq */
5564 static void gen_srlq(DisasContext *ctx)
5565 {
5566 TCGLabel *l1 = gen_new_label();
5567 TCGLabel *l2 = gen_new_label();
5568 TCGv t0 = tcg_temp_local_new();
5569 TCGv t1 = tcg_temp_local_new();
5570 TCGv t2 = tcg_temp_local_new();
5571 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5572 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5573 tcg_gen_shr_tl(t2, t1, t2);
5574 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5575 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5576 gen_load_spr(t0, SPR_MQ);
5577 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5578 tcg_gen_br(l2);
5579 gen_set_label(l1);
5580 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5581 tcg_gen_and_tl(t0, t0, t2);
5582 gen_load_spr(t1, SPR_MQ);
5583 tcg_gen_andc_tl(t1, t1, t2);
5584 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5585 gen_set_label(l2);
5586 tcg_temp_free(t0);
5587 tcg_temp_free(t1);
5588 tcg_temp_free(t2);
5589 if (unlikely(Rc(ctx->opcode) != 0))
5590 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5591 }
5592
5593 /* srq */
5594 static void gen_srq(DisasContext *ctx)
5595 {
5596 TCGLabel *l1 = gen_new_label();
5597 TCGv t0 = tcg_temp_new();
5598 TCGv t1 = tcg_temp_new();
5599 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5600 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5601 tcg_gen_subfi_tl(t1, 32, t1);
5602 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5603 tcg_gen_or_tl(t1, t0, t1);
5604 gen_store_spr(SPR_MQ, t1);
5605 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5606 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5607 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5608 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5609 gen_set_label(l1);
5610 tcg_temp_free(t0);
5611 tcg_temp_free(t1);
5612 if (unlikely(Rc(ctx->opcode) != 0))
5613 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5614 }
5615
5616 /* PowerPC 602 specific instructions */
5617
5618 /* dsa */
5619 static void gen_dsa(DisasContext *ctx)
5620 {
5621 /* XXX: TODO */
5622 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5623 }
5624
5625 /* esa */
5626 static void gen_esa(DisasContext *ctx)
5627 {
5628 /* XXX: TODO */
5629 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5630 }
5631
5632 /* mfrom */
5633 static void gen_mfrom(DisasContext *ctx)
5634 {
5635 #if defined(CONFIG_USER_ONLY)
5636 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5637 #else
5638 if (unlikely(ctx->pr)) {
5639 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5640 return;
5641 }
5642 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5643 #endif
5644 }
5645
5646 /* 602 - 603 - G2 TLB management */
5647
5648 /* tlbld */
5649 static void gen_tlbld_6xx(DisasContext *ctx)
5650 {
5651 #if defined(CONFIG_USER_ONLY)
5652 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5653 #else
5654 if (unlikely(ctx->pr)) {
5655 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5656 return;
5657 }
5658 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5659 #endif
5660 }
5661
5662 /* tlbli */
5663 static void gen_tlbli_6xx(DisasContext *ctx)
5664 {
5665 #if defined(CONFIG_USER_ONLY)
5666 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5667 #else
5668 if (unlikely(ctx->pr)) {
5669 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5670 return;
5671 }
5672 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5673 #endif
5674 }
5675
5676 /* 74xx TLB management */
5677
5678 /* tlbld */
5679 static void gen_tlbld_74xx(DisasContext *ctx)
5680 {
5681 #if defined(CONFIG_USER_ONLY)
5682 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5683 #else
5684 if (unlikely(ctx->pr)) {
5685 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5686 return;
5687 }
5688 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5689 #endif
5690 }
5691
5692 /* tlbli */
5693 static void gen_tlbli_74xx(DisasContext *ctx)
5694 {
5695 #if defined(CONFIG_USER_ONLY)
5696 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5697 #else
5698 if (unlikely(ctx->pr)) {
5699 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5700 return;
5701 }
5702 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5703 #endif
5704 }
5705
5706 /* POWER instructions not in PowerPC 601 */
5707
5708 /* clf */
5709 static void gen_clf(DisasContext *ctx)
5710 {
5711 /* Cache line flush: implemented as no-op */
5712 }
5713
5714 /* cli */
5715 static void gen_cli(DisasContext *ctx)
5716 {
5717 /* Cache line invalidate: privileged and treated as no-op */
5718 #if defined(CONFIG_USER_ONLY)
5719 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5720 #else
5721 if (unlikely(ctx->pr)) {
5722 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5723 return;
5724 }
5725 #endif
5726 }
5727
5728 /* dclst */
5729 static void gen_dclst(DisasContext *ctx)
5730 {
5731 /* Data cache line store: treated as no-op */
5732 }
5733
5734 static void gen_mfsri(DisasContext *ctx)
5735 {
5736 #if defined(CONFIG_USER_ONLY)
5737 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5738 #else
5739 int ra = rA(ctx->opcode);
5740 int rd = rD(ctx->opcode);
5741 TCGv t0;
5742 if (unlikely(ctx->pr)) {
5743 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5744 return;
5745 }
5746 t0 = tcg_temp_new();
5747 gen_addr_reg_index(ctx, t0);
5748 tcg_gen_shri_tl(t0, t0, 28);
5749 tcg_gen_andi_tl(t0, t0, 0xF);
5750 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5751 tcg_temp_free(t0);
5752 if (ra != 0 && ra != rd)
5753 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5754 #endif
5755 }
5756
5757 static void gen_rac(DisasContext *ctx)
5758 {
5759 #if defined(CONFIG_USER_ONLY)
5760 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5761 #else
5762 TCGv t0;
5763 if (unlikely(ctx->pr)) {
5764 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5765 return;
5766 }
5767 t0 = tcg_temp_new();
5768 gen_addr_reg_index(ctx, t0);
5769 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5770 tcg_temp_free(t0);
5771 #endif
5772 }
5773
5774 static void gen_rfsvc(DisasContext *ctx)
5775 {
5776 #if defined(CONFIG_USER_ONLY)
5777 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5778 #else
5779 if (unlikely(ctx->pr)) {
5780 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5781 return;
5782 }
5783 gen_helper_rfsvc(cpu_env);
5784 gen_sync_exception(ctx);
5785 #endif
5786 }
5787
5788 /* svc is not implemented for now */
5789
5790 /* POWER2 specific instructions */
5791 /* Quad manipulation (load/store two floats at a time) */
5792
5793 /* lfq */
5794 static void gen_lfq(DisasContext *ctx)
5795 {
5796 int rd = rD(ctx->opcode);
5797 TCGv t0;
5798 gen_set_access_type(ctx, ACCESS_FLOAT);
5799 t0 = tcg_temp_new();
5800 gen_addr_imm_index(ctx, t0, 0);
5801 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5802 gen_addr_add(ctx, t0, t0, 8);
5803 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5804 tcg_temp_free(t0);
5805 }
5806
5807 /* lfqu */
5808 static void gen_lfqu(DisasContext *ctx)
5809 {
5810 int ra = rA(ctx->opcode);
5811 int rd = rD(ctx->opcode);
5812 TCGv t0, t1;
5813 gen_set_access_type(ctx, ACCESS_FLOAT);
5814 t0 = tcg_temp_new();
5815 t1 = tcg_temp_new();
5816 gen_addr_imm_index(ctx, t0, 0);
5817 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5818 gen_addr_add(ctx, t1, t0, 8);
5819 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5820 if (ra != 0)
5821 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5822 tcg_temp_free(t0);
5823 tcg_temp_free(t1);
5824 }
5825
5826 /* lfqux */
5827 static void gen_lfqux(DisasContext *ctx)
5828 {
5829 int ra = rA(ctx->opcode);
5830 int rd = rD(ctx->opcode);
5831 gen_set_access_type(ctx, ACCESS_FLOAT);
5832 TCGv t0, t1;
5833 t0 = tcg_temp_new();
5834 gen_addr_reg_index(ctx, t0);
5835 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5836 t1 = tcg_temp_new();
5837 gen_addr_add(ctx, t1, t0, 8);
5838 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5839 tcg_temp_free(t1);
5840 if (ra != 0)
5841 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5842 tcg_temp_free(t0);
5843 }
5844
5845 /* lfqx */
5846 static void gen_lfqx(DisasContext *ctx)
5847 {
5848 int rd = rD(ctx->opcode);
5849 TCGv t0;
5850 gen_set_access_type(ctx, ACCESS_FLOAT);
5851 t0 = tcg_temp_new();
5852 gen_addr_reg_index(ctx, t0);
5853 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5854 gen_addr_add(ctx, t0, t0, 8);
5855 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5856 tcg_temp_free(t0);
5857 }
5858
5859 /* stfq */
5860 static void gen_stfq(DisasContext *ctx)
5861 {
5862 int rd = rD(ctx->opcode);
5863 TCGv t0;
5864 gen_set_access_type(ctx, ACCESS_FLOAT);
5865 t0 = tcg_temp_new();
5866 gen_addr_imm_index(ctx, t0, 0);
5867 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5868 gen_addr_add(ctx, t0, t0, 8);
5869 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5870 tcg_temp_free(t0);
5871 }
5872
5873 /* stfqu */
5874 static void gen_stfqu(DisasContext *ctx)
5875 {
5876 int ra = rA(ctx->opcode);
5877 int rd = rD(ctx->opcode);
5878 TCGv t0, t1;
5879 gen_set_access_type(ctx, ACCESS_FLOAT);
5880 t0 = tcg_temp_new();
5881 gen_addr_imm_index(ctx, t0, 0);
5882 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5883 t1 = tcg_temp_new();
5884 gen_addr_add(ctx, t1, t0, 8);
5885 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5886 tcg_temp_free(t1);
5887 if (ra != 0)
5888 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5889 tcg_temp_free(t0);
5890 }
5891
5892 /* stfqux */
5893 static void gen_stfqux(DisasContext *ctx)
5894 {
5895 int ra = rA(ctx->opcode);
5896 int rd = rD(ctx->opcode);
5897 TCGv t0, t1;
5898 gen_set_access_type(ctx, ACCESS_FLOAT);
5899 t0 = tcg_temp_new();
5900 gen_addr_reg_index(ctx, t0);
5901 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5902 t1 = tcg_temp_new();
5903 gen_addr_add(ctx, t1, t0, 8);
5904 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5905 tcg_temp_free(t1);
5906 if (ra != 0)
5907 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5908 tcg_temp_free(t0);
5909 }
5910
5911 /* stfqx */
5912 static void gen_stfqx(DisasContext *ctx)
5913 {
5914 int rd = rD(ctx->opcode);
5915 TCGv t0;
5916 gen_set_access_type(ctx, ACCESS_FLOAT);
5917 t0 = tcg_temp_new();
5918 gen_addr_reg_index(ctx, t0);
5919 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5920 gen_addr_add(ctx, t0, t0, 8);
5921 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5922 tcg_temp_free(t0);
5923 }
5924
5925 /* BookE specific instructions */
5926
5927 /* XXX: not implemented on 440 ? */
5928 static void gen_mfapidi(DisasContext *ctx)
5929 {
5930 /* XXX: TODO */
5931 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5932 }
5933
5934 /* XXX: not implemented on 440 ? */
5935 static void gen_tlbiva(DisasContext *ctx)
5936 {
5937 #if defined(CONFIG_USER_ONLY)
5938 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5939 #else
5940 TCGv t0;
5941 if (unlikely(ctx->pr)) {
5942 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5943 return;
5944 }
5945 t0 = tcg_temp_new();
5946 gen_addr_reg_index(ctx, t0);
5947 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5948 tcg_temp_free(t0);
5949 #endif
5950 }
5951
5952 /* All 405 MAC instructions are translated here */
5953 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5954 int ra, int rb, int rt, int Rc)
5955 {
5956 TCGv t0, t1;
5957
5958 t0 = tcg_temp_local_new();
5959 t1 = tcg_temp_local_new();
5960
5961 switch (opc3 & 0x0D) {
5962 case 0x05:
5963 /* macchw - macchw. - macchwo - macchwo. */
5964 /* macchws - macchws. - macchwso - macchwso. */
5965 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5966 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5967 /* mulchw - mulchw. */
5968 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5969 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5970 tcg_gen_ext16s_tl(t1, t1);
5971 break;
5972 case 0x04:
5973 /* macchwu - macchwu. - macchwuo - macchwuo. */
5974 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5975 /* mulchwu - mulchwu. */
5976 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5977 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5978 tcg_gen_ext16u_tl(t1, t1);
5979 break;
5980 case 0x01:
5981 /* machhw - machhw. - machhwo - machhwo. */
5982 /* machhws - machhws. - machhwso - machhwso. */
5983 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5984 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5985 /* mulhhw - mulhhw. */
5986 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5987 tcg_gen_ext16s_tl(t0, t0);
5988 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5989 tcg_gen_ext16s_tl(t1, t1);
5990 break;
5991 case 0x00:
5992 /* machhwu - machhwu. - machhwuo - machhwuo. */
5993 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5994 /* mulhhwu - mulhhwu. */
5995 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5996 tcg_gen_ext16u_tl(t0, t0);
5997 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5998 tcg_gen_ext16u_tl(t1, t1);
5999 break;
6000 case 0x0D:
6001 /* maclhw - maclhw. - maclhwo - maclhwo. */
6002 /* maclhws - maclhws. - maclhwso - maclhwso. */
6003 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
6004 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
6005 /* mullhw - mullhw. */
6006 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
6007 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
6008 break;
6009 case 0x0C:
6010 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
6011 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
6012 /* mullhwu - mullhwu. */
6013 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6014 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
6015 break;
6016 }
6017 if (opc2 & 0x04) {
6018 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
6019 tcg_gen_mul_tl(t1, t0, t1);
6020 if (opc2 & 0x02) {
6021 /* nmultiply-and-accumulate (0x0E) */
6022 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
6023 } else {
6024 /* multiply-and-accumulate (0x0C) */
6025 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
6026 }
6027
6028 if (opc3 & 0x12) {
6029 /* Check overflow and/or saturate */
6030 TCGLabel *l1 = gen_new_label();
6031
6032 if (opc3 & 0x10) {
6033 /* Start with XER OV disabled, the most likely case */
6034 tcg_gen_movi_tl(cpu_ov, 0);
6035 }
6036 if (opc3 & 0x01) {
6037 /* Signed */
6038 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
6039 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
6040 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
6041 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
6042 if (opc3 & 0x02) {
6043 /* Saturate */
6044 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
6045 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
6046 }
6047 } else {
6048 /* Unsigned */
6049 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
6050 if (opc3 & 0x02) {
6051 /* Saturate */
6052 tcg_gen_movi_tl(t0, UINT32_MAX);
6053 }
6054 }
6055 if (opc3 & 0x10) {
6056 /* Check overflow */
6057 tcg_gen_movi_tl(cpu_ov, 1);
6058 tcg_gen_movi_tl(cpu_so, 1);
6059 }
6060 gen_set_label(l1);
6061 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6062 }
6063 } else {
6064 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
6065 }
6066 tcg_temp_free(t0);
6067 tcg_temp_free(t1);
6068 if (unlikely(Rc) != 0) {
6069 /* Update Rc0 */
6070 gen_set_Rc0(ctx, cpu_gpr[rt]);
6071 }
6072 }
6073
6074 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6075 static void glue(gen_, name)(DisasContext *ctx) \
6076 { \
6077 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6078 rD(ctx->opcode), Rc(ctx->opcode)); \
6079 }
6080
6081 /* macchw - macchw. */
6082 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
6083 /* macchwo - macchwo. */
6084 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
6085 /* macchws - macchws. */
6086 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
6087 /* macchwso - macchwso. */
6088 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
6089 /* macchwsu - macchwsu. */
6090 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
6091 /* macchwsuo - macchwsuo. */
6092 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
6093 /* macchwu - macchwu. */
6094 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
6095 /* macchwuo - macchwuo. */
6096 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
6097 /* machhw - machhw. */
6098 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
6099 /* machhwo - machhwo. */
6100 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
6101 /* machhws - machhws. */
6102 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
6103 /* machhwso - machhwso. */
6104 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
6105 /* machhwsu - machhwsu. */
6106 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
6107 /* machhwsuo - machhwsuo. */
6108 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
6109 /* machhwu - machhwu. */
6110 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
6111 /* machhwuo - machhwuo. */
6112 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
6113 /* maclhw - maclhw. */
6114 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
6115 /* maclhwo - maclhwo. */
6116 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
6117 /* maclhws - maclhws. */
6118 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
6119 /* maclhwso - maclhwso. */
6120 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6121 /* maclhwu - maclhwu. */
6122 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6123 /* maclhwuo - maclhwuo. */
6124 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6125 /* maclhwsu - maclhwsu. */
6126 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6127 /* maclhwsuo - maclhwsuo. */
6128 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6129 /* nmacchw - nmacchw. */
6130 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6131 /* nmacchwo - nmacchwo. */
6132 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6133 /* nmacchws - nmacchws. */
6134 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6135 /* nmacchwso - nmacchwso. */
6136 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6137 /* nmachhw - nmachhw. */
6138 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6139 /* nmachhwo - nmachhwo. */
6140 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6141 /* nmachhws - nmachhws. */
6142 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6143 /* nmachhwso - nmachhwso. */
6144 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6145 /* nmaclhw - nmaclhw. */
6146 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6147 /* nmaclhwo - nmaclhwo. */
6148 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6149 /* nmaclhws - nmaclhws. */
6150 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6151 /* nmaclhwso - nmaclhwso. */
6152 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6153
6154 /* mulchw - mulchw. */
6155 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6156 /* mulchwu - mulchwu. */
6157 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6158 /* mulhhw - mulhhw. */
6159 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6160 /* mulhhwu - mulhhwu. */
6161 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6162 /* mullhw - mullhw. */
6163 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6164 /* mullhwu - mullhwu. */
6165 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6166
6167 /* mfdcr */
6168 static void gen_mfdcr(DisasContext *ctx)
6169 {
6170 #if defined(CONFIG_USER_ONLY)
6171 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6172 #else
6173 TCGv dcrn;
6174 if (unlikely(ctx->pr)) {
6175 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6176 return;
6177 }
6178 /* NIP cannot be restored if the memory exception comes from an helper */
6179 gen_update_nip(ctx, ctx->nip - 4);
6180 dcrn = tcg_const_tl(SPR(ctx->opcode));
6181 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6182 tcg_temp_free(dcrn);
6183 #endif
6184 }
6185
6186 /* mtdcr */
6187 static void gen_mtdcr(DisasContext *ctx)
6188 {
6189 #if defined(CONFIG_USER_ONLY)
6190 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6191 #else
6192 TCGv dcrn;
6193 if (unlikely(ctx->pr)) {
6194 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6195 return;
6196 }
6197 /* NIP cannot be restored if the memory exception comes from an helper */
6198 gen_update_nip(ctx, ctx->nip - 4);
6199 dcrn = tcg_const_tl(SPR(ctx->opcode));
6200 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6201 tcg_temp_free(dcrn);
6202 #endif
6203 }
6204
6205 /* mfdcrx */
6206 /* XXX: not implemented on 440 ? */
6207 static void gen_mfdcrx(DisasContext *ctx)
6208 {
6209 #if defined(CONFIG_USER_ONLY)
6210 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6211 #else
6212 if (unlikely(ctx->pr)) {
6213 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6214 return;
6215 }
6216 /* NIP cannot be restored if the memory exception comes from an helper */
6217 gen_update_nip(ctx, ctx->nip - 4);
6218 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6219 cpu_gpr[rA(ctx->opcode)]);
6220 /* Note: Rc update flag set leads to undefined state of Rc0 */
6221 #endif
6222 }
6223
6224 /* mtdcrx */
6225 /* XXX: not implemented on 440 ? */
6226 static void gen_mtdcrx(DisasContext *ctx)
6227 {
6228 #if defined(CONFIG_USER_ONLY)
6229 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6230 #else
6231 if (unlikely(ctx->pr)) {
6232 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6233 return;
6234 }
6235 /* NIP cannot be restored if the memory exception comes from an helper */
6236 gen_update_nip(ctx, ctx->nip - 4);
6237 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6238 cpu_gpr[rS(ctx->opcode)]);
6239 /* Note: Rc update flag set leads to undefined state of Rc0 */
6240 #endif
6241 }
6242
6243 /* mfdcrux (PPC 460) : user-mode access to DCR */
6244 static void gen_mfdcrux(DisasContext *ctx)
6245 {
6246 /* NIP cannot be restored if the memory exception comes from an helper */
6247 gen_update_nip(ctx, ctx->nip - 4);
6248 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6249 cpu_gpr[rA(ctx->opcode)]);
6250 /* Note: Rc update flag set leads to undefined state of Rc0 */
6251 }
6252
6253 /* mtdcrux (PPC 460) : user-mode access to DCR */
6254 static void gen_mtdcrux(DisasContext *ctx)
6255 {
6256 /* NIP cannot be restored if the memory exception comes from an helper */
6257 gen_update_nip(ctx, ctx->nip - 4);
6258 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6259 cpu_gpr[rS(ctx->opcode)]);
6260 /* Note: Rc update flag set leads to undefined state of Rc0 */
6261 }
6262
6263 /* dccci */
6264 static void gen_dccci(DisasContext *ctx)
6265 {
6266 #if defined(CONFIG_USER_ONLY)
6267 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6268 #else
6269 if (unlikely(ctx->pr)) {
6270 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6271 return;
6272 }
6273 /* interpreted as no-op */
6274 #endif
6275 }
6276
6277 /* dcread */
6278 static void gen_dcread(DisasContext *ctx)
6279 {
6280 #if defined(CONFIG_USER_ONLY)
6281 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6282 #else
6283 TCGv EA, val;
6284 if (unlikely(ctx->pr)) {
6285 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6286 return;
6287 }
6288 gen_set_access_type(ctx, ACCESS_CACHE);
6289 EA = tcg_temp_new();
6290 gen_addr_reg_index(ctx, EA);
6291 val = tcg_temp_new();
6292 gen_qemu_ld32u(ctx, val, EA);
6293 tcg_temp_free(val);
6294 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6295 tcg_temp_free(EA);
6296 #endif
6297 }
6298
6299 /* icbt */
6300 static void gen_icbt_40x(DisasContext *ctx)
6301 {
6302 /* interpreted as no-op */
6303 /* XXX: specification say this is treated as a load by the MMU
6304 * but does not generate any exception
6305 */
6306 }
6307
6308 /* iccci */
6309 static void gen_iccci(DisasContext *ctx)
6310 {
6311 #if defined(CONFIG_USER_ONLY)
6312 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6313 #else
6314 if (unlikely(ctx->pr)) {
6315 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6316 return;
6317 }
6318 /* interpreted as no-op */
6319 #endif
6320 }
6321
6322 /* icread */
6323 static void gen_icread(DisasContext *ctx)
6324 {
6325 #if defined(CONFIG_USER_ONLY)
6326 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6327 #else
6328 if (unlikely(ctx->pr)) {
6329 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6330 return;
6331 }
6332 /* interpreted as no-op */
6333 #endif
6334 }
6335
6336 /* rfci (supervisor only) */
6337 static void gen_rfci_40x(DisasContext *ctx)
6338 {
6339 #if defined(CONFIG_USER_ONLY)
6340 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6341 #else
6342 if (unlikely(ctx->pr)) {
6343 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6344 return;
6345 }
6346 /* Restore CPU state */
6347 gen_helper_40x_rfci(cpu_env);
6348 gen_sync_exception(ctx);
6349 #endif
6350 }
6351
6352 static void gen_rfci(DisasContext *ctx)
6353 {
6354 #if defined(CONFIG_USER_ONLY)
6355 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6356 #else
6357 if (unlikely(ctx->pr)) {
6358 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6359 return;
6360 }
6361 /* Restore CPU state */
6362 gen_helper_rfci(cpu_env);
6363 gen_sync_exception(ctx);
6364 #endif
6365 }
6366
6367 /* BookE specific */
6368
6369 /* XXX: not implemented on 440 ? */
6370 static void gen_rfdi(DisasContext *ctx)
6371 {
6372 #if defined(CONFIG_USER_ONLY)
6373 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6374 #else
6375 if (unlikely(ctx->pr)) {
6376 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6377 return;
6378 }
6379 /* Restore CPU state */
6380 gen_helper_rfdi(cpu_env);
6381 gen_sync_exception(ctx);
6382 #endif
6383 }
6384
6385 /* XXX: not implemented on 440 ? */
6386 static void gen_rfmci(DisasContext *ctx)
6387 {
6388 #if defined(CONFIG_USER_ONLY)
6389 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6390 #else
6391 if (unlikely(ctx->pr)) {
6392 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6393 return;
6394 }
6395 /* Restore CPU state */
6396 gen_helper_rfmci(cpu_env);
6397 gen_sync_exception(ctx);
6398 #endif
6399 }
6400
6401 /* TLB management - PowerPC 405 implementation */
6402
6403 /* tlbre */
6404 static void gen_tlbre_40x(DisasContext *ctx)
6405 {
6406 #if defined(CONFIG_USER_ONLY)
6407 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6408 #else
6409 if (unlikely(ctx->pr)) {
6410 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6411 return;
6412 }
6413 switch (rB(ctx->opcode)) {
6414 case 0:
6415 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6416 cpu_gpr[rA(ctx->opcode)]);
6417 break;
6418 case 1:
6419 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6420 cpu_gpr[rA(ctx->opcode)]);
6421 break;
6422 default:
6423 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6424 break;
6425 }
6426 #endif
6427 }
6428
6429 /* tlbsx - tlbsx. */
6430 static void gen_tlbsx_40x(DisasContext *ctx)
6431 {
6432 #if defined(CONFIG_USER_ONLY)
6433 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6434 #else
6435 TCGv t0;
6436 if (unlikely(ctx->pr)) {
6437 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6438 return;
6439 }
6440 t0 = tcg_temp_new();
6441 gen_addr_reg_index(ctx, t0);
6442 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6443 tcg_temp_free(t0);
6444 if (Rc(ctx->opcode)) {
6445 TCGLabel *l1 = gen_new_label();
6446 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6447 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6448 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6449 gen_set_label(l1);
6450 }
6451 #endif
6452 }
6453
6454 /* tlbwe */
6455 static void gen_tlbwe_40x(DisasContext *ctx)
6456 {
6457 #if defined(CONFIG_USER_ONLY)
6458 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6459 #else
6460 if (unlikely(ctx->pr)) {
6461 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6462 return;
6463 }
6464 switch (rB(ctx->opcode)) {
6465 case 0:
6466 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6467 cpu_gpr[rS(ctx->opcode)]);
6468 break;
6469 case 1:
6470 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6471 cpu_gpr[rS(ctx->opcode)]);
6472 break;
6473 default:
6474 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6475 break;
6476 }
6477 #endif
6478 }
6479
6480 /* TLB management - PowerPC 440 implementation */
6481
6482 /* tlbre */
6483 static void gen_tlbre_440(DisasContext *ctx)
6484 {
6485 #if defined(CONFIG_USER_ONLY)
6486 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6487 #else
6488 if (unlikely(ctx->pr)) {
6489 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6490 return;
6491 }
6492 switch (rB(ctx->opcode)) {
6493 case 0:
6494 case 1:
6495 case 2:
6496 {
6497 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6498 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6499 t0, cpu_gpr[rA(ctx->opcode)]);
6500 tcg_temp_free_i32(t0);
6501 }
6502 break;
6503 default:
6504 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6505 break;
6506 }
6507 #endif
6508 }
6509
6510 /* tlbsx - tlbsx. */
6511 static void gen_tlbsx_440(DisasContext *ctx)
6512 {
6513 #if defined(CONFIG_USER_ONLY)
6514 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6515 #else
6516 TCGv t0;
6517 if (unlikely(ctx->pr)) {
6518 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6519 return;
6520 }
6521 t0 = tcg_temp_new();
6522 gen_addr_reg_index(ctx, t0);
6523 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6524 tcg_temp_free(t0);
6525 if (Rc(ctx->opcode)) {
6526 TCGLabel *l1 = gen_new_label();
6527 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6528 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6529 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6530 gen_set_label(l1);
6531 }
6532 #endif
6533 }
6534
6535 /* tlbwe */
6536 static void gen_tlbwe_440(DisasContext *ctx)
6537 {
6538 #if defined(CONFIG_USER_ONLY)
6539 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6540 #else
6541 if (unlikely(ctx->pr)) {
6542 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6543 return;
6544 }
6545 switch (rB(ctx->opcode)) {
6546 case 0:
6547 case 1:
6548 case 2:
6549 {
6550 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6551 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6552 cpu_gpr[rS(ctx->opcode)]);
6553 tcg_temp_free_i32(t0);
6554 }
6555 break;
6556 default:
6557 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6558 break;
6559 }
6560 #endif
6561 }
6562
6563 /* TLB management - PowerPC BookE 2.06 implementation */
6564
6565 /* tlbre */
6566 static void gen_tlbre_booke206(DisasContext *ctx)
6567 {
6568 #if defined(CONFIG_USER_ONLY)
6569 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6570 #else
6571 if (unlikely(ctx->pr)) {
6572 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6573 return;
6574 }
6575
6576 gen_helper_booke206_tlbre(cpu_env);
6577 #endif
6578 }
6579
6580 /* tlbsx - tlbsx. */
6581 static void gen_tlbsx_booke206(DisasContext *ctx)
6582 {
6583 #if defined(CONFIG_USER_ONLY)
6584 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6585 #else
6586 TCGv t0;
6587 if (unlikely(ctx->pr)) {
6588 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6589 return;
6590 }
6591
6592 if (rA(ctx->opcode)) {
6593 t0 = tcg_temp_new();
6594 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6595 } else {
6596 t0 = tcg_const_tl(0);
6597 }
6598
6599 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6600 gen_helper_booke206_tlbsx(cpu_env, t0);
6601 tcg_temp_free(t0);
6602 #endif
6603 }
6604
6605 /* tlbwe */
6606 static void gen_tlbwe_booke206(DisasContext *ctx)
6607 {
6608 #if defined(CONFIG_USER_ONLY)
6609 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6610 #else
6611 if (unlikely(ctx->pr)) {
6612 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6613 return;
6614 }
6615 gen_update_nip(ctx, ctx->nip - 4);
6616 gen_helper_booke206_tlbwe(cpu_env);
6617 #endif
6618 }
6619
6620 static void gen_tlbivax_booke206(DisasContext *ctx)
6621 {
6622 #if defined(CONFIG_USER_ONLY)
6623 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6624 #else
6625 TCGv t0;
6626 if (unlikely(ctx->pr)) {
6627 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6628 return;
6629 }
6630
6631 t0 = tcg_temp_new();
6632 gen_addr_reg_index(ctx, t0);
6633
6634 gen_helper_booke206_tlbivax(cpu_env, t0);
6635 tcg_temp_free(t0);
6636 #endif
6637 }
6638
6639 static void gen_tlbilx_booke206(DisasContext *ctx)
6640 {
6641 #if defined(CONFIG_USER_ONLY)
6642 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6643 #else
6644 TCGv t0;
6645 if (unlikely(ctx->pr)) {
6646 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6647 return;
6648 }
6649
6650 t0 = tcg_temp_new();
6651 gen_addr_reg_index(ctx, t0);
6652
6653 switch((ctx->opcode >> 21) & 0x3) {
6654 case 0:
6655 gen_helper_booke206_tlbilx0(cpu_env, t0);
6656 break;
6657 case 1:
6658 gen_helper_booke206_tlbilx1(cpu_env, t0);
6659 break;
6660 case 3:
6661 gen_helper_booke206_tlbilx3(cpu_env, t0);
6662 break;
6663 default:
6664 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6665 break;
6666 }
6667
6668 tcg_temp_free(t0);
6669 #endif
6670 }
6671
6672
6673 /* wrtee */
6674 static void gen_wrtee(DisasContext *ctx)
6675 {
6676 #if defined(CONFIG_USER_ONLY)
6677 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6678 #else
6679 TCGv t0;
6680 if (unlikely(ctx->pr)) {
6681 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6682 return;
6683 }
6684 t0 = tcg_temp_new();
6685 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6686 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6687 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6688 tcg_temp_free(t0);
6689 /* Stop translation to have a chance to raise an exception
6690 * if we just set msr_ee to 1
6691 */
6692 gen_stop_exception(ctx);
6693 #endif
6694 }
6695
6696 /* wrteei */
6697 static void gen_wrteei(DisasContext *ctx)
6698 {
6699 #if defined(CONFIG_USER_ONLY)
6700 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6701 #else
6702 if (unlikely(ctx->pr)) {
6703 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6704 return;
6705 }
6706 if (ctx->opcode & 0x00008000) {
6707 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6708 /* Stop translation to have a chance to raise an exception */
6709 gen_stop_exception(ctx);
6710 } else {
6711 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6712 }
6713 #endif
6714 }
6715
6716 /* PowerPC 440 specific instructions */
6717
6718 /* dlmzb */
6719 static void gen_dlmzb(DisasContext *ctx)
6720 {
6721 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6722 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6723 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6724 tcg_temp_free_i32(t0);
6725 }
6726
6727 /* mbar replaces eieio on 440 */
6728 static void gen_mbar(DisasContext *ctx)
6729 {
6730 /* interpreted as no-op */
6731 }
6732
6733 /* msync replaces sync on 440 */
6734 static void gen_msync_4xx(DisasContext *ctx)
6735 {
6736 /* interpreted as no-op */
6737 }
6738
6739 /* icbt */
6740 static void gen_icbt_440(DisasContext *ctx)
6741 {
6742 /* interpreted as no-op */
6743 /* XXX: specification say this is treated as a load by the MMU
6744 * but does not generate any exception
6745 */
6746 }
6747
6748 /* Embedded.Processor Control */
6749
6750 static void gen_msgclr(DisasContext *ctx)
6751 {
6752 #if defined(CONFIG_USER_ONLY)
6753 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6754 #else
6755 if (unlikely(ctx->pr)) {
6756 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6757 return;
6758 }
6759
6760 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6761 #endif
6762 }
6763
6764 static void gen_msgsnd(DisasContext *ctx)
6765 {
6766 #if defined(CONFIG_USER_ONLY)
6767 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6768 #else
6769 if (unlikely(ctx->pr)) {
6770 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6771 return;
6772 }
6773
6774 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6775 #endif
6776 }
6777
6778 /*** Altivec vector extension ***/
6779 /* Altivec registers moves */
6780
6781 static inline TCGv_ptr gen_avr_ptr(int reg)
6782 {
6783 TCGv_ptr r = tcg_temp_new_ptr();
6784 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6785 return r;
6786 }
6787
6788 #define GEN_VR_LDX(name, opc2, opc3) \
6789 static void glue(gen_, name)(DisasContext *ctx) \
6790 { \
6791 TCGv EA; \
6792 if (unlikely(!ctx->altivec_enabled)) { \
6793 gen_exception(ctx, POWERPC_EXCP_VPU); \
6794 return; \
6795 } \
6796 gen_set_access_type(ctx, ACCESS_INT); \
6797 EA = tcg_temp_new(); \
6798 gen_addr_reg_index(ctx, EA); \
6799 tcg_gen_andi_tl(EA, EA, ~0xf); \
6800 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6801 64-bit byteswap already. */ \
6802 if (ctx->le_mode) { \
6803 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6804 tcg_gen_addi_tl(EA, EA, 8); \
6805 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6806 } else { \
6807 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6808 tcg_gen_addi_tl(EA, EA, 8); \
6809 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6810 } \
6811 tcg_temp_free(EA); \
6812 }
6813
6814 #define GEN_VR_STX(name, opc2, opc3) \
6815 static void gen_st##name(DisasContext *ctx) \
6816 { \
6817 TCGv EA; \
6818 if (unlikely(!ctx->altivec_enabled)) { \
6819 gen_exception(ctx, POWERPC_EXCP_VPU); \
6820 return; \
6821 } \
6822 gen_set_access_type(ctx, ACCESS_INT); \
6823 EA = tcg_temp_new(); \
6824 gen_addr_reg_index(ctx, EA); \
6825 tcg_gen_andi_tl(EA, EA, ~0xf); \
6826 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6827 64-bit byteswap already. */ \
6828 if (ctx->le_mode) { \
6829 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6830 tcg_gen_addi_tl(EA, EA, 8); \
6831 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6832 } else { \
6833 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6834 tcg_gen_addi_tl(EA, EA, 8); \
6835 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6836 } \
6837 tcg_temp_free(EA); \
6838 }
6839
6840 #define GEN_VR_LVE(name, opc2, opc3, size) \
6841 static void gen_lve##name(DisasContext *ctx) \
6842 { \
6843 TCGv EA; \
6844 TCGv_ptr rs; \
6845 if (unlikely(!ctx->altivec_enabled)) { \
6846 gen_exception(ctx, POWERPC_EXCP_VPU); \
6847 return; \
6848 } \
6849 gen_set_access_type(ctx, ACCESS_INT); \
6850 EA = tcg_temp_new(); \
6851 gen_addr_reg_index(ctx, EA); \
6852 if (size > 1) { \
6853 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6854 } \
6855 rs = gen_avr_ptr(rS(ctx->opcode)); \
6856 gen_helper_lve##name(cpu_env, rs, EA); \
6857 tcg_temp_free(EA); \
6858 tcg_temp_free_ptr(rs); \
6859 }
6860
6861 #define GEN_VR_STVE(name, opc2, opc3, size) \
6862 static void gen_stve##name(DisasContext *ctx) \
6863 { \
6864 TCGv EA; \
6865 TCGv_ptr rs; \
6866 if (unlikely(!ctx->altivec_enabled)) { \
6867 gen_exception(ctx, POWERPC_EXCP_VPU); \
6868 return; \
6869 } \
6870 gen_set_access_type(ctx, ACCESS_INT); \
6871 EA = tcg_temp_new(); \
6872 gen_addr_reg_index(ctx, EA); \
6873 if (size > 1) { \
6874 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6875 } \
6876 rs = gen_avr_ptr(rS(ctx->opcode)); \
6877 gen_helper_stve##name(cpu_env, rs, EA); \
6878 tcg_temp_free(EA); \
6879 tcg_temp_free_ptr(rs); \
6880 }
6881
6882 GEN_VR_LDX(lvx, 0x07, 0x03);
6883 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6884 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6885
6886 GEN_VR_LVE(bx, 0x07, 0x00, 1);
6887 GEN_VR_LVE(hx, 0x07, 0x01, 2);
6888 GEN_VR_LVE(wx, 0x07, 0x02, 4);
6889
6890 GEN_VR_STX(svx, 0x07, 0x07);
6891 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6892 GEN_VR_STX(svxl, 0x07, 0x0F);
6893
6894 GEN_VR_STVE(bx, 0x07, 0x04, 1);
6895 GEN_VR_STVE(hx, 0x07, 0x05, 2);
6896 GEN_VR_STVE(wx, 0x07, 0x06, 4);
6897
6898 static void gen_lvsl(DisasContext *ctx)
6899 {
6900 TCGv_ptr rd;
6901 TCGv EA;
6902 if (unlikely(!ctx->altivec_enabled)) {
6903 gen_exception(ctx, POWERPC_EXCP_VPU);
6904 return;
6905 }
6906 EA = tcg_temp_new();
6907 gen_addr_reg_index(ctx, EA);
6908 rd = gen_avr_ptr(rD(ctx->opcode));
6909 gen_helper_lvsl(rd, EA);
6910 tcg_temp_free(EA);
6911 tcg_temp_free_ptr(rd);
6912 }
6913
6914 static void gen_lvsr(DisasContext *ctx)
6915 {
6916 TCGv_ptr rd;
6917 TCGv EA;
6918 if (unlikely(!ctx->altivec_enabled)) {
6919 gen_exception(ctx, POWERPC_EXCP_VPU);
6920 return;
6921 }
6922 EA = tcg_temp_new();
6923 gen_addr_reg_index(ctx, EA);
6924 rd = gen_avr_ptr(rD(ctx->opcode));
6925 gen_helper_lvsr(rd, EA);
6926 tcg_temp_free(EA);
6927 tcg_temp_free_ptr(rd);
6928 }
6929
6930 static void gen_mfvscr(DisasContext *ctx)
6931 {
6932 TCGv_i32 t;
6933 if (unlikely(!ctx->altivec_enabled)) {
6934 gen_exception(ctx, POWERPC_EXCP_VPU);
6935 return;
6936 }
6937 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6938 t = tcg_temp_new_i32();
6939 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6940 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6941 tcg_temp_free_i32(t);
6942 }
6943
6944 static void gen_mtvscr(DisasContext *ctx)
6945 {
6946 TCGv_ptr p;
6947 if (unlikely(!ctx->altivec_enabled)) {
6948 gen_exception(ctx, POWERPC_EXCP_VPU);
6949 return;
6950 }
6951 p = gen_avr_ptr(rB(ctx->opcode));
6952 gen_helper_mtvscr(cpu_env, p);
6953 tcg_temp_free_ptr(p);
6954 }
6955
6956 /* Logical operations */
6957 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6958 static void glue(gen_, name)(DisasContext *ctx) \
6959 { \
6960 if (unlikely(!ctx->altivec_enabled)) { \
6961 gen_exception(ctx, POWERPC_EXCP_VPU); \
6962 return; \
6963 } \
6964 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6965 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6966 }
6967
6968 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6969 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6970 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6971 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6972 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6973 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
6974 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
6975 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
6976
6977 #define GEN_VXFORM(name, opc2, opc3) \
6978 static void glue(gen_, name)(DisasContext *ctx) \
6979 { \
6980 TCGv_ptr ra, rb, rd; \
6981 if (unlikely(!ctx->altivec_enabled)) { \
6982 gen_exception(ctx, POWERPC_EXCP_VPU); \
6983 return; \
6984 } \
6985 ra = gen_avr_ptr(rA(ctx->opcode)); \
6986 rb = gen_avr_ptr(rB(ctx->opcode)); \
6987 rd = gen_avr_ptr(rD(ctx->opcode)); \
6988 gen_helper_##name (rd, ra, rb); \
6989 tcg_temp_free_ptr(ra); \
6990 tcg_temp_free_ptr(rb); \
6991 tcg_temp_free_ptr(rd); \
6992 }
6993
6994 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6995 static void glue(gen_, name)(DisasContext *ctx) \
6996 { \
6997 TCGv_ptr ra, rb, rd; \
6998 if (unlikely(!ctx->altivec_enabled)) { \
6999 gen_exception(ctx, POWERPC_EXCP_VPU); \
7000 return; \
7001 } \
7002 ra = gen_avr_ptr(rA(ctx->opcode)); \
7003 rb = gen_avr_ptr(rB(ctx->opcode)); \
7004 rd = gen_avr_ptr(rD(ctx->opcode)); \
7005 gen_helper_##name(cpu_env, rd, ra, rb); \
7006 tcg_temp_free_ptr(ra); \
7007 tcg_temp_free_ptr(rb); \
7008 tcg_temp_free_ptr(rd); \
7009 }
7010
7011 #define GEN_VXFORM3(name, opc2, opc3) \
7012 static void glue(gen_, name)(DisasContext *ctx) \
7013 { \
7014 TCGv_ptr ra, rb, rc, rd; \
7015 if (unlikely(!ctx->altivec_enabled)) { \
7016 gen_exception(ctx, POWERPC_EXCP_VPU); \
7017 return; \
7018 } \
7019 ra = gen_avr_ptr(rA(ctx->opcode)); \
7020 rb = gen_avr_ptr(rB(ctx->opcode)); \
7021 rc = gen_avr_ptr(rC(ctx->opcode)); \
7022 rd = gen_avr_ptr(rD(ctx->opcode)); \
7023 gen_helper_##name(rd, ra, rb, rc); \
7024 tcg_temp_free_ptr(ra); \
7025 tcg_temp_free_ptr(rb); \
7026 tcg_temp_free_ptr(rc); \
7027 tcg_temp_free_ptr(rd); \
7028 }
7029
7030 /*
7031 * Support for Altivec instruction pairs that use bit 31 (Rc) as
7032 * an opcode bit. In general, these pairs come from different
7033 * versions of the ISA, so we must also support a pair of flags for
7034 * each instruction.
7035 */
7036 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7037 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7038 { \
7039 if ((Rc(ctx->opcode) == 0) && \
7040 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7041 gen_##name0(ctx); \
7042 } else if ((Rc(ctx->opcode) == 1) && \
7043 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7044 gen_##name1(ctx); \
7045 } else { \
7046 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7047 } \
7048 }
7049
7050 GEN_VXFORM(vaddubm, 0, 0);
7051 GEN_VXFORM(vadduhm, 0, 1);
7052 GEN_VXFORM(vadduwm, 0, 2);
7053 GEN_VXFORM(vaddudm, 0, 3);
7054 GEN_VXFORM(vsububm, 0, 16);
7055 GEN_VXFORM(vsubuhm, 0, 17);
7056 GEN_VXFORM(vsubuwm, 0, 18);
7057 GEN_VXFORM(vsubudm, 0, 19);
7058 GEN_VXFORM(vmaxub, 1, 0);
7059 GEN_VXFORM(vmaxuh, 1, 1);
7060 GEN_VXFORM(vmaxuw, 1, 2);
7061 GEN_VXFORM(vmaxud, 1, 3);
7062 GEN_VXFORM(vmaxsb, 1, 4);
7063 GEN_VXFORM(vmaxsh, 1, 5);
7064 GEN_VXFORM(vmaxsw, 1, 6);
7065 GEN_VXFORM(vmaxsd, 1, 7);
7066 GEN_VXFORM(vminub, 1, 8);
7067 GEN_VXFORM(vminuh, 1, 9);
7068 GEN_VXFORM(vminuw, 1, 10);
7069 GEN_VXFORM(vminud, 1, 11);
7070 GEN_VXFORM(vminsb, 1, 12);
7071 GEN_VXFORM(vminsh, 1, 13);
7072 GEN_VXFORM(vminsw, 1, 14);
7073 GEN_VXFORM(vminsd, 1, 15);
7074 GEN_VXFORM(vavgub, 1, 16);
7075 GEN_VXFORM(vavguh, 1, 17);
7076 GEN_VXFORM(vavguw, 1, 18);
7077 GEN_VXFORM(vavgsb, 1, 20);
7078 GEN_VXFORM(vavgsh, 1, 21);
7079 GEN_VXFORM(vavgsw, 1, 22);
7080 GEN_VXFORM(vmrghb, 6, 0);
7081 GEN_VXFORM(vmrghh, 6, 1);
7082 GEN_VXFORM(vmrghw, 6, 2);
7083 GEN_VXFORM(vmrglb, 6, 4);
7084 GEN_VXFORM(vmrglh, 6, 5);
7085 GEN_VXFORM(vmrglw, 6, 6);
7086
7087 static void gen_vmrgew(DisasContext *ctx)
7088 {
7089 TCGv_i64 tmp;
7090 int VT, VA, VB;
7091 if (unlikely(!ctx->altivec_enabled)) {
7092 gen_exception(ctx, POWERPC_EXCP_VPU);
7093 return;
7094 }
7095 VT = rD(ctx->opcode);
7096 VA = rA(ctx->opcode);
7097 VB = rB(ctx->opcode);
7098 tmp = tcg_temp_new_i64();
7099 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7100 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7101 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7102 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7103 tcg_temp_free_i64(tmp);
7104 }
7105
7106 static void gen_vmrgow(DisasContext *ctx)
7107 {
7108 int VT, VA, VB;
7109 if (unlikely(!ctx->altivec_enabled)) {
7110 gen_exception(ctx, POWERPC_EXCP_VPU);
7111 return;
7112 }
7113 VT = rD(ctx->opcode);
7114 VA = rA(ctx->opcode);
7115 VB = rB(ctx->opcode);
7116
7117 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7118 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7119 }
7120
7121 GEN_VXFORM(vmuloub, 4, 0);
7122 GEN_VXFORM(vmulouh, 4, 1);
7123 GEN_VXFORM(vmulouw, 4, 2);
7124 GEN_VXFORM(vmuluwm, 4, 2);
7125 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7126 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
7127 GEN_VXFORM(vmulosb, 4, 4);
7128 GEN_VXFORM(vmulosh, 4, 5);
7129 GEN_VXFORM(vmulosw, 4, 6);
7130 GEN_VXFORM(vmuleub, 4, 8);
7131 GEN_VXFORM(vmuleuh, 4, 9);
7132 GEN_VXFORM(vmuleuw, 4, 10);
7133 GEN_VXFORM(vmulesb, 4, 12);
7134 GEN_VXFORM(vmulesh, 4, 13);
7135 GEN_VXFORM(vmulesw, 4, 14);
7136 GEN_VXFORM(vslb, 2, 4);
7137 GEN_VXFORM(vslh, 2, 5);
7138 GEN_VXFORM(vslw, 2, 6);
7139 GEN_VXFORM(vsld, 2, 23);
7140 GEN_VXFORM(vsrb, 2, 8);
7141 GEN_VXFORM(vsrh, 2, 9);
7142 GEN_VXFORM(vsrw, 2, 10);
7143 GEN_VXFORM(vsrd, 2, 27);
7144 GEN_VXFORM(vsrab, 2, 12);
7145 GEN_VXFORM(vsrah, 2, 13);
7146 GEN_VXFORM(vsraw, 2, 14);
7147 GEN_VXFORM(vsrad, 2, 15);
7148 GEN_VXFORM(vslo, 6, 16);
7149 GEN_VXFORM(vsro, 6, 17);
7150 GEN_VXFORM(vaddcuw, 0, 6);
7151 GEN_VXFORM(vsubcuw, 0, 22);
7152 GEN_VXFORM_ENV(vaddubs, 0, 8);
7153 GEN_VXFORM_ENV(vadduhs, 0, 9);
7154 GEN_VXFORM_ENV(vadduws, 0, 10);
7155 GEN_VXFORM_ENV(vaddsbs, 0, 12);
7156 GEN_VXFORM_ENV(vaddshs, 0, 13);
7157 GEN_VXFORM_ENV(vaddsws, 0, 14);
7158 GEN_VXFORM_ENV(vsububs, 0, 24);
7159 GEN_VXFORM_ENV(vsubuhs, 0, 25);
7160 GEN_VXFORM_ENV(vsubuws, 0, 26);
7161 GEN_VXFORM_ENV(vsubsbs, 0, 28);
7162 GEN_VXFORM_ENV(vsubshs, 0, 29);
7163 GEN_VXFORM_ENV(vsubsws, 0, 30);
7164 GEN_VXFORM(vadduqm, 0, 4);
7165 GEN_VXFORM(vaddcuq, 0, 5);
7166 GEN_VXFORM3(vaddeuqm, 30, 0);
7167 GEN_VXFORM3(vaddecuq, 30, 0);
7168 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7169 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7170 GEN_VXFORM(vsubuqm, 0, 20);
7171 GEN_VXFORM(vsubcuq, 0, 21);
7172 GEN_VXFORM3(vsubeuqm, 31, 0);
7173 GEN_VXFORM3(vsubecuq, 31, 0);
7174 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7175 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
7176 GEN_VXFORM(vrlb, 2, 0);
7177 GEN_VXFORM(vrlh, 2, 1);
7178 GEN_VXFORM(vrlw, 2, 2);
7179 GEN_VXFORM(vrld, 2, 3);
7180 GEN_VXFORM(vsl, 2, 7);
7181 GEN_VXFORM(vsr, 2, 11);
7182 GEN_VXFORM_ENV(vpkuhum, 7, 0);
7183 GEN_VXFORM_ENV(vpkuwum, 7, 1);
7184 GEN_VXFORM_ENV(vpkudum, 7, 17);
7185 GEN_VXFORM_ENV(vpkuhus, 7, 2);
7186 GEN_VXFORM_ENV(vpkuwus, 7, 3);
7187 GEN_VXFORM_ENV(vpkudus, 7, 19);
7188 GEN_VXFORM_ENV(vpkshus, 7, 4);
7189 GEN_VXFORM_ENV(vpkswus, 7, 5);
7190 GEN_VXFORM_ENV(vpksdus, 7, 21);
7191 GEN_VXFORM_ENV(vpkshss, 7, 6);
7192 GEN_VXFORM_ENV(vpkswss, 7, 7);
7193 GEN_VXFORM_ENV(vpksdss, 7, 23);
7194 GEN_VXFORM(vpkpx, 7, 12);
7195 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7196 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7197 GEN_VXFORM_ENV(vsum4shs, 4, 25);
7198 GEN_VXFORM_ENV(vsum2sws, 4, 26);
7199 GEN_VXFORM_ENV(vsumsws, 4, 30);
7200 GEN_VXFORM_ENV(vaddfp, 5, 0);
7201 GEN_VXFORM_ENV(vsubfp, 5, 1);
7202 GEN_VXFORM_ENV(vmaxfp, 5, 16);
7203 GEN_VXFORM_ENV(vminfp, 5, 17);
7204
7205 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7206 static void glue(gen_, name)(DisasContext *ctx) \
7207 { \
7208 TCGv_ptr ra, rb, rd; \
7209 if (unlikely(!ctx->altivec_enabled)) { \
7210 gen_exception(ctx, POWERPC_EXCP_VPU); \
7211 return; \
7212 } \
7213 ra = gen_avr_ptr(rA(ctx->opcode)); \
7214 rb = gen_avr_ptr(rB(ctx->opcode)); \
7215 rd = gen_avr_ptr(rD(ctx->opcode)); \
7216 gen_helper_##opname(cpu_env, rd, ra, rb); \
7217 tcg_temp_free_ptr(ra); \
7218 tcg_temp_free_ptr(rb); \
7219 tcg_temp_free_ptr(rd); \
7220 }
7221
7222 #define GEN_VXRFORM(name, opc2, opc3) \
7223 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7224 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7225
7226 /*
7227 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7228 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7229 * come from different versions of the ISA, so we must also support a
7230 * pair of flags for each instruction.
7231 */
7232 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7233 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7234 { \
7235 if ((Rc(ctx->opcode) == 0) && \
7236 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7237 if (Rc21(ctx->opcode) == 0) { \
7238 gen_##name0(ctx); \
7239 } else { \
7240 gen_##name0##_(ctx); \
7241 } \
7242 } else if ((Rc(ctx->opcode) == 1) && \
7243 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7244 if (Rc21(ctx->opcode) == 0) { \
7245 gen_##name1(ctx); \
7246 } else { \
7247 gen_##name1##_(ctx); \
7248 } \
7249 } else { \
7250 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7251 } \
7252 }
7253
7254 GEN_VXRFORM(vcmpequb, 3, 0)
7255 GEN_VXRFORM(vcmpequh, 3, 1)
7256 GEN_VXRFORM(vcmpequw, 3, 2)
7257 GEN_VXRFORM(vcmpequd, 3, 3)
7258 GEN_VXRFORM(vcmpgtsb, 3, 12)
7259 GEN_VXRFORM(vcmpgtsh, 3, 13)
7260 GEN_VXRFORM(vcmpgtsw, 3, 14)
7261 GEN_VXRFORM(vcmpgtsd, 3, 15)
7262 GEN_VXRFORM(vcmpgtub, 3, 8)
7263 GEN_VXRFORM(vcmpgtuh, 3, 9)
7264 GEN_VXRFORM(vcmpgtuw, 3, 10)
7265 GEN_VXRFORM(vcmpgtud, 3, 11)
7266 GEN_VXRFORM(vcmpeqfp, 3, 3)
7267 GEN_VXRFORM(vcmpgefp, 3, 7)
7268 GEN_VXRFORM(vcmpgtfp, 3, 11)
7269 GEN_VXRFORM(vcmpbfp, 3, 15)
7270
7271 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7272 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7273 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7274 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7275 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7276 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7277
7278 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7279 static void glue(gen_, name)(DisasContext *ctx) \
7280 { \
7281 TCGv_ptr rd; \
7282 TCGv_i32 simm; \
7283 if (unlikely(!ctx->altivec_enabled)) { \
7284 gen_exception(ctx, POWERPC_EXCP_VPU); \
7285 return; \
7286 } \
7287 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7288 rd = gen_avr_ptr(rD(ctx->opcode)); \
7289 gen_helper_##name (rd, simm); \
7290 tcg_temp_free_i32(simm); \
7291 tcg_temp_free_ptr(rd); \
7292 }
7293
7294 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7295 GEN_VXFORM_SIMM(vspltish, 6, 13);
7296 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7297
7298 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7299 static void glue(gen_, name)(DisasContext *ctx) \
7300 { \
7301 TCGv_ptr rb, rd; \
7302 if (unlikely(!ctx->altivec_enabled)) { \
7303 gen_exception(ctx, POWERPC_EXCP_VPU); \
7304 return; \
7305 } \
7306 rb = gen_avr_ptr(rB(ctx->opcode)); \
7307 rd = gen_avr_ptr(rD(ctx->opcode)); \
7308 gen_helper_##name (rd, rb); \
7309 tcg_temp_free_ptr(rb); \
7310 tcg_temp_free_ptr(rd); \
7311 }
7312
7313 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7314 static void glue(gen_, name)(DisasContext *ctx) \
7315 { \
7316 TCGv_ptr rb, rd; \
7317 \
7318 if (unlikely(!ctx->altivec_enabled)) { \
7319 gen_exception(ctx, POWERPC_EXCP_VPU); \
7320 return; \
7321 } \
7322 rb = gen_avr_ptr(rB(ctx->opcode)); \
7323 rd = gen_avr_ptr(rD(ctx->opcode)); \
7324 gen_helper_##name(cpu_env, rd, rb); \
7325 tcg_temp_free_ptr(rb); \
7326 tcg_temp_free_ptr(rd); \
7327 }
7328
7329 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7330 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7331 GEN_VXFORM_NOA(vupkhsw, 7, 25);
7332 GEN_VXFORM_NOA(vupklsb, 7, 10);
7333 GEN_VXFORM_NOA(vupklsh, 7, 11);
7334 GEN_VXFORM_NOA(vupklsw, 7, 27);
7335 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7336 GEN_VXFORM_NOA(vupklpx, 7, 15);
7337 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7338 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7339 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7340 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7341 GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
7342 GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
7343 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7344 GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
7345
7346 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7347 static void glue(gen_, name)(DisasContext *ctx) \
7348 { \
7349 TCGv_ptr rd; \
7350 TCGv_i32 simm; \
7351 if (unlikely(!ctx->altivec_enabled)) { \
7352 gen_exception(ctx, POWERPC_EXCP_VPU); \
7353 return; \
7354 } \
7355 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7356 rd = gen_avr_ptr(rD(ctx->opcode)); \
7357 gen_helper_##name (rd, simm); \
7358 tcg_temp_free_i32(simm); \
7359 tcg_temp_free_ptr(rd); \
7360 }
7361
7362 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7363 static void glue(gen_, name)(DisasContext *ctx) \
7364 { \
7365 TCGv_ptr rb, rd; \
7366 TCGv_i32 uimm; \
7367 if (unlikely(!ctx->altivec_enabled)) { \
7368 gen_exception(ctx, POWERPC_EXCP_VPU); \
7369 return; \
7370 } \
7371 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7372 rb = gen_avr_ptr(rB(ctx->opcode)); \
7373 rd = gen_avr_ptr(rD(ctx->opcode)); \
7374 gen_helper_##name (rd, rb, uimm); \
7375 tcg_temp_free_i32(uimm); \
7376 tcg_temp_free_ptr(rb); \
7377 tcg_temp_free_ptr(rd); \
7378 }
7379
7380 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7381 static void glue(gen_, name)(DisasContext *ctx) \
7382 { \
7383 TCGv_ptr rb, rd; \
7384 TCGv_i32 uimm; \
7385 \
7386 if (unlikely(!ctx->altivec_enabled)) { \
7387 gen_exception(ctx, POWERPC_EXCP_VPU); \
7388 return; \
7389 } \
7390 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7391 rb = gen_avr_ptr(rB(ctx->opcode)); \
7392 rd = gen_avr_ptr(rD(ctx->opcode)); \
7393 gen_helper_##name(cpu_env, rd, rb, uimm); \
7394 tcg_temp_free_i32(uimm); \
7395 tcg_temp_free_ptr(rb); \
7396 tcg_temp_free_ptr(rd); \
7397 }
7398
7399 GEN_VXFORM_UIMM(vspltb, 6, 8);
7400 GEN_VXFORM_UIMM(vsplth, 6, 9);
7401 GEN_VXFORM_UIMM(vspltw, 6, 10);
7402 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7403 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7404 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7405 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7406
7407 static void gen_vsldoi(DisasContext *ctx)
7408 {
7409 TCGv_ptr ra, rb, rd;
7410 TCGv_i32 sh;
7411 if (unlikely(!ctx->altivec_enabled)) {
7412 gen_exception(ctx, POWERPC_EXCP_VPU);
7413 return;
7414 }
7415 ra = gen_avr_ptr(rA(ctx->opcode));
7416 rb = gen_avr_ptr(rB(ctx->opcode));
7417 rd = gen_avr_ptr(rD(ctx->opcode));
7418 sh = tcg_const_i32(VSH(ctx->opcode));
7419 gen_helper_vsldoi (rd, ra, rb, sh);
7420 tcg_temp_free_ptr(ra);
7421 tcg_temp_free_ptr(rb);
7422 tcg_temp_free_ptr(rd);
7423 tcg_temp_free_i32(sh);
7424 }
7425
7426 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7427 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7428 { \
7429 TCGv_ptr ra, rb, rc, rd; \
7430 if (unlikely(!ctx->altivec_enabled)) { \
7431 gen_exception(ctx, POWERPC_EXCP_VPU); \
7432 return; \
7433 } \
7434 ra = gen_avr_ptr(rA(ctx->opcode)); \
7435 rb = gen_avr_ptr(rB(ctx->opcode)); \
7436 rc = gen_avr_ptr(rC(ctx->opcode)); \
7437 rd = gen_avr_ptr(rD(ctx->opcode)); \
7438 if (Rc(ctx->opcode)) { \
7439 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7440 } else { \
7441 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7442 } \
7443 tcg_temp_free_ptr(ra); \
7444 tcg_temp_free_ptr(rb); \
7445 tcg_temp_free_ptr(rc); \
7446 tcg_temp_free_ptr(rd); \
7447 }
7448
7449 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7450
7451 static void gen_vmladduhm(DisasContext *ctx)
7452 {
7453 TCGv_ptr ra, rb, rc, rd;
7454 if (unlikely(!ctx->altivec_enabled)) {
7455 gen_exception(ctx, POWERPC_EXCP_VPU);
7456 return;
7457 }
7458 ra = gen_avr_ptr(rA(ctx->opcode));
7459 rb = gen_avr_ptr(rB(ctx->opcode));
7460 rc = gen_avr_ptr(rC(ctx->opcode));
7461 rd = gen_avr_ptr(rD(ctx->opcode));
7462 gen_helper_vmladduhm(rd, ra, rb, rc);
7463 tcg_temp_free_ptr(ra);
7464 tcg_temp_free_ptr(rb);
7465 tcg_temp_free_ptr(rc);
7466 tcg_temp_free_ptr(rd);
7467 }
7468
7469 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7470 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7471 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7472 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7473 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7474
7475 GEN_VXFORM_NOA(vclzb, 1, 28)
7476 GEN_VXFORM_NOA(vclzh, 1, 29)
7477 GEN_VXFORM_NOA(vclzw, 1, 30)
7478 GEN_VXFORM_NOA(vclzd, 1, 31)
7479 GEN_VXFORM_NOA(vpopcntb, 1, 28)
7480 GEN_VXFORM_NOA(vpopcnth, 1, 29)
7481 GEN_VXFORM_NOA(vpopcntw, 1, 30)
7482 GEN_VXFORM_NOA(vpopcntd, 1, 31)
7483 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7484 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7485 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7486 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7487 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7488 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7489 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7490 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
7491 GEN_VXFORM(vbpermq, 6, 21);
7492 GEN_VXFORM_NOA(vgbbd, 6, 20);
7493 GEN_VXFORM(vpmsumb, 4, 16)
7494 GEN_VXFORM(vpmsumh, 4, 17)
7495 GEN_VXFORM(vpmsumw, 4, 18)
7496 GEN_VXFORM(vpmsumd, 4, 19)
7497
7498 #define GEN_BCD(op) \
7499 static void gen_##op(DisasContext *ctx) \
7500 { \
7501 TCGv_ptr ra, rb, rd; \
7502 TCGv_i32 ps; \
7503 \
7504 if (unlikely(!ctx->altivec_enabled)) { \
7505 gen_exception(ctx, POWERPC_EXCP_VPU); \
7506 return; \
7507 } \
7508 \
7509 ra = gen_avr_ptr(rA(ctx->opcode)); \
7510 rb = gen_avr_ptr(rB(ctx->opcode)); \
7511 rd = gen_avr_ptr(rD(ctx->opcode)); \
7512 \
7513 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7514 \
7515 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7516 \
7517 tcg_temp_free_ptr(ra); \
7518 tcg_temp_free_ptr(rb); \
7519 tcg_temp_free_ptr(rd); \
7520 tcg_temp_free_i32(ps); \
7521 }
7522
7523 GEN_BCD(bcdadd)
7524 GEN_BCD(bcdsub)
7525
7526 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7527 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7528 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7529 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7530 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7531 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7532 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7533 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7534
7535 static void gen_vsbox(DisasContext *ctx)
7536 {
7537 TCGv_ptr ra, rd;
7538 if (unlikely(!ctx->altivec_enabled)) {
7539 gen_exception(ctx, POWERPC_EXCP_VPU);
7540 return;
7541 }
7542 ra = gen_avr_ptr(rA(ctx->opcode));
7543 rd = gen_avr_ptr(rD(ctx->opcode));
7544 gen_helper_vsbox(rd, ra);
7545 tcg_temp_free_ptr(ra);
7546 tcg_temp_free_ptr(rd);
7547 }
7548
7549 GEN_VXFORM(vcipher, 4, 20)
7550 GEN_VXFORM(vcipherlast, 4, 20)
7551 GEN_VXFORM(vncipher, 4, 21)
7552 GEN_VXFORM(vncipherlast, 4, 21)
7553
7554 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7555 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7556 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7557 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7558
7559 #define VSHASIGMA(op) \
7560 static void gen_##op(DisasContext *ctx) \
7561 { \
7562 TCGv_ptr ra, rd; \
7563 TCGv_i32 st_six; \
7564 if (unlikely(!ctx->altivec_enabled)) { \
7565 gen_exception(ctx, POWERPC_EXCP_VPU); \
7566 return; \
7567 } \
7568 ra = gen_avr_ptr(rA(ctx->opcode)); \
7569 rd = gen_avr_ptr(rD(ctx->opcode)); \
7570 st_six = tcg_const_i32(rB(ctx->opcode)); \
7571 gen_helper_##op(rd, ra, st_six); \
7572 tcg_temp_free_ptr(ra); \
7573 tcg_temp_free_ptr(rd); \
7574 tcg_temp_free_i32(st_six); \
7575 }
7576
7577 VSHASIGMA(vshasigmaw)
7578 VSHASIGMA(vshasigmad)
7579
7580 GEN_VXFORM3(vpermxor, 22, 0xFF)
7581 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7582 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7583
7584 /*** VSX extension ***/
7585
7586 static inline TCGv_i64 cpu_vsrh(int n)
7587 {
7588 if (n < 32) {
7589 return cpu_fpr[n];
7590 } else {
7591 return cpu_avrh[n-32];
7592 }
7593 }
7594
7595 static inline TCGv_i64 cpu_vsrl(int n)
7596 {
7597 if (n < 32) {
7598 return cpu_vsr[n];
7599 } else {
7600 return cpu_avrl[n-32];
7601 }
7602 }
7603
7604 #define VSX_LOAD_SCALAR(name, operation) \
7605 static void gen_##name(DisasContext *ctx) \
7606 { \
7607 TCGv EA; \
7608 if (unlikely(!ctx->vsx_enabled)) { \
7609 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7610 return; \
7611 } \
7612 gen_set_access_type(ctx, ACCESS_INT); \
7613 EA = tcg_temp_new(); \
7614 gen_addr_reg_index(ctx, EA); \
7615 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7616 /* NOTE: cpu_vsrl is undefined */ \
7617 tcg_temp_free(EA); \
7618 }
7619
7620 VSX_LOAD_SCALAR(lxsdx, ld64)
7621 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7622 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7623 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7624
7625 static void gen_lxvd2x(DisasContext *ctx)
7626 {
7627 TCGv EA;
7628 if (unlikely(!ctx->vsx_enabled)) {
7629 gen_exception(ctx, POWERPC_EXCP_VSXU);
7630 return;
7631 }
7632 gen_set_access_type(ctx, ACCESS_INT);
7633 EA = tcg_temp_new();
7634 gen_addr_reg_index(ctx, EA);
7635 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7636 tcg_gen_addi_tl(EA, EA, 8);
7637 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7638 tcg_temp_free(EA);
7639 }
7640
7641 static void gen_lxvdsx(DisasContext *ctx)
7642 {
7643 TCGv EA;
7644 if (unlikely(!ctx->vsx_enabled)) {
7645 gen_exception(ctx, POWERPC_EXCP_VSXU);
7646 return;
7647 }
7648 gen_set_access_type(ctx, ACCESS_INT);
7649 EA = tcg_temp_new();
7650 gen_addr_reg_index(ctx, EA);
7651 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7652 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7653 tcg_temp_free(EA);
7654 }
7655
7656 static void gen_lxvw4x(DisasContext *ctx)
7657 {
7658 TCGv EA;
7659 TCGv_i64 tmp;
7660 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7661 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7662 if (unlikely(!ctx->vsx_enabled)) {
7663 gen_exception(ctx, POWERPC_EXCP_VSXU);
7664 return;
7665 }
7666 gen_set_access_type(ctx, ACCESS_INT);
7667 EA = tcg_temp_new();
7668 tmp = tcg_temp_new_i64();
7669
7670 gen_addr_reg_index(ctx, EA);
7671 gen_qemu_ld32u_i64(ctx, tmp, EA);
7672 tcg_gen_addi_tl(EA, EA, 4);
7673 gen_qemu_ld32u_i64(ctx, xth, EA);
7674 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7675
7676 tcg_gen_addi_tl(EA, EA, 4);
7677 gen_qemu_ld32u_i64(ctx, tmp, EA);
7678 tcg_gen_addi_tl(EA, EA, 4);
7679 gen_qemu_ld32u_i64(ctx, xtl, EA);
7680 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7681
7682 tcg_temp_free(EA);
7683 tcg_temp_free_i64(tmp);
7684 }
7685
7686 #define VSX_STORE_SCALAR(name, operation) \
7687 static void gen_##name(DisasContext *ctx) \
7688 { \
7689 TCGv EA; \
7690 if (unlikely(!ctx->vsx_enabled)) { \
7691 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7692 return; \
7693 } \
7694 gen_set_access_type(ctx, ACCESS_INT); \
7695 EA = tcg_temp_new(); \
7696 gen_addr_reg_index(ctx, EA); \
7697 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7698 tcg_temp_free(EA); \
7699 }
7700
7701 VSX_STORE_SCALAR(stxsdx, st64)
7702 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7703 VSX_STORE_SCALAR(stxsspx, st32fs)
7704
7705 static void gen_stxvd2x(DisasContext *ctx)
7706 {
7707 TCGv EA;
7708 if (unlikely(!ctx->vsx_enabled)) {
7709 gen_exception(ctx, POWERPC_EXCP_VSXU);
7710 return;
7711 }
7712 gen_set_access_type(ctx, ACCESS_INT);
7713 EA = tcg_temp_new();
7714 gen_addr_reg_index(ctx, EA);
7715 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7716 tcg_gen_addi_tl(EA, EA, 8);
7717 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7718 tcg_temp_free(EA);
7719 }
7720
7721 static void gen_stxvw4x(DisasContext *ctx)
7722 {
7723 TCGv_i64 tmp;
7724 TCGv EA;
7725 if (unlikely(!ctx->vsx_enabled)) {
7726 gen_exception(ctx, POWERPC_EXCP_VSXU);
7727 return;
7728 }
7729 gen_set_access_type(ctx, ACCESS_INT);
7730 EA = tcg_temp_new();
7731 gen_addr_reg_index(ctx, EA);
7732 tmp = tcg_temp_new_i64();
7733
7734 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7735 gen_qemu_st32_i64(ctx, tmp, EA);
7736 tcg_gen_addi_tl(EA, EA, 4);
7737 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7738
7739 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7740 tcg_gen_addi_tl(EA, EA, 4);
7741 gen_qemu_st32_i64(ctx, tmp, EA);
7742 tcg_gen_addi_tl(EA, EA, 4);
7743 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7744
7745 tcg_temp_free(EA);
7746 tcg_temp_free_i64(tmp);
7747 }
7748
7749 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7750 static void gen_##name(DisasContext *ctx) \
7751 { \
7752 if (xS(ctx->opcode) < 32) { \
7753 if (unlikely(!ctx->fpu_enabled)) { \
7754 gen_exception(ctx, POWERPC_EXCP_FPU); \
7755 return; \
7756 } \
7757 } else { \
7758 if (unlikely(!ctx->altivec_enabled)) { \
7759 gen_exception(ctx, POWERPC_EXCP_VPU); \
7760 return; \
7761 } \
7762 } \
7763 TCGv_i64 tmp = tcg_temp_new_i64(); \
7764 tcg_gen_##tcgop1(tmp, source); \
7765 tcg_gen_##tcgop2(target, tmp); \
7766 tcg_temp_free_i64(tmp); \
7767 }
7768
7769
7770 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7771 cpu_vsrh(xS(ctx->opcode)))
7772 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7773 cpu_gpr[rA(ctx->opcode)])
7774 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7775 cpu_gpr[rA(ctx->opcode)])
7776
7777 #if defined(TARGET_PPC64)
7778 #define MV_VSRD(name, target, source) \
7779 static void gen_##name(DisasContext *ctx) \
7780 { \
7781 if (xS(ctx->opcode) < 32) { \
7782 if (unlikely(!ctx->fpu_enabled)) { \
7783 gen_exception(ctx, POWERPC_EXCP_FPU); \
7784 return; \
7785 } \
7786 } else { \
7787 if (unlikely(!ctx->altivec_enabled)) { \
7788 gen_exception(ctx, POWERPC_EXCP_VPU); \
7789 return; \
7790 } \
7791 } \
7792 tcg_gen_mov_i64(target, source); \
7793 }
7794
7795 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7796 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7797
7798 #endif
7799
7800 static void gen_xxpermdi(DisasContext *ctx)
7801 {
7802 if (unlikely(!ctx->vsx_enabled)) {
7803 gen_exception(ctx, POWERPC_EXCP_VSXU);
7804 return;
7805 }
7806
7807 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7808 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7809 TCGv_i64 xh, xl;
7810
7811 xh = tcg_temp_new_i64();
7812 xl = tcg_temp_new_i64();
7813
7814 if ((DM(ctx->opcode) & 2) == 0) {
7815 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7816 } else {
7817 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7818 }
7819 if ((DM(ctx->opcode) & 1) == 0) {
7820 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7821 } else {
7822 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7823 }
7824
7825 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7826 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7827
7828 tcg_temp_free_i64(xh);
7829 tcg_temp_free_i64(xl);
7830 } else {
7831 if ((DM(ctx->opcode) & 2) == 0) {
7832 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7833 } else {
7834 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7835 }
7836 if ((DM(ctx->opcode) & 1) == 0) {
7837 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7838 } else {
7839 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7840 }
7841 }
7842 }
7843
7844 #define OP_ABS 1
7845 #define OP_NABS 2
7846 #define OP_NEG 3
7847 #define OP_CPSGN 4
7848 #define SGN_MASK_DP 0x8000000000000000ull
7849 #define SGN_MASK_SP 0x8000000080000000ull
7850
7851 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7852 static void glue(gen_, name)(DisasContext * ctx) \
7853 { \
7854 TCGv_i64 xb, sgm; \
7855 if (unlikely(!ctx->vsx_enabled)) { \
7856 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7857 return; \
7858 } \
7859 xb = tcg_temp_new_i64(); \
7860 sgm = tcg_temp_new_i64(); \
7861 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7862 tcg_gen_movi_i64(sgm, sgn_mask); \
7863 switch (op) { \
7864 case OP_ABS: { \
7865 tcg_gen_andc_i64(xb, xb, sgm); \
7866 break; \
7867 } \
7868 case OP_NABS: { \
7869 tcg_gen_or_i64(xb, xb, sgm); \
7870 break; \
7871 } \
7872 case OP_NEG: { \
7873 tcg_gen_xor_i64(xb, xb, sgm); \
7874 break; \
7875 } \
7876 case OP_CPSGN: { \
7877 TCGv_i64 xa = tcg_temp_new_i64(); \
7878 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7879 tcg_gen_and_i64(xa, xa, sgm); \
7880 tcg_gen_andc_i64(xb, xb, sgm); \
7881 tcg_gen_or_i64(xb, xb, xa); \
7882 tcg_temp_free_i64(xa); \
7883 break; \
7884 } \
7885 } \
7886 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7887 tcg_temp_free_i64(xb); \
7888 tcg_temp_free_i64(sgm); \
7889 }
7890
7891 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7892 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7893 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7894 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7895
7896 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7897 static void glue(gen_, name)(DisasContext * ctx) \
7898 { \
7899 TCGv_i64 xbh, xbl, sgm; \
7900 if (unlikely(!ctx->vsx_enabled)) { \
7901 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7902 return; \
7903 } \
7904 xbh = tcg_temp_new_i64(); \
7905 xbl = tcg_temp_new_i64(); \
7906 sgm = tcg_temp_new_i64(); \
7907 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7908 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7909 tcg_gen_movi_i64(sgm, sgn_mask); \
7910 switch (op) { \
7911 case OP_ABS: { \
7912 tcg_gen_andc_i64(xbh, xbh, sgm); \
7913 tcg_gen_andc_i64(xbl, xbl, sgm); \
7914 break; \
7915 } \
7916 case OP_NABS: { \
7917 tcg_gen_or_i64(xbh, xbh, sgm); \
7918 tcg_gen_or_i64(xbl, xbl, sgm); \
7919 break; \
7920 } \
7921 case OP_NEG: { \
7922 tcg_gen_xor_i64(xbh, xbh, sgm); \
7923 tcg_gen_xor_i64(xbl, xbl, sgm); \
7924 break; \
7925 } \
7926 case OP_CPSGN: { \
7927 TCGv_i64 xah = tcg_temp_new_i64(); \
7928 TCGv_i64 xal = tcg_temp_new_i64(); \
7929 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7930 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7931 tcg_gen_and_i64(xah, xah, sgm); \
7932 tcg_gen_and_i64(xal, xal, sgm); \
7933 tcg_gen_andc_i64(xbh, xbh, sgm); \
7934 tcg_gen_andc_i64(xbl, xbl, sgm); \
7935 tcg_gen_or_i64(xbh, xbh, xah); \
7936 tcg_gen_or_i64(xbl, xbl, xal); \
7937 tcg_temp_free_i64(xah); \
7938 tcg_temp_free_i64(xal); \
7939 break; \
7940 } \
7941 } \
7942 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7943 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7944 tcg_temp_free_i64(xbh); \
7945 tcg_temp_free_i64(xbl); \
7946 tcg_temp_free_i64(sgm); \
7947 }
7948
7949 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7950 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7951 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7952 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7953 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7954 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7955 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7956 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7957
7958 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7959 static void gen_##name(DisasContext * ctx) \
7960 { \
7961 TCGv_i32 opc; \
7962 if (unlikely(!ctx->vsx_enabled)) { \
7963 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7964 return; \
7965 } \
7966 /* NIP cannot be restored if the memory exception comes from an helper */ \
7967 gen_update_nip(ctx, ctx->nip - 4); \
7968 opc = tcg_const_i32(ctx->opcode); \
7969 gen_helper_##name(cpu_env, opc); \
7970 tcg_temp_free_i32(opc); \
7971 }
7972
7973 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7974 static void gen_##name(DisasContext * ctx) \
7975 { \
7976 if (unlikely(!ctx->vsx_enabled)) { \
7977 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7978 return; \
7979 } \
7980 /* NIP cannot be restored if the exception comes */ \
7981 /* from a helper. */ \
7982 gen_update_nip(ctx, ctx->nip - 4); \
7983 \
7984 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7985 cpu_vsrh(xB(ctx->opcode))); \
7986 }
7987
7988 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7989 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
7990 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
7991 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
7992 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
7993 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
7994 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
7995 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
7996 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
7997 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7998 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7999 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
8000 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
8001 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
8002 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
8003 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
8004 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
8005 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
8006 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
8007 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
8008 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
8009 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
8010 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
8011 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
8012 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
8013 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
8014 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
8015 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
8016 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
8017 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
8018 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
8019 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
8020 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
8021 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
8022 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
8023 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
8024 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
8025
8026 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
8027 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
8028 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
8029 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
8030 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
8031 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
8032 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
8033 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
8034 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
8035 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
8036 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
8037 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
8038 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
8039 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
8040 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
8041 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
8042 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
8043
8044 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
8045 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
8046 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
8047 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
8048 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
8049 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
8050 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
8051 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
8052 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
8053 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
8054 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
8055 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
8056 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
8057 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
8058 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
8059 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
8060 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
8061 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
8062 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
8063 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
8064 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
8065 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
8066 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
8067 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
8068 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
8069 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
8070 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
8071 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
8072 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
8073 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
8074 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
8075 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
8076 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
8077 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
8078 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
8079 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
8080
8081 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
8082 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
8083 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
8084 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
8085 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
8086 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
8087 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
8088 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
8089 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
8090 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
8091 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
8092 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
8093 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
8094 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
8095 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
8096 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
8097 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
8098 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
8099 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
8100 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8101 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8102 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
8103 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
8104 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8105 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8106 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8107 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8108 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8109 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8110 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8111 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
8112 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8113 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8114 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8115 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8116 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
8117
8118 #define VSX_LOGICAL(name, tcg_op) \
8119 static void glue(gen_, name)(DisasContext * ctx) \
8120 { \
8121 if (unlikely(!ctx->vsx_enabled)) { \
8122 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8123 return; \
8124 } \
8125 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8126 cpu_vsrh(xB(ctx->opcode))); \
8127 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8128 cpu_vsrl(xB(ctx->opcode))); \
8129 }
8130
8131 VSX_LOGICAL(xxland, tcg_gen_and_i64)
8132 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8133 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8134 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8135 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
8136 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8137 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8138 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
8139
8140 #define VSX_XXMRG(name, high) \
8141 static void glue(gen_, name)(DisasContext * ctx) \
8142 { \
8143 TCGv_i64 a0, a1, b0, b1; \
8144 if (unlikely(!ctx->vsx_enabled)) { \
8145 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8146 return; \
8147 } \
8148 a0 = tcg_temp_new_i64(); \
8149 a1 = tcg_temp_new_i64(); \
8150 b0 = tcg_temp_new_i64(); \
8151 b1 = tcg_temp_new_i64(); \
8152 if (high) { \
8153 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8154 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8155 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8156 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8157 } else { \
8158 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8159 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8160 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8161 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8162 } \
8163 tcg_gen_shri_i64(a0, a0, 32); \
8164 tcg_gen_shri_i64(b0, b0, 32); \
8165 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8166 b0, a0, 32, 32); \
8167 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8168 b1, a1, 32, 32); \
8169 tcg_temp_free_i64(a0); \
8170 tcg_temp_free_i64(a1); \
8171 tcg_temp_free_i64(b0); \
8172 tcg_temp_free_i64(b1); \
8173 }
8174
8175 VSX_XXMRG(xxmrghw, 1)
8176 VSX_XXMRG(xxmrglw, 0)
8177
8178 static void gen_xxsel(DisasContext * ctx)
8179 {
8180 TCGv_i64 a, b, c;
8181 if (unlikely(!ctx->vsx_enabled)) {
8182 gen_exception(ctx, POWERPC_EXCP_VSXU);
8183 return;
8184 }
8185 a = tcg_temp_new_i64();
8186 b = tcg_temp_new_i64();
8187 c = tcg_temp_new_i64();
8188
8189 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8190 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8191 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8192
8193 tcg_gen_and_i64(b, b, c);
8194 tcg_gen_andc_i64(a, a, c);
8195 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8196
8197 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8198 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8199 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8200
8201 tcg_gen_and_i64(b, b, c);
8202 tcg_gen_andc_i64(a, a, c);
8203 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8204
8205 tcg_temp_free_i64(a);
8206 tcg_temp_free_i64(b);
8207 tcg_temp_free_i64(c);
8208 }
8209
8210 static void gen_xxspltw(DisasContext *ctx)
8211 {
8212 TCGv_i64 b, b2;
8213 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8214 cpu_vsrl(xB(ctx->opcode)) :
8215 cpu_vsrh(xB(ctx->opcode));
8216
8217 if (unlikely(!ctx->vsx_enabled)) {
8218 gen_exception(ctx, POWERPC_EXCP_VSXU);
8219 return;
8220 }
8221
8222 b = tcg_temp_new_i64();
8223 b2 = tcg_temp_new_i64();
8224
8225 if (UIM(ctx->opcode) & 1) {
8226 tcg_gen_ext32u_i64(b, vsr);
8227 } else {
8228 tcg_gen_shri_i64(b, vsr, 32);
8229 }
8230
8231 tcg_gen_shli_i64(b2, b, 32);
8232 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8233 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8234
8235 tcg_temp_free_i64(b);
8236 tcg_temp_free_i64(b2);
8237 }
8238
8239 static void gen_xxsldwi(DisasContext *ctx)
8240 {
8241 TCGv_i64 xth, xtl;
8242 if (unlikely(!ctx->vsx_enabled)) {
8243 gen_exception(ctx, POWERPC_EXCP_VSXU);
8244 return;
8245 }
8246 xth = tcg_temp_new_i64();
8247 xtl = tcg_temp_new_i64();
8248
8249 switch (SHW(ctx->opcode)) {
8250 case 0: {
8251 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8252 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8253 break;
8254 }
8255 case 1: {
8256 TCGv_i64 t0 = tcg_temp_new_i64();
8257 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8258 tcg_gen_shli_i64(xth, xth, 32);
8259 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8260 tcg_gen_shri_i64(t0, t0, 32);
8261 tcg_gen_or_i64(xth, xth, t0);
8262 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8263 tcg_gen_shli_i64(xtl, xtl, 32);
8264 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8265 tcg_gen_shri_i64(t0, t0, 32);
8266 tcg_gen_or_i64(xtl, xtl, t0);
8267 tcg_temp_free_i64(t0);
8268 break;
8269 }
8270 case 2: {
8271 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8272 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8273 break;
8274 }
8275 case 3: {
8276 TCGv_i64 t0 = tcg_temp_new_i64();
8277 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8278 tcg_gen_shli_i64(xth, xth, 32);
8279 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8280 tcg_gen_shri_i64(t0, t0, 32);
8281 tcg_gen_or_i64(xth, xth, t0);
8282 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8283 tcg_gen_shli_i64(xtl, xtl, 32);
8284 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8285 tcg_gen_shri_i64(t0, t0, 32);
8286 tcg_gen_or_i64(xtl, xtl, t0);
8287 tcg_temp_free_i64(t0);
8288 break;
8289 }
8290 }
8291
8292 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8293 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8294
8295 tcg_temp_free_i64(xth);
8296 tcg_temp_free_i64(xtl);
8297 }
8298
8299 /*** Decimal Floating Point ***/
8300
8301 static inline TCGv_ptr gen_fprp_ptr(int reg)
8302 {
8303 TCGv_ptr r = tcg_temp_new_ptr();
8304 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8305 return r;
8306 }
8307
8308 #define GEN_DFP_T_A_B_Rc(name) \
8309 static void gen_##name(DisasContext *ctx) \
8310 { \
8311 TCGv_ptr rd, ra, rb; \
8312 if (unlikely(!ctx->fpu_enabled)) { \
8313 gen_exception(ctx, POWERPC_EXCP_FPU); \
8314 return; \
8315 } \
8316 gen_update_nip(ctx, ctx->nip - 4); \
8317 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8318 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8319 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8320 gen_helper_##name(cpu_env, rd, ra, rb); \
8321 if (unlikely(Rc(ctx->opcode) != 0)) { \
8322 gen_set_cr1_from_fpscr(ctx); \
8323 } \
8324 tcg_temp_free_ptr(rd); \
8325 tcg_temp_free_ptr(ra); \
8326 tcg_temp_free_ptr(rb); \
8327 }
8328
8329 #define GEN_DFP_BF_A_B(name) \
8330 static void gen_##name(DisasContext *ctx) \
8331 { \
8332 TCGv_ptr ra, rb; \
8333 if (unlikely(!ctx->fpu_enabled)) { \
8334 gen_exception(ctx, POWERPC_EXCP_FPU); \
8335 return; \
8336 } \
8337 gen_update_nip(ctx, ctx->nip - 4); \
8338 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8339 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8340 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8341 cpu_env, ra, rb); \
8342 tcg_temp_free_ptr(ra); \
8343 tcg_temp_free_ptr(rb); \
8344 }
8345
8346 #define GEN_DFP_BF_A_DCM(name) \
8347 static void gen_##name(DisasContext *ctx) \
8348 { \
8349 TCGv_ptr ra; \
8350 TCGv_i32 dcm; \
8351 if (unlikely(!ctx->fpu_enabled)) { \
8352 gen_exception(ctx, POWERPC_EXCP_FPU); \
8353 return; \
8354 } \
8355 gen_update_nip(ctx, ctx->nip - 4); \
8356 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8357 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8358 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8359 cpu_env, ra, dcm); \
8360 tcg_temp_free_ptr(ra); \
8361 tcg_temp_free_i32(dcm); \
8362 }
8363
8364 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8365 static void gen_##name(DisasContext *ctx) \
8366 { \
8367 TCGv_ptr rt, rb; \
8368 TCGv_i32 u32_1, u32_2; \
8369 if (unlikely(!ctx->fpu_enabled)) { \
8370 gen_exception(ctx, POWERPC_EXCP_FPU); \
8371 return; \
8372 } \
8373 gen_update_nip(ctx, ctx->nip - 4); \
8374 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8375 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8376 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8377 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8378 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8379 if (unlikely(Rc(ctx->opcode) != 0)) { \
8380 gen_set_cr1_from_fpscr(ctx); \
8381 } \
8382 tcg_temp_free_ptr(rt); \
8383 tcg_temp_free_ptr(rb); \
8384 tcg_temp_free_i32(u32_1); \
8385 tcg_temp_free_i32(u32_2); \
8386 }
8387
8388 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8389 static void gen_##name(DisasContext *ctx) \
8390 { \
8391 TCGv_ptr rt, ra, rb; \
8392 TCGv_i32 i32; \
8393 if (unlikely(!ctx->fpu_enabled)) { \
8394 gen_exception(ctx, POWERPC_EXCP_FPU); \
8395 return; \
8396 } \
8397 gen_update_nip(ctx, ctx->nip - 4); \
8398 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8399 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8400 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8401 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8402 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8403 if (unlikely(Rc(ctx->opcode) != 0)) { \
8404 gen_set_cr1_from_fpscr(ctx); \
8405 } \
8406 tcg_temp_free_ptr(rt); \
8407 tcg_temp_free_ptr(rb); \
8408 tcg_temp_free_ptr(ra); \
8409 tcg_temp_free_i32(i32); \
8410 }
8411
8412 #define GEN_DFP_T_B_Rc(name) \
8413 static void gen_##name(DisasContext *ctx) \
8414 { \
8415 TCGv_ptr rt, rb; \
8416 if (unlikely(!ctx->fpu_enabled)) { \
8417 gen_exception(ctx, POWERPC_EXCP_FPU); \
8418 return; \
8419 } \
8420 gen_update_nip(ctx, ctx->nip - 4); \
8421 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8422 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8423 gen_helper_##name(cpu_env, rt, rb); \
8424 if (unlikely(Rc(ctx->opcode) != 0)) { \
8425 gen_set_cr1_from_fpscr(ctx); \
8426 } \
8427 tcg_temp_free_ptr(rt); \
8428 tcg_temp_free_ptr(rb); \
8429 }
8430
8431 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8432 static void gen_##name(DisasContext *ctx) \
8433 { \
8434 TCGv_ptr rt, rs; \
8435 TCGv_i32 i32; \
8436 if (unlikely(!ctx->fpu_enabled)) { \
8437 gen_exception(ctx, POWERPC_EXCP_FPU); \
8438 return; \
8439 } \
8440 gen_update_nip(ctx, ctx->nip - 4); \
8441 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8442 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8443 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8444 gen_helper_##name(cpu_env, rt, rs, i32); \
8445 if (unlikely(Rc(ctx->opcode) != 0)) { \
8446 gen_set_cr1_from_fpscr(ctx); \
8447 } \
8448 tcg_temp_free_ptr(rt); \
8449 tcg_temp_free_ptr(rs); \
8450 tcg_temp_free_i32(i32); \
8451 }
8452
8453 GEN_DFP_T_A_B_Rc(dadd)
8454 GEN_DFP_T_A_B_Rc(daddq)
8455 GEN_DFP_T_A_B_Rc(dsub)
8456 GEN_DFP_T_A_B_Rc(dsubq)
8457 GEN_DFP_T_A_B_Rc(dmul)
8458 GEN_DFP_T_A_B_Rc(dmulq)
8459 GEN_DFP_T_A_B_Rc(ddiv)
8460 GEN_DFP_T_A_B_Rc(ddivq)
8461 GEN_DFP_BF_A_B(dcmpu)
8462 GEN_DFP_BF_A_B(dcmpuq)
8463 GEN_DFP_BF_A_B(dcmpo)
8464 GEN_DFP_BF_A_B(dcmpoq)
8465 GEN_DFP_BF_A_DCM(dtstdc)
8466 GEN_DFP_BF_A_DCM(dtstdcq)
8467 GEN_DFP_BF_A_DCM(dtstdg)
8468 GEN_DFP_BF_A_DCM(dtstdgq)
8469 GEN_DFP_BF_A_B(dtstex)
8470 GEN_DFP_BF_A_B(dtstexq)
8471 GEN_DFP_BF_A_B(dtstsf)
8472 GEN_DFP_BF_A_B(dtstsfq)
8473 GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8474 GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8475 GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8476 GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
8477 GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8478 GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
8479 GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8480 GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8481 GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8482 GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
8483 GEN_DFP_T_B_Rc(dctdp)
8484 GEN_DFP_T_B_Rc(dctqpq)
8485 GEN_DFP_T_B_Rc(drsp)
8486 GEN_DFP_T_B_Rc(drdpq)
8487 GEN_DFP_T_B_Rc(dcffix)
8488 GEN_DFP_T_B_Rc(dcffixq)
8489 GEN_DFP_T_B_Rc(dctfix)
8490 GEN_DFP_T_B_Rc(dctfixq)
8491 GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8492 GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
8493 GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8494 GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
8495 GEN_DFP_T_B_Rc(dxex)
8496 GEN_DFP_T_B_Rc(dxexq)
8497 GEN_DFP_T_A_B_Rc(diex)
8498 GEN_DFP_T_A_B_Rc(diexq)
8499 GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8500 GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8501 GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8502 GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8503
8504 /*** SPE extension ***/
8505 /* Register moves */
8506
8507 static inline void gen_evmra(DisasContext *ctx)
8508 {
8509
8510 if (unlikely(!ctx->spe_enabled)) {
8511 gen_exception(ctx, POWERPC_EXCP_SPEU);
8512 return;
8513 }
8514
8515 TCGv_i64 tmp = tcg_temp_new_i64();
8516
8517 /* tmp := rA_lo + rA_hi << 32 */
8518 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8519
8520 /* spe_acc := tmp */
8521 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8522 tcg_temp_free_i64(tmp);
8523
8524 /* rD := rA */
8525 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8526 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8527 }
8528
8529 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8530 {
8531 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
8532 }
8533
8534 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8535 {
8536 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
8537 }
8538
8539 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8540 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8541 { \
8542 if (Rc(ctx->opcode)) \
8543 gen_##name1(ctx); \
8544 else \
8545 gen_##name0(ctx); \
8546 }
8547
8548 /* Handler for undefined SPE opcodes */
8549 static inline void gen_speundef(DisasContext *ctx)
8550 {
8551 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8552 }
8553
8554 /* SPE logic */
8555 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8556 static inline void gen_##name(DisasContext *ctx) \
8557 { \
8558 if (unlikely(!ctx->spe_enabled)) { \
8559 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8560 return; \
8561 } \
8562 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8563 cpu_gpr[rB(ctx->opcode)]); \
8564 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8565 cpu_gprh[rB(ctx->opcode)]); \
8566 }
8567
8568 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8569 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8570 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8571 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8572 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8573 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8574 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8575 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8576
8577 /* SPE logic immediate */
8578 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8579 static inline void gen_##name(DisasContext *ctx) \
8580 { \
8581 TCGv_i32 t0; \
8582 if (unlikely(!ctx->spe_enabled)) { \
8583 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8584 return; \
8585 } \
8586 t0 = tcg_temp_new_i32(); \
8587 \
8588 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8589 tcg_opi(t0, t0, rB(ctx->opcode)); \
8590 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8591 \
8592 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8593 tcg_opi(t0, t0, rB(ctx->opcode)); \
8594 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8595 \
8596 tcg_temp_free_i32(t0); \
8597 }
8598 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8599 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8600 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8601 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8602
8603 /* SPE arithmetic */
8604 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8605 static inline void gen_##name(DisasContext *ctx) \
8606 { \
8607 TCGv_i32 t0; \
8608 if (unlikely(!ctx->spe_enabled)) { \
8609 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8610 return; \
8611 } \
8612 t0 = tcg_temp_new_i32(); \
8613 \
8614 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8615 tcg_op(t0, t0); \
8616 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8617 \
8618 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8619 tcg_op(t0, t0); \
8620 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8621 \
8622 tcg_temp_free_i32(t0); \
8623 }
8624
8625 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8626 {
8627 TCGLabel *l1 = gen_new_label();
8628 TCGLabel *l2 = gen_new_label();
8629
8630 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8631 tcg_gen_neg_i32(ret, arg1);
8632 tcg_gen_br(l2);
8633 gen_set_label(l1);
8634 tcg_gen_mov_i32(ret, arg1);
8635 gen_set_label(l2);
8636 }
8637 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8638 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8639 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8640 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8641 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8642 {
8643 tcg_gen_addi_i32(ret, arg1, 0x8000);
8644 tcg_gen_ext16u_i32(ret, ret);
8645 }
8646 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8647 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8648 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8649
8650 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8651 static inline void gen_##name(DisasContext *ctx) \
8652 { \
8653 TCGv_i32 t0, t1; \
8654 if (unlikely(!ctx->spe_enabled)) { \
8655 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8656 return; \
8657 } \
8658 t0 = tcg_temp_new_i32(); \
8659 t1 = tcg_temp_new_i32(); \
8660 \
8661 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8662 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8663 tcg_op(t0, t0, t1); \
8664 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8665 \
8666 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8667 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8668 tcg_op(t0, t0, t1); \
8669 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8670 \
8671 tcg_temp_free_i32(t0); \
8672 tcg_temp_free_i32(t1); \
8673 }
8674
8675 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8676 {
8677 TCGLabel *l1 = gen_new_label();
8678 TCGLabel *l2 = gen_new_label();
8679 TCGv_i32 t0 = tcg_temp_local_new_i32();
8680
8681 /* No error here: 6 bits are used */
8682 tcg_gen_andi_i32(t0, arg2, 0x3F);
8683 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8684 tcg_gen_shr_i32(ret, arg1, t0);
8685 tcg_gen_br(l2);
8686 gen_set_label(l1);
8687 tcg_gen_movi_i32(ret, 0);
8688 gen_set_label(l2);
8689 tcg_temp_free_i32(t0);
8690 }
8691 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8692 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8693 {
8694 TCGLabel *l1 = gen_new_label();
8695 TCGLabel *l2 = gen_new_label();
8696 TCGv_i32 t0 = tcg_temp_local_new_i32();
8697
8698 /* No error here: 6 bits are used */
8699 tcg_gen_andi_i32(t0, arg2, 0x3F);
8700 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8701 tcg_gen_sar_i32(ret, arg1, t0);
8702 tcg_gen_br(l2);
8703 gen_set_label(l1);
8704 tcg_gen_movi_i32(ret, 0);
8705 gen_set_label(l2);
8706 tcg_temp_free_i32(t0);
8707 }
8708 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8709 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8710 {
8711 TCGLabel *l1 = gen_new_label();
8712 TCGLabel *l2 = gen_new_label();
8713 TCGv_i32 t0 = tcg_temp_local_new_i32();
8714
8715 /* No error here: 6 bits are used */
8716 tcg_gen_andi_i32(t0, arg2, 0x3F);
8717 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8718 tcg_gen_shl_i32(ret, arg1, t0);
8719 tcg_gen_br(l2);
8720 gen_set_label(l1);
8721 tcg_gen_movi_i32(ret, 0);
8722 gen_set_label(l2);
8723 tcg_temp_free_i32(t0);
8724 }
8725 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8726 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8727 {
8728 TCGv_i32 t0 = tcg_temp_new_i32();
8729 tcg_gen_andi_i32(t0, arg2, 0x1F);
8730 tcg_gen_rotl_i32(ret, arg1, t0);
8731 tcg_temp_free_i32(t0);
8732 }
8733 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8734 static inline void gen_evmergehi(DisasContext *ctx)
8735 {
8736 if (unlikely(!ctx->spe_enabled)) {
8737 gen_exception(ctx, POWERPC_EXCP_SPEU);
8738 return;
8739 }
8740 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8741 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8742 }
8743 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8744 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8745 {
8746 tcg_gen_sub_i32(ret, arg2, arg1);
8747 }
8748 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8749
8750 /* SPE arithmetic immediate */
8751 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8752 static inline void gen_##name(DisasContext *ctx) \
8753 { \
8754 TCGv_i32 t0; \
8755 if (unlikely(!ctx->spe_enabled)) { \
8756 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8757 return; \
8758 } \
8759 t0 = tcg_temp_new_i32(); \
8760 \
8761 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8762 tcg_op(t0, t0, rA(ctx->opcode)); \
8763 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8764 \
8765 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8766 tcg_op(t0, t0, rA(ctx->opcode)); \
8767 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8768 \
8769 tcg_temp_free_i32(t0); \
8770 }
8771 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8772 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8773
8774 /* SPE comparison */
8775 #define GEN_SPEOP_COMP(name, tcg_cond) \
8776 static inline void gen_##name(DisasContext *ctx) \
8777 { \
8778 if (unlikely(!ctx->spe_enabled)) { \
8779 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8780 return; \
8781 } \
8782 TCGLabel *l1 = gen_new_label(); \
8783 TCGLabel *l2 = gen_new_label(); \
8784 TCGLabel *l3 = gen_new_label(); \
8785 TCGLabel *l4 = gen_new_label(); \
8786 \
8787 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8788 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8789 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8790 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8791 \
8792 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8793 cpu_gpr[rB(ctx->opcode)], l1); \
8794 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8795 tcg_gen_br(l2); \
8796 gen_set_label(l1); \
8797 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8798 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8799 gen_set_label(l2); \
8800 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8801 cpu_gprh[rB(ctx->opcode)], l3); \
8802 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8803 ~(CRF_CH | CRF_CH_AND_CL)); \
8804 tcg_gen_br(l4); \
8805 gen_set_label(l3); \
8806 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8807 CRF_CH | CRF_CH_OR_CL); \
8808 gen_set_label(l4); \
8809 }
8810 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8811 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8812 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8813 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8814 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8815
8816 /* SPE misc */
8817 static inline void gen_brinc(DisasContext *ctx)
8818 {
8819 /* Note: brinc is usable even if SPE is disabled */
8820 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8821 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8822 }
8823 static inline void gen_evmergelo(DisasContext *ctx)
8824 {
8825 if (unlikely(!ctx->spe_enabled)) {
8826 gen_exception(ctx, POWERPC_EXCP_SPEU);
8827 return;
8828 }
8829 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8830 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8831 }
8832 static inline void gen_evmergehilo(DisasContext *ctx)
8833 {
8834 if (unlikely(!ctx->spe_enabled)) {
8835 gen_exception(ctx, POWERPC_EXCP_SPEU);
8836 return;
8837 }
8838 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8839 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8840 }
8841 static inline void gen_evmergelohi(DisasContext *ctx)
8842 {
8843 if (unlikely(!ctx->spe_enabled)) {
8844 gen_exception(ctx, POWERPC_EXCP_SPEU);
8845 return;
8846 }
8847 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8848 TCGv tmp = tcg_temp_new();
8849 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8850 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8851 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8852 tcg_temp_free(tmp);
8853 } else {
8854 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8855 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8856 }
8857 }
8858 static inline void gen_evsplati(DisasContext *ctx)
8859 {
8860 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8861
8862 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8863 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8864 }
8865 static inline void gen_evsplatfi(DisasContext *ctx)
8866 {
8867 uint64_t imm = rA(ctx->opcode) << 27;
8868
8869 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8870 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8871 }
8872
8873 static inline void gen_evsel(DisasContext *ctx)
8874 {
8875 TCGLabel *l1 = gen_new_label();
8876 TCGLabel *l2 = gen_new_label();
8877 TCGLabel *l3 = gen_new_label();
8878 TCGLabel *l4 = gen_new_label();
8879 TCGv_i32 t0 = tcg_temp_local_new_i32();
8880
8881 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8882 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8883 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8884 tcg_gen_br(l2);
8885 gen_set_label(l1);
8886 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8887 gen_set_label(l2);
8888 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8889 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8890 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8891 tcg_gen_br(l4);
8892 gen_set_label(l3);
8893 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8894 gen_set_label(l4);
8895 tcg_temp_free_i32(t0);
8896 }
8897
8898 static void gen_evsel0(DisasContext *ctx)
8899 {
8900 gen_evsel(ctx);
8901 }
8902
8903 static void gen_evsel1(DisasContext *ctx)
8904 {
8905 gen_evsel(ctx);
8906 }
8907
8908 static void gen_evsel2(DisasContext *ctx)
8909 {
8910 gen_evsel(ctx);
8911 }
8912
8913 static void gen_evsel3(DisasContext *ctx)
8914 {
8915 gen_evsel(ctx);
8916 }
8917
8918 /* Multiply */
8919
8920 static inline void gen_evmwumi(DisasContext *ctx)
8921 {
8922 TCGv_i64 t0, t1;
8923
8924 if (unlikely(!ctx->spe_enabled)) {
8925 gen_exception(ctx, POWERPC_EXCP_SPEU);
8926 return;
8927 }
8928
8929 t0 = tcg_temp_new_i64();
8930 t1 = tcg_temp_new_i64();
8931
8932 /* t0 := rA; t1 := rB */
8933 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8934 tcg_gen_ext32u_i64(t0, t0);
8935 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8936 tcg_gen_ext32u_i64(t1, t1);
8937
8938 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8939
8940 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8941
8942 tcg_temp_free_i64(t0);
8943 tcg_temp_free_i64(t1);
8944 }
8945
8946 static inline void gen_evmwumia(DisasContext *ctx)
8947 {
8948 TCGv_i64 tmp;
8949
8950 if (unlikely(!ctx->spe_enabled)) {
8951 gen_exception(ctx, POWERPC_EXCP_SPEU);
8952 return;
8953 }
8954
8955 gen_evmwumi(ctx); /* rD := rA * rB */
8956
8957 tmp = tcg_temp_new_i64();
8958
8959 /* acc := rD */
8960 gen_load_gpr64(tmp, rD(ctx->opcode));
8961 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8962 tcg_temp_free_i64(tmp);
8963 }
8964
8965 static inline void gen_evmwumiaa(DisasContext *ctx)
8966 {
8967 TCGv_i64 acc;
8968 TCGv_i64 tmp;
8969
8970 if (unlikely(!ctx->spe_enabled)) {
8971 gen_exception(ctx, POWERPC_EXCP_SPEU);
8972 return;
8973 }
8974
8975 gen_evmwumi(ctx); /* rD := rA * rB */
8976
8977 acc = tcg_temp_new_i64();
8978 tmp = tcg_temp_new_i64();
8979
8980 /* tmp := rD */
8981 gen_load_gpr64(tmp, rD(ctx->opcode));
8982
8983 /* Load acc */
8984 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8985
8986 /* acc := tmp + acc */
8987 tcg_gen_add_i64(acc, acc, tmp);
8988
8989 /* Store acc */
8990 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8991
8992 /* rD := acc */
8993 gen_store_gpr64(rD(ctx->opcode), acc);
8994
8995 tcg_temp_free_i64(acc);
8996 tcg_temp_free_i64(tmp);
8997 }
8998
8999 static inline void gen_evmwsmi(DisasContext *ctx)
9000 {
9001 TCGv_i64 t0, t1;
9002
9003 if (unlikely(!ctx->spe_enabled)) {
9004 gen_exception(ctx, POWERPC_EXCP_SPEU);
9005 return;
9006 }
9007
9008 t0 = tcg_temp_new_i64();
9009 t1 = tcg_temp_new_i64();
9010
9011 /* t0 := rA; t1 := rB */
9012 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
9013 tcg_gen_ext32s_i64(t0, t0);
9014 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
9015 tcg_gen_ext32s_i64(t1, t1);
9016
9017 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
9018
9019 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
9020
9021 tcg_temp_free_i64(t0);
9022 tcg_temp_free_i64(t1);
9023 }
9024
9025 static inline void gen_evmwsmia(DisasContext *ctx)
9026 {
9027 TCGv_i64 tmp;
9028
9029 gen_evmwsmi(ctx); /* rD := rA * rB */
9030
9031 tmp = tcg_temp_new_i64();
9032
9033 /* acc := rD */
9034 gen_load_gpr64(tmp, rD(ctx->opcode));
9035 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
9036
9037 tcg_temp_free_i64(tmp);
9038 }
9039
9040 static inline void gen_evmwsmiaa(DisasContext *ctx)
9041 {
9042 TCGv_i64 acc = tcg_temp_new_i64();
9043 TCGv_i64 tmp = tcg_temp_new_i64();
9044
9045 gen_evmwsmi(ctx); /* rD := rA * rB */
9046
9047 acc = tcg_temp_new_i64();
9048 tmp = tcg_temp_new_i64();
9049
9050 /* tmp := rD */
9051 gen_load_gpr64(tmp, rD(ctx->opcode));
9052
9053 /* Load acc */
9054 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9055
9056 /* acc := tmp + acc */
9057 tcg_gen_add_i64(acc, acc, tmp);
9058
9059 /* Store acc */
9060 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9061
9062 /* rD := acc */
9063 gen_store_gpr64(rD(ctx->opcode), acc);
9064
9065 tcg_temp_free_i64(acc);
9066 tcg_temp_free_i64(tmp);
9067 }
9068
9069 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9070 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9071 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9072 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9073 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9074 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9075 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9076 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
9077 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
9078 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9079 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9080 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9081 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9082 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9083 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9084 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9085 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9086 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9087 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9088 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9089 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9090 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9091 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9092 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9093 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9094 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9095 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9096 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9097 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
9098
9099 /* SPE load and stores */
9100 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
9101 {
9102 target_ulong uimm = rB(ctx->opcode);
9103
9104 if (rA(ctx->opcode) == 0) {
9105 tcg_gen_movi_tl(EA, uimm << sh);
9106 } else {
9107 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
9108 if (NARROW_MODE(ctx)) {
9109 tcg_gen_ext32u_tl(EA, EA);
9110 }
9111 }
9112 }
9113
9114 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
9115 {
9116 TCGv_i64 t0 = tcg_temp_new_i64();
9117 gen_qemu_ld64(ctx, t0, addr);
9118 gen_store_gpr64(rD(ctx->opcode), t0);
9119 tcg_temp_free_i64(t0);
9120 }
9121
9122 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
9123 {
9124 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9125 gen_addr_add(ctx, addr, addr, 4);
9126 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9127 }
9128
9129 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
9130 {
9131 TCGv t0 = tcg_temp_new();
9132 gen_qemu_ld16u(ctx, t0, addr);
9133 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9134 gen_addr_add(ctx, addr, addr, 2);
9135 gen_qemu_ld16u(ctx, t0, addr);
9136 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9137 gen_addr_add(ctx, addr, addr, 2);
9138 gen_qemu_ld16u(ctx, t0, addr);
9139 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9140 gen_addr_add(ctx, addr, addr, 2);
9141 gen_qemu_ld16u(ctx, t0, addr);
9142 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9143 tcg_temp_free(t0);
9144 }
9145
9146 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
9147 {
9148 TCGv t0 = tcg_temp_new();
9149 gen_qemu_ld16u(ctx, t0, addr);
9150 tcg_gen_shli_tl(t0, t0, 16);
9151 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9152 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9153 tcg_temp_free(t0);
9154 }
9155
9156 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
9157 {
9158 TCGv t0 = tcg_temp_new();
9159 gen_qemu_ld16u(ctx, t0, addr);
9160 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9161 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9162 tcg_temp_free(t0);
9163 }
9164
9165 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
9166 {
9167 TCGv t0 = tcg_temp_new();
9168 gen_qemu_ld16s(ctx, t0, addr);
9169 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9170 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9171 tcg_temp_free(t0);
9172 }
9173
9174 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
9175 {
9176 TCGv t0 = tcg_temp_new();
9177 gen_qemu_ld16u(ctx, t0, addr);
9178 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9179 gen_addr_add(ctx, addr, addr, 2);
9180 gen_qemu_ld16u(ctx, t0, addr);
9181 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9182 tcg_temp_free(t0);
9183 }
9184
9185 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
9186 {
9187 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9188 gen_addr_add(ctx, addr, addr, 2);
9189 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9190 }
9191
9192 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
9193 {
9194 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9195 gen_addr_add(ctx, addr, addr, 2);
9196 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9197 }
9198
9199 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
9200 {
9201 TCGv t0 = tcg_temp_new();
9202 gen_qemu_ld32u(ctx, t0, addr);
9203 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9204 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9205 tcg_temp_free(t0);
9206 }
9207
9208 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
9209 {
9210 TCGv t0 = tcg_temp_new();
9211 gen_qemu_ld16u(ctx, t0, addr);
9212 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9213 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9214 gen_addr_add(ctx, addr, addr, 2);
9215 gen_qemu_ld16u(ctx, t0, addr);
9216 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9217 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9218 tcg_temp_free(t0);
9219 }
9220
9221 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
9222 {
9223 TCGv_i64 t0 = tcg_temp_new_i64();
9224 gen_load_gpr64(t0, rS(ctx->opcode));
9225 gen_qemu_st64(ctx, t0, addr);
9226 tcg_temp_free_i64(t0);
9227 }
9228
9229 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
9230 {
9231 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9232 gen_addr_add(ctx, addr, addr, 4);
9233 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9234 }
9235
9236 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
9237 {
9238 TCGv t0 = tcg_temp_new();
9239 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9240 gen_qemu_st16(ctx, t0, addr);
9241 gen_addr_add(ctx, addr, addr, 2);
9242 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9243 gen_addr_add(ctx, addr, addr, 2);
9244 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9245 gen_qemu_st16(ctx, t0, addr);
9246 tcg_temp_free(t0);
9247 gen_addr_add(ctx, addr, addr, 2);
9248 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9249 }
9250
9251 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9252 {
9253 TCGv t0 = tcg_temp_new();
9254 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9255 gen_qemu_st16(ctx, t0, addr);
9256 gen_addr_add(ctx, addr, addr, 2);
9257 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9258 gen_qemu_st16(ctx, t0, addr);
9259 tcg_temp_free(t0);
9260 }
9261
9262 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9263 {
9264 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9265 gen_addr_add(ctx, addr, addr, 2);
9266 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9267 }
9268
9269 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9270 {
9271 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9272 }
9273
9274 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9275 {
9276 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9277 }
9278
9279 #define GEN_SPEOP_LDST(name, opc2, sh) \
9280 static void glue(gen_, name)(DisasContext *ctx) \
9281 { \
9282 TCGv t0; \
9283 if (unlikely(!ctx->spe_enabled)) { \
9284 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9285 return; \
9286 } \
9287 gen_set_access_type(ctx, ACCESS_INT); \
9288 t0 = tcg_temp_new(); \
9289 if (Rc(ctx->opcode)) { \
9290 gen_addr_spe_imm_index(ctx, t0, sh); \
9291 } else { \
9292 gen_addr_reg_index(ctx, t0); \
9293 } \
9294 gen_op_##name(ctx, t0); \
9295 tcg_temp_free(t0); \
9296 }
9297
9298 GEN_SPEOP_LDST(evldd, 0x00, 3);
9299 GEN_SPEOP_LDST(evldw, 0x01, 3);
9300 GEN_SPEOP_LDST(evldh, 0x02, 3);
9301 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9302 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9303 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9304 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9305 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9306 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9307 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9308 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9309
9310 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9311 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9312 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9313 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9314 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9315 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9316 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9317
9318 /* Multiply and add - TODO */
9319 #if 0
9320 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9321 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9322 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9323 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9324 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9325 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9326 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9327 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9328 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9329 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9330 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9331 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9332
9333 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9334 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9335 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9336 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9337 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9338 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9339 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9340 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9341 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9342 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9343 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9344 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9345
9346 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9347 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9348 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9349 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9350 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9351
9352 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9353 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9354 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9355 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9356 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9357 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9358 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9359 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9360 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9361 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9362 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9363 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9364
9365 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9366 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9367 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9368 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9369
9370 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9371 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9372 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9373 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9374 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9375 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9376 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9377 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9378 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9379 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9380 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9381 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9382
9383 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9384 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9385 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9386 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9387 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9388 #endif
9389
9390 /*** SPE floating-point extension ***/
9391 #define GEN_SPEFPUOP_CONV_32_32(name) \
9392 static inline void gen_##name(DisasContext *ctx) \
9393 { \
9394 TCGv_i32 t0 = tcg_temp_new_i32(); \
9395 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9396 gen_helper_##name(t0, cpu_env, t0); \
9397 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9398 tcg_temp_free_i32(t0); \
9399 }
9400 #define GEN_SPEFPUOP_CONV_32_64(name) \
9401 static inline void gen_##name(DisasContext *ctx) \
9402 { \
9403 TCGv_i64 t0 = tcg_temp_new_i64(); \
9404 TCGv_i32 t1 = tcg_temp_new_i32(); \
9405 gen_load_gpr64(t0, rB(ctx->opcode)); \
9406 gen_helper_##name(t1, cpu_env, t0); \
9407 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9408 tcg_temp_free_i64(t0); \
9409 tcg_temp_free_i32(t1); \
9410 }
9411 #define GEN_SPEFPUOP_CONV_64_32(name) \
9412 static inline void gen_##name(DisasContext *ctx) \
9413 { \
9414 TCGv_i64 t0 = tcg_temp_new_i64(); \
9415 TCGv_i32 t1 = tcg_temp_new_i32(); \
9416 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9417 gen_helper_##name(t0, cpu_env, t1); \
9418 gen_store_gpr64(rD(ctx->opcode), t0); \
9419 tcg_temp_free_i64(t0); \
9420 tcg_temp_free_i32(t1); \
9421 }
9422 #define GEN_SPEFPUOP_CONV_64_64(name) \
9423 static inline void gen_##name(DisasContext *ctx) \
9424 { \
9425 TCGv_i64 t0 = tcg_temp_new_i64(); \
9426 gen_load_gpr64(t0, rB(ctx->opcode)); \
9427 gen_helper_##name(t0, cpu_env, t0); \
9428 gen_store_gpr64(rD(ctx->opcode), t0); \
9429 tcg_temp_free_i64(t0); \
9430 }
9431 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9432 static inline void gen_##name(DisasContext *ctx) \
9433 { \
9434 TCGv_i32 t0, t1; \
9435 if (unlikely(!ctx->spe_enabled)) { \
9436 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9437 return; \
9438 } \
9439 t0 = tcg_temp_new_i32(); \
9440 t1 = tcg_temp_new_i32(); \
9441 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9442 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9443 gen_helper_##name(t0, cpu_env, t0, t1); \
9444 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9445 \
9446 tcg_temp_free_i32(t0); \
9447 tcg_temp_free_i32(t1); \
9448 }
9449 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9450 static inline void gen_##name(DisasContext *ctx) \
9451 { \
9452 TCGv_i64 t0, t1; \
9453 if (unlikely(!ctx->spe_enabled)) { \
9454 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9455 return; \
9456 } \
9457 t0 = tcg_temp_new_i64(); \
9458 t1 = tcg_temp_new_i64(); \
9459 gen_load_gpr64(t0, rA(ctx->opcode)); \
9460 gen_load_gpr64(t1, rB(ctx->opcode)); \
9461 gen_helper_##name(t0, cpu_env, t0, t1); \
9462 gen_store_gpr64(rD(ctx->opcode), t0); \
9463 tcg_temp_free_i64(t0); \
9464 tcg_temp_free_i64(t1); \
9465 }
9466 #define GEN_SPEFPUOP_COMP_32(name) \
9467 static inline void gen_##name(DisasContext *ctx) \
9468 { \
9469 TCGv_i32 t0, t1; \
9470 if (unlikely(!ctx->spe_enabled)) { \
9471 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9472 return; \
9473 } \
9474 t0 = tcg_temp_new_i32(); \
9475 t1 = tcg_temp_new_i32(); \
9476 \
9477 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9478 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9479 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9480 \
9481 tcg_temp_free_i32(t0); \
9482 tcg_temp_free_i32(t1); \
9483 }
9484 #define GEN_SPEFPUOP_COMP_64(name) \
9485 static inline void gen_##name(DisasContext *ctx) \
9486 { \
9487 TCGv_i64 t0, t1; \
9488 if (unlikely(!ctx->spe_enabled)) { \
9489 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9490 return; \
9491 } \
9492 t0 = tcg_temp_new_i64(); \
9493 t1 = tcg_temp_new_i64(); \
9494 gen_load_gpr64(t0, rA(ctx->opcode)); \
9495 gen_load_gpr64(t1, rB(ctx->opcode)); \
9496 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9497 tcg_temp_free_i64(t0); \
9498 tcg_temp_free_i64(t1); \
9499 }
9500
9501 /* Single precision floating-point vectors operations */
9502 /* Arithmetic */
9503 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9504 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9505 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9506 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9507 static inline void gen_evfsabs(DisasContext *ctx)
9508 {
9509 if (unlikely(!ctx->spe_enabled)) {
9510 gen_exception(ctx, POWERPC_EXCP_SPEU);
9511 return;
9512 }
9513 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9514 ~0x80000000);
9515 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9516 ~0x80000000);
9517 }
9518 static inline void gen_evfsnabs(DisasContext *ctx)
9519 {
9520 if (unlikely(!ctx->spe_enabled)) {
9521 gen_exception(ctx, POWERPC_EXCP_SPEU);
9522 return;
9523 }
9524 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9525 0x80000000);
9526 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9527 0x80000000);
9528 }
9529 static inline void gen_evfsneg(DisasContext *ctx)
9530 {
9531 if (unlikely(!ctx->spe_enabled)) {
9532 gen_exception(ctx, POWERPC_EXCP_SPEU);
9533 return;
9534 }
9535 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9536 0x80000000);
9537 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9538 0x80000000);
9539 }
9540
9541 /* Conversion */
9542 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9543 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9544 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9545 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9546 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9547 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9548 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9549 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9550 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9551 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9552
9553 /* Comparison */
9554 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9555 GEN_SPEFPUOP_COMP_64(evfscmplt);
9556 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9557 GEN_SPEFPUOP_COMP_64(evfststgt);
9558 GEN_SPEFPUOP_COMP_64(evfststlt);
9559 GEN_SPEFPUOP_COMP_64(evfststeq);
9560
9561 /* Opcodes definitions */
9562 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9563 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9564 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9565 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9566 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9567 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9568 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9569 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9570 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9571 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9572 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9573 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9574 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9575 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9576
9577 /* Single precision floating-point operations */
9578 /* Arithmetic */
9579 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9580 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9581 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9582 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9583 static inline void gen_efsabs(DisasContext *ctx)
9584 {
9585 if (unlikely(!ctx->spe_enabled)) {
9586 gen_exception(ctx, POWERPC_EXCP_SPEU);
9587 return;
9588 }
9589 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9590 }
9591 static inline void gen_efsnabs(DisasContext *ctx)
9592 {
9593 if (unlikely(!ctx->spe_enabled)) {
9594 gen_exception(ctx, POWERPC_EXCP_SPEU);
9595 return;
9596 }
9597 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9598 }
9599 static inline void gen_efsneg(DisasContext *ctx)
9600 {
9601 if (unlikely(!ctx->spe_enabled)) {
9602 gen_exception(ctx, POWERPC_EXCP_SPEU);
9603 return;
9604 }
9605 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9606 }
9607
9608 /* Conversion */
9609 GEN_SPEFPUOP_CONV_32_32(efscfui);
9610 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9611 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9612 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9613 GEN_SPEFPUOP_CONV_32_32(efsctui);
9614 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9615 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9616 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9617 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9618 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9619 GEN_SPEFPUOP_CONV_32_64(efscfd);
9620
9621 /* Comparison */
9622 GEN_SPEFPUOP_COMP_32(efscmpgt);
9623 GEN_SPEFPUOP_COMP_32(efscmplt);
9624 GEN_SPEFPUOP_COMP_32(efscmpeq);
9625 GEN_SPEFPUOP_COMP_32(efststgt);
9626 GEN_SPEFPUOP_COMP_32(efststlt);
9627 GEN_SPEFPUOP_COMP_32(efststeq);
9628
9629 /* Opcodes definitions */
9630 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9631 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9632 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9633 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9634 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9635 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9636 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9637 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9638 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9639 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9640 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9641 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9642 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9643 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9644
9645 /* Double precision floating-point operations */
9646 /* Arithmetic */
9647 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9648 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9649 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9650 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9651 static inline void gen_efdabs(DisasContext *ctx)
9652 {
9653 if (unlikely(!ctx->spe_enabled)) {
9654 gen_exception(ctx, POWERPC_EXCP_SPEU);
9655 return;
9656 }
9657 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9658 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9659 ~0x80000000);
9660 }
9661 static inline void gen_efdnabs(DisasContext *ctx)
9662 {
9663 if (unlikely(!ctx->spe_enabled)) {
9664 gen_exception(ctx, POWERPC_EXCP_SPEU);
9665 return;
9666 }
9667 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9668 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9669 0x80000000);
9670 }
9671 static inline void gen_efdneg(DisasContext *ctx)
9672 {
9673 if (unlikely(!ctx->spe_enabled)) {
9674 gen_exception(ctx, POWERPC_EXCP_SPEU);
9675 return;
9676 }
9677 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9678 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9679 0x80000000);
9680 }
9681
9682 /* Conversion */
9683 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9684 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9685 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9686 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9687 GEN_SPEFPUOP_CONV_32_64(efdctui);
9688 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9689 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9690 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9691 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9692 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9693 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9694 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9695 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9696 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9697 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9698
9699 /* Comparison */
9700 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9701 GEN_SPEFPUOP_COMP_64(efdcmplt);
9702 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9703 GEN_SPEFPUOP_COMP_64(efdtstgt);
9704 GEN_SPEFPUOP_COMP_64(efdtstlt);
9705 GEN_SPEFPUOP_COMP_64(efdtsteq);
9706
9707 /* Opcodes definitions */
9708 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9709 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9710 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9711 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9712 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9713 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9714 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9715 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9716 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9717 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9718 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9719 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9720 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9721 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9722 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9723 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9724
9725 static void gen_tbegin(DisasContext *ctx)
9726 {
9727 if (unlikely(!ctx->tm_enabled)) {
9728 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9729 return;
9730 }
9731 gen_helper_tbegin(cpu_env);
9732 }
9733
9734 #define GEN_TM_NOOP(name) \
9735 static inline void gen_##name(DisasContext *ctx) \
9736 { \
9737 if (unlikely(!ctx->tm_enabled)) { \
9738 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9739 return; \
9740 } \
9741 /* Because tbegin always fails in QEMU, these user \
9742 * space instructions all have a simple implementation: \
9743 * \
9744 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9745 * = 0b0 || 0b00 || 0b0 \
9746 */ \
9747 tcg_gen_movi_i32(cpu_crf[0], 0); \
9748 }
9749
9750 GEN_TM_NOOP(tend);
9751 GEN_TM_NOOP(tabort);
9752 GEN_TM_NOOP(tabortwc);
9753 GEN_TM_NOOP(tabortwci);
9754 GEN_TM_NOOP(tabortdc);
9755 GEN_TM_NOOP(tabortdci);
9756 GEN_TM_NOOP(tsr);
9757
9758 static void gen_tcheck(DisasContext *ctx)
9759 {
9760 if (unlikely(!ctx->tm_enabled)) {
9761 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9762 return;
9763 }
9764 /* Because tbegin always fails, the tcheck implementation
9765 * is simple:
9766 *
9767 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
9768 * = 0b1 || 0b00 || 0b0
9769 */
9770 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
9771 }
9772
9773 #if defined(CONFIG_USER_ONLY)
9774 #define GEN_TM_PRIV_NOOP(name) \
9775 static inline void gen_##name(DisasContext *ctx) \
9776 { \
9777 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9778 }
9779
9780 #else
9781
9782 #define GEN_TM_PRIV_NOOP(name) \
9783 static inline void gen_##name(DisasContext *ctx) \
9784 { \
9785 if (unlikely(ctx->pr)) { \
9786 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9787 return; \
9788 } \
9789 if (unlikely(!ctx->tm_enabled)) { \
9790 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9791 return; \
9792 } \
9793 /* Because tbegin always fails, the implementation is \
9794 * simple: \
9795 * \
9796 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9797 * = 0b0 || 0b00 | 0b0 \
9798 */ \
9799 tcg_gen_movi_i32(cpu_crf[0], 0); \
9800 }
9801
9802 #endif
9803
9804 GEN_TM_PRIV_NOOP(treclaim);
9805 GEN_TM_PRIV_NOOP(trechkpt);
9806
9807 static opcode_t opcodes[] = {
9808 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9809 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9810 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9811 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9812 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9813 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9814 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9815 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9816 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9817 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9818 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9819 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9820 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9821 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9822 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9823 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9824 #if defined(TARGET_PPC64)
9825 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9826 #endif
9827 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9828 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9829 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9830 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9831 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9832 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9833 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9834 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9835 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9836 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9837 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9838 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9839 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
9840 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9841 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9842 #if defined(TARGET_PPC64)
9843 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9844 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9845 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9846 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9847 #endif
9848 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9849 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9850 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9851 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9852 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9853 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9854 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9855 #if defined(TARGET_PPC64)
9856 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9857 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9858 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9859 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9860 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9861 #endif
9862 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9863 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9864 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9865 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9866 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9867 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9868 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9869 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9870 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9871 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9872 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9873 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9874 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9875 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9876 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9877 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9878 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9879 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9880 #if defined(TARGET_PPC64)
9881 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9882 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9883 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9884 #endif
9885 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9886 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9887 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9888 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9889 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9890 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9891 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9892 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9893 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9894 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9895 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9896 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9897 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9898 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9899 #if defined(TARGET_PPC64)
9900 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9901 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
9902 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9903 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
9904 #endif
9905 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9906 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9907 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9908 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9909 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9910 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9911 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
9912 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9913 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9914 #if defined(TARGET_PPC64)
9915 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9916 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9917 #endif
9918 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9919 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9920 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9921 #if defined(TARGET_PPC64)
9922 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9923 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9924 #endif
9925 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9926 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9927 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9928 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9929 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9930 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9931 #if defined(TARGET_PPC64)
9932 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9933 #endif
9934 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
9935 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
9936 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9937 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9938 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9939 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9940 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
9941 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
9942 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9943 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9944 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9945 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9946 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9947 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9948 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9949 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9950 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9951 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9952 #if defined(TARGET_PPC64)
9953 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9954 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9955 PPC_SEGMENT_64B),
9956 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9957 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9958 PPC_SEGMENT_64B),
9959 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9960 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9961 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
9962 #endif
9963 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9964 /* XXX Those instructions will need to be handled differently for
9965 * different ISA versions */
9966 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
9967 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
9968 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9969 #if defined(TARGET_PPC64)
9970 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9971 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9972 #endif
9973 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9974 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9975 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9976 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9977 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9978 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9979 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9980 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9981 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9982 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9983 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9984 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9985 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9986 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9987 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9988 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9989 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9990 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9991 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9992 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9993 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9994 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9995 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9996 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9997 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9998 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9999 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
10000 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
10001 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
10002 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
10003 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
10004 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
10005 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
10006 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
10007 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
10008 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
10009 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
10010 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
10011 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
10012 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
10013 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
10014 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
10015 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
10016 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
10017 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
10018 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
10019 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
10020 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
10021 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
10022 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10023 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10024 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
10025 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
10026 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10027 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10028 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
10029 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
10030 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
10031 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
10032 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
10033 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
10034 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
10035 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
10036 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
10037 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
10038 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
10039 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
10040 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
10041 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
10042 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
10043 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
10044 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
10045 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
10046 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
10047 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
10048 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
10049 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
10050 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
10051 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
10052 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
10053 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10054 PPC_NONE, PPC2_BOOKE206),
10055 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10056 PPC_NONE, PPC2_BOOKE206),
10057 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10058 PPC_NONE, PPC2_BOOKE206),
10059 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10060 PPC_NONE, PPC2_BOOKE206),
10061 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10062 PPC_NONE, PPC2_BOOKE206),
10063 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10064 PPC_NONE, PPC2_PRCNTL),
10065 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10066 PPC_NONE, PPC2_PRCNTL),
10067 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
10068 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
10069 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
10070 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
10071 PPC_BOOKE, PPC2_BOOKE206),
10072 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
10073 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10074 PPC_BOOKE, PPC2_BOOKE206),
10075 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
10076 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
10077 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
10078 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
10079 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
10080 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
10081 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
10082 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
10083 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
10084
10085 #undef GEN_INT_ARITH_ADD
10086 #undef GEN_INT_ARITH_ADD_CONST
10087 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10088 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10089 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10090 add_ca, compute_ca, compute_ov) \
10091 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10092 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
10093 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
10094 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
10095 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
10096 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
10097 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
10098 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
10099 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
10100 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
10101 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
10102
10103 #undef GEN_INT_ARITH_DIVW
10104 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10105 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10106 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
10107 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
10108 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
10109 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
10110 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10111 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10112 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10113 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10114
10115 #if defined(TARGET_PPC64)
10116 #undef GEN_INT_ARITH_DIVD
10117 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10118 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10119 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
10120 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
10121 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
10122 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10123
10124 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10125 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10126 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10127 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10128
10129 #undef GEN_INT_ARITH_MUL_HELPER
10130 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10131 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10132 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10133 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10134 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10135 #endif
10136
10137 #undef GEN_INT_ARITH_SUBF
10138 #undef GEN_INT_ARITH_SUBF_CONST
10139 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10140 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10141 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10142 add_ca, compute_ca, compute_ov) \
10143 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10144 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10145 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10146 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10147 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10148 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10149 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10150 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10151 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10152 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10153 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10154
10155 #undef GEN_LOGICAL1
10156 #undef GEN_LOGICAL2
10157 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
10158 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10159 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
10160 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10161 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10162 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10163 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10164 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10165 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10166 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10167 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10168 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10169 #if defined(TARGET_PPC64)
10170 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10171 #endif
10172
10173 #if defined(TARGET_PPC64)
10174 #undef GEN_PPC64_R2
10175 #undef GEN_PPC64_R4
10176 #define GEN_PPC64_R2(name, opc1, opc2) \
10177 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10178 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10179 PPC_64B)
10180 #define GEN_PPC64_R4(name, opc1, opc2) \
10181 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10182 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10183 PPC_64B), \
10184 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10185 PPC_64B), \
10186 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10187 PPC_64B)
10188 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10189 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10190 GEN_PPC64_R4(rldic, 0x1E, 0x04),
10191 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10192 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10193 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10194 #endif
10195
10196 #undef _GEN_FLOAT_ACB
10197 #undef GEN_FLOAT_ACB
10198 #undef _GEN_FLOAT_AB
10199 #undef GEN_FLOAT_AB
10200 #undef _GEN_FLOAT_AC
10201 #undef GEN_FLOAT_AC
10202 #undef GEN_FLOAT_B
10203 #undef GEN_FLOAT_BS
10204 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10205 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10206 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10207 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10208 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10209 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10210 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10211 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10212 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10213 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10214 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10215 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10216 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10217 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10218 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10219 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10220 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10221 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10222 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10223
10224 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10225 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10226 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10227 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10228 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10229 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10230 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10231 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10232 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10233 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10234 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10235 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10236 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10237 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10238 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10239 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10240 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10241 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10242 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10243 GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10244 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10245 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10246 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10247 GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10248 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10249 GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10250 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10251 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10252 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10253 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10254 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10255
10256 #undef GEN_LD
10257 #undef GEN_LDU
10258 #undef GEN_LDUX
10259 #undef GEN_LDX_E
10260 #undef GEN_LDS
10261 #define GEN_LD(name, ldop, opc, type) \
10262 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10263 #define GEN_LDU(name, ldop, opc, type) \
10264 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10265 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10266 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10267 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10268 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10269 #define GEN_LDS(name, ldop, op, type) \
10270 GEN_LD(name, ldop, op | 0x20, type) \
10271 GEN_LDU(name, ldop, op | 0x21, type) \
10272 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10273 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10274
10275 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10276 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10277 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10278 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10279 #if defined(TARGET_PPC64)
10280 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10281 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10282 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10283 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10284 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
10285 #endif
10286 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10287 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10288
10289 #undef GEN_ST
10290 #undef GEN_STU
10291 #undef GEN_STUX
10292 #undef GEN_STX_E
10293 #undef GEN_STS
10294 #define GEN_ST(name, stop, opc, type) \
10295 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10296 #define GEN_STU(name, stop, opc, type) \
10297 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10298 #define GEN_STUX(name, stop, opc2, opc3, type) \
10299 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10300 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10301 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10302 #define GEN_STS(name, stop, op, type) \
10303 GEN_ST(name, stop, op | 0x20, type) \
10304 GEN_STU(name, stop, op | 0x21, type) \
10305 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10306 GEN_STX(name, stop, 0x17, op | 0x00, type)
10307
10308 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10309 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10310 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10311 #if defined(TARGET_PPC64)
10312 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10313 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10314 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
10315 #endif
10316 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10317 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10318
10319 #undef GEN_LDF
10320 #undef GEN_LDUF
10321 #undef GEN_LDUXF
10322 #undef GEN_LDXF
10323 #undef GEN_LDFS
10324 #define GEN_LDF(name, ldop, opc, type) \
10325 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10326 #define GEN_LDUF(name, ldop, opc, type) \
10327 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10328 #define GEN_LDUXF(name, ldop, opc, type) \
10329 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10330 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10331 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10332 #define GEN_LDFS(name, ldop, op, type) \
10333 GEN_LDF(name, ldop, op | 0x20, type) \
10334 GEN_LDUF(name, ldop, op | 0x21, type) \
10335 GEN_LDUXF(name, ldop, op | 0x01, type) \
10336 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10337
10338 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10339 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10340 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10341 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10342 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10343 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10344
10345 #undef GEN_STF
10346 #undef GEN_STUF
10347 #undef GEN_STUXF
10348 #undef GEN_STXF
10349 #undef GEN_STFS
10350 #define GEN_STF(name, stop, opc, type) \
10351 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10352 #define GEN_STUF(name, stop, opc, type) \
10353 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10354 #define GEN_STUXF(name, stop, opc, type) \
10355 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10356 #define GEN_STXF(name, stop, opc2, opc3, type) \
10357 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10358 #define GEN_STFS(name, stop, op, type) \
10359 GEN_STF(name, stop, op | 0x20, type) \
10360 GEN_STUF(name, stop, op | 0x21, type) \
10361 GEN_STUXF(name, stop, op | 0x01, type) \
10362 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10363
10364 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10365 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10366 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10367 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10368 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10369
10370 #undef GEN_CRLOGIC
10371 #define GEN_CRLOGIC(name, tcg_op, opc) \
10372 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10373 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10374 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10375 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10376 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10377 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10378 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10379 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10380 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10381
10382 #undef GEN_MAC_HANDLER
10383 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10384 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10385 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10386 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10387 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10388 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10389 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10390 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10391 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10392 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10393 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10394 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10395 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10396 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10397 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10398 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10399 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10400 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10401 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10402 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10403 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10404 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10405 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10406 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10407 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10408 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10409 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10410 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10411 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10412 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10413 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10414 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10415 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10416 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10417 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10418 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10419 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10420 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10421 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10422 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10423 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10424 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10425 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10426 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10427
10428 #undef GEN_VR_LDX
10429 #undef GEN_VR_STX
10430 #undef GEN_VR_LVE
10431 #undef GEN_VR_STVE
10432 #define GEN_VR_LDX(name, opc2, opc3) \
10433 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10434 #define GEN_VR_STX(name, opc2, opc3) \
10435 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10436 #define GEN_VR_LVE(name, opc2, opc3) \
10437 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10438 #define GEN_VR_STVE(name, opc2, opc3) \
10439 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10440 GEN_VR_LDX(lvx, 0x07, 0x03),
10441 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10442 GEN_VR_LVE(bx, 0x07, 0x00),
10443 GEN_VR_LVE(hx, 0x07, 0x01),
10444 GEN_VR_LVE(wx, 0x07, 0x02),
10445 GEN_VR_STX(svx, 0x07, 0x07),
10446 GEN_VR_STX(svxl, 0x07, 0x0F),
10447 GEN_VR_STVE(bx, 0x07, 0x04),
10448 GEN_VR_STVE(hx, 0x07, 0x05),
10449 GEN_VR_STVE(wx, 0x07, 0x06),
10450
10451 #undef GEN_VX_LOGICAL
10452 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10453 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10454
10455 #undef GEN_VX_LOGICAL_207
10456 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10457 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10458
10459 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10460 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10461 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10462 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10463 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10464 GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10465 GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10466 GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
10467
10468 #undef GEN_VXFORM
10469 #define GEN_VXFORM(name, opc2, opc3) \
10470 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10471
10472 #undef GEN_VXFORM_207
10473 #define GEN_VXFORM_207(name, opc2, opc3) \
10474 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10475
10476 #undef GEN_VXFORM_DUAL
10477 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10478 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10479
10480 #undef GEN_VXRFORM_DUAL
10481 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10482 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10483 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10484
10485 GEN_VXFORM(vaddubm, 0, 0),
10486 GEN_VXFORM(vadduhm, 0, 1),
10487 GEN_VXFORM(vadduwm, 0, 2),
10488 GEN_VXFORM_207(vaddudm, 0, 3),
10489 GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10490 GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
10491 GEN_VXFORM(vsubuwm, 0, 18),
10492 GEN_VXFORM_207(vsubudm, 0, 19),
10493 GEN_VXFORM(vmaxub, 1, 0),
10494 GEN_VXFORM(vmaxuh, 1, 1),
10495 GEN_VXFORM(vmaxuw, 1, 2),
10496 GEN_VXFORM_207(vmaxud, 1, 3),
10497 GEN_VXFORM(vmaxsb, 1, 4),
10498 GEN_VXFORM(vmaxsh, 1, 5),
10499 GEN_VXFORM(vmaxsw, 1, 6),
10500 GEN_VXFORM_207(vmaxsd, 1, 7),
10501 GEN_VXFORM(vminub, 1, 8),
10502 GEN_VXFORM(vminuh, 1, 9),
10503 GEN_VXFORM(vminuw, 1, 10),
10504 GEN_VXFORM_207(vminud, 1, 11),
10505 GEN_VXFORM(vminsb, 1, 12),
10506 GEN_VXFORM(vminsh, 1, 13),
10507 GEN_VXFORM(vminsw, 1, 14),
10508 GEN_VXFORM_207(vminsd, 1, 15),
10509 GEN_VXFORM(vavgub, 1, 16),
10510 GEN_VXFORM(vavguh, 1, 17),
10511 GEN_VXFORM(vavguw, 1, 18),
10512 GEN_VXFORM(vavgsb, 1, 20),
10513 GEN_VXFORM(vavgsh, 1, 21),
10514 GEN_VXFORM(vavgsw, 1, 22),
10515 GEN_VXFORM(vmrghb, 6, 0),
10516 GEN_VXFORM(vmrghh, 6, 1),
10517 GEN_VXFORM(vmrghw, 6, 2),
10518 GEN_VXFORM(vmrglb, 6, 4),
10519 GEN_VXFORM(vmrglh, 6, 5),
10520 GEN_VXFORM(vmrglw, 6, 6),
10521 GEN_VXFORM_207(vmrgew, 6, 30),
10522 GEN_VXFORM_207(vmrgow, 6, 26),
10523 GEN_VXFORM(vmuloub, 4, 0),
10524 GEN_VXFORM(vmulouh, 4, 1),
10525 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
10526 GEN_VXFORM(vmulosb, 4, 4),
10527 GEN_VXFORM(vmulosh, 4, 5),
10528 GEN_VXFORM_207(vmulosw, 4, 6),
10529 GEN_VXFORM(vmuleub, 4, 8),
10530 GEN_VXFORM(vmuleuh, 4, 9),
10531 GEN_VXFORM_207(vmuleuw, 4, 10),
10532 GEN_VXFORM(vmulesb, 4, 12),
10533 GEN_VXFORM(vmulesh, 4, 13),
10534 GEN_VXFORM_207(vmulesw, 4, 14),
10535 GEN_VXFORM(vslb, 2, 4),
10536 GEN_VXFORM(vslh, 2, 5),
10537 GEN_VXFORM(vslw, 2, 6),
10538 GEN_VXFORM_207(vsld, 2, 23),
10539 GEN_VXFORM(vsrb, 2, 8),
10540 GEN_VXFORM(vsrh, 2, 9),
10541 GEN_VXFORM(vsrw, 2, 10),
10542 GEN_VXFORM_207(vsrd, 2, 27),
10543 GEN_VXFORM(vsrab, 2, 12),
10544 GEN_VXFORM(vsrah, 2, 13),
10545 GEN_VXFORM(vsraw, 2, 14),
10546 GEN_VXFORM_207(vsrad, 2, 15),
10547 GEN_VXFORM(vslo, 6, 16),
10548 GEN_VXFORM(vsro, 6, 17),
10549 GEN_VXFORM(vaddcuw, 0, 6),
10550 GEN_VXFORM(vsubcuw, 0, 22),
10551 GEN_VXFORM(vaddubs, 0, 8),
10552 GEN_VXFORM(vadduhs, 0, 9),
10553 GEN_VXFORM(vadduws, 0, 10),
10554 GEN_VXFORM(vaddsbs, 0, 12),
10555 GEN_VXFORM(vaddshs, 0, 13),
10556 GEN_VXFORM(vaddsws, 0, 14),
10557 GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10558 GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
10559 GEN_VXFORM(vsubuws, 0, 26),
10560 GEN_VXFORM(vsubsbs, 0, 28),
10561 GEN_VXFORM(vsubshs, 0, 29),
10562 GEN_VXFORM(vsubsws, 0, 30),
10563 GEN_VXFORM_207(vadduqm, 0, 4),
10564 GEN_VXFORM_207(vaddcuq, 0, 5),
10565 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10566 GEN_VXFORM_207(vsubuqm, 0, 20),
10567 GEN_VXFORM_207(vsubcuq, 0, 21),
10568 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10569 GEN_VXFORM(vrlb, 2, 0),
10570 GEN_VXFORM(vrlh, 2, 1),
10571 GEN_VXFORM(vrlw, 2, 2),
10572 GEN_VXFORM_207(vrld, 2, 3),
10573 GEN_VXFORM(vsl, 2, 7),
10574 GEN_VXFORM(vsr, 2, 11),
10575 GEN_VXFORM(vpkuhum, 7, 0),
10576 GEN_VXFORM(vpkuwum, 7, 1),
10577 GEN_VXFORM_207(vpkudum, 7, 17),
10578 GEN_VXFORM(vpkuhus, 7, 2),
10579 GEN_VXFORM(vpkuwus, 7, 3),
10580 GEN_VXFORM_207(vpkudus, 7, 19),
10581 GEN_VXFORM(vpkshus, 7, 4),
10582 GEN_VXFORM(vpkswus, 7, 5),
10583 GEN_VXFORM_207(vpksdus, 7, 21),
10584 GEN_VXFORM(vpkshss, 7, 6),
10585 GEN_VXFORM(vpkswss, 7, 7),
10586 GEN_VXFORM_207(vpksdss, 7, 23),
10587 GEN_VXFORM(vpkpx, 7, 12),
10588 GEN_VXFORM(vsum4ubs, 4, 24),
10589 GEN_VXFORM(vsum4sbs, 4, 28),
10590 GEN_VXFORM(vsum4shs, 4, 25),
10591 GEN_VXFORM(vsum2sws, 4, 26),
10592 GEN_VXFORM(vsumsws, 4, 30),
10593 GEN_VXFORM(vaddfp, 5, 0),
10594 GEN_VXFORM(vsubfp, 5, 1),
10595 GEN_VXFORM(vmaxfp, 5, 16),
10596 GEN_VXFORM(vminfp, 5, 17),
10597
10598 #undef GEN_VXRFORM1
10599 #undef GEN_VXRFORM
10600 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10601 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10602 #define GEN_VXRFORM(name, opc2, opc3) \
10603 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10604 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10605 GEN_VXRFORM(vcmpequb, 3, 0)
10606 GEN_VXRFORM(vcmpequh, 3, 1)
10607 GEN_VXRFORM(vcmpequw, 3, 2)
10608 GEN_VXRFORM(vcmpgtsb, 3, 12)
10609 GEN_VXRFORM(vcmpgtsh, 3, 13)
10610 GEN_VXRFORM(vcmpgtsw, 3, 14)
10611 GEN_VXRFORM(vcmpgtub, 3, 8)
10612 GEN_VXRFORM(vcmpgtuh, 3, 9)
10613 GEN_VXRFORM(vcmpgtuw, 3, 10)
10614 GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
10615 GEN_VXRFORM(vcmpgefp, 3, 7)
10616 GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10617 GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
10618
10619 #undef GEN_VXFORM_SIMM
10620 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10621 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10622 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10623 GEN_VXFORM_SIMM(vspltish, 6, 13),
10624 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10625
10626 #undef GEN_VXFORM_NOA
10627 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10628 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10629 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10630 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10631 GEN_VXFORM_207(vupkhsw, 7, 25),
10632 GEN_VXFORM_NOA(vupklsb, 7, 10),
10633 GEN_VXFORM_NOA(vupklsh, 7, 11),
10634 GEN_VXFORM_207(vupklsw, 7, 27),
10635 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10636 GEN_VXFORM_NOA(vupklpx, 7, 15),
10637 GEN_VXFORM_NOA(vrefp, 5, 4),
10638 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10639 GEN_VXFORM_NOA(vexptefp, 5, 6),
10640 GEN_VXFORM_NOA(vlogefp, 5, 7),
10641 GEN_VXFORM_NOA(vrfim, 5, 11),
10642 GEN_VXFORM_NOA(vrfin, 5, 8),
10643 GEN_VXFORM_NOA(vrfip, 5, 10),
10644 GEN_VXFORM_NOA(vrfiz, 5, 9),
10645
10646 #undef GEN_VXFORM_UIMM
10647 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10648 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10649 GEN_VXFORM_UIMM(vspltb, 6, 8),
10650 GEN_VXFORM_UIMM(vsplth, 6, 9),
10651 GEN_VXFORM_UIMM(vspltw, 6, 10),
10652 GEN_VXFORM_UIMM(vcfux, 5, 12),
10653 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10654 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10655 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10656
10657 #undef GEN_VAFORM_PAIRED
10658 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10659 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10660 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10661 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10662 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10663 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10664 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10665 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10666
10667 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10668 GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10669 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10670 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10671
10672 GEN_VXFORM_207(vbpermq, 6, 21),
10673 GEN_VXFORM_207(vgbbd, 6, 20),
10674 GEN_VXFORM_207(vpmsumb, 4, 16),
10675 GEN_VXFORM_207(vpmsumh, 4, 17),
10676 GEN_VXFORM_207(vpmsumw, 4, 18),
10677 GEN_VXFORM_207(vpmsumd, 4, 19),
10678
10679 GEN_VXFORM_207(vsbox, 4, 23),
10680
10681 GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10682 GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10683
10684 GEN_VXFORM_207(vshasigmaw, 1, 26),
10685 GEN_VXFORM_207(vshasigmad, 1, 27),
10686
10687 GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10688
10689 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10690 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10691 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10692 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10693 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10694 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10695 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10696
10697 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10698 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10699 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10700 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10701 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10702
10703 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10704 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10705 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10706 #if defined(TARGET_PPC64)
10707 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10708 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10709 #endif
10710
10711 #undef GEN_XX2FORM
10712 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10713 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10714 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10715
10716 #undef GEN_XX3FORM
10717 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10718 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10719 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10720 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10721 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10722
10723 #undef GEN_XX2IFORM
10724 #define GEN_XX2IFORM(name, opc2, opc3, fl2) \
10725 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
10726 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
10727 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
10728 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
10729
10730 #undef GEN_XX3_RC_FORM
10731 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10732 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10733 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10734 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10735 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10736 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10737 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10738 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10739 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10740
10741 #undef GEN_XX3FORM_DM
10742 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10743 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10744 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10745 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10746 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10747 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10748 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10749 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10750 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10751 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10752 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10753 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10754 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10755 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10756 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10757 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10758 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10759
10760 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10761 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10762 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10763 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10764
10765 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10766 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10767 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10768 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10769 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10770 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10771 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10772 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10773
10774 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10775 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10776 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10777 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10778 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10779 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10780 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10781 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10782 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10783 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10784 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10785 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10786 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10787 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10788 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10789 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10790 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10791 GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10792 GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10793 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10794 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10795 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10796 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10797 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10798 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10799 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10800 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10801 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10802 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10803 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10804 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10805 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10806 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10807 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10808 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10809 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10810
10811 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10812 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10813 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10814 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10815 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10816 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10817 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10818 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10819 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10820 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10821 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10822 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10823 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10824 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10825 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10826 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10827 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10828 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10829
10830 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10831 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10832 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10833 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10834 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10835 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10836 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10837 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10838 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10839 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10840 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10841 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10842 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10843 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10844 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10845 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10846 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10847 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10848 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10849 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10850 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10851 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10852 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10853 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10854 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10855 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10856 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10857 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10858 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10859 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10860 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10861 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10862 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10863 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10864 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10865 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10866
10867 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10868 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10869 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10870 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10871 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10872 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10873 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10874 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10875 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10876 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10877 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10878 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10879 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10880 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10881 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10882 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10883 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10884 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10885 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10886 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10887 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10888 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10889 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10890 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10891 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10892 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10893 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10894 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10895 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10896 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10897 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10898 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10899 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10900 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10901 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10902 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10903
10904 #undef VSX_LOGICAL
10905 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10906 GEN_XX3FORM(name, opc2, opc3, fl2)
10907
10908 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10909 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10910 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10911 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10912 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10913 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10914 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10915 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10916 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10917 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10918 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10919 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10920
10921 #define GEN_XXSEL_ROW(opc3) \
10922 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10923 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10924 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10925 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10926 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10927 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10928 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10929 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10930
10931 GEN_XXSEL_ROW(0x00)
10932 GEN_XXSEL_ROW(0x01)
10933 GEN_XXSEL_ROW(0x02)
10934 GEN_XXSEL_ROW(0x03)
10935 GEN_XXSEL_ROW(0x04)
10936 GEN_XXSEL_ROW(0x05)
10937 GEN_XXSEL_ROW(0x06)
10938 GEN_XXSEL_ROW(0x07)
10939 GEN_XXSEL_ROW(0x08)
10940 GEN_XXSEL_ROW(0x09)
10941 GEN_XXSEL_ROW(0x0A)
10942 GEN_XXSEL_ROW(0x0B)
10943 GEN_XXSEL_ROW(0x0C)
10944 GEN_XXSEL_ROW(0x0D)
10945 GEN_XXSEL_ROW(0x0E)
10946 GEN_XXSEL_ROW(0x0F)
10947 GEN_XXSEL_ROW(0x10)
10948 GEN_XXSEL_ROW(0x11)
10949 GEN_XXSEL_ROW(0x12)
10950 GEN_XXSEL_ROW(0x13)
10951 GEN_XXSEL_ROW(0x14)
10952 GEN_XXSEL_ROW(0x15)
10953 GEN_XXSEL_ROW(0x16)
10954 GEN_XXSEL_ROW(0x17)
10955 GEN_XXSEL_ROW(0x18)
10956 GEN_XXSEL_ROW(0x19)
10957 GEN_XXSEL_ROW(0x1A)
10958 GEN_XXSEL_ROW(0x1B)
10959 GEN_XXSEL_ROW(0x1C)
10960 GEN_XXSEL_ROW(0x1D)
10961 GEN_XXSEL_ROW(0x1E)
10962 GEN_XXSEL_ROW(0x1F)
10963
10964 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10965
10966 #undef GEN_DFP_T_A_B_Rc
10967 #undef GEN_DFP_BF_A_B
10968 #undef GEN_DFP_BF_A_DCM
10969 #undef GEN_DFP_T_B_U32_U32_Rc
10970 #undef GEN_DFP_T_A_B_I32_Rc
10971 #undef GEN_DFP_T_B_Rc
10972 #undef GEN_DFP_T_FPR_I32_Rc
10973
10974 #define _GEN_DFP_LONG(name, op1, op2, mask) \
10975 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
10976
10977 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
10978 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10979 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10980
10981 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
10982 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10983 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10984 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10985 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10986
10987 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
10988 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
10989
10990 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
10991 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10992 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10993
10994 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
10995 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10996 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10997 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10998 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10999
11000 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
11001 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
11002
11003 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
11004 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
11005
11006 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
11007 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
11008
11009 #define GEN_DFP_T_B_Rc(name, op1, op2) \
11010 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
11011
11012 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
11013 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
11014
11015 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
11016 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
11017
11018 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
11019 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
11020
11021 #define GEN_DFP_BF_A_B(name, op1, op2) \
11022 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
11023
11024 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
11025 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
11026
11027 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
11028 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
11029
11030 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
11031 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
11032
11033 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
11034 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
11035
11036 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
11037 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11038
11039 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
11040 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
11041
11042 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
11043 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
11044
11045 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
11046 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11047
11048 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
11049 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
11050
11051 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11052 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11053
11054 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11055 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11056
11057 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11058 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
11059
11060 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11061 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11062
11063 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11064 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11065
11066 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11067 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11068
11069 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11070 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11071
11072 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11073 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11074
11075 GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
11076 GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
11077 GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
11078 GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
11079 GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
11080 GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
11081 GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
11082 GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
11083 GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
11084 GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
11085 GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
11086 GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
11087 GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
11088 GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
11089 GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
11090 GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
11091 GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
11092 GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
11093 GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
11094 GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
11095 GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
11096 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
11097 GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
11098 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
11099 GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
11100 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
11101 GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
11102 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
11103 GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
11104 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
11105 GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
11106 GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
11107 GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
11108 GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
11109 GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
11110 GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
11111 GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
11112 GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
11113 GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
11114 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
11115 GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
11116 GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
11117 GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
11118 GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
11119 GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
11120 GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
11121 GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
11122 GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
11123 GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
11124 GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
11125
11126 #undef GEN_SPE
11127 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11128 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11129 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11130 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11131 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11132 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11133 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11134 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11135 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11136 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
11137 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
11138 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11139 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11140 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11141 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11142 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11143 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11144 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
11145 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11146 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11147 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11148 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11149 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11150 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11151 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11152 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11153 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11154 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11155 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11156 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11157 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11158
11159 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11160 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11161 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11162 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11163 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11164 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11165 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11166 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11167 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11168 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11169 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11170 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11171 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11172 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11173
11174 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11175 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11176 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11177 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11178 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11179 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11180 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11181 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11182 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11183 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11184 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11185 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11186 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11187 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11188
11189 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11190 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11191 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11192 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11193 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11194 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11195 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11196 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11197 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11198 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11199 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11200 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11201 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11202 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11203 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11204 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11205
11206 #undef GEN_SPEOP_LDST
11207 #define GEN_SPEOP_LDST(name, opc2, sh) \
11208 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11209 GEN_SPEOP_LDST(evldd, 0x00, 3),
11210 GEN_SPEOP_LDST(evldw, 0x01, 3),
11211 GEN_SPEOP_LDST(evldh, 0x02, 3),
11212 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11213 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11214 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11215 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11216 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11217 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11218 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11219 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11220
11221 GEN_SPEOP_LDST(evstdd, 0x10, 3),
11222 GEN_SPEOP_LDST(evstdw, 0x11, 3),
11223 GEN_SPEOP_LDST(evstdh, 0x12, 3),
11224 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11225 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11226 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11227 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
11228
11229 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11230 PPC_NONE, PPC2_TM),
11231 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11232 PPC_NONE, PPC2_TM),
11233 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11234 PPC_NONE, PPC2_TM),
11235 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11236 PPC_NONE, PPC2_TM),
11237 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11238 PPC_NONE, PPC2_TM),
11239 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11240 PPC_NONE, PPC2_TM),
11241 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11242 PPC_NONE, PPC2_TM),
11243 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11244 PPC_NONE, PPC2_TM),
11245 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
11246 PPC_NONE, PPC2_TM),
11247 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
11248 PPC_NONE, PPC2_TM),
11249 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
11250 PPC_NONE, PPC2_TM),
11251 };
11252
11253 #include "helper_regs.h"
11254 #include "translate_init.c"
11255
11256 /*****************************************************************************/
11257 /* Misc PowerPC helpers */
11258 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11259 int flags)
11260 {
11261 #define RGPL 4
11262 #define RFPL 4
11263
11264 PowerPCCPU *cpu = POWERPC_CPU(cs);
11265 CPUPPCState *env = &cpu->env;
11266 int i;
11267
11268 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
11269 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
11270 env->nip, env->lr, env->ctr, cpu_read_xer(env),
11271 cs->cpu_index);
11272 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11273 TARGET_FMT_lx " iidx %d didx %d\n",
11274 env->msr, env->spr[SPR_HID0],
11275 env->hflags, env->immu_idx, env->dmmu_idx);
11276 #if !defined(NO_TIMER_DUMP)
11277 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
11278 #if !defined(CONFIG_USER_ONLY)
11279 " DECR %08" PRIu32
11280 #endif
11281 "\n",
11282 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
11283 #if !defined(CONFIG_USER_ONLY)
11284 , cpu_ppc_load_decr(env)
11285 #endif
11286 );
11287 #endif
11288 for (i = 0; i < 32; i++) {
11289 if ((i & (RGPL - 1)) == 0)
11290 cpu_fprintf(f, "GPR%02d", i);
11291 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
11292 if ((i & (RGPL - 1)) == (RGPL - 1))
11293 cpu_fprintf(f, "\n");
11294 }
11295 cpu_fprintf(f, "CR ");
11296 for (i = 0; i < 8; i++)
11297 cpu_fprintf(f, "%01x", env->crf[i]);
11298 cpu_fprintf(f, " [");
11299 for (i = 0; i < 8; i++) {
11300 char a = '-';
11301 if (env->crf[i] & 0x08)
11302 a = 'L';
11303 else if (env->crf[i] & 0x04)
11304 a = 'G';
11305 else if (env->crf[i] & 0x02)
11306 a = 'E';
11307 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
11308 }
11309 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11310 env->reserve_addr);
11311 for (i = 0; i < 32; i++) {
11312 if ((i & (RFPL - 1)) == 0)
11313 cpu_fprintf(f, "FPR%02d", i);
11314 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
11315 if ((i & (RFPL - 1)) == (RFPL - 1))
11316 cpu_fprintf(f, "\n");
11317 }
11318 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
11319 #if !defined(CONFIG_USER_ONLY)
11320 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11321 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11322 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11323 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11324
11325 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11326 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11327 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11328 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11329
11330 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11331 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11332 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11333 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11334
11335 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11336 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11337 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11338 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11339 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11340
11341 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11342 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11343 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11344 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11345
11346 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11347 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11348 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11349 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11350
11351 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11352 " EPR " TARGET_FMT_lx "\n",
11353 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11354 env->spr[SPR_BOOKE_EPR]);
11355
11356 /* FSL-specific */
11357 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11358 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11359 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11360 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11361
11362 /*
11363 * IVORs are left out as they are large and do not change often --
11364 * they can be read with "p $ivor0", "p $ivor1", etc.
11365 */
11366 }
11367
11368 #if defined(TARGET_PPC64)
11369 if (env->flags & POWERPC_FLAG_CFAR) {
11370 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11371 }
11372 #endif
11373
11374 switch (env->mmu_model) {
11375 case POWERPC_MMU_32B:
11376 case POWERPC_MMU_601:
11377 case POWERPC_MMU_SOFT_6xx:
11378 case POWERPC_MMU_SOFT_74xx:
11379 #if defined(TARGET_PPC64)
11380 case POWERPC_MMU_64B:
11381 case POWERPC_MMU_2_03:
11382 case POWERPC_MMU_2_06:
11383 case POWERPC_MMU_2_06a:
11384 case POWERPC_MMU_2_07:
11385 case POWERPC_MMU_2_07a:
11386 #endif
11387 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11388 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11389 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
11390 break;
11391 case POWERPC_MMU_BOOKE206:
11392 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11393 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11394 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11395 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11396
11397 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11398 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11399 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11400 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11401
11402 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11403 " TLB1CFG " TARGET_FMT_lx "\n",
11404 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11405 env->spr[SPR_BOOKE_TLB1CFG]);
11406 break;
11407 default:
11408 break;
11409 }
11410 #endif
11411
11412 #undef RGPL
11413 #undef RFPL
11414 }
11415
11416 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11417 fprintf_function cpu_fprintf, int flags)
11418 {
11419 #if defined(DO_PPC_STATISTICS)
11420 PowerPCCPU *cpu = POWERPC_CPU(cs);
11421 opc_handler_t **t1, **t2, **t3, *handler;
11422 int op1, op2, op3;
11423
11424 t1 = cpu->env.opcodes;
11425 for (op1 = 0; op1 < 64; op1++) {
11426 handler = t1[op1];
11427 if (is_indirect_opcode(handler)) {
11428 t2 = ind_table(handler);
11429 for (op2 = 0; op2 < 32; op2++) {
11430 handler = t2[op2];
11431 if (is_indirect_opcode(handler)) {
11432 t3 = ind_table(handler);
11433 for (op3 = 0; op3 < 32; op3++) {
11434 handler = t3[op3];
11435 if (handler->count == 0)
11436 continue;
11437 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
11438 "%016" PRIx64 " %" PRId64 "\n",
11439 op1, op2, op3, op1, (op3 << 5) | op2,
11440 handler->oname,
11441 handler->count, handler->count);
11442 }
11443 } else {
11444 if (handler->count == 0)
11445 continue;
11446 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
11447 "%016" PRIx64 " %" PRId64 "\n",
11448 op1, op2, op1, op2, handler->oname,
11449 handler->count, handler->count);
11450 }
11451 }
11452 } else {
11453 if (handler->count == 0)
11454 continue;
11455 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11456 " %" PRId64 "\n",
11457 op1, op1, handler->oname,
11458 handler->count, handler->count);
11459 }
11460 }
11461 #endif
11462 }
11463
11464 /*****************************************************************************/
11465 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
11466 {
11467 PowerPCCPU *cpu = ppc_env_get_cpu(env);
11468 CPUState *cs = CPU(cpu);
11469 DisasContext ctx, *ctxp = &ctx;
11470 opc_handler_t **table, *handler;
11471 target_ulong pc_start;
11472 int num_insns;
11473 int max_insns;
11474
11475 pc_start = tb->pc;
11476 ctx.nip = pc_start;
11477 ctx.tb = tb;
11478 ctx.exception = POWERPC_EXCP_NONE;
11479 ctx.spr_cb = env->spr_cb;
11480 ctx.pr = msr_pr;
11481 ctx.hv = !msr_pr && msr_hv;
11482 ctx.mem_idx = env->dmmu_idx;
11483 ctx.insns_flags = env->insns_flags;
11484 ctx.insns_flags2 = env->insns_flags2;
11485 ctx.access_type = -1;
11486 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
11487 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
11488 #if defined(TARGET_PPC64)
11489 ctx.sf_mode = msr_is_64bit(env, env->msr);
11490 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11491 #endif
11492 ctx.fpu_enabled = msr_fp;
11493 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11494 ctx.spe_enabled = msr_spe;
11495 else
11496 ctx.spe_enabled = 0;
11497 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11498 ctx.altivec_enabled = msr_vr;
11499 else
11500 ctx.altivec_enabled = 0;
11501 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11502 ctx.vsx_enabled = msr_vsx;
11503 } else {
11504 ctx.vsx_enabled = 0;
11505 }
11506 #if defined(TARGET_PPC64)
11507 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
11508 ctx.tm_enabled = msr_tm;
11509 } else {
11510 ctx.tm_enabled = 0;
11511 }
11512 #endif
11513 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11514 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11515 else
11516 ctx.singlestep_enabled = 0;
11517 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11518 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11519 if (unlikely(cs->singlestep_enabled)) {
11520 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11521 }
11522 #if defined (DO_SINGLE_STEP) && 0
11523 /* Single step trace mode */
11524 msr_se = 1;
11525 #endif
11526 num_insns = 0;
11527 max_insns = tb->cflags & CF_COUNT_MASK;
11528 if (max_insns == 0) {
11529 max_insns = CF_COUNT_MASK;
11530 }
11531 if (max_insns > TCG_MAX_INSNS) {
11532 max_insns = TCG_MAX_INSNS;
11533 }
11534
11535 gen_tb_start(tb);
11536 tcg_clear_temp_count();
11537 /* Set env in case of segfault during code fetch */
11538 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
11539 tcg_gen_insn_start(ctx.nip);
11540 num_insns++;
11541
11542 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
11543 gen_debug_exception(ctxp);
11544 /* The address covered by the breakpoint must be included in
11545 [tb->pc, tb->pc + tb->size) in order to for it to be
11546 properly cleared -- thus we increment the PC here so that
11547 the logic setting tb->size below does the right thing. */
11548 ctx.nip += 4;
11549 break;
11550 }
11551
11552 LOG_DISAS("----------------\n");
11553 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11554 ctx.nip, ctx.mem_idx, (int)msr_ir);
11555 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
11556 gen_io_start();
11557 if (unlikely(need_byteswap(&ctx))) {
11558 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11559 } else {
11560 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11561 }
11562 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11563 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11564 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11565 ctx.nip += 4;
11566 table = env->opcodes;
11567 handler = table[opc1(ctx.opcode)];
11568 if (is_indirect_opcode(handler)) {
11569 table = ind_table(handler);
11570 handler = table[opc2(ctx.opcode)];
11571 if (is_indirect_opcode(handler)) {
11572 table = ind_table(handler);
11573 handler = table[opc3(ctx.opcode)];
11574 }
11575 }
11576 /* Is opcode *REALLY* valid ? */
11577 if (unlikely(handler->handler == &gen_invalid)) {
11578 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
11579 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11580 opc1(ctx.opcode), opc2(ctx.opcode),
11581 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11582 } else {
11583 uint32_t inval;
11584
11585 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11586 inval = handler->inval2;
11587 } else {
11588 inval = handler->inval1;
11589 }
11590
11591 if (unlikely((ctx.opcode & inval) != 0)) {
11592 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
11593 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11594 ctx.opcode & inval, opc1(ctx.opcode),
11595 opc2(ctx.opcode), opc3(ctx.opcode),
11596 ctx.opcode, ctx.nip - 4);
11597 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11598 break;
11599 }
11600 }
11601 (*(handler->handler))(&ctx);
11602 #if defined(DO_PPC_STATISTICS)
11603 handler->count++;
11604 #endif
11605 /* Check trace mode exceptions */
11606 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11607 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11608 ctx.exception != POWERPC_SYSCALL &&
11609 ctx.exception != POWERPC_EXCP_TRAP &&
11610 ctx.exception != POWERPC_EXCP_BRANCH)) {
11611 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11612 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11613 (cs->singlestep_enabled) ||
11614 singlestep ||
11615 num_insns >= max_insns)) {
11616 /* if we reach a page boundary or are single stepping, stop
11617 * generation
11618 */
11619 break;
11620 }
11621 if (tcg_check_temp_count()) {
11622 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11623 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11624 ctx.opcode);
11625 exit(1);
11626 }
11627 }
11628 if (tb->cflags & CF_LAST_IO)
11629 gen_io_end();
11630 if (ctx.exception == POWERPC_EXCP_NONE) {
11631 gen_goto_tb(&ctx, 0, ctx.nip);
11632 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11633 if (unlikely(cs->singlestep_enabled)) {
11634 gen_debug_exception(ctxp);
11635 }
11636 /* Generate the return instruction */
11637 tcg_gen_exit_tb(0);
11638 }
11639 gen_tb_end(tb, num_insns);
11640
11641 tb->size = ctx.nip - pc_start;
11642 tb->icount = num_insns;
11643
11644 #if defined(DEBUG_DISAS)
11645 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
11646 && qemu_log_in_addr_range(pc_start)) {
11647 int flags;
11648 flags = env->bfd_mach;
11649 flags |= ctx.le_mode << 16;
11650 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11651 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
11652 qemu_log("\n");
11653 }
11654 #endif
11655 }
11656
11657 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
11658 target_ulong *data)
11659 {
11660 env->nip = data[0];
11661 }
AR7 emulation for QEMU