hw/arm/fsl-imx7.c

   1 /*
   2  * Copyright (c) 2018, Impinj, Inc.
   3  *
   4  * i.MX7 SoC definitions
   5  *
   6  * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
   7  *
   8  * Based on hw/arm/fsl-imx6.c
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18  * GNU General Public License for more details.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "hw/arm/fsl-imx7.h"
  24 #include "hw/misc/unimp.h"
  25 #include "hw/boards.h"
  26 #include "sysemu/sysemu.h"
  27 #include "qemu/error-report.h"
  28 #include "qemu/module.h"
  29
  30 #define NAME_SIZE 20
  31
  32 static void fsl_imx7_init(Object *obj)
  33 {
  34     MachineState *ms = MACHINE(qdev_get_machine());
  35     FslIMX7State *s = FSL_IMX7(obj);
  36     char name[NAME_SIZE];
  37     int i;
  38
  39     for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) {
  40         snprintf(name, NAME_SIZE, "cpu%d", i);
  41         object_initialize_child(obj, name, &s->cpu[i],
  42                                 ARM_CPU_TYPE_NAME("cortex-a7"));
  43     }
  44
  45     /*
  46      * A7MPCORE
  47      */
  48     object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
  49                             TYPE_A15MPCORE_PRIV);
  50
  51     /*
  52      * GPIOs 1 to 7
  53      */
  54     for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
  55         snprintf(name, NAME_SIZE, "gpio%d", i);
  56         object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
  57     }
  58
  59     /*
  60      * GPT1, 2, 3, 4
  61      */
  62     for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
  63         snprintf(name, NAME_SIZE, "gpt%d", i);
  64         object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX7_GPT);
  65     }
  66
  67     /*
  68      * CCM
  69      */
  70     object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX7_CCM);
  71
  72     /*
  73      * Analog
  74      */
  75     object_initialize_child(obj, "analog", &s->analog, TYPE_IMX7_ANALOG);
  76
  77     /*
  78      * GPCv2
  79      */
  80     object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
  81
  82     for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
  83         snprintf(name, NAME_SIZE, "spi%d", i + 1);
  84         object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
  85     }
  86
  87
  88     for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
  89         snprintf(name, NAME_SIZE, "i2c%d", i + 1);
  90         object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
  91     }
  92
  93     /*
  94      * UART
  95      */
  96     for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
  97             snprintf(name, NAME_SIZE, "uart%d", i);
  98             object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
  99     }
 100
 101     /*
 102      * Ethernet
 103      */
 104     for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
 105             snprintf(name, NAME_SIZE, "eth%d", i);
 106             object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
 107     }
 108
 109     /*
 110      * SDHCI
 111      */
 112     for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
 113             snprintf(name, NAME_SIZE, "usdhc%d", i);
 114             object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
 115     }
 116
 117     /*
 118      * SNVS
 119      */
 120     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
 121
 122     /*
 123      * Watchdog
 124      */
 125     for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
 126             snprintf(name, NAME_SIZE, "wdt%d", i);
 127             object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);
 128     }
 129
 130     /*
 131      * GPR
 132      */
 133     object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
 134
 135     object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
 136
 137     for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
 138         snprintf(name, NAME_SIZE, "usb%d", i);
 139         object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
 140     }
 141 }
 142
 143 static void fsl_imx7_realize(DeviceState *dev, Error **errp)
 144 {
 145     MachineState *ms = MACHINE(qdev_get_machine());
 146     FslIMX7State *s = FSL_IMX7(dev);
 147     Object *o;
 148     int i;
 149     qemu_irq irq;
 150     char name[NAME_SIZE];
 151     unsigned int smp_cpus = ms->smp.cpus;
 152
 153     if (smp_cpus > FSL_IMX7_NUM_CPUS) {
 154         error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
 155                    TYPE_FSL_IMX7, FSL_IMX7_NUM_CPUS, smp_cpus);
 156         return;
 157     }
 158
 159     for (i = 0; i < smp_cpus; i++) {
 160         o = OBJECT(&s->cpu[i]);
 161
 162         object_property_set_int(o, QEMU_PSCI_CONDUIT_SMC,
 163                                 "psci-conduit", &error_abort);
 164
 165         /* On uniprocessor, the CBAR is set to 0 */
 166         if (smp_cpus > 1) {
 167             object_property_set_int(o, FSL_IMX7_A7MPCORE_ADDR,
 168                                     "reset-cbar", &error_abort);
 169         }
 170
 171         if (i) {
 172             /* Secondary CPUs start in PSCI powered-down state */
 173             object_property_set_bool(o, true,
 174                                      "start-powered-off", &error_abort);
 175         }
 176
 177         qdev_realize(DEVICE(o), NULL, &error_abort);
 178     }
 179
 180     /*
 181      * A7MPCORE
 182      */
 183     object_property_set_int(OBJECT(&s->a7mpcore), smp_cpus, "num-cpu",
 184                             &error_abort);
 185     object_property_set_int(OBJECT(&s->a7mpcore),
 186                             FSL_IMX7_MAX_IRQ + GIC_INTERNAL,
 187                             "num-irq", &error_abort);
 188
 189     sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
 190     sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX7_A7MPCORE_ADDR);
 191
 192     for (i = 0; i < smp_cpus; i++) {
 193         SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
 194         DeviceState  *d   = DEVICE(qemu_get_cpu(i));
 195
 196         irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
 197         sysbus_connect_irq(sbd, i, irq);
 198         irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
 199         sysbus_connect_irq(sbd, i + smp_cpus, irq);
 200         irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
 201         sysbus_connect_irq(sbd, i + 2 * smp_cpus, irq);
 202         irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
 203         sysbus_connect_irq(sbd, i + 3 * smp_cpus, irq);
 204     }
 205
 206     /*
 207      * A7MPCORE DAP
 208      */
 209     create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR,
 210                                 0x100000);
 211
 212     /*
 213      * GPT1, 2, 3, 4
 214      */
 215     for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
 216         static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = {
 217             FSL_IMX7_GPT1_ADDR,
 218             FSL_IMX7_GPT2_ADDR,
 219             FSL_IMX7_GPT3_ADDR,
 220             FSL_IMX7_GPT4_ADDR,
 221         };
 222
 223         s->gpt[i].ccm = IMX_CCM(&s->ccm);
 224         sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort);
 225         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]);
 226     }
 227
 228     for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
 229         static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = {
 230             FSL_IMX7_GPIO1_ADDR,
 231             FSL_IMX7_GPIO2_ADDR,
 232             FSL_IMX7_GPIO3_ADDR,
 233             FSL_IMX7_GPIO4_ADDR,
 234             FSL_IMX7_GPIO5_ADDR,
 235             FSL_IMX7_GPIO6_ADDR,
 236             FSL_IMX7_GPIO7_ADDR,
 237         };
 238
 239         sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort);
 240         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, FSL_IMX7_GPIOn_ADDR[i]);
 241     }
 242
 243     /*
 244      * IOMUXC and IOMUXC_LPSR
 245      */
 246     for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) {
 247         static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = {
 248             FSL_IMX7_IOMUXC_ADDR,
 249             FSL_IMX7_IOMUXC_LPSR_ADDR,
 250         };
 251
 252         snprintf(name, NAME_SIZE, "iomuxc%d", i);
 253         create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i],
 254                                     FSL_IMX7_IOMUXCn_SIZE);
 255     }
 256
 257     /*
 258      * CCM
 259      */
 260     sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_abort);
 261     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX7_CCM_ADDR);
 262
 263     /*
 264      * Analog
 265      */
 266     sysbus_realize(SYS_BUS_DEVICE(&s->analog), &error_abort);
 267     sysbus_mmio_map(SYS_BUS_DEVICE(&s->analog), 0, FSL_IMX7_ANALOG_ADDR);
 268
 269     /*
 270      * GPCv2
 271      */
 272     sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
 273     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR);
 274
 275     /* Initialize all ECSPI */
 276     for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
 277         static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = {
 278             FSL_IMX7_ECSPI1_ADDR,
 279             FSL_IMX7_ECSPI2_ADDR,
 280             FSL_IMX7_ECSPI3_ADDR,
 281             FSL_IMX7_ECSPI4_ADDR,
 282         };
 283
 284         static const int FSL_IMX7_SPIn_IRQ[FSL_IMX7_NUM_ECSPIS] = {
 285             FSL_IMX7_ECSPI1_IRQ,
 286             FSL_IMX7_ECSPI2_IRQ,
 287             FSL_IMX7_ECSPI3_IRQ,
 288             FSL_IMX7_ECSPI4_IRQ,
 289         };
 290
 291         /* Initialize the SPI */
 292         sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &error_abort);
 293         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
 294                         FSL_IMX7_SPIn_ADDR[i]);
 295         sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
 296                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 297                                             FSL_IMX7_SPIn_IRQ[i]));
 298     }
 299
 300     for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
 301         static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = {
 302             FSL_IMX7_I2C1_ADDR,
 303             FSL_IMX7_I2C2_ADDR,
 304             FSL_IMX7_I2C3_ADDR,
 305             FSL_IMX7_I2C4_ADDR,
 306         };
 307
 308         static const int FSL_IMX7_I2Cn_IRQ[FSL_IMX7_NUM_I2CS] = {
 309             FSL_IMX7_I2C1_IRQ,
 310             FSL_IMX7_I2C2_IRQ,
 311             FSL_IMX7_I2C3_IRQ,
 312             FSL_IMX7_I2C4_IRQ,
 313         };
 314
 315         sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &error_abort);
 316         sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX7_I2Cn_ADDR[i]);
 317
 318         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
 319                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 320                                             FSL_IMX7_I2Cn_IRQ[i]));
 321     }
 322
 323     /*
 324      * UART
 325      */
 326     for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
 327         static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = {
 328             FSL_IMX7_UART1_ADDR,
 329             FSL_IMX7_UART2_ADDR,
 330             FSL_IMX7_UART3_ADDR,
 331             FSL_IMX7_UART4_ADDR,
 332             FSL_IMX7_UART5_ADDR,
 333             FSL_IMX7_UART6_ADDR,
 334             FSL_IMX7_UART7_ADDR,
 335         };
 336
 337         static const int FSL_IMX7_UARTn_IRQ[FSL_IMX7_NUM_UARTS] = {
 338             FSL_IMX7_UART1_IRQ,
 339             FSL_IMX7_UART2_IRQ,
 340             FSL_IMX7_UART3_IRQ,
 341             FSL_IMX7_UART4_IRQ,
 342             FSL_IMX7_UART5_IRQ,
 343             FSL_IMX7_UART6_IRQ,
 344             FSL_IMX7_UART7_IRQ,
 345         };
 346
 347
 348         qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
 349
 350         sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &error_abort);
 351
 352         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, FSL_IMX7_UARTn_ADDR[i]);
 353
 354         irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_UARTn_IRQ[i]);
 355         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, irq);
 356     }
 357
 358     /*
 359      * Ethernet
 360      */
 361     for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
 362         static const hwaddr FSL_IMX7_ENETn_ADDR[FSL_IMX7_NUM_ETHS] = {
 363             FSL_IMX7_ENET1_ADDR,
 364             FSL_IMX7_ENET2_ADDR,
 365         };
 366
 367         object_property_set_uint(OBJECT(&s->eth[i]), FSL_IMX7_ETH_NUM_TX_RINGS,
 368                                  "tx-ring-num", &error_abort);
 369         qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]);
 370         sysbus_realize(SYS_BUS_DEVICE(&s->eth[i]), &error_abort);
 371
 372         sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, FSL_IMX7_ENETn_ADDR[i]);
 373
 374         irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 0));
 375         sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, irq);
 376         irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 3));
 377         sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, irq);
 378     }
 379
 380     /*
 381      * USDHC
 382      */
 383     for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
 384         static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = {
 385             FSL_IMX7_USDHC1_ADDR,
 386             FSL_IMX7_USDHC2_ADDR,
 387             FSL_IMX7_USDHC3_ADDR,
 388         };
 389
 390         static const int FSL_IMX7_USDHCn_IRQ[FSL_IMX7_NUM_USDHCS] = {
 391             FSL_IMX7_USDHC1_IRQ,
 392             FSL_IMX7_USDHC2_IRQ,
 393             FSL_IMX7_USDHC3_IRQ,
 394         };
 395
 396         object_property_set_uint(OBJECT(&s->usdhc[i]), SDHCI_VENDOR_IMX,
 397                                  "vendor", &error_abort);
 398         sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort);
 399
 400         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
 401                         FSL_IMX7_USDHCn_ADDR[i]);
 402
 403         irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USDHCn_IRQ[i]);
 404         sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, irq);
 405     }
 406
 407     /*
 408      * SNVS
 409      */
 410     sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
 411     sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR);
 412
 413     /*
 414      * SRC
 415      */
 416     create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
 417
 418     /*
 419      * Watchdog
 420      */
 421     for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
 422         static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = {
 423             FSL_IMX7_WDOG1_ADDR,
 424             FSL_IMX7_WDOG2_ADDR,
 425             FSL_IMX7_WDOG3_ADDR,
 426             FSL_IMX7_WDOG4_ADDR,
 427         };
 428         static const int FSL_IMX7_WDOGn_IRQ[FSL_IMX7_NUM_WDTS] = {
 429             FSL_IMX7_WDOG1_IRQ,
 430             FSL_IMX7_WDOG2_IRQ,
 431             FSL_IMX7_WDOG3_IRQ,
 432             FSL_IMX7_WDOG4_IRQ,
 433         };
 434
 435         object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support",
 436                                  &error_abort);
 437         sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort);
 438
 439         sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]);
 440         sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
 441                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 442                                             FSL_IMX7_WDOGn_IRQ[i]));
 443     }
 444
 445     /*
 446      * SDMA
 447      */
 448     create_unimplemented_device("sdma", FSL_IMX7_SDMA_ADDR, FSL_IMX7_SDMA_SIZE);
 449
 450     /*
 451      * CAAM
 452      */
 453     create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE);
 454
 455     /*
 456      * PWM
 457      */
 458     create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE);
 459     create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE);
 460     create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE);
 461     create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE);
 462
 463     /*
 464      * CAN
 465      */
 466     create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE);
 467     create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE);
 468
 469     /*
 470      * OCOTP
 471      */
 472     create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
 473                                 FSL_IMX7_OCOTP_SIZE);
 474
 475     sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
 476     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR);
 477
 478     sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
 479     sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
 480
 481     irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTA_IRQ);
 482     sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq);
 483     irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTB_IRQ);
 484     sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq);
 485     irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTC_IRQ);
 486     sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq);
 487     irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ);
 488     sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
 489
 490
 491     for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
 492         static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = {
 493             FSL_IMX7_USBMISC1_ADDR,
 494             FSL_IMX7_USBMISC2_ADDR,
 495             FSL_IMX7_USBMISC3_ADDR,
 496         };
 497
 498         static const hwaddr FSL_IMX7_USBn_ADDR[FSL_IMX7_NUM_USBS] = {
 499             FSL_IMX7_USB1_ADDR,
 500             FSL_IMX7_USB2_ADDR,
 501             FSL_IMX7_USB3_ADDR,
 502         };
 503
 504         static const int FSL_IMX7_USBn_IRQ[FSL_IMX7_NUM_USBS] = {
 505             FSL_IMX7_USB1_IRQ,
 506             FSL_IMX7_USB2_IRQ,
 507             FSL_IMX7_USB3_IRQ,
 508         };
 509
 510         sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
 511         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
 512                         FSL_IMX7_USBn_ADDR[i]);
 513
 514         irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USBn_IRQ[i]);
 515         sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, irq);
 516
 517         snprintf(name, NAME_SIZE, "usbmisc%d", i);
 518         create_unimplemented_device(name, FSL_IMX7_USBMISCn_ADDR[i],
 519                                     FSL_IMX7_USBMISCn_SIZE);
 520     }
 521
 522     /*
 523      * ADCs
 524      */
 525     for (i = 0; i < FSL_IMX7_NUM_ADCS; i++) {
 526         static const hwaddr FSL_IMX7_ADCn_ADDR[FSL_IMX7_NUM_ADCS] = {
 527             FSL_IMX7_ADC1_ADDR,
 528             FSL_IMX7_ADC2_ADDR,
 529         };
 530
 531         snprintf(name, NAME_SIZE, "adc%d", i);
 532         create_unimplemented_device(name, FSL_IMX7_ADCn_ADDR[i],
 533                                     FSL_IMX7_ADCn_SIZE);
 534     }
 535
 536     /*
 537      * LCD
 538      */
 539     create_unimplemented_device("lcdif", FSL_IMX7_LCDIF_ADDR,
 540                                 FSL_IMX7_LCDIF_SIZE);
 541
 542     /*
 543      * DMA APBH
 544      */
 545     create_unimplemented_device("dma-apbh", FSL_IMX7_DMA_APBH_ADDR,
 546                                 FSL_IMX7_DMA_APBH_SIZE);
 547     /*
 548      * PCIe PHY
 549      */
 550     create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
 551                                 FSL_IMX7_PCIE_PHY_SIZE);
 552 }
 553
 554 static void fsl_imx7_class_init(ObjectClass *oc, void *data)
 555 {
 556     DeviceClass *dc = DEVICE_CLASS(oc);
 557
 558     dc->realize = fsl_imx7_realize;
 559
 560     /* Reason: Uses serial_hds and nd_table in realize() directly */
 561     dc->user_creatable = false;
 562     dc->desc = "i.MX7 SOC";
 563 }
 564
 565 static const TypeInfo fsl_imx7_type_info = {
 566     .name = TYPE_FSL_IMX7,
 567     .parent = TYPE_DEVICE,
 568     .instance_size = sizeof(FslIMX7State),
 569     .instance_init = fsl_imx7_init,
 570     .class_init = fsl_imx7_class_init,
 571 };
 572
 573 static void fsl_imx7_register_types(void)
 574 {
 575     type_register_static(&fsl_imx7_type_info);
 576 }
 577 type_init(fsl_imx7_register_types)