hw/intc/ompic.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Authors: Stafford Horne <shorne@gmail.com>
   7  */
   8
   9 #include "qemu/osdep.h"
  10 #include "qemu/module.h"
  11 #include "qapi/error.h"
  12 #include "hw/irq.h"
  13 #include "hw/qdev-properties.h"
  14 #include "hw/sysbus.h"
  15 #include "migration/vmstate.h"
  16 #include "exec/memory.h"
  17 #include "qom/object.h"
  18
  19 #define TYPE_OR1K_OMPIC "or1k-ompic"
  20 OBJECT_DECLARE_SIMPLE_TYPE(OR1KOMPICState, OR1K_OMPIC)
  21
  22 #define OMPIC_CTRL_IRQ_ACK  (1 << 31)
  23 #define OMPIC_CTRL_IRQ_GEN  (1 << 30)
  24 #define OMPIC_CTRL_DST(cpu) (((cpu) >> 16) & 0x3fff)
  25
  26 #define OMPIC_REG(addr)     (((addr) >> 2) & 0x1)
  27 #define OMPIC_SRC_CPU(addr) (((addr) >> 3) & 0x4f)
  28 #define OMPIC_DST_CPU(addr) (((addr) >> 3) & 0x4f)
  29
  30 #define OMPIC_STATUS_IRQ_PENDING (1 << 30)
  31 #define OMPIC_STATUS_SRC(cpu)    (((cpu) & 0x3fff) << 16)
  32 #define OMPIC_STATUS_DATA(data)  ((data) & 0xffff)
  33
  34 #define OMPIC_CONTROL 0
  35 #define OMPIC_STATUS  1
  36
  37 #define OMPIC_MAX_CPUS 4 /* Real max is much higher, but dont waste memory */
  38 #define OMPIC_ADDRSPACE_SZ (OMPIC_MAX_CPUS * 2 * 4) /* 2 32-bit regs per cpu */
  39
  40 typedef struct OR1KOMPICCPUState OR1KOMPICCPUState;
  41
  42 struct OR1KOMPICCPUState {
  43     qemu_irq irq;
  44     uint32_t status;
  45     uint32_t control;
  46 };
  47
  48 struct OR1KOMPICState {
  49     SysBusDevice parent_obj;
  50     MemoryRegion mr;
  51
  52     OR1KOMPICCPUState cpus[OMPIC_MAX_CPUS];
  53
  54     uint32_t num_cpus;
  55 };
  56
  57 static uint64_t ompic_read(void *opaque, hwaddr addr, unsigned size)
  58 {
  59     OR1KOMPICState *s = opaque;
  60     int src_cpu = OMPIC_SRC_CPU(addr);
  61
  62     /* We can only write to control control, write control + update status */
  63     if (OMPIC_REG(addr) == OMPIC_CONTROL) {
  64         return s->cpus[src_cpu].control;
  65     } else {
  66         return s->cpus[src_cpu].status;
  67    }
  68
  69 }
  70
  71 static void ompic_write(void *opaque, hwaddr addr, uint64_t data, unsigned size)
  72 {
  73     OR1KOMPICState *s = opaque;
  74     /* We can only write to control control, write control + update status */
  75     if (OMPIC_REG(addr) == OMPIC_CONTROL) {
  76         int src_cpu = OMPIC_SRC_CPU(addr);
  77
  78         s->cpus[src_cpu].control = data;
  79
  80         if (data & OMPIC_CTRL_IRQ_GEN) {
  81             int dst_cpu = OMPIC_CTRL_DST(data);
  82
  83             s->cpus[dst_cpu].status = OMPIC_STATUS_IRQ_PENDING |
  84                 OMPIC_STATUS_SRC(src_cpu) |
  85                 OMPIC_STATUS_DATA(data);
  86
  87             qemu_irq_raise(s->cpus[dst_cpu].irq);
  88         }
  89         if (data & OMPIC_CTRL_IRQ_ACK) {
  90             s->cpus[src_cpu].status &= ~OMPIC_STATUS_IRQ_PENDING;
  91             qemu_irq_lower(s->cpus[src_cpu].irq);
  92         }
  93     }
  94 }
  95
  96 static const MemoryRegionOps ompic_ops = {
  97     .read = ompic_read,
  98     .write = ompic_write,
  99     .endianness = DEVICE_NATIVE_ENDIAN,
 100     .impl = {
 101         .max_access_size = 8,
 102     },
 103 };
 104
 105 static void or1k_ompic_init(Object *obj)
 106 {
 107     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 108     OR1KOMPICState *s = OR1K_OMPIC(obj);
 109
 110     memory_region_init_io(&s->mr, OBJECT(s), &ompic_ops, s,
 111                           "or1k-ompic", OMPIC_ADDRSPACE_SZ);
 112     sysbus_init_mmio(sbd, &s->mr);
 113 }
 114
 115 static void or1k_ompic_realize(DeviceState *dev, Error **errp)
 116 {
 117     OR1KOMPICState *s = OR1K_OMPIC(dev);
 118     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 119     int i;
 120
 121     if (s->num_cpus > OMPIC_MAX_CPUS) {
 122         error_setg(errp, "Exceeded maximum CPUs %d", s->num_cpus);
 123         return;
 124     }
 125     /* Init IRQ sources for all CPUs */
 126     for (i = 0; i < s->num_cpus; i++) {
 127         sysbus_init_irq(sbd, &s->cpus[i].irq);
 128     }
 129 }
 130
 131 static Property or1k_ompic_properties[] = {
 132     DEFINE_PROP_UINT32("num-cpus", OR1KOMPICState, num_cpus, 1),
 133     DEFINE_PROP_END_OF_LIST(),
 134 };
 135
 136 static const VMStateDescription vmstate_or1k_ompic_cpu = {
 137     .name = "or1k_ompic_cpu",
 138     .version_id = 1,
 139     .minimum_version_id = 1,
 140     .fields = (const VMStateField[]) {
 141          VMSTATE_UINT32(status, OR1KOMPICCPUState),
 142          VMSTATE_UINT32(control, OR1KOMPICCPUState),
 143          VMSTATE_END_OF_LIST()
 144     }
 145 };
 146
 147 static const VMStateDescription vmstate_or1k_ompic = {
 148     .name = TYPE_OR1K_OMPIC,
 149     .version_id = 1,
 150     .minimum_version_id = 1,
 151     .fields = (const VMStateField[]) {
 152          VMSTATE_STRUCT_ARRAY(cpus, OR1KOMPICState, OMPIC_MAX_CPUS, 1,
 153              vmstate_or1k_ompic_cpu, OR1KOMPICCPUState),
 154          VMSTATE_UINT32(num_cpus, OR1KOMPICState),
 155          VMSTATE_END_OF_LIST()
 156     }
 157 };
 158
 159 static void or1k_ompic_class_init(ObjectClass *klass, void *data)
 160 {
 161     DeviceClass *dc = DEVICE_CLASS(klass);
 162
 163     device_class_set_props(dc, or1k_ompic_properties);
 164     dc->realize = or1k_ompic_realize;
 165     dc->vmsd = &vmstate_or1k_ompic;
 166 }
 167
 168 static const TypeInfo or1k_ompic_info = {
 169     .name          = TYPE_OR1K_OMPIC,
 170     .parent        = TYPE_SYS_BUS_DEVICE,
 171     .instance_size = sizeof(OR1KOMPICState),
 172     .instance_init = or1k_ompic_init,
 173     .class_init    = or1k_ompic_class_init,
 174 };
 175
 176 static void or1k_ompic_register_types(void)
 177 {
 178     type_register_static(&or1k_ompic_info);
 179 }
 180
 181 type_init(or1k_ompic_register_types)