1 // Copyright 2013, ARM Limited
2 // All rights reserved.
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are met:
7 // * Redistributions of source code must retain the above copyright notice,
8 // this list of conditions and the following disclaimer.
9 // * Redistributions in binary form must reproduce the above copyright notice,
10 // this list of conditions and the following disclaimer in the documentation
11 // and/or other materials provided with the distribution.
12 // * Neither the name of ARM Limited nor the names of its contributors may be
13 // used to endorse or promote products derived from this software without
14 // specific prior written permission.
16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #ifndef VIXL_A64_ASSEMBLER_A64_H_
28 #define VIXL_A64_ASSEMBLER_A64_H_
35 #include "code-buffer.h"
36 #include "a64/instructions-a64.h"
40 typedef uint64_t RegList
;
41 static const int kRegListSizeInBits
= sizeof(RegList
) * 8;
46 // Some CPURegister methods can return Register and FPRegister types, so we
47 // need to declare them in advance.
55 // The kInvalid value is used to detect uninitialized static instances,
56 // which are always zero-initialized before any constructors are called.
63 CPURegister() : code_(0), size_(0), type_(kNoRegister
) {
64 VIXL_ASSERT(!IsValid());
65 VIXL_ASSERT(IsNone());
68 CPURegister(unsigned code
, unsigned size
, RegisterType type
)
69 : code_(code
), size_(size
), type_(type
) {
70 VIXL_ASSERT(IsValidOrNone());
73 unsigned code() const {
74 VIXL_ASSERT(IsValid());
78 RegisterType
type() const {
79 VIXL_ASSERT(IsValidOrNone());
84 VIXL_ASSERT(code_
< (sizeof(RegList
) * 8));
85 return IsValid() ? (static_cast<RegList
>(1) << code_
) : 0;
88 unsigned size() const {
89 VIXL_ASSERT(IsValid());
93 int SizeInBytes() const {
94 VIXL_ASSERT(IsValid());
95 VIXL_ASSERT(size() % 8 == 0);
99 int SizeInBits() const {
100 VIXL_ASSERT(IsValid());
104 bool Is32Bits() const {
105 VIXL_ASSERT(IsValid());
109 bool Is64Bits() const {
110 VIXL_ASSERT(IsValid());
114 bool IsValid() const {
115 if (IsValidRegister() || IsValidFPRegister()) {
116 VIXL_ASSERT(!IsNone());
119 VIXL_ASSERT(IsNone());
124 bool IsValidRegister() const {
125 return IsRegister() &&
126 ((size_
== kWRegSize
) || (size_
== kXRegSize
)) &&
127 ((code_
< kNumberOfRegisters
) || (code_
== kSPRegInternalCode
));
130 bool IsValidFPRegister() const {
131 return IsFPRegister() &&
132 ((size_
== kSRegSize
) || (size_
== kDRegSize
)) &&
133 (code_
< kNumberOfFPRegisters
);
136 bool IsNone() const {
137 // kNoRegister types should always have size 0 and code 0.
138 VIXL_ASSERT((type_
!= kNoRegister
) || (code_
== 0));
139 VIXL_ASSERT((type_
!= kNoRegister
) || (size_
== 0));
141 return type_
== kNoRegister
;
144 bool Aliases(const CPURegister
& other
) const {
145 VIXL_ASSERT(IsValidOrNone() && other
.IsValidOrNone());
146 return (code_
== other
.code_
) && (type_
== other
.type_
);
149 bool Is(const CPURegister
& other
) const {
150 VIXL_ASSERT(IsValidOrNone() && other
.IsValidOrNone());
151 return Aliases(other
) && (size_
== other
.size_
);
154 bool IsZero() const {
155 VIXL_ASSERT(IsValid());
156 return IsRegister() && (code_
== kZeroRegCode
);
160 VIXL_ASSERT(IsValid());
161 return IsRegister() && (code_
== kSPRegInternalCode
);
164 bool IsRegister() const {
165 return type_
== kRegister
;
168 bool IsFPRegister() const {
169 return type_
== kFPRegister
;
172 bool IsW() const { return IsValidRegister() && Is32Bits(); }
173 bool IsX() const { return IsValidRegister() && Is64Bits(); }
174 bool IsS() const { return IsValidFPRegister() && Is32Bits(); }
175 bool IsD() const { return IsValidFPRegister() && Is64Bits(); }
177 const Register
& W() const;
178 const Register
& X() const;
179 const FPRegister
& S() const;
180 const FPRegister
& D() const;
182 bool IsSameSizeAndType(const CPURegister
& other
) const {
183 return (size_
== other
.size_
) && (type_
== other
.type_
);
192 bool IsValidOrNone() const {
193 return IsValid() || IsNone();
198 class Register
: public CPURegister
{
200 Register() : CPURegister() {}
201 explicit Register(const CPURegister
& other
)
202 : CPURegister(other
.code(), other
.size(), other
.type()) {
203 VIXL_ASSERT(IsValidRegister());
205 Register(unsigned code
, unsigned size
)
206 : CPURegister(code
, size
, kRegister
) {}
208 bool IsValid() const {
209 VIXL_ASSERT(IsRegister() || IsNone());
210 return IsValidRegister();
213 static const Register
& WRegFromCode(unsigned code
);
214 static const Register
& XRegFromCode(unsigned code
);
217 static const Register wregisters
[];
218 static const Register xregisters
[];
222 class FPRegister
: public CPURegister
{
224 FPRegister() : CPURegister() {}
225 explicit FPRegister(const CPURegister
& other
)
226 : CPURegister(other
.code(), other
.size(), other
.type()) {
227 VIXL_ASSERT(IsValidFPRegister());
229 FPRegister(unsigned code
, unsigned size
)
230 : CPURegister(code
, size
, kFPRegister
) {}
232 bool IsValid() const {
233 VIXL_ASSERT(IsFPRegister() || IsNone());
234 return IsValidFPRegister();
237 static const FPRegister
& SRegFromCode(unsigned code
);
238 static const FPRegister
& DRegFromCode(unsigned code
);
241 static const FPRegister sregisters
[];
242 static const FPRegister dregisters
[];
246 // No*Reg is used to indicate an unused argument, or an error case. Note that
247 // these all compare equal (using the Is() method). The Register and FPRegister
248 // variants are provided for convenience.
249 const Register NoReg
;
250 const FPRegister NoFPReg
;
251 const CPURegister NoCPUReg
;
254 #define DEFINE_REGISTERS(N) \
255 const Register w##N(N, kWRegSize); \
256 const Register x##N(N, kXRegSize);
257 REGISTER_CODE_LIST(DEFINE_REGISTERS
)
258 #undef DEFINE_REGISTERS
259 const Register
wsp(kSPRegInternalCode
, kWRegSize
);
260 const Register
sp(kSPRegInternalCode
, kXRegSize
);
263 #define DEFINE_FPREGISTERS(N) \
264 const FPRegister s##N(N, kSRegSize); \
265 const FPRegister d##N(N, kDRegSize);
266 REGISTER_CODE_LIST(DEFINE_FPREGISTERS
)
267 #undef DEFINE_FPREGISTERS
270 // Registers aliases.
271 const Register ip0
= x16
;
272 const Register ip1
= x17
;
273 const Register lr
= x30
;
274 const Register xzr
= x31
;
275 const Register wzr
= w31
;
278 // AreAliased returns true if any of the named registers overlap. Arguments
279 // set to NoReg are ignored. The system stack pointer may be specified.
280 bool AreAliased(const CPURegister
& reg1
,
281 const CPURegister
& reg2
,
282 const CPURegister
& reg3
= NoReg
,
283 const CPURegister
& reg4
= NoReg
,
284 const CPURegister
& reg5
= NoReg
,
285 const CPURegister
& reg6
= NoReg
,
286 const CPURegister
& reg7
= NoReg
,
287 const CPURegister
& reg8
= NoReg
);
290 // AreSameSizeAndType returns true if all of the specified registers have the
291 // same size, and are of the same type. The system stack pointer may be
292 // specified. Arguments set to NoReg are ignored, as are any subsequent
293 // arguments. At least one argument (reg1) must be valid (not NoCPUReg).
294 bool AreSameSizeAndType(const CPURegister
& reg1
,
295 const CPURegister
& reg2
,
296 const CPURegister
& reg3
= NoCPUReg
,
297 const CPURegister
& reg4
= NoCPUReg
,
298 const CPURegister
& reg5
= NoCPUReg
,
299 const CPURegister
& reg6
= NoCPUReg
,
300 const CPURegister
& reg7
= NoCPUReg
,
301 const CPURegister
& reg8
= NoCPUReg
);
304 // Lists of registers.
307 explicit CPURegList(CPURegister reg1
,
308 CPURegister reg2
= NoCPUReg
,
309 CPURegister reg3
= NoCPUReg
,
310 CPURegister reg4
= NoCPUReg
)
311 : list_(reg1
.Bit() | reg2
.Bit() | reg3
.Bit() | reg4
.Bit()),
312 size_(reg1
.size()), type_(reg1
.type()) {
313 VIXL_ASSERT(AreSameSizeAndType(reg1
, reg2
, reg3
, reg4
));
314 VIXL_ASSERT(IsValid());
317 CPURegList(CPURegister::RegisterType type
, unsigned size
, RegList list
)
318 : list_(list
), size_(size
), type_(type
) {
319 VIXL_ASSERT(IsValid());
322 CPURegList(CPURegister::RegisterType type
, unsigned size
,
323 unsigned first_reg
, unsigned last_reg
)
324 : size_(size
), type_(type
) {
325 VIXL_ASSERT(((type
== CPURegister::kRegister
) &&
326 (last_reg
< kNumberOfRegisters
)) ||
327 ((type
== CPURegister::kFPRegister
) &&
328 (last_reg
< kNumberOfFPRegisters
)));
329 VIXL_ASSERT(last_reg
>= first_reg
);
330 list_
= (UINT64_C(1) << (last_reg
+ 1)) - 1;
331 list_
&= ~((UINT64_C(1) << first_reg
) - 1);
332 VIXL_ASSERT(IsValid());
335 CPURegister::RegisterType
type() const {
336 VIXL_ASSERT(IsValid());
340 // Combine another CPURegList into this one. Registers that already exist in
341 // this list are left unchanged. The type and size of the registers in the
342 // 'other' list must match those in this list.
343 void Combine(const CPURegList
& other
) {
344 VIXL_ASSERT(IsValid());
345 VIXL_ASSERT(other
.type() == type_
);
346 VIXL_ASSERT(other
.RegisterSizeInBits() == size_
);
347 list_
|= other
.list();
350 // Remove every register in the other CPURegList from this one. Registers that
351 // do not exist in this list are ignored. The type and size of the registers
352 // in the 'other' list must match those in this list.
353 void Remove(const CPURegList
& other
) {
354 VIXL_ASSERT(IsValid());
355 VIXL_ASSERT(other
.type() == type_
);
356 VIXL_ASSERT(other
.RegisterSizeInBits() == size_
);
357 list_
&= ~other
.list();
360 // Variants of Combine and Remove which take a single register.
361 void Combine(const CPURegister
& other
) {
362 VIXL_ASSERT(other
.type() == type_
);
363 VIXL_ASSERT(other
.size() == size_
);
364 Combine(other
.code());
367 void Remove(const CPURegister
& other
) {
368 VIXL_ASSERT(other
.type() == type_
);
369 VIXL_ASSERT(other
.size() == size_
);
370 Remove(other
.code());
373 // Variants of Combine and Remove which take a single register by its code;
374 // the type and size of the register is inferred from this list.
375 void Combine(int code
) {
376 VIXL_ASSERT(IsValid());
377 VIXL_ASSERT(CPURegister(code
, size_
, type_
).IsValid());
378 list_
|= (UINT64_C(1) << code
);
381 void Remove(int code
) {
382 VIXL_ASSERT(IsValid());
383 VIXL_ASSERT(CPURegister(code
, size_
, type_
).IsValid());
384 list_
&= ~(UINT64_C(1) << code
);
387 static CPURegList
Union(const CPURegList
& list_1
, const CPURegList
& list_2
) {
388 VIXL_ASSERT(list_1
.type_
== list_2
.type_
);
389 VIXL_ASSERT(list_1
.size_
== list_2
.size_
);
390 return CPURegList(list_1
.type_
, list_1
.size_
, list_1
.list_
| list_2
.list_
);
392 static CPURegList
Union(const CPURegList
& list_1
,
393 const CPURegList
& list_2
,
394 const CPURegList
& list_3
);
395 static CPURegList
Union(const CPURegList
& list_1
,
396 const CPURegList
& list_2
,
397 const CPURegList
& list_3
,
398 const CPURegList
& list_4
);
400 static CPURegList
Intersection(const CPURegList
& list_1
,
401 const CPURegList
& list_2
) {
402 VIXL_ASSERT(list_1
.type_
== list_2
.type_
);
403 VIXL_ASSERT(list_1
.size_
== list_2
.size_
);
404 return CPURegList(list_1
.type_
, list_1
.size_
, list_1
.list_
& list_2
.list_
);
406 static CPURegList
Intersection(const CPURegList
& list_1
,
407 const CPURegList
& list_2
,
408 const CPURegList
& list_3
);
409 static CPURegList
Intersection(const CPURegList
& list_1
,
410 const CPURegList
& list_2
,
411 const CPURegList
& list_3
,
412 const CPURegList
& list_4
);
414 RegList
list() const {
415 VIXL_ASSERT(IsValid());
419 void set_list(RegList new_list
) {
420 VIXL_ASSERT(IsValid());
424 // Remove all callee-saved registers from the list. This can be useful when
425 // preparing registers for an AAPCS64 function call, for example.
426 void RemoveCalleeSaved();
428 CPURegister
PopLowestIndex();
429 CPURegister
PopHighestIndex();
431 // AAPCS64 callee-saved registers.
432 static CPURegList
GetCalleeSaved(unsigned size
= kXRegSize
);
433 static CPURegList
GetCalleeSavedFP(unsigned size
= kDRegSize
);
435 // AAPCS64 caller-saved registers. Note that this includes lr.
436 static CPURegList
GetCallerSaved(unsigned size
= kXRegSize
);
437 static CPURegList
GetCallerSavedFP(unsigned size
= kDRegSize
);
439 bool IsEmpty() const {
440 VIXL_ASSERT(IsValid());
444 bool IncludesAliasOf(const CPURegister
& other
) const {
445 VIXL_ASSERT(IsValid());
446 return (type_
== other
.type()) && ((other
.Bit() & list_
) != 0);
449 bool IncludesAliasOf(int code
) const {
450 VIXL_ASSERT(IsValid());
451 return ((code
& list_
) != 0);
455 VIXL_ASSERT(IsValid());
456 return CountSetBits(list_
, kRegListSizeInBits
);
459 unsigned RegisterSizeInBits() const {
460 VIXL_ASSERT(IsValid());
464 unsigned RegisterSizeInBytes() const {
465 int size_in_bits
= RegisterSizeInBits();
466 VIXL_ASSERT((size_in_bits
% 8) == 0);
467 return size_in_bits
/ 8;
470 unsigned TotalSizeInBytes() const {
471 VIXL_ASSERT(IsValid());
472 return RegisterSizeInBytes() * Count();
478 CPURegister::RegisterType type_
;
480 bool IsValid() const;
484 // AAPCS64 callee-saved registers.
485 extern const CPURegList kCalleeSaved
;
486 extern const CPURegList kCalleeSavedFP
;
489 // AAPCS64 caller-saved registers. Note that this includes lr.
490 extern const CPURegList kCallerSaved
;
491 extern const CPURegList kCallerSavedFP
;
498 // where <immediate> is int64_t.
499 // This is allowed to be an implicit constructor because Operand is
500 // a wrapper class that doesn't normally perform any type conversion.
501 Operand(int64_t immediate
); // NOLINT(runtime/explicit)
503 // rm, {<shift> #<shift_amount>}
504 // where <shift> is one of {LSL, LSR, ASR, ROR}.
505 // <shift_amount> is uint6_t.
506 // This is allowed to be an implicit constructor because Operand is
507 // a wrapper class that doesn't normally perform any type conversion.
508 Operand(Register reg
,
510 unsigned shift_amount
= 0); // NOLINT(runtime/explicit)
512 // rm, {<extend> {#<shift_amount>}}
513 // where <extend> is one of {UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW, SXTX}.
514 // <shift_amount> is uint2_t.
515 explicit Operand(Register reg
, Extend extend
, unsigned shift_amount
= 0);
517 bool IsImmediate() const;
518 bool IsShiftedRegister() const;
519 bool IsExtendedRegister() const;
522 // This returns an LSL shift (<= 4) operand as an equivalent extend operand,
523 // which helps in the encoding of instructions that use the stack pointer.
524 Operand
ToExtendedRegister() const;
526 int64_t immediate() const {
527 VIXL_ASSERT(IsImmediate());
531 Register
reg() const {
532 VIXL_ASSERT(IsShiftedRegister() || IsExtendedRegister());
536 Shift
shift() const {
537 VIXL_ASSERT(IsShiftedRegister());
541 Extend
extend() const {
542 VIXL_ASSERT(IsExtendedRegister());
546 unsigned shift_amount() const {
547 VIXL_ASSERT(IsShiftedRegister() || IsExtendedRegister());
548 return shift_amount_
;
556 unsigned shift_amount_
;
560 // MemOperand represents the addressing mode of a load or store instruction.
563 explicit MemOperand(Register base
,
565 AddrMode addrmode
= Offset
);
566 explicit MemOperand(Register base
,
569 unsigned shift_amount
= 0);
570 explicit MemOperand(Register base
,
573 unsigned shift_amount
= 0);
574 explicit MemOperand(Register base
,
575 const Operand
& offset
,
576 AddrMode addrmode
= Offset
);
578 const Register
& base() const { return base_
; }
579 const Register
& regoffset() const { return regoffset_
; }
580 int64_t offset() const { return offset_
; }
581 AddrMode
addrmode() const { return addrmode_
; }
582 Shift
shift() const { return shift_
; }
583 Extend
extend() const { return extend_
; }
584 unsigned shift_amount() const { return shift_amount_
; }
585 bool IsImmediateOffset() const;
586 bool IsRegisterOffset() const;
587 bool IsPreIndex() const;
588 bool IsPostIndex() const;
597 unsigned shift_amount_
;
603 Label() : location_(kLocationUnbound
) {}
605 // If the label has been linked to, it needs to be bound to a target.
606 VIXL_ASSERT(!IsLinked() || IsBound());
609 bool IsBound() const { return location_
>= 0; }
610 bool IsLinked() const { return !links_
.empty(); }
612 ptrdiff_t location() const { return location_
; }
615 // The list of linked instructions is stored in a stack-like structure. We
616 // don't use std::stack directly because it's slow for the common case where
617 // only one or two instructions refer to a label, and labels themselves are
618 // short-lived. This class behaves like std::stack, but the first few links
619 // are preallocated (configured by kPreallocatedLinks).
621 // If more than N links are required, this falls back to std::stack.
624 LinksStack() : size_(0), links_extended_(NULL
) {}
626 delete links_extended_
;
629 size_t size() const {
637 void push(ptrdiff_t value
) {
638 if (size_
< kPreallocatedLinks
) {
639 links_
[size_
] = value
;
641 if (links_extended_
== NULL
) {
642 links_extended_
= new std::stack
<ptrdiff_t>();
644 VIXL_ASSERT(size_
== (links_extended_
->size() + kPreallocatedLinks
));
645 links_extended_
->push(value
);
650 ptrdiff_t top() const {
651 return (size_
<= kPreallocatedLinks
) ? links_
[size_
- 1]
652 : links_extended_
->top();
657 if (size_
>= kPreallocatedLinks
) {
658 links_extended_
->pop();
659 VIXL_ASSERT(size_
== (links_extended_
->size() + kPreallocatedLinks
));
664 static const size_t kPreallocatedLinks
= 4;
667 ptrdiff_t links_
[kPreallocatedLinks
];
668 std::stack
<ptrdiff_t> * links_extended_
;
671 void Bind(ptrdiff_t location
) {
672 // Labels can only be bound once.
673 VIXL_ASSERT(!IsBound());
674 location_
= location
;
677 void AddLink(ptrdiff_t instruction
) {
678 // If a label is bound, the assembler already has the information it needs
679 // to write the instruction, so there is no need to add it to links_.
680 VIXL_ASSERT(!IsBound());
681 links_
.push(instruction
);
684 ptrdiff_t GetAndRemoveNextLink() {
685 VIXL_ASSERT(IsLinked());
686 ptrdiff_t link
= links_
.top();
691 // The offsets of the instructions that have linked to this label.
693 // The label location.
696 static const ptrdiff_t kLocationUnbound
= -1;
698 // It is not safe to copy labels, so disable the copy constructor by declaring
699 // it private (without an implementation).
702 // The Assembler class is responsible for binding and linking labels, since
703 // the stored offsets need to be consistent with the Assembler's buffer.
704 friend class Assembler
;
708 // A literal is a 32-bit or 64-bit piece of data stored in the instruction
709 // stream and loaded through a pc relative load. The same literal can be
710 // referred to by multiple instructions but a literal can only reside at one
711 // place in memory. A literal can be used by a load before or after being
714 // Internally an offset of 0 is associated with a literal which has been
715 // neither used nor placed. Then two possibilities arise:
716 // 1) the label is placed, the offset (stored as offset + 1) is used to
717 // resolve any subsequent load using the label.
718 // 2) the label is not placed and offset is the offset of the last load using
719 // the literal (stored as -offset -1). If multiple loads refer to this
720 // literal then the last load holds the offset of the preceding load and
721 // all loads form a chain. Once the offset is placed all the loads in the
722 // chain are resolved and future loads fall back to possibility 1.
725 RawLiteral() : size_(0), offset_(0), raw_value_(0) {}
728 VIXL_STATIC_ASSERT(kDRegSizeInBytes
== kXRegSizeInBytes
);
729 VIXL_STATIC_ASSERT(kSRegSizeInBytes
== kWRegSizeInBytes
);
730 VIXL_ASSERT((size_
== kXRegSizeInBytes
) || (size_
== kWRegSizeInBytes
));
733 uint64_t raw_value64() {
734 VIXL_ASSERT(size_
== kXRegSizeInBytes
);
737 uint32_t raw_value32() {
738 VIXL_ASSERT(size_
== kWRegSizeInBytes
);
739 VIXL_ASSERT(is_uint32(raw_value_
) || is_int32(raw_value_
));
740 return static_cast<uint32_t>(raw_value_
);
742 bool IsUsed() { return offset_
< 0; }
743 bool IsPlaced() { return offset_
> 0; }
747 VIXL_ASSERT(IsPlaced());
750 void set_offset(ptrdiff_t offset
) {
751 VIXL_ASSERT(offset
>= 0);
752 VIXL_ASSERT(IsWordAligned(offset
));
753 VIXL_ASSERT(!IsPlaced());
754 offset_
= offset
+ 1;
756 ptrdiff_t last_use() {
757 VIXL_ASSERT(IsUsed());
760 void set_last_use(ptrdiff_t offset
) {
761 VIXL_ASSERT(offset
>= 0);
762 VIXL_ASSERT(IsWordAligned(offset
));
763 VIXL_ASSERT(!IsPlaced());
764 offset_
= -offset
- 1;
771 friend class Assembler
;
775 template <typename T
>
776 class Literal
: public RawLiteral
{
778 explicit Literal(T value
) {
779 size_
= sizeof(value
);
780 memcpy(&raw_value_
, &value
, sizeof(value
));
785 // Control whether or not position-independent code should be emitted.
786 enum PositionIndependentCodeOption
{
787 // All code generated will be position-independent; all branches and
788 // references to labels generated with the Label class will use PC-relative
790 PositionIndependentCode
,
792 // Allow VIXL to generate code that refers to absolute addresses. With this
793 // option, it will not be possible to copy the code buffer and run it from a
794 // different address; code must be generated in its final location.
795 PositionDependentCode
,
797 // Allow VIXL to assume that the bottom 12 bits of the address will be
798 // constant, but that the top 48 bits may change. This allows `adrp` to
799 // function in systems which copy code between pages, but otherwise maintain
800 // 4KB page alignment.
801 PageOffsetDependentCode
805 // Control how scaled- and unscaled-offset loads and stores are generated.
806 enum LoadStoreScalingOption
{
807 // Prefer scaled-immediate-offset instructions, but emit unscaled-offset,
808 // register-offset, pre-index or post-index instructions if necessary.
811 // Prefer unscaled-immediate-offset instructions, but emit scaled-offset,
812 // register-offset, pre-index or post-index instructions if necessary.
813 PreferUnscaledOffset
,
815 // Require scaled-immediate-offset instructions.
818 // Require unscaled-immediate-offset instructions.
819 RequireUnscaledOffset
826 Assembler(size_t capacity
,
827 PositionIndependentCodeOption pic
= PositionIndependentCode
);
828 Assembler(byte
* buffer
, size_t capacity
,
829 PositionIndependentCodeOption pic
= PositionIndependentCode
);
831 // The destructor asserts that one of the following is true:
832 // * The Assembler object has not been used.
833 // * Nothing has been emitted since the last Reset() call.
834 // * Nothing has been emitted since the last FinalizeCode() call.
839 // Start generating code from the beginning of the buffer, discarding any code
840 // and data that has already been emitted into the buffer.
843 // Finalize a code buffer of generated instructions. This function must be
844 // called before executing or copying code from the buffer.
848 // Bind a label to the current PC.
849 void bind(Label
* label
);
851 // Bind a label to a specified offset from the start of the buffer.
852 void BindToOffset(Label
* label
, ptrdiff_t offset
);
854 // Place a literal at the current PC.
855 void place(RawLiteral
* literal
);
857 ptrdiff_t CursorOffset() const {
858 return buffer_
->CursorOffset();
861 ptrdiff_t BufferEndOffset() const {
862 return static_cast<ptrdiff_t>(buffer_
->capacity());
865 // Return the address of an offset in the buffer.
866 template <typename T
>
867 T
GetOffsetAddress(ptrdiff_t offset
) {
868 VIXL_STATIC_ASSERT(sizeof(T
) >= sizeof(uintptr_t));
869 return buffer_
->GetOffsetAddress
<T
>(offset
);
872 // Return the address of a bound label.
873 template <typename T
>
874 T
GetLabelAddress(const Label
* label
) {
875 VIXL_ASSERT(label
->IsBound());
876 VIXL_STATIC_ASSERT(sizeof(T
) >= sizeof(uintptr_t));
877 return GetOffsetAddress
<T
>(label
->location());
880 // Return the address of the cursor.
881 template <typename T
>
882 T
GetCursorAddress() {
883 VIXL_STATIC_ASSERT(sizeof(T
) >= sizeof(uintptr_t));
884 return GetOffsetAddress
<T
>(CursorOffset());
887 // Return the address of the start of the buffer.
888 template <typename T
>
889 T
GetStartAddress() {
890 VIXL_STATIC_ASSERT(sizeof(T
) >= sizeof(uintptr_t));
891 return GetOffsetAddress
<T
>(0);
894 // Instruction set functions.
896 // Branch / Jump instructions.
897 // Branch to register.
898 void br(const Register
& xn
);
900 // Branch with link to register.
901 void blr(const Register
& xn
);
903 // Branch to register with return hint.
904 void ret(const Register
& xn
= lr
);
906 // Unconditional branch to label.
907 void b(Label
* label
);
909 // Conditional branch to label.
910 void b(Label
* label
, Condition cond
);
912 // Unconditional branch to PC offset.
915 // Conditional branch to PC offset.
916 void b(int imm19
, Condition cond
);
918 // Branch with link to label.
919 void bl(Label
* label
);
921 // Branch with link to PC offset.
924 // Compare and branch to label if zero.
925 void cbz(const Register
& rt
, Label
* label
);
927 // Compare and branch to PC offset if zero.
928 void cbz(const Register
& rt
, int imm19
);
930 // Compare and branch to label if not zero.
931 void cbnz(const Register
& rt
, Label
* label
);
933 // Compare and branch to PC offset if not zero.
934 void cbnz(const Register
& rt
, int imm19
);
936 // Test bit and branch to label if zero.
937 void tbz(const Register
& rt
, unsigned bit_pos
, Label
* label
);
939 // Test bit and branch to PC offset if zero.
940 void tbz(const Register
& rt
, unsigned bit_pos
, int imm14
);
942 // Test bit and branch to label if not zero.
943 void tbnz(const Register
& rt
, unsigned bit_pos
, Label
* label
);
945 // Test bit and branch to PC offset if not zero.
946 void tbnz(const Register
& rt
, unsigned bit_pos
, int imm14
);
948 // Address calculation instructions.
949 // Calculate a PC-relative address. Unlike for branches the offset in adr is
950 // unscaled (i.e. the result can be unaligned).
952 // Calculate the address of a label.
953 void adr(const Register
& rd
, Label
* label
);
955 // Calculate the address of a PC offset.
956 void adr(const Register
& rd
, int imm21
);
958 // Calculate the page address of a label.
959 void adrp(const Register
& rd
, Label
* label
);
961 // Calculate the page address of a PC offset.
962 void adrp(const Register
& rd
, int imm21
);
964 // Data Processing instructions.
966 void add(const Register
& rd
,
968 const Operand
& operand
);
970 // Add and update status flags.
971 void adds(const Register
& rd
,
973 const Operand
& operand
);
976 void cmn(const Register
& rn
, const Operand
& operand
);
979 void sub(const Register
& rd
,
981 const Operand
& operand
);
983 // Subtract and update status flags.
984 void subs(const Register
& rd
,
986 const Operand
& operand
);
989 void cmp(const Register
& rn
, const Operand
& operand
);
992 void neg(const Register
& rd
,
993 const Operand
& operand
);
995 // Negate and update status flags.
996 void negs(const Register
& rd
,
997 const Operand
& operand
);
999 // Add with carry bit.
1000 void adc(const Register
& rd
,
1002 const Operand
& operand
);
1004 // Add with carry bit and update status flags.
1005 void adcs(const Register
& rd
,
1007 const Operand
& operand
);
1009 // Subtract with carry bit.
1010 void sbc(const Register
& rd
,
1012 const Operand
& operand
);
1014 // Subtract with carry bit and update status flags.
1015 void sbcs(const Register
& rd
,
1017 const Operand
& operand
);
1019 // Negate with carry bit.
1020 void ngc(const Register
& rd
,
1021 const Operand
& operand
);
1023 // Negate with carry bit and update status flags.
1024 void ngcs(const Register
& rd
,
1025 const Operand
& operand
);
1027 // Logical instructions.
1028 // Bitwise and (A & B).
1029 void and_(const Register
& rd
,
1031 const Operand
& operand
);
1033 // Bitwise and (A & B) and update status flags.
1034 void ands(const Register
& rd
,
1036 const Operand
& operand
);
1038 // Bit test and set flags.
1039 void tst(const Register
& rn
, const Operand
& operand
);
1041 // Bit clear (A & ~B).
1042 void bic(const Register
& rd
,
1044 const Operand
& operand
);
1046 // Bit clear (A & ~B) and update status flags.
1047 void bics(const Register
& rd
,
1049 const Operand
& operand
);
1051 // Bitwise or (A | B).
1052 void orr(const Register
& rd
, const Register
& rn
, const Operand
& operand
);
1054 // Bitwise nor (A | ~B).
1055 void orn(const Register
& rd
, const Register
& rn
, const Operand
& operand
);
1057 // Bitwise eor/xor (A ^ B).
1058 void eor(const Register
& rd
, const Register
& rn
, const Operand
& operand
);
1060 // Bitwise enor/xnor (A ^ ~B).
1061 void eon(const Register
& rd
, const Register
& rn
, const Operand
& operand
);
1063 // Logical shift left by variable.
1064 void lslv(const Register
& rd
, const Register
& rn
, const Register
& rm
);
1066 // Logical shift right by variable.
1067 void lsrv(const Register
& rd
, const Register
& rn
, const Register
& rm
);
1069 // Arithmetic shift right by variable.
1070 void asrv(const Register
& rd
, const Register
& rn
, const Register
& rm
);
1072 // Rotate right by variable.
1073 void rorv(const Register
& rd
, const Register
& rn
, const Register
& rm
);
1075 // Bitfield instructions.
1077 void bfm(const Register
& rd
,
1082 // Signed bitfield move.
1083 void sbfm(const Register
& rd
,
1088 // Unsigned bitfield move.
1089 void ubfm(const Register
& rd
,
1096 void bfi(const Register
& rd
,
1100 VIXL_ASSERT(width
>= 1);
1101 VIXL_ASSERT(lsb
+ width
<= rn
.size());
1102 bfm(rd
, rn
, (rd
.size() - lsb
) & (rd
.size() - 1), width
- 1);
1105 // Bitfield extract and insert low.
1106 void bfxil(const Register
& rd
,
1110 VIXL_ASSERT(width
>= 1);
1111 VIXL_ASSERT(lsb
+ width
<= rn
.size());
1112 bfm(rd
, rn
, lsb
, lsb
+ width
- 1);
1116 // Arithmetic shift right.
1117 void asr(const Register
& rd
, const Register
& rn
, unsigned shift
) {
1118 VIXL_ASSERT(shift
< rd
.size());
1119 sbfm(rd
, rn
, shift
, rd
.size() - 1);
1122 // Signed bitfield insert with zero at right.
1123 void sbfiz(const Register
& rd
,
1127 VIXL_ASSERT(width
>= 1);
1128 VIXL_ASSERT(lsb
+ width
<= rn
.size());
1129 sbfm(rd
, rn
, (rd
.size() - lsb
) & (rd
.size() - 1), width
- 1);
1132 // Signed bitfield extract.
1133 void sbfx(const Register
& rd
,
1137 VIXL_ASSERT(width
>= 1);
1138 VIXL_ASSERT(lsb
+ width
<= rn
.size());
1139 sbfm(rd
, rn
, lsb
, lsb
+ width
- 1);
1142 // Signed extend byte.
1143 void sxtb(const Register
& rd
, const Register
& rn
) {
1147 // Signed extend halfword.
1148 void sxth(const Register
& rd
, const Register
& rn
) {
1149 sbfm(rd
, rn
, 0, 15);
1152 // Signed extend word.
1153 void sxtw(const Register
& rd
, const Register
& rn
) {
1154 sbfm(rd
, rn
, 0, 31);
1158 // Logical shift left.
1159 void lsl(const Register
& rd
, const Register
& rn
, unsigned shift
) {
1160 unsigned reg_size
= rd
.size();
1161 VIXL_ASSERT(shift
< reg_size
);
1162 ubfm(rd
, rn
, (reg_size
- shift
) % reg_size
, reg_size
- shift
- 1);
1165 // Logical shift right.
1166 void lsr(const Register
& rd
, const Register
& rn
, unsigned shift
) {
1167 VIXL_ASSERT(shift
< rd
.size());
1168 ubfm(rd
, rn
, shift
, rd
.size() - 1);
1171 // Unsigned bitfield insert with zero at right.
1172 void ubfiz(const Register
& rd
,
1176 VIXL_ASSERT(width
>= 1);
1177 VIXL_ASSERT(lsb
+ width
<= rn
.size());
1178 ubfm(rd
, rn
, (rd
.size() - lsb
) & (rd
.size() - 1), width
- 1);
1181 // Unsigned bitfield extract.
1182 void ubfx(const Register
& rd
,
1186 VIXL_ASSERT(width
>= 1);
1187 VIXL_ASSERT(lsb
+ width
<= rn
.size());
1188 ubfm(rd
, rn
, lsb
, lsb
+ width
- 1);
1191 // Unsigned extend byte.
1192 void uxtb(const Register
& rd
, const Register
& rn
) {
1196 // Unsigned extend halfword.
1197 void uxth(const Register
& rd
, const Register
& rn
) {
1198 ubfm(rd
, rn
, 0, 15);
1201 // Unsigned extend word.
1202 void uxtw(const Register
& rd
, const Register
& rn
) {
1203 ubfm(rd
, rn
, 0, 31);
1207 void extr(const Register
& rd
,
1212 // Conditional select: rd = cond ? rn : rm.
1213 void csel(const Register
& rd
,
1218 // Conditional select increment: rd = cond ? rn : rm + 1.
1219 void csinc(const Register
& rd
,
1224 // Conditional select inversion: rd = cond ? rn : ~rm.
1225 void csinv(const Register
& rd
,
1230 // Conditional select negation: rd = cond ? rn : -rm.
1231 void csneg(const Register
& rd
,
1236 // Conditional set: rd = cond ? 1 : 0.
1237 void cset(const Register
& rd
, Condition cond
);
1239 // Conditional set mask: rd = cond ? -1 : 0.
1240 void csetm(const Register
& rd
, Condition cond
);
1242 // Conditional increment: rd = cond ? rn + 1 : rn.
1243 void cinc(const Register
& rd
, const Register
& rn
, Condition cond
);
1245 // Conditional invert: rd = cond ? ~rn : rn.
1246 void cinv(const Register
& rd
, const Register
& rn
, Condition cond
);
1248 // Conditional negate: rd = cond ? -rn : rn.
1249 void cneg(const Register
& rd
, const Register
& rn
, Condition cond
);
1252 void ror(const Register
& rd
, const Register
& rs
, unsigned shift
) {
1253 extr(rd
, rs
, rs
, shift
);
1256 // Conditional comparison.
1257 // Conditional compare negative.
1258 void ccmn(const Register
& rn
,
1259 const Operand
& operand
,
1263 // Conditional compare.
1264 void ccmp(const Register
& rn
,
1265 const Operand
& operand
,
1270 void mul(const Register
& rd
, const Register
& rn
, const Register
& rm
);
1272 // Negated multiply.
1273 void mneg(const Register
& rd
, const Register
& rn
, const Register
& rm
);
1275 // Signed long multiply: 32 x 32 -> 64-bit.
1276 void smull(const Register
& rd
, const Register
& rn
, const Register
& rm
);
1278 // Signed multiply high: 64 x 64 -> 64-bit <127:64>.
1279 void smulh(const Register
& xd
, const Register
& xn
, const Register
& xm
);
1281 // Multiply and accumulate.
1282 void madd(const Register
& rd
,
1285 const Register
& ra
);
1287 // Multiply and subtract.
1288 void msub(const Register
& rd
,
1291 const Register
& ra
);
1293 // Signed long multiply and accumulate: 32 x 32 + 64 -> 64-bit.
1294 void smaddl(const Register
& rd
,
1297 const Register
& ra
);
1299 // Unsigned long multiply and accumulate: 32 x 32 + 64 -> 64-bit.
1300 void umaddl(const Register
& rd
,
1303 const Register
& ra
);
1305 // Signed long multiply and subtract: 64 - (32 x 32) -> 64-bit.
1306 void smsubl(const Register
& rd
,
1309 const Register
& ra
);
1311 // Unsigned long multiply and subtract: 64 - (32 x 32) -> 64-bit.
1312 void umsubl(const Register
& rd
,
1315 const Register
& ra
);
1317 // Signed integer divide.
1318 void sdiv(const Register
& rd
, const Register
& rn
, const Register
& rm
);
1320 // Unsigned integer divide.
1321 void udiv(const Register
& rd
, const Register
& rn
, const Register
& rm
);
1324 void rbit(const Register
& rd
, const Register
& rn
);
1326 // Reverse bytes in 16-bit half words.
1327 void rev16(const Register
& rd
, const Register
& rn
);
1329 // Reverse bytes in 32-bit words.
1330 void rev32(const Register
& rd
, const Register
& rn
);
1333 void rev(const Register
& rd
, const Register
& rn
);
1335 // Count leading zeroes.
1336 void clz(const Register
& rd
, const Register
& rn
);
1338 // Count leading sign bits.
1339 void cls(const Register
& rd
, const Register
& rn
);
1341 // Memory instructions.
1342 // Load integer or FP register.
1343 void ldr(const CPURegister
& rt
, const MemOperand
& src
,
1344 LoadStoreScalingOption option
= PreferScaledOffset
);
1346 // Store integer or FP register.
1347 void str(const CPURegister
& rt
, const MemOperand
& dst
,
1348 LoadStoreScalingOption option
= PreferScaledOffset
);
1350 // Load word with sign extension.
1351 void ldrsw(const Register
& rt
, const MemOperand
& src
,
1352 LoadStoreScalingOption option
= PreferScaledOffset
);
1355 void ldrb(const Register
& rt
, const MemOperand
& src
,
1356 LoadStoreScalingOption option
= PreferScaledOffset
);
1359 void strb(const Register
& rt
, const MemOperand
& dst
,
1360 LoadStoreScalingOption option
= PreferScaledOffset
);
1362 // Load byte with sign extension.
1363 void ldrsb(const Register
& rt
, const MemOperand
& src
,
1364 LoadStoreScalingOption option
= PreferScaledOffset
);
1367 void ldrh(const Register
& rt
, const MemOperand
& src
,
1368 LoadStoreScalingOption option
= PreferScaledOffset
);
1371 void strh(const Register
& rt
, const MemOperand
& dst
,
1372 LoadStoreScalingOption option
= PreferScaledOffset
);
1374 // Load half-word with sign extension.
1375 void ldrsh(const Register
& rt
, const MemOperand
& src
,
1376 LoadStoreScalingOption option
= PreferScaledOffset
);
1378 // Load integer or FP register (with unscaled offset).
1379 void ldur(const CPURegister
& rt
, const MemOperand
& src
,
1380 LoadStoreScalingOption option
= PreferUnscaledOffset
);
1382 // Store integer or FP register (with unscaled offset).
1383 void stur(const CPURegister
& rt
, const MemOperand
& src
,
1384 LoadStoreScalingOption option
= PreferUnscaledOffset
);
1386 // Load word with sign extension.
1387 void ldursw(const Register
& rt
, const MemOperand
& src
,
1388 LoadStoreScalingOption option
= PreferUnscaledOffset
);
1390 // Load byte (with unscaled offset).
1391 void ldurb(const Register
& rt
, const MemOperand
& src
,
1392 LoadStoreScalingOption option
= PreferUnscaledOffset
);
1394 // Store byte (with unscaled offset).
1395 void sturb(const Register
& rt
, const MemOperand
& dst
,
1396 LoadStoreScalingOption option
= PreferUnscaledOffset
);
1398 // Load byte with sign extension (and unscaled offset).
1399 void ldursb(const Register
& rt
, const MemOperand
& src
,
1400 LoadStoreScalingOption option
= PreferUnscaledOffset
);
1402 // Load half-word (with unscaled offset).
1403 void ldurh(const Register
& rt
, const MemOperand
& src
,
1404 LoadStoreScalingOption option
= PreferUnscaledOffset
);
1406 // Store half-word (with unscaled offset).
1407 void sturh(const Register
& rt
, const MemOperand
& dst
,
1408 LoadStoreScalingOption option
= PreferUnscaledOffset
);
1410 // Load half-word with sign extension (and unscaled offset).
1411 void ldursh(const Register
& rt
, const MemOperand
& src
,
1412 LoadStoreScalingOption option
= PreferUnscaledOffset
);
1414 // Load integer or FP register pair.
1415 void ldp(const CPURegister
& rt
, const CPURegister
& rt2
,
1416 const MemOperand
& src
);
1418 // Store integer or FP register pair.
1419 void stp(const CPURegister
& rt
, const CPURegister
& rt2
,
1420 const MemOperand
& dst
);
1422 // Load word pair with sign extension.
1423 void ldpsw(const Register
& rt
, const Register
& rt2
, const MemOperand
& src
);
1425 // Load integer or FP register pair, non-temporal.
1426 void ldnp(const CPURegister
& rt
, const CPURegister
& rt2
,
1427 const MemOperand
& src
);
1429 // Store integer or FP register pair, non-temporal.
1430 void stnp(const CPURegister
& rt
, const CPURegister
& rt2
,
1431 const MemOperand
& dst
);
1433 // Load integer or FP register from literal pool.
1434 void ldr(const CPURegister
& rt
, RawLiteral
* literal
);
1436 // Load word with sign extension from literal pool.
1437 void ldrsw(const Register
& rt
, RawLiteral
* literal
);
1439 // Load integer or FP register from pc + imm19 << 2.
1440 void ldr(const CPURegister
& rt
, int imm19
);
1442 // Load word with sign extension from pc + imm19 << 2.
1443 void ldrsw(const Register
& rt
, int imm19
);
1445 // Store exclusive byte.
1446 void stxrb(const Register
& rs
, const Register
& rt
, const MemOperand
& dst
);
1448 // Store exclusive half-word.
1449 void stxrh(const Register
& rs
, const Register
& rt
, const MemOperand
& dst
);
1451 // Store exclusive register.
1452 void stxr(const Register
& rs
, const Register
& rt
, const MemOperand
& dst
);
1454 // Load exclusive byte.
1455 void ldxrb(const Register
& rt
, const MemOperand
& src
);
1457 // Load exclusive half-word.
1458 void ldxrh(const Register
& rt
, const MemOperand
& src
);
1460 // Load exclusive register.
1461 void ldxr(const Register
& rt
, const MemOperand
& src
);
1463 // Store exclusive register pair.
1464 void stxp(const Register
& rs
,
1466 const Register
& rt2
,
1467 const MemOperand
& dst
);
1469 // Load exclusive register pair.
1470 void ldxp(const Register
& rt
, const Register
& rt2
, const MemOperand
& src
);
1472 // Store-release exclusive byte.
1473 void stlxrb(const Register
& rs
, const Register
& rt
, const MemOperand
& dst
);
1475 // Store-release exclusive half-word.
1476 void stlxrh(const Register
& rs
, const Register
& rt
, const MemOperand
& dst
);
1478 // Store-release exclusive register.
1479 void stlxr(const Register
& rs
, const Register
& rt
, const MemOperand
& dst
);
1481 // Load-acquire exclusive byte.
1482 void ldaxrb(const Register
& rt
, const MemOperand
& src
);
1484 // Load-acquire exclusive half-word.
1485 void ldaxrh(const Register
& rt
, const MemOperand
& src
);
1487 // Load-acquire exclusive register.
1488 void ldaxr(const Register
& rt
, const MemOperand
& src
);
1490 // Store-release exclusive register pair.
1491 void stlxp(const Register
& rs
,
1493 const Register
& rt2
,
1494 const MemOperand
& dst
);
1496 // Load-acquire exclusive register pair.
1497 void ldaxp(const Register
& rt
, const Register
& rt2
, const MemOperand
& src
);
1499 // Store-release byte.
1500 void stlrb(const Register
& rt
, const MemOperand
& dst
);
1502 // Store-release half-word.
1503 void stlrh(const Register
& rt
, const MemOperand
& dst
);
1505 // Store-release register.
1506 void stlr(const Register
& rt
, const MemOperand
& dst
);
1508 // Load-acquire byte.
1509 void ldarb(const Register
& rt
, const MemOperand
& src
);
1511 // Load-acquire half-word.
1512 void ldarh(const Register
& rt
, const MemOperand
& src
);
1514 // Load-acquire register.
1515 void ldar(const Register
& rt
, const MemOperand
& src
);
1518 void prfm(PrefetchOperation op
, const MemOperand
& addr
,
1519 LoadStoreScalingOption option
= PreferScaledOffset
);
1521 // Prefetch memory (with unscaled offset).
1522 void prfum(PrefetchOperation op
, const MemOperand
& addr
,
1523 LoadStoreScalingOption option
= PreferUnscaledOffset
);
1525 // Prefetch memory in the literal pool.
1526 void prfm(PrefetchOperation op
, RawLiteral
* literal
);
1528 // Prefetch from pc + imm19 << 2.
1529 void prfm(PrefetchOperation op
, int imm19
);
1531 // Move instructions. The default shift of -1 indicates that the move
1532 // instruction will calculate an appropriate 16-bit immediate and left shift
1533 // that is equal to the 64-bit immediate argument. If an explicit left shift
1534 // is specified (0, 16, 32 or 48), the immediate must be a 16-bit value.
1536 // For movk, an explicit shift can be used to indicate which half word should
1537 // be overwritten, eg. movk(x0, 0, 0) will overwrite the least-significant
1538 // half word with zero, whereas movk(x0, 0, 48) will overwrite the
1539 // most-significant.
1541 // Move immediate and keep.
1542 void movk(const Register
& rd
, uint64_t imm
, int shift
= -1) {
1543 MoveWide(rd
, imm
, shift
, MOVK
);
1546 // Move inverted immediate.
1547 void movn(const Register
& rd
, uint64_t imm
, int shift
= -1) {
1548 MoveWide(rd
, imm
, shift
, MOVN
);
1552 void movz(const Register
& rd
, uint64_t imm
, int shift
= -1) {
1553 MoveWide(rd
, imm
, shift
, MOVZ
);
1556 // Misc instructions.
1557 // Monitor debug-mode breakpoint.
1560 // Halting debug-mode breakpoint.
1563 // Move register to register.
1564 void mov(const Register
& rd
, const Register
& rn
);
1566 // Move inverted operand to register.
1567 void mvn(const Register
& rd
, const Operand
& operand
);
1569 // System instructions.
1570 // Move to register from system register.
1571 void mrs(const Register
& rt
, SystemRegister sysreg
);
1573 // Move from register to system register.
1574 void msr(SystemRegister sysreg
, const Register
& rt
);
1577 void hint(SystemHint code
);
1579 // Clear exclusive monitor.
1580 void clrex(int imm4
= 0xf);
1582 // Data memory barrier.
1583 void dmb(BarrierDomain domain
, BarrierType type
);
1585 // Data synchronization barrier.
1586 void dsb(BarrierDomain domain
, BarrierType type
);
1588 // Instruction synchronization barrier.
1591 // Alias for system instructions.
1598 // Move double precision immediate to FP register.
1599 void fmov(const FPRegister
& fd
, double imm
);
1601 // Move single precision immediate to FP register.
1602 void fmov(const FPRegister
& fd
, float imm
);
1604 // Move FP register to register.
1605 void fmov(const Register
& rd
, const FPRegister
& fn
);
1607 // Move register to FP register.
1608 void fmov(const FPRegister
& fd
, const Register
& rn
);
1610 // Move FP register to FP register.
1611 void fmov(const FPRegister
& fd
, const FPRegister
& fn
);
1614 void fadd(const FPRegister
& fd
, const FPRegister
& fn
, const FPRegister
& fm
);
1617 void fsub(const FPRegister
& fd
, const FPRegister
& fn
, const FPRegister
& fm
);
1620 void fmul(const FPRegister
& fd
, const FPRegister
& fn
, const FPRegister
& fm
);
1622 // FP fused multiply and add.
1623 void fmadd(const FPRegister
& fd
,
1624 const FPRegister
& fn
,
1625 const FPRegister
& fm
,
1626 const FPRegister
& fa
);
1628 // FP fused multiply and subtract.
1629 void fmsub(const FPRegister
& fd
,
1630 const FPRegister
& fn
,
1631 const FPRegister
& fm
,
1632 const FPRegister
& fa
);
1634 // FP fused multiply, add and negate.
1635 void fnmadd(const FPRegister
& fd
,
1636 const FPRegister
& fn
,
1637 const FPRegister
& fm
,
1638 const FPRegister
& fa
);
1640 // FP fused multiply, subtract and negate.
1641 void fnmsub(const FPRegister
& fd
,
1642 const FPRegister
& fn
,
1643 const FPRegister
& fm
,
1644 const FPRegister
& fa
);
1647 void fdiv(const FPRegister
& fd
, const FPRegister
& fn
, const FPRegister
& fm
);
1650 void fmax(const FPRegister
& fd
, const FPRegister
& fn
, const FPRegister
& fm
);
1653 void fmin(const FPRegister
& fd
, const FPRegister
& fn
, const FPRegister
& fm
);
1655 // FP maximum number.
1656 void fmaxnm(const FPRegister
& fd
, const FPRegister
& fn
, const FPRegister
& fm
);
1658 // FP minimum number.
1659 void fminnm(const FPRegister
& fd
, const FPRegister
& fn
, const FPRegister
& fm
);
1662 void fabs(const FPRegister
& fd
, const FPRegister
& fn
);
1665 void fneg(const FPRegister
& fd
, const FPRegister
& fn
);
1668 void fsqrt(const FPRegister
& fd
, const FPRegister
& fn
);
1670 // FP round to integer (nearest with ties to away).
1671 void frinta(const FPRegister
& fd
, const FPRegister
& fn
);
1673 // FP round to integer (implicit rounding).
1674 void frinti(const FPRegister
& fd
, const FPRegister
& fn
);
1676 // FP round to integer (toward minus infinity).
1677 void frintm(const FPRegister
& fd
, const FPRegister
& fn
);
1679 // FP round to integer (nearest with ties to even).
1680 void frintn(const FPRegister
& fd
, const FPRegister
& fn
);
1682 // FP round to integer (toward plus infinity).
1683 void frintp(const FPRegister
& fd
, const FPRegister
& fn
);
1685 // FP round to integer (exact, implicit rounding).
1686 void frintx(const FPRegister
& fd
, const FPRegister
& fn
);
1688 // FP round to integer (towards zero).
1689 void frintz(const FPRegister
& fd
, const FPRegister
& fn
);
1691 // FP compare registers.
1692 void fcmp(const FPRegister
& fn
, const FPRegister
& fm
);
1694 // FP compare immediate.
1695 void fcmp(const FPRegister
& fn
, double value
);
1697 // FP conditional compare.
1698 void fccmp(const FPRegister
& fn
,
1699 const FPRegister
& fm
,
1703 // FP conditional select.
1704 void fcsel(const FPRegister
& fd
,
1705 const FPRegister
& fn
,
1706 const FPRegister
& fm
,
1709 // Common FP Convert function.
1710 void FPConvertToInt(const Register
& rd
,
1711 const FPRegister
& fn
,
1712 FPIntegerConvertOp op
);
1714 // FP convert between single and double precision.
1715 void fcvt(const FPRegister
& fd
, const FPRegister
& fn
);
1717 // Convert FP to signed integer (nearest with ties to away).
1718 void fcvtas(const Register
& rd
, const FPRegister
& fn
);
1720 // Convert FP to unsigned integer (nearest with ties to away).
1721 void fcvtau(const Register
& rd
, const FPRegister
& fn
);
1723 // Convert FP to signed integer (round towards -infinity).
1724 void fcvtms(const Register
& rd
, const FPRegister
& fn
);
1726 // Convert FP to unsigned integer (round towards -infinity).
1727 void fcvtmu(const Register
& rd
, const FPRegister
& fn
);
1729 // Convert FP to signed integer (nearest with ties to even).
1730 void fcvtns(const Register
& rd
, const FPRegister
& fn
);
1732 // Convert FP to unsigned integer (nearest with ties to even).
1733 void fcvtnu(const Register
& rd
, const FPRegister
& fn
);
1735 // Convert FP to signed integer (round towards zero).
1736 void fcvtzs(const Register
& rd
, const FPRegister
& fn
);
1738 // Convert FP to unsigned integer (round towards zero).
1739 void fcvtzu(const Register
& rd
, const FPRegister
& fn
);
1741 // Convert signed integer or fixed point to FP.
1742 void scvtf(const FPRegister
& fd
, const Register
& rn
, unsigned fbits
= 0);
1744 // Convert unsigned integer or fixed point to FP.
1745 void ucvtf(const FPRegister
& fd
, const Register
& rn
, unsigned fbits
= 0);
1747 // Emit generic instructions.
1748 // Emit raw instructions into the instruction stream.
1749 void dci(Instr raw_inst
) { Emit(raw_inst
); }
1751 // Emit 32 bits of data into the instruction stream.
1752 void dc32(uint32_t data
) {
1753 VIXL_ASSERT(buffer_monitor_
> 0);
1754 buffer_
->Emit32(data
);
1757 // Emit 64 bits of data into the instruction stream.
1758 void dc64(uint64_t data
) {
1759 VIXL_ASSERT(buffer_monitor_
> 0);
1760 buffer_
->Emit64(data
);
1763 // Copy a string into the instruction stream, including the terminating NULL
1764 // character. The instruction pointer is then aligned correctly for
1765 // subsequent instructions.
1766 void EmitString(const char * string
) {
1767 VIXL_ASSERT(string
!= NULL
);
1768 VIXL_ASSERT(buffer_monitor_
> 0);
1770 buffer_
->EmitString(string
);
1774 // Code generation helpers.
1776 // Register encoding.
1777 static Instr
Rd(CPURegister rd
) {
1778 VIXL_ASSERT(rd
.code() != kSPRegInternalCode
);
1779 return rd
.code() << Rd_offset
;
1782 static Instr
Rn(CPURegister rn
) {
1783 VIXL_ASSERT(rn
.code() != kSPRegInternalCode
);
1784 return rn
.code() << Rn_offset
;
1787 static Instr
Rm(CPURegister rm
) {
1788 VIXL_ASSERT(rm
.code() != kSPRegInternalCode
);
1789 return rm
.code() << Rm_offset
;
1792 static Instr
Ra(CPURegister ra
) {
1793 VIXL_ASSERT(ra
.code() != kSPRegInternalCode
);
1794 return ra
.code() << Ra_offset
;
1797 static Instr
Rt(CPURegister rt
) {
1798 VIXL_ASSERT(rt
.code() != kSPRegInternalCode
);
1799 return rt
.code() << Rt_offset
;
1802 static Instr
Rt2(CPURegister rt2
) {
1803 VIXL_ASSERT(rt2
.code() != kSPRegInternalCode
);
1804 return rt2
.code() << Rt2_offset
;
1807 static Instr
Rs(CPURegister rs
) {
1808 VIXL_ASSERT(rs
.code() != kSPRegInternalCode
);
1809 return rs
.code() << Rs_offset
;
1812 // These encoding functions allow the stack pointer to be encoded, and
1813 // disallow the zero register.
1814 static Instr
RdSP(Register rd
) {
1815 VIXL_ASSERT(!rd
.IsZero());
1816 return (rd
.code() & kRegCodeMask
) << Rd_offset
;
1819 static Instr
RnSP(Register rn
) {
1820 VIXL_ASSERT(!rn
.IsZero());
1821 return (rn
.code() & kRegCodeMask
) << Rn_offset
;
1825 static Instr
Flags(FlagsUpdate S
) {
1826 if (S
== SetFlags
) {
1827 return 1 << FlagsUpdate_offset
;
1828 } else if (S
== LeaveFlags
) {
1829 return 0 << FlagsUpdate_offset
;
1835 static Instr
Cond(Condition cond
) {
1836 return cond
<< Condition_offset
;
1839 // PC-relative address encoding.
1840 static Instr
ImmPCRelAddress(int imm21
) {
1841 VIXL_ASSERT(is_int21(imm21
));
1842 Instr imm
= static_cast<Instr
>(truncate_to_int21(imm21
));
1843 Instr immhi
= (imm
>> ImmPCRelLo_width
) << ImmPCRelHi_offset
;
1844 Instr immlo
= imm
<< ImmPCRelLo_offset
;
1845 return (immhi
& ImmPCRelHi_mask
) | (immlo
& ImmPCRelLo_mask
);
1849 static Instr
ImmUncondBranch(int imm26
) {
1850 VIXL_ASSERT(is_int26(imm26
));
1851 return truncate_to_int26(imm26
) << ImmUncondBranch_offset
;
1854 static Instr
ImmCondBranch(int imm19
) {
1855 VIXL_ASSERT(is_int19(imm19
));
1856 return truncate_to_int19(imm19
) << ImmCondBranch_offset
;
1859 static Instr
ImmCmpBranch(int imm19
) {
1860 VIXL_ASSERT(is_int19(imm19
));
1861 return truncate_to_int19(imm19
) << ImmCmpBranch_offset
;
1864 static Instr
ImmTestBranch(int imm14
) {
1865 VIXL_ASSERT(is_int14(imm14
));
1866 return truncate_to_int14(imm14
) << ImmTestBranch_offset
;
1869 static Instr
ImmTestBranchBit(unsigned bit_pos
) {
1870 VIXL_ASSERT(is_uint6(bit_pos
));
1871 // Subtract five from the shift offset, as we need bit 5 from bit_pos.
1872 unsigned b5
= bit_pos
<< (ImmTestBranchBit5_offset
- 5);
1873 unsigned b40
= bit_pos
<< ImmTestBranchBit40_offset
;
1874 b5
&= ImmTestBranchBit5_mask
;
1875 b40
&= ImmTestBranchBit40_mask
;
1879 // Data Processing encoding.
1880 static Instr
SF(Register rd
) {
1881 return rd
.Is64Bits() ? SixtyFourBits
: ThirtyTwoBits
;
1884 static Instr
ImmAddSub(int64_t imm
) {
1885 VIXL_ASSERT(IsImmAddSub(imm
));
1886 if (is_uint12(imm
)) { // No shift required.
1887 return imm
<< ImmAddSub_offset
;
1889 return ((imm
>> 12) << ImmAddSub_offset
) | (1 << ShiftAddSub_offset
);
1893 static Instr
ImmS(unsigned imms
, unsigned reg_size
) {
1894 VIXL_ASSERT(((reg_size
== kXRegSize
) && is_uint6(imms
)) ||
1895 ((reg_size
== kWRegSize
) && is_uint5(imms
)));
1897 return imms
<< ImmS_offset
;
1900 static Instr
ImmR(unsigned immr
, unsigned reg_size
) {
1901 VIXL_ASSERT(((reg_size
== kXRegSize
) && is_uint6(immr
)) ||
1902 ((reg_size
== kWRegSize
) && is_uint5(immr
)));
1904 VIXL_ASSERT(is_uint6(immr
));
1905 return immr
<< ImmR_offset
;
1908 static Instr
ImmSetBits(unsigned imms
, unsigned reg_size
) {
1909 VIXL_ASSERT((reg_size
== kWRegSize
) || (reg_size
== kXRegSize
));
1910 VIXL_ASSERT(is_uint6(imms
));
1911 VIXL_ASSERT((reg_size
== kXRegSize
) || is_uint6(imms
+ 3));
1913 return imms
<< ImmSetBits_offset
;
1916 static Instr
ImmRotate(unsigned immr
, unsigned reg_size
) {
1917 VIXL_ASSERT((reg_size
== kWRegSize
) || (reg_size
== kXRegSize
));
1918 VIXL_ASSERT(((reg_size
== kXRegSize
) && is_uint6(immr
)) ||
1919 ((reg_size
== kWRegSize
) && is_uint5(immr
)));
1921 return immr
<< ImmRotate_offset
;
1924 static Instr
ImmLLiteral(int imm19
) {
1925 VIXL_ASSERT(is_int19(imm19
));
1926 return truncate_to_int19(imm19
) << ImmLLiteral_offset
;
1929 static Instr
BitN(unsigned bitn
, unsigned reg_size
) {
1930 VIXL_ASSERT((reg_size
== kWRegSize
) || (reg_size
== kXRegSize
));
1931 VIXL_ASSERT((reg_size
== kXRegSize
) || (bitn
== 0));
1933 return bitn
<< BitN_offset
;
1936 static Instr
ShiftDP(Shift shift
) {
1937 VIXL_ASSERT(shift
== LSL
|| shift
== LSR
|| shift
== ASR
|| shift
== ROR
);
1938 return shift
<< ShiftDP_offset
;
1941 static Instr
ImmDPShift(unsigned amount
) {
1942 VIXL_ASSERT(is_uint6(amount
));
1943 return amount
<< ImmDPShift_offset
;
1946 static Instr
ExtendMode(Extend extend
) {
1947 return extend
<< ExtendMode_offset
;
1950 static Instr
ImmExtendShift(unsigned left_shift
) {
1951 VIXL_ASSERT(left_shift
<= 4);
1952 return left_shift
<< ImmExtendShift_offset
;
1955 static Instr
ImmCondCmp(unsigned imm
) {
1956 VIXL_ASSERT(is_uint5(imm
));
1957 return imm
<< ImmCondCmp_offset
;
1960 static Instr
Nzcv(StatusFlags nzcv
) {
1961 return ((nzcv
>> Flags_offset
) & 0xf) << Nzcv_offset
;
1964 // MemOperand offset encoding.
1965 static Instr
ImmLSUnsigned(int imm12
) {
1966 VIXL_ASSERT(is_uint12(imm12
));
1967 return imm12
<< ImmLSUnsigned_offset
;
1970 static Instr
ImmLS(int imm9
) {
1971 VIXL_ASSERT(is_int9(imm9
));
1972 return truncate_to_int9(imm9
) << ImmLS_offset
;
1975 static Instr
ImmLSPair(int imm7
, LSDataSize size
) {
1976 VIXL_ASSERT(((imm7
>> size
) << size
) == imm7
);
1977 int scaled_imm7
= imm7
>> size
;
1978 VIXL_ASSERT(is_int7(scaled_imm7
));
1979 return truncate_to_int7(scaled_imm7
) << ImmLSPair_offset
;
1982 static Instr
ImmShiftLS(unsigned shift_amount
) {
1983 VIXL_ASSERT(is_uint1(shift_amount
));
1984 return shift_amount
<< ImmShiftLS_offset
;
1987 static Instr
ImmPrefetchOperation(int imm5
) {
1988 VIXL_ASSERT(is_uint5(imm5
));
1989 return imm5
<< ImmPrefetchOperation_offset
;
1992 static Instr
ImmException(int imm16
) {
1993 VIXL_ASSERT(is_uint16(imm16
));
1994 return imm16
<< ImmException_offset
;
1997 static Instr
ImmSystemRegister(int imm15
) {
1998 VIXL_ASSERT(is_uint15(imm15
));
1999 return imm15
<< ImmSystemRegister_offset
;
2002 static Instr
ImmHint(int imm7
) {
2003 VIXL_ASSERT(is_uint7(imm7
));
2004 return imm7
<< ImmHint_offset
;
2007 static Instr
CRm(int imm4
) {
2008 VIXL_ASSERT(is_uint4(imm4
));
2009 return imm4
<< CRm_offset
;
2012 static Instr
ImmBarrierDomain(int imm2
) {
2013 VIXL_ASSERT(is_uint2(imm2
));
2014 return imm2
<< ImmBarrierDomain_offset
;
2017 static Instr
ImmBarrierType(int imm2
) {
2018 VIXL_ASSERT(is_uint2(imm2
));
2019 return imm2
<< ImmBarrierType_offset
;
2022 static LSDataSize
CalcLSDataSize(LoadStoreOp op
) {
2023 VIXL_ASSERT((SizeLS_offset
+ SizeLS_width
) == (kInstructionSize
* 8));
2024 return static_cast<LSDataSize
>(op
>> SizeLS_offset
);
2027 // Move immediates encoding.
2028 static Instr
ImmMoveWide(uint64_t imm
) {
2029 VIXL_ASSERT(is_uint16(imm
));
2030 return imm
<< ImmMoveWide_offset
;
2033 static Instr
ShiftMoveWide(int64_t shift
) {
2034 VIXL_ASSERT(is_uint2(shift
));
2035 return shift
<< ShiftMoveWide_offset
;
2039 static Instr
ImmFP32(float imm
);
2040 static Instr
ImmFP64(double imm
);
2042 // FP register type.
2043 static Instr
FPType(FPRegister fd
) {
2044 return fd
.Is64Bits() ? FP64
: FP32
;
2047 static Instr
FPScale(unsigned scale
) {
2048 VIXL_ASSERT(is_uint6(scale
));
2049 return scale
<< FPScale_offset
;
2052 // Immediate field checking helpers.
2053 static bool IsImmAddSub(int64_t immediate
);
2054 static bool IsImmConditionalCompare(int64_t immediate
);
2055 static bool IsImmFP32(float imm
);
2056 static bool IsImmFP64(double imm
);
2057 static bool IsImmLogical(uint64_t value
,
2060 unsigned* imm_s
= NULL
,
2061 unsigned* imm_r
= NULL
);
2062 static bool IsImmLSPair(int64_t offset
, LSDataSize size
);
2063 static bool IsImmLSScaled(int64_t offset
, LSDataSize size
);
2064 static bool IsImmLSUnscaled(int64_t offset
);
2065 static bool IsImmMovn(uint64_t imm
, unsigned reg_size
);
2066 static bool IsImmMovz(uint64_t imm
, unsigned reg_size
);
2068 // Size of the code generated since label to the current position.
2069 size_t SizeOfCodeGeneratedSince(Label
* label
) const {
2070 VIXL_ASSERT(label
->IsBound());
2071 return buffer_
->OffsetFrom(label
->location());
2074 size_t SizeOfCodeGenerated() const {
2075 return buffer_
->CursorOffset();
2078 size_t BufferCapacity() const { return buffer_
->capacity(); }
2080 size_t RemainingBufferSpace() const { return buffer_
->RemainingBytes(); }
2082 void EnsureSpaceFor(size_t amount
) {
2083 if (buffer_
->RemainingBytes() < amount
) {
2084 size_t capacity
= buffer_
->capacity();
2085 size_t size
= buffer_
->CursorOffset();
2087 // TODO(all): refine.
2089 } while ((capacity
- size
) < amount
);
2090 buffer_
->Grow(capacity
);
2095 void AcquireBuffer() {
2096 VIXL_ASSERT(buffer_monitor_
>= 0);
2100 void ReleaseBuffer() {
2102 VIXL_ASSERT(buffer_monitor_
>= 0);
2106 PositionIndependentCodeOption
pic() const {
2110 bool AllowPageOffsetDependentCode() const {
2111 return (pic() == PageOffsetDependentCode
) ||
2112 (pic() == PositionDependentCode
);
2115 static const Register
& AppropriateZeroRegFor(const CPURegister
& reg
) {
2116 return reg
.Is64Bits() ? xzr
: wzr
;
2121 void LoadStore(const CPURegister
& rt
,
2122 const MemOperand
& addr
,
2124 LoadStoreScalingOption option
= PreferScaledOffset
);
2126 void LoadStorePair(const CPURegister
& rt
,
2127 const CPURegister
& rt2
,
2128 const MemOperand
& addr
,
2129 LoadStorePairOp op
);
2131 void Prefetch(PrefetchOperation op
,
2132 const MemOperand
& addr
,
2133 LoadStoreScalingOption option
= PreferScaledOffset
);
2135 // TODO(all): The third parameter should be passed by reference but gcc 4.8.2
2136 // reports a bogus uninitialised warning then.
2137 void Logical(const Register
& rd
,
2139 const Operand operand
,
2141 void LogicalImmediate(const Register
& rd
,
2148 void ConditionalCompare(const Register
& rn
,
2149 const Operand
& operand
,
2152 ConditionalCompareOp op
);
2154 void AddSubWithCarry(const Register
& rd
,
2156 const Operand
& operand
,
2158 AddSubWithCarryOp op
);
2161 // Functions for emulating operands not directly supported by the instruction
2163 void EmitShift(const Register
& rd
,
2167 void EmitExtendShift(const Register
& rd
,
2170 unsigned left_shift
);
2172 void AddSub(const Register
& rd
,
2174 const Operand
& operand
,
2178 // Find an appropriate LoadStoreOp or LoadStorePairOp for the specified
2179 // registers. Only simple loads are supported; sign- and zero-extension (such
2180 // as in LDPSW_x or LDRB_w) are not supported.
2181 static LoadStoreOp
LoadOpFor(const CPURegister
& rt
);
2182 static LoadStorePairOp
LoadPairOpFor(const CPURegister
& rt
,
2183 const CPURegister
& rt2
);
2184 static LoadStoreOp
StoreOpFor(const CPURegister
& rt
);
2185 static LoadStorePairOp
StorePairOpFor(const CPURegister
& rt
,
2186 const CPURegister
& rt2
);
2187 static LoadStorePairNonTemporalOp
LoadPairNonTemporalOpFor(
2188 const CPURegister
& rt
, const CPURegister
& rt2
);
2189 static LoadStorePairNonTemporalOp
StorePairNonTemporalOpFor(
2190 const CPURegister
& rt
, const CPURegister
& rt2
);
2191 static LoadLiteralOp
LoadLiteralOpFor(const CPURegister
& rt
);
2195 // Instruction helpers.
2196 void MoveWide(const Register
& rd
,
2199 MoveWideImmediateOp mov_op
);
2200 void DataProcShiftedRegister(const Register
& rd
,
2202 const Operand
& operand
,
2205 void DataProcExtendedRegister(const Register
& rd
,
2207 const Operand
& operand
,
2210 void LoadStorePairNonTemporal(const CPURegister
& rt
,
2211 const CPURegister
& rt2
,
2212 const MemOperand
& addr
,
2213 LoadStorePairNonTemporalOp op
);
2214 void LoadLiteral(const CPURegister
& rt
, uint64_t imm
, LoadLiteralOp op
);
2215 void ConditionalSelect(const Register
& rd
,
2219 ConditionalSelectOp op
);
2220 void DataProcessing1Source(const Register
& rd
,
2222 DataProcessing1SourceOp op
);
2223 void DataProcessing3Source(const Register
& rd
,
2227 DataProcessing3SourceOp op
);
2228 void FPDataProcessing1Source(const FPRegister
& fd
,
2229 const FPRegister
& fn
,
2230 FPDataProcessing1SourceOp op
);
2231 void FPDataProcessing2Source(const FPRegister
& fd
,
2232 const FPRegister
& fn
,
2233 const FPRegister
& fm
,
2234 FPDataProcessing2SourceOp op
);
2235 void FPDataProcessing3Source(const FPRegister
& fd
,
2236 const FPRegister
& fn
,
2237 const FPRegister
& fm
,
2238 const FPRegister
& fa
,
2239 FPDataProcessing3SourceOp op
);
2241 // Encode the specified MemOperand for the specified access size and scaling
2243 Instr
LoadStoreMemOperand(const MemOperand
& addr
,
2245 LoadStoreScalingOption option
);
2247 // Link the current (not-yet-emitted) instruction to the specified label, then
2248 // return an offset to be encoded in the instruction. If the label is not yet
2249 // bound, an offset of 0 is returned.
2250 ptrdiff_t LinkAndGetByteOffsetTo(Label
* label
);
2251 ptrdiff_t LinkAndGetInstructionOffsetTo(Label
* label
);
2252 ptrdiff_t LinkAndGetPageOffsetTo(Label
* label
);
2254 // A common implementation for the LinkAndGet<Type>OffsetTo helpers.
2255 template <int element_shift
>
2256 ptrdiff_t LinkAndGetOffsetTo(Label
* label
);
2258 // Literal load offset are in words (32-bit).
2259 ptrdiff_t LinkAndGetWordOffsetTo(RawLiteral
* literal
);
2261 // Emit the instruction in buffer_.
2262 void Emit(Instr instruction
) {
2263 VIXL_STATIC_ASSERT(sizeof(instruction
) == kInstructionSize
);
2264 VIXL_ASSERT(buffer_monitor_
> 0);
2265 buffer_
->Emit32(instruction
);
2268 // Buffer where the code is emitted.
2269 CodeBuffer
* buffer_
;
2270 PositionIndependentCodeOption pic_
;
2273 int64_t buffer_monitor_
;
2278 // All Assembler emits MUST acquire/release the underlying code buffer. The
2279 // helper scope below will do so and optionally ensure the buffer is big enough
2280 // to receive the emit. It is possible to request the scope not to perform any
2281 // checks (kNoCheck) if for example it is known in advance the buffer size is
2282 // adequate or there is some other size checking mechanism in place.
2283 class CodeBufferCheckScope
{
2285 // Tell whether or not the scope needs to ensure the associated CodeBuffer
2286 // has enough space for the requested size.
2292 // Tell whether or not the scope should assert the amount of code emitted
2293 // within the scope is consistent with the requested amount.
2295 kNoAssert
, // No assert required.
2296 kExactSize
, // The code emitted must be exactly size bytes.
2297 kMaximumSize
// The code emitted must be at most size bytes.
2300 CodeBufferCheckScope(Assembler
* assm
,
2302 CheckPolicy check_policy
= kCheck
,
2303 AssertPolicy assert_policy
= kMaximumSize
)
2305 if (check_policy
== kCheck
) assm
->EnsureSpaceFor(size
);
2307 assm
->bind(&start_
);
2309 assert_policy_
= assert_policy
;
2310 assm
->AcquireBuffer();
2316 // This is a shortcut for CodeBufferCheckScope(assm, 0, kNoCheck, kNoAssert).
2317 explicit CodeBufferCheckScope(Assembler
* assm
) : assm_(assm
) {
2320 assert_policy_
= kNoAssert
;
2321 assm
->AcquireBuffer();
2325 ~CodeBufferCheckScope() {
2327 assm_
->ReleaseBuffer();
2328 switch (assert_policy_
) {
2329 case kNoAssert
: break;
2331 VIXL_ASSERT(assm_
->SizeOfCodeGeneratedSince(&start_
) == size_
);
2334 VIXL_ASSERT(assm_
->SizeOfCodeGeneratedSince(&start_
) <= size_
);
2347 AssertPolicy assert_policy_
;
2353 #endif // VIXL_A64_ASSEMBLER_A64_H_