target/sh4/op_helper.c

   1 /*
   2  *  SH4 emulation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "exec/helper-proto.h"
  22 #include "exec/exec-all.h"
  23 #include "exec/cpu_ldst.h"
  24 #include "fpu/softfloat.h"
  25
  26 #ifndef CONFIG_USER_ONLY
  27
  28 void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
  29                                     MMUAccessType access_type,
  30                                     int mmu_idx, uintptr_t retaddr)
  31 {
  32     switch (access_type) {
  33     case MMU_INST_FETCH:
  34     case MMU_DATA_LOAD:
  35         cs->exception_index = 0x0e0;
  36         break;
  37     case MMU_DATA_STORE:
  38         cs->exception_index = 0x100;
  39         break;
  40     }
  41     cpu_loop_exit_restore(cs, retaddr);
  42 }
  43
  44 #endif
  45
  46 void helper_ldtlb(CPUSH4State *env)
  47 {
  48 #ifdef CONFIG_USER_ONLY
  49     SuperHCPU *cpu = sh_env_get_cpu(env);
  50
  51     /* XXXXX */
  52     cpu_abort(CPU(cpu), "Unhandled ldtlb");
  53 #else
  54     cpu_load_tlb(env);
  55 #endif
  56 }
  57
  58 static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index,
  59                                                  uintptr_t retaddr)
  60 {
  61     CPUState *cs = CPU(sh_env_get_cpu(env));
  62
  63     cs->exception_index = index;
  64     cpu_loop_exit_restore(cs, retaddr);
  65 }
  66
  67 void helper_raise_illegal_instruction(CPUSH4State *env)
  68 {
  69     raise_exception(env, 0x180, 0);
  70 }
  71
  72 void helper_raise_slot_illegal_instruction(CPUSH4State *env)
  73 {
  74     raise_exception(env, 0x1a0, 0);
  75 }
  76
  77 void helper_raise_fpu_disable(CPUSH4State *env)
  78 {
  79     raise_exception(env, 0x800, 0);
  80 }
  81
  82 void helper_raise_slot_fpu_disable(CPUSH4State *env)
  83 {
  84     raise_exception(env, 0x820, 0);
  85 }
  86
  87 void helper_debug(CPUSH4State *env)
  88 {
  89     raise_exception(env, EXCP_DEBUG, 0);
  90 }
  91
  92 void helper_sleep(CPUSH4State *env)
  93 {
  94     CPUState *cs = CPU(sh_env_get_cpu(env));
  95
  96     cs->halted = 1;
  97     env->in_sleep = 1;
  98     raise_exception(env, EXCP_HLT, 0);
  99 }
 100
 101 void helper_trapa(CPUSH4State *env, uint32_t tra)
 102 {
 103     env->tra = tra << 2;
 104     raise_exception(env, 0x160, 0);
 105 }
 106
 107 void helper_exclusive(CPUSH4State *env)
 108 {
 109     /* We do not want cpu_restore_state to run.  */
 110     cpu_loop_exit_atomic(ENV_GET_CPU(env), 0);
 111 }
 112
 113 void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value)
 114 {
 115     if (cpu_sh4_is_cached (env, address))
 116     {
 117         memory_content *r = g_new(memory_content, 1);
 118
 119         r->address = address;
 120         r->value = value;
 121         r->next = NULL;
 122
 123         *(env->movcal_backup_tail) = r;
 124         env->movcal_backup_tail = &(r->next);
 125     }
 126 }
 127
 128 void helper_discard_movcal_backup(CPUSH4State *env)
 129 {
 130     memory_content *current = env->movcal_backup;
 131
 132     while(current)
 133     {
 134         memory_content *next = current->next;
 135         g_free(current);
 136         env->movcal_backup = current = next;
 137         if (current == NULL)
 138             env->movcal_backup_tail = &(env->movcal_backup);
 139     }
 140 }
 141
 142 void helper_ocbi(CPUSH4State *env, uint32_t address)
 143 {
 144     memory_content **current = &(env->movcal_backup);
 145     while (*current)
 146     {
 147         uint32_t a = (*current)->address;
 148         if ((a & ~0x1F) == (address & ~0x1F))
 149         {
 150             memory_content *next = (*current)->next;
 151             cpu_stl_data(env, a, (*current)->value);
 152
 153             if (next == NULL)
 154             {
 155                 env->movcal_backup_tail = current;
 156             }
 157
 158             g_free(*current);
 159             *current = next;
 160             break;
 161         }
 162     }
 163 }
 164
 165 void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 166 {
 167     int64_t res;
 168
 169     res = ((uint64_t) env->mach << 32) | env->macl;
 170     res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1;
 171     env->mach = (res >> 32) & 0xffffffff;
 172     env->macl = res & 0xffffffff;
 173     if (env->sr & (1u << SR_S)) {
 174         if (res < 0)
 175             env->mach |= 0xffff0000;
 176         else
 177             env->mach &= 0x00007fff;
 178     }
 179 }
 180
 181 void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 182 {
 183     int64_t res;
 184
 185     res = ((uint64_t) env->mach << 32) | env->macl;
 186     res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1;
 187     env->mach = (res >> 32) & 0xffffffff;
 188     env->macl = res & 0xffffffff;
 189     if (env->sr & (1u << SR_S)) {
 190         if (res < -0x80000000) {
 191             env->mach = 1;
 192             env->macl = 0x80000000;
 193         } else if (res > 0x000000007fffffff) {
 194             env->mach = 1;
 195             env->macl = 0x7fffffff;
 196         }
 197     }
 198 }
 199
 200 void helper_ld_fpscr(CPUSH4State *env, uint32_t val)
 201 {
 202     env->fpscr = val & FPSCR_MASK;
 203     if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
 204         set_float_rounding_mode(float_round_to_zero, &env->fp_status);
 205     } else {
 206         set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
 207     }
 208     set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
 209 }
 210
 211 static void update_fpscr(CPUSH4State *env, uintptr_t retaddr)
 212 {
 213     int xcpt, cause, enable;
 214
 215     xcpt = get_float_exception_flags(&env->fp_status);
 216
 217     /* Clear the cause entries */
 218     env->fpscr &= ~FPSCR_CAUSE_MASK;
 219
 220     if (unlikely(xcpt)) {
 221         if (xcpt & float_flag_invalid) {
 222             env->fpscr |= FPSCR_CAUSE_V;
 223         }
 224         if (xcpt & float_flag_divbyzero) {
 225             env->fpscr |= FPSCR_CAUSE_Z;
 226         }
 227         if (xcpt & float_flag_overflow) {
 228             env->fpscr |= FPSCR_CAUSE_O;
 229         }
 230         if (xcpt & float_flag_underflow) {
 231             env->fpscr |= FPSCR_CAUSE_U;
 232         }
 233         if (xcpt & float_flag_inexact) {
 234             env->fpscr |= FPSCR_CAUSE_I;
 235         }
 236
 237         /* Accumulate in flag entries */
 238         env->fpscr |= (env->fpscr & FPSCR_CAUSE_MASK)
 239                       >> (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT);
 240
 241         /* Generate an exception if enabled */
 242         cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT;
 243         enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT;
 244         if (cause & enable) {
 245             raise_exception(env, 0x120, retaddr);
 246         }
 247     }
 248 }
 249
 250 float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1)
 251 {
 252     set_float_exception_flags(0, &env->fp_status);
 253     t0 = float32_add(t0, t1, &env->fp_status);
 254     update_fpscr(env, GETPC());
 255     return t0;
 256 }
 257
 258 float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1)
 259 {
 260     set_float_exception_flags(0, &env->fp_status);
 261     t0 = float64_add(t0, t1, &env->fp_status);
 262     update_fpscr(env, GETPC());
 263     return t0;
 264 }
 265
 266 uint32_t helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1)
 267 {
 268     int relation;
 269
 270     set_float_exception_flags(0, &env->fp_status);
 271     relation = float32_compare(t0, t1, &env->fp_status);
 272     update_fpscr(env, GETPC());
 273     return relation == float_relation_equal;
 274 }
 275
 276 uint32_t helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1)
 277 {
 278     int relation;
 279
 280     set_float_exception_flags(0, &env->fp_status);
 281     relation = float64_compare(t0, t1, &env->fp_status);
 282     update_fpscr(env, GETPC());
 283     return relation == float_relation_equal;
 284 }
 285
 286 uint32_t helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1)
 287 {
 288     int relation;
 289
 290     set_float_exception_flags(0, &env->fp_status);
 291     relation = float32_compare(t0, t1, &env->fp_status);
 292     update_fpscr(env, GETPC());
 293     return relation == float_relation_greater;
 294 }
 295
 296 uint32_t helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1)
 297 {
 298     int relation;
 299
 300     set_float_exception_flags(0, &env->fp_status);
 301     relation = float64_compare(t0, t1, &env->fp_status);
 302     update_fpscr(env, GETPC());
 303     return relation == float_relation_greater;
 304 }
 305
 306 float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0)
 307 {
 308     float64 ret;
 309     set_float_exception_flags(0, &env->fp_status);
 310     ret = float32_to_float64(t0, &env->fp_status);
 311     update_fpscr(env, GETPC());
 312     return ret;
 313 }
 314
 315 float32 helper_fcnvds_DT_FT(CPUSH4State *env, float64 t0)
 316 {
 317     float32 ret;
 318     set_float_exception_flags(0, &env->fp_status);
 319     ret = float64_to_float32(t0, &env->fp_status);
 320     update_fpscr(env, GETPC());
 321     return ret;
 322 }
 323
 324 float32 helper_fdiv_FT(CPUSH4State *env, float32 t0, float32 t1)
 325 {
 326     set_float_exception_flags(0, &env->fp_status);
 327     t0 = float32_div(t0, t1, &env->fp_status);
 328     update_fpscr(env, GETPC());
 329     return t0;
 330 }
 331
 332 float64 helper_fdiv_DT(CPUSH4State *env, float64 t0, float64 t1)
 333 {
 334     set_float_exception_flags(0, &env->fp_status);
 335     t0 = float64_div(t0, t1, &env->fp_status);
 336     update_fpscr(env, GETPC());
 337     return t0;
 338 }
 339
 340 float32 helper_float_FT(CPUSH4State *env, uint32_t t0)
 341 {
 342     float32 ret;
 343     set_float_exception_flags(0, &env->fp_status);
 344     ret = int32_to_float32(t0, &env->fp_status);
 345     update_fpscr(env, GETPC());
 346     return ret;
 347 }
 348
 349 float64 helper_float_DT(CPUSH4State *env, uint32_t t0)
 350 {
 351     float64 ret;
 352     set_float_exception_flags(0, &env->fp_status);
 353     ret = int32_to_float64(t0, &env->fp_status);
 354     update_fpscr(env, GETPC());
 355     return ret;
 356 }
 357
 358 float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2)
 359 {
 360     set_float_exception_flags(0, &env->fp_status);
 361     t0 = float32_muladd(t0, t1, t2, 0, &env->fp_status);
 362     update_fpscr(env, GETPC());
 363     return t0;
 364 }
 365
 366 float32 helper_fmul_FT(CPUSH4State *env, float32 t0, float32 t1)
 367 {
 368     set_float_exception_flags(0, &env->fp_status);
 369     t0 = float32_mul(t0, t1, &env->fp_status);
 370     update_fpscr(env, GETPC());
 371     return t0;
 372 }
 373
 374 float64 helper_fmul_DT(CPUSH4State *env, float64 t0, float64 t1)
 375 {
 376     set_float_exception_flags(0, &env->fp_status);
 377     t0 = float64_mul(t0, t1, &env->fp_status);
 378     update_fpscr(env, GETPC());
 379     return t0;
 380 }
 381
 382 float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0)
 383 {
 384     set_float_exception_flags(0, &env->fp_status);
 385     t0 = float32_sqrt(t0, &env->fp_status);
 386     update_fpscr(env, GETPC());
 387     return t0;
 388 }
 389
 390 float64 helper_fsqrt_DT(CPUSH4State *env, float64 t0)
 391 {
 392     set_float_exception_flags(0, &env->fp_status);
 393     t0 = float64_sqrt(t0, &env->fp_status);
 394     update_fpscr(env, GETPC());
 395     return t0;
 396 }
 397
 398 float32 helper_fsrra_FT(CPUSH4State *env, float32 t0)
 399 {
 400     set_float_exception_flags(0, &env->fp_status);
 401     /* "Approximate" 1/sqrt(x) via actual computation.  */
 402     t0 = float32_sqrt(t0, &env->fp_status);
 403     t0 = float32_div(float32_one, t0, &env->fp_status);
 404     /* Since this is supposed to be an approximation, an imprecision
 405        exception is required.  One supposes this also follows the usual
 406        IEEE rule that other exceptions take precidence.  */
 407     if (get_float_exception_flags(&env->fp_status) == 0) {
 408         set_float_exception_flags(float_flag_inexact, &env->fp_status);
 409     }
 410     update_fpscr(env, GETPC());
 411     return t0;
 412 }
 413
 414 float32 helper_fsub_FT(CPUSH4State *env, float32 t0, float32 t1)
 415 {
 416     set_float_exception_flags(0, &env->fp_status);
 417     t0 = float32_sub(t0, t1, &env->fp_status);
 418     update_fpscr(env, GETPC());
 419     return t0;
 420 }
 421
 422 float64 helper_fsub_DT(CPUSH4State *env, float64 t0, float64 t1)
 423 {
 424     set_float_exception_flags(0, &env->fp_status);
 425     t0 = float64_sub(t0, t1, &env->fp_status);
 426     update_fpscr(env, GETPC());
 427     return t0;
 428 }
 429
 430 uint32_t helper_ftrc_FT(CPUSH4State *env, float32 t0)
 431 {
 432     uint32_t ret;
 433     set_float_exception_flags(0, &env->fp_status);
 434     ret = float32_to_int32_round_to_zero(t0, &env->fp_status);
 435     update_fpscr(env, GETPC());
 436     return ret;
 437 }
 438
 439 uint32_t helper_ftrc_DT(CPUSH4State *env, float64 t0)
 440 {
 441     uint32_t ret;
 442     set_float_exception_flags(0, &env->fp_status);
 443     ret = float64_to_int32_round_to_zero(t0, &env->fp_status);
 444     update_fpscr(env, GETPC());
 445     return ret;
 446 }
 447
 448 void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n)
 449 {
 450     int bank, i;
 451     float32 r, p;
 452
 453     bank = (env->sr & FPSCR_FR) ? 16 : 0;
 454     r = float32_zero;
 455     set_float_exception_flags(0, &env->fp_status);
 456
 457     for (i = 0 ; i < 4 ; i++) {
 458         p = float32_mul(env->fregs[bank + m + i],
 459                         env->fregs[bank + n + i],
 460                         &env->fp_status);
 461         r = float32_add(r, p, &env->fp_status);
 462     }
 463     update_fpscr(env, GETPC());
 464
 465     env->fregs[bank + n + 3] = r;
 466 }
 467
 468 void helper_ftrv(CPUSH4State *env, uint32_t n)
 469 {
 470     int bank_matrix, bank_vector;
 471     int i, j;
 472     float32 r[4];
 473     float32 p;
 474
 475     bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16;
 476     bank_vector = (env->sr & FPSCR_FR) ? 16 : 0;
 477     set_float_exception_flags(0, &env->fp_status);
 478     for (i = 0 ; i < 4 ; i++) {
 479         r[i] = float32_zero;
 480         for (j = 0 ; j < 4 ; j++) {
 481             p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
 482                             env->fregs[bank_vector + j],
 483                             &env->fp_status);
 484             r[i] = float32_add(r[i], p, &env->fp_status);
 485         }
 486     }
 487     update_fpscr(env, GETPC());
 488
 489     for (i = 0 ; i < 4 ; i++) {
 490         env->fregs[bank_vector + i] = r[i];
 491     }
 492 }