2 * MIPS SIMD Architecture (MSA) translation routines
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
7 * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
8 * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
9 * Copyright (c) 2020 Philippe Mathieu-Daudé
11 * SPDX-License-Identifier: LGPL-2.1-or-later
13 #include "qemu/osdep.h"
14 #include "tcg/tcg-op.h"
15 #include "exec/helper-gen.h"
16 #include "translate.h"
17 #include "fpu_helper.h"
20 /* Include the auto-generated decoder. */
21 #include "decode-msa32.c.inc"
22 #include "decode-msa64.c.inc"
24 #define OPC_MSA (0x1E << 26)
26 #define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
28 OPC_MSA_I8_00
= 0x00 | OPC_MSA
,
29 OPC_MSA_I8_01
= 0x01 | OPC_MSA
,
30 OPC_MSA_I8_02
= 0x02 | OPC_MSA
,
31 OPC_MSA_I5_06
= 0x06 | OPC_MSA
,
32 OPC_MSA_I5_07
= 0x07 | OPC_MSA
,
33 OPC_MSA_BIT_09
= 0x09 | OPC_MSA
,
34 OPC_MSA_BIT_0A
= 0x0A | OPC_MSA
,
35 OPC_MSA_3R_0D
= 0x0D | OPC_MSA
,
36 OPC_MSA_3R_0E
= 0x0E | OPC_MSA
,
37 OPC_MSA_3R_0F
= 0x0F | OPC_MSA
,
38 OPC_MSA_3R_10
= 0x10 | OPC_MSA
,
39 OPC_MSA_3R_11
= 0x11 | OPC_MSA
,
40 OPC_MSA_3R_12
= 0x12 | OPC_MSA
,
41 OPC_MSA_3R_13
= 0x13 | OPC_MSA
,
42 OPC_MSA_3R_14
= 0x14 | OPC_MSA
,
43 OPC_MSA_3R_15
= 0x15 | OPC_MSA
,
44 OPC_MSA_ELM
= 0x19 | OPC_MSA
,
45 OPC_MSA_3RF_1A
= 0x1A | OPC_MSA
,
46 OPC_MSA_3RF_1B
= 0x1B | OPC_MSA
,
47 OPC_MSA_3RF_1C
= 0x1C | OPC_MSA
,
48 OPC_MSA_VEC
= 0x1E | OPC_MSA
,
50 /* MI10 instruction */
51 OPC_LD_B
= (0x20) | OPC_MSA
,
52 OPC_LD_H
= (0x21) | OPC_MSA
,
53 OPC_LD_W
= (0x22) | OPC_MSA
,
54 OPC_LD_D
= (0x23) | OPC_MSA
,
55 OPC_ST_B
= (0x24) | OPC_MSA
,
56 OPC_ST_H
= (0x25) | OPC_MSA
,
57 OPC_ST_W
= (0x26) | OPC_MSA
,
58 OPC_ST_D
= (0x27) | OPC_MSA
,
62 /* I5 instruction df(bits 22..21) = _b, _h, _w, _d */
63 OPC_ADDVI_df
= (0x0 << 23) | OPC_MSA_I5_06
,
64 OPC_CEQI_df
= (0x0 << 23) | OPC_MSA_I5_07
,
65 OPC_SUBVI_df
= (0x1 << 23) | OPC_MSA_I5_06
,
66 OPC_MAXI_S_df
= (0x2 << 23) | OPC_MSA_I5_06
,
67 OPC_CLTI_S_df
= (0x2 << 23) | OPC_MSA_I5_07
,
68 OPC_MAXI_U_df
= (0x3 << 23) | OPC_MSA_I5_06
,
69 OPC_CLTI_U_df
= (0x3 << 23) | OPC_MSA_I5_07
,
70 OPC_MINI_S_df
= (0x4 << 23) | OPC_MSA_I5_06
,
71 OPC_CLEI_S_df
= (0x4 << 23) | OPC_MSA_I5_07
,
72 OPC_MINI_U_df
= (0x5 << 23) | OPC_MSA_I5_06
,
73 OPC_CLEI_U_df
= (0x5 << 23) | OPC_MSA_I5_07
,
74 OPC_LDI_df
= (0x6 << 23) | OPC_MSA_I5_07
,
77 OPC_ANDI_B
= (0x0 << 24) | OPC_MSA_I8_00
,
78 OPC_BMNZI_B
= (0x0 << 24) | OPC_MSA_I8_01
,
79 OPC_SHF_B
= (0x0 << 24) | OPC_MSA_I8_02
,
80 OPC_ORI_B
= (0x1 << 24) | OPC_MSA_I8_00
,
81 OPC_BMZI_B
= (0x1 << 24) | OPC_MSA_I8_01
,
82 OPC_SHF_H
= (0x1 << 24) | OPC_MSA_I8_02
,
83 OPC_NORI_B
= (0x2 << 24) | OPC_MSA_I8_00
,
84 OPC_BSELI_B
= (0x2 << 24) | OPC_MSA_I8_01
,
85 OPC_SHF_W
= (0x2 << 24) | OPC_MSA_I8_02
,
86 OPC_XORI_B
= (0x3 << 24) | OPC_MSA_I8_00
,
88 /* VEC/2R/2RF instruction */
89 OPC_AND_V
= (0x00 << 21) | OPC_MSA_VEC
,
90 OPC_OR_V
= (0x01 << 21) | OPC_MSA_VEC
,
91 OPC_NOR_V
= (0x02 << 21) | OPC_MSA_VEC
,
92 OPC_XOR_V
= (0x03 << 21) | OPC_MSA_VEC
,
93 OPC_BMNZ_V
= (0x04 << 21) | OPC_MSA_VEC
,
94 OPC_BMZ_V
= (0x05 << 21) | OPC_MSA_VEC
,
95 OPC_BSEL_V
= (0x06 << 21) | OPC_MSA_VEC
,
97 OPC_MSA_2R
= (0x18 << 21) | OPC_MSA_VEC
,
98 OPC_MSA_2RF
= (0x19 << 21) | OPC_MSA_VEC
,
100 /* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
101 OPC_FILL_df
= (0x00 << 18) | OPC_MSA_2R
,
102 OPC_PCNT_df
= (0x01 << 18) | OPC_MSA_2R
,
103 OPC_NLOC_df
= (0x02 << 18) | OPC_MSA_2R
,
104 OPC_NLZC_df
= (0x03 << 18) | OPC_MSA_2R
,
106 /* 2RF instruction df(bit 16) = _w, _d */
107 OPC_FCLASS_df
= (0x00 << 17) | OPC_MSA_2RF
,
108 OPC_FTRUNC_S_df
= (0x01 << 17) | OPC_MSA_2RF
,
109 OPC_FTRUNC_U_df
= (0x02 << 17) | OPC_MSA_2RF
,
110 OPC_FSQRT_df
= (0x03 << 17) | OPC_MSA_2RF
,
111 OPC_FRSQRT_df
= (0x04 << 17) | OPC_MSA_2RF
,
112 OPC_FRCP_df
= (0x05 << 17) | OPC_MSA_2RF
,
113 OPC_FRINT_df
= (0x06 << 17) | OPC_MSA_2RF
,
114 OPC_FLOG2_df
= (0x07 << 17) | OPC_MSA_2RF
,
115 OPC_FEXUPL_df
= (0x08 << 17) | OPC_MSA_2RF
,
116 OPC_FEXUPR_df
= (0x09 << 17) | OPC_MSA_2RF
,
117 OPC_FFQL_df
= (0x0A << 17) | OPC_MSA_2RF
,
118 OPC_FFQR_df
= (0x0B << 17) | OPC_MSA_2RF
,
119 OPC_FTINT_S_df
= (0x0C << 17) | OPC_MSA_2RF
,
120 OPC_FTINT_U_df
= (0x0D << 17) | OPC_MSA_2RF
,
121 OPC_FFINT_S_df
= (0x0E << 17) | OPC_MSA_2RF
,
122 OPC_FFINT_U_df
= (0x0F << 17) | OPC_MSA_2RF
,
124 /* 3R instruction df(bits 22..21) = _b, _h, _w, d */
125 OPC_SLL_df
= (0x0 << 23) | OPC_MSA_3R_0D
,
126 OPC_ADDV_df
= (0x0 << 23) | OPC_MSA_3R_0E
,
127 OPC_CEQ_df
= (0x0 << 23) | OPC_MSA_3R_0F
,
128 OPC_ADD_A_df
= (0x0 << 23) | OPC_MSA_3R_10
,
129 OPC_SUBS_S_df
= (0x0 << 23) | OPC_MSA_3R_11
,
130 OPC_MULV_df
= (0x0 << 23) | OPC_MSA_3R_12
,
131 OPC_DOTP_S_df
= (0x0 << 23) | OPC_MSA_3R_13
,
132 OPC_SLD_df
= (0x0 << 23) | OPC_MSA_3R_14
,
133 OPC_VSHF_df
= (0x0 << 23) | OPC_MSA_3R_15
,
134 OPC_SRA_df
= (0x1 << 23) | OPC_MSA_3R_0D
,
135 OPC_SUBV_df
= (0x1 << 23) | OPC_MSA_3R_0E
,
136 OPC_ADDS_A_df
= (0x1 << 23) | OPC_MSA_3R_10
,
137 OPC_SUBS_U_df
= (0x1 << 23) | OPC_MSA_3R_11
,
138 OPC_MADDV_df
= (0x1 << 23) | OPC_MSA_3R_12
,
139 OPC_DOTP_U_df
= (0x1 << 23) | OPC_MSA_3R_13
,
140 OPC_SPLAT_df
= (0x1 << 23) | OPC_MSA_3R_14
,
141 OPC_SRAR_df
= (0x1 << 23) | OPC_MSA_3R_15
,
142 OPC_SRL_df
= (0x2 << 23) | OPC_MSA_3R_0D
,
143 OPC_MAX_S_df
= (0x2 << 23) | OPC_MSA_3R_0E
,
144 OPC_CLT_S_df
= (0x2 << 23) | OPC_MSA_3R_0F
,
145 OPC_ADDS_S_df
= (0x2 << 23) | OPC_MSA_3R_10
,
146 OPC_SUBSUS_U_df
= (0x2 << 23) | OPC_MSA_3R_11
,
147 OPC_MSUBV_df
= (0x2 << 23) | OPC_MSA_3R_12
,
148 OPC_DPADD_S_df
= (0x2 << 23) | OPC_MSA_3R_13
,
149 OPC_PCKEV_df
= (0x2 << 23) | OPC_MSA_3R_14
,
150 OPC_SRLR_df
= (0x2 << 23) | OPC_MSA_3R_15
,
151 OPC_BCLR_df
= (0x3 << 23) | OPC_MSA_3R_0D
,
152 OPC_MAX_U_df
= (0x3 << 23) | OPC_MSA_3R_0E
,
153 OPC_CLT_U_df
= (0x3 << 23) | OPC_MSA_3R_0F
,
154 OPC_ADDS_U_df
= (0x3 << 23) | OPC_MSA_3R_10
,
155 OPC_SUBSUU_S_df
= (0x3 << 23) | OPC_MSA_3R_11
,
156 OPC_DPADD_U_df
= (0x3 << 23) | OPC_MSA_3R_13
,
157 OPC_PCKOD_df
= (0x3 << 23) | OPC_MSA_3R_14
,
158 OPC_BSET_df
= (0x4 << 23) | OPC_MSA_3R_0D
,
159 OPC_MIN_S_df
= (0x4 << 23) | OPC_MSA_3R_0E
,
160 OPC_CLE_S_df
= (0x4 << 23) | OPC_MSA_3R_0F
,
161 OPC_AVE_S_df
= (0x4 << 23) | OPC_MSA_3R_10
,
162 OPC_ASUB_S_df
= (0x4 << 23) | OPC_MSA_3R_11
,
163 OPC_DIV_S_df
= (0x4 << 23) | OPC_MSA_3R_12
,
164 OPC_DPSUB_S_df
= (0x4 << 23) | OPC_MSA_3R_13
,
165 OPC_ILVL_df
= (0x4 << 23) | OPC_MSA_3R_14
,
166 OPC_HADD_S_df
= (0x4 << 23) | OPC_MSA_3R_15
,
167 OPC_BNEG_df
= (0x5 << 23) | OPC_MSA_3R_0D
,
168 OPC_MIN_U_df
= (0x5 << 23) | OPC_MSA_3R_0E
,
169 OPC_CLE_U_df
= (0x5 << 23) | OPC_MSA_3R_0F
,
170 OPC_AVE_U_df
= (0x5 << 23) | OPC_MSA_3R_10
,
171 OPC_ASUB_U_df
= (0x5 << 23) | OPC_MSA_3R_11
,
172 OPC_DIV_U_df
= (0x5 << 23) | OPC_MSA_3R_12
,
173 OPC_DPSUB_U_df
= (0x5 << 23) | OPC_MSA_3R_13
,
174 OPC_ILVR_df
= (0x5 << 23) | OPC_MSA_3R_14
,
175 OPC_HADD_U_df
= (0x5 << 23) | OPC_MSA_3R_15
,
176 OPC_BINSL_df
= (0x6 << 23) | OPC_MSA_3R_0D
,
177 OPC_MAX_A_df
= (0x6 << 23) | OPC_MSA_3R_0E
,
178 OPC_AVER_S_df
= (0x6 << 23) | OPC_MSA_3R_10
,
179 OPC_MOD_S_df
= (0x6 << 23) | OPC_MSA_3R_12
,
180 OPC_ILVEV_df
= (0x6 << 23) | OPC_MSA_3R_14
,
181 OPC_HSUB_S_df
= (0x6 << 23) | OPC_MSA_3R_15
,
182 OPC_BINSR_df
= (0x7 << 23) | OPC_MSA_3R_0D
,
183 OPC_MIN_A_df
= (0x7 << 23) | OPC_MSA_3R_0E
,
184 OPC_AVER_U_df
= (0x7 << 23) | OPC_MSA_3R_10
,
185 OPC_MOD_U_df
= (0x7 << 23) | OPC_MSA_3R_12
,
186 OPC_ILVOD_df
= (0x7 << 23) | OPC_MSA_3R_14
,
187 OPC_HSUB_U_df
= (0x7 << 23) | OPC_MSA_3R_15
,
189 /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
190 OPC_SLDI_df
= (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM
,
191 OPC_CTCMSA
= (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM
,
192 OPC_SPLATI_df
= (0x1 << 22) | (0x00 << 16) | OPC_MSA_ELM
,
193 OPC_CFCMSA
= (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM
,
194 OPC_COPY_S_df
= (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM
,
195 OPC_MOVE_V
= (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM
,
196 OPC_COPY_U_df
= (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM
,
197 OPC_INSERT_df
= (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM
,
198 OPC_INSVE_df
= (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM
,
200 /* 3RF instruction _df(bit 21) = _w, _d */
201 OPC_FCAF_df
= (0x0 << 22) | OPC_MSA_3RF_1A
,
202 OPC_FADD_df
= (0x0 << 22) | OPC_MSA_3RF_1B
,
203 OPC_FCUN_df
= (0x1 << 22) | OPC_MSA_3RF_1A
,
204 OPC_FSUB_df
= (0x1 << 22) | OPC_MSA_3RF_1B
,
205 OPC_FCOR_df
= (0x1 << 22) | OPC_MSA_3RF_1C
,
206 OPC_FCEQ_df
= (0x2 << 22) | OPC_MSA_3RF_1A
,
207 OPC_FMUL_df
= (0x2 << 22) | OPC_MSA_3RF_1B
,
208 OPC_FCUNE_df
= (0x2 << 22) | OPC_MSA_3RF_1C
,
209 OPC_FCUEQ_df
= (0x3 << 22) | OPC_MSA_3RF_1A
,
210 OPC_FDIV_df
= (0x3 << 22) | OPC_MSA_3RF_1B
,
211 OPC_FCNE_df
= (0x3 << 22) | OPC_MSA_3RF_1C
,
212 OPC_FCLT_df
= (0x4 << 22) | OPC_MSA_3RF_1A
,
213 OPC_FMADD_df
= (0x4 << 22) | OPC_MSA_3RF_1B
,
214 OPC_MUL_Q_df
= (0x4 << 22) | OPC_MSA_3RF_1C
,
215 OPC_FCULT_df
= (0x5 << 22) | OPC_MSA_3RF_1A
,
216 OPC_FMSUB_df
= (0x5 << 22) | OPC_MSA_3RF_1B
,
217 OPC_MADD_Q_df
= (0x5 << 22) | OPC_MSA_3RF_1C
,
218 OPC_FCLE_df
= (0x6 << 22) | OPC_MSA_3RF_1A
,
219 OPC_MSUB_Q_df
= (0x6 << 22) | OPC_MSA_3RF_1C
,
220 OPC_FCULE_df
= (0x7 << 22) | OPC_MSA_3RF_1A
,
221 OPC_FEXP2_df
= (0x7 << 22) | OPC_MSA_3RF_1B
,
222 OPC_FSAF_df
= (0x8 << 22) | OPC_MSA_3RF_1A
,
223 OPC_FEXDO_df
= (0x8 << 22) | OPC_MSA_3RF_1B
,
224 OPC_FSUN_df
= (0x9 << 22) | OPC_MSA_3RF_1A
,
225 OPC_FSOR_df
= (0x9 << 22) | OPC_MSA_3RF_1C
,
226 OPC_FSEQ_df
= (0xA << 22) | OPC_MSA_3RF_1A
,
227 OPC_FTQ_df
= (0xA << 22) | OPC_MSA_3RF_1B
,
228 OPC_FSUNE_df
= (0xA << 22) | OPC_MSA_3RF_1C
,
229 OPC_FSUEQ_df
= (0xB << 22) | OPC_MSA_3RF_1A
,
230 OPC_FSNE_df
= (0xB << 22) | OPC_MSA_3RF_1C
,
231 OPC_FSLT_df
= (0xC << 22) | OPC_MSA_3RF_1A
,
232 OPC_FMIN_df
= (0xC << 22) | OPC_MSA_3RF_1B
,
233 OPC_MULR_Q_df
= (0xC << 22) | OPC_MSA_3RF_1C
,
234 OPC_FSULT_df
= (0xD << 22) | OPC_MSA_3RF_1A
,
235 OPC_FMIN_A_df
= (0xD << 22) | OPC_MSA_3RF_1B
,
236 OPC_MADDR_Q_df
= (0xD << 22) | OPC_MSA_3RF_1C
,
237 OPC_FSLE_df
= (0xE << 22) | OPC_MSA_3RF_1A
,
238 OPC_FMAX_df
= (0xE << 22) | OPC_MSA_3RF_1B
,
239 OPC_MSUBR_Q_df
= (0xE << 22) | OPC_MSA_3RF_1C
,
240 OPC_FSULE_df
= (0xF << 22) | OPC_MSA_3RF_1A
,
241 OPC_FMAX_A_df
= (0xF << 22) | OPC_MSA_3RF_1B
,
243 /* BIT instruction df(bits 22..16) = _B _H _W _D */
244 OPC_SLLI_df
= (0x0 << 23) | OPC_MSA_BIT_09
,
245 OPC_SAT_S_df
= (0x0 << 23) | OPC_MSA_BIT_0A
,
246 OPC_SRAI_df
= (0x1 << 23) | OPC_MSA_BIT_09
,
247 OPC_SAT_U_df
= (0x1 << 23) | OPC_MSA_BIT_0A
,
248 OPC_SRLI_df
= (0x2 << 23) | OPC_MSA_BIT_09
,
249 OPC_SRARI_df
= (0x2 << 23) | OPC_MSA_BIT_0A
,
250 OPC_BCLRI_df
= (0x3 << 23) | OPC_MSA_BIT_09
,
251 OPC_SRLRI_df
= (0x3 << 23) | OPC_MSA_BIT_0A
,
252 OPC_BSETI_df
= (0x4 << 23) | OPC_MSA_BIT_09
,
253 OPC_BNEGI_df
= (0x5 << 23) | OPC_MSA_BIT_09
,
254 OPC_BINSLI_df
= (0x6 << 23) | OPC_MSA_BIT_09
,
255 OPC_BINSRI_df
= (0x7 << 23) | OPC_MSA_BIT_09
,
258 static const char * const msaregnames
[] = {
259 "w0.d0", "w0.d1", "w1.d0", "w1.d1",
260 "w2.d0", "w2.d1", "w3.d0", "w3.d1",
261 "w4.d0", "w4.d1", "w5.d0", "w5.d1",
262 "w6.d0", "w6.d1", "w7.d0", "w7.d1",
263 "w8.d0", "w8.d1", "w9.d0", "w9.d1",
264 "w10.d0", "w10.d1", "w11.d0", "w11.d1",
265 "w12.d0", "w12.d1", "w13.d0", "w13.d1",
266 "w14.d0", "w14.d1", "w15.d0", "w15.d1",
267 "w16.d0", "w16.d1", "w17.d0", "w17.d1",
268 "w18.d0", "w18.d1", "w19.d0", "w19.d1",
269 "w20.d0", "w20.d1", "w21.d0", "w21.d1",
270 "w22.d0", "w22.d1", "w23.d0", "w23.d1",
271 "w24.d0", "w24.d1", "w25.d0", "w25.d1",
272 "w26.d0", "w26.d1", "w27.d0", "w27.d1",
273 "w28.d0", "w28.d1", "w29.d0", "w29.d1",
274 "w30.d0", "w30.d1", "w31.d0", "w31.d1",
277 static TCGv_i64 msa_wr_d
[64];
279 void msa_translate_init(void)
283 for (i
= 0; i
< 32; i
++) {
284 int off
= offsetof(CPUMIPSState
, active_fpu
.fpr
[i
].wr
.d
[0]);
287 * The MSA vector registers are mapped on the
288 * scalar floating-point unit (FPU) registers.
290 msa_wr_d
[i
* 2] = fpu_f64
[i
];
291 off
= offsetof(CPUMIPSState
, active_fpu
.fpr
[i
].wr
.d
[1]);
292 msa_wr_d
[i
* 2 + 1] =
293 tcg_global_mem_new_i64(cpu_env
, off
, msaregnames
[i
* 2 + 1]);
297 static inline int check_msa_access(DisasContext
*ctx
)
299 if (unlikely((ctx
->hflags
& MIPS_HFLAG_FPU
) &&
300 !(ctx
->hflags
& MIPS_HFLAG_F64
))) {
301 gen_reserved_instruction(ctx
);
305 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_MSA
))) {
306 generate_exception_end(ctx
, EXCP_MSADIS
);
312 static void gen_check_zero_element(TCGv tresult
, uint8_t df
, uint8_t wt
,
315 /* generates tcg ops to check if any element is 0 */
316 /* Note this function only works with MSA_WRLEN = 128 */
317 uint64_t eval_zero_or_big
= 0;
318 uint64_t eval_big
= 0;
319 TCGv_i64 t0
= tcg_temp_new_i64();
320 TCGv_i64 t1
= tcg_temp_new_i64();
323 eval_zero_or_big
= 0x0101010101010101ULL
;
324 eval_big
= 0x8080808080808080ULL
;
327 eval_zero_or_big
= 0x0001000100010001ULL
;
328 eval_big
= 0x8000800080008000ULL
;
331 eval_zero_or_big
= 0x0000000100000001ULL
;
332 eval_big
= 0x8000000080000000ULL
;
335 eval_zero_or_big
= 0x0000000000000001ULL
;
336 eval_big
= 0x8000000000000000ULL
;
339 tcg_gen_subi_i64(t0
, msa_wr_d
[wt
<< 1], eval_zero_or_big
);
340 tcg_gen_andc_i64(t0
, t0
, msa_wr_d
[wt
<< 1]);
341 tcg_gen_andi_i64(t0
, t0
, eval_big
);
342 tcg_gen_subi_i64(t1
, msa_wr_d
[(wt
<< 1) + 1], eval_zero_or_big
);
343 tcg_gen_andc_i64(t1
, t1
, msa_wr_d
[(wt
<< 1) + 1]);
344 tcg_gen_andi_i64(t1
, t1
, eval_big
);
345 tcg_gen_or_i64(t0
, t0
, t1
);
346 /* if all bits are zero then all elements are not zero */
347 /* if some bit is non-zero then some element is zero */
348 tcg_gen_setcondi_i64(cond
, t0
, t0
, 0);
349 tcg_gen_trunc_i64_tl(tresult
, t0
);
350 tcg_temp_free_i64(t0
);
351 tcg_temp_free_i64(t1
);
354 static bool gen_msa_BxZ_V(DisasContext
*ctx
, int wt
, int s16
, TCGCond cond
)
358 check_msa_access(ctx
);
360 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
361 gen_reserved_instruction(ctx
);
364 t0
= tcg_temp_new_i64();
365 tcg_gen_or_i64(t0
, msa_wr_d
[wt
<< 1], msa_wr_d
[(wt
<< 1) + 1]);
366 tcg_gen_setcondi_i64(cond
, t0
, t0
, 0);
367 tcg_gen_trunc_i64_tl(bcond
, t0
);
368 tcg_temp_free_i64(t0
);
370 ctx
->btarget
= ctx
->base
.pc_next
+ (s16
<< 2) + 4;
372 ctx
->hflags
|= MIPS_HFLAG_BC
;
373 ctx
->hflags
|= MIPS_HFLAG_BDS32
;
378 static bool trans_BZ_V(DisasContext
*ctx
, arg_msa_bz
*a
)
380 return gen_msa_BxZ_V(ctx
, a
->wt
, a
->s16
, TCG_COND_EQ
);
383 static bool trans_BNZ_V(DisasContext
*ctx
, arg_msa_bz
*a
)
385 return gen_msa_BxZ_V(ctx
, a
->wt
, a
->s16
, TCG_COND_NE
);
388 static bool gen_msa_BxZ(DisasContext
*ctx
, int df
, int wt
, int s16
, bool if_not
)
390 check_msa_access(ctx
);
392 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
393 gen_reserved_instruction(ctx
);
397 gen_check_zero_element(bcond
, df
, wt
, if_not
? TCG_COND_EQ
: TCG_COND_NE
);
399 ctx
->btarget
= ctx
->base
.pc_next
+ (s16
<< 2) + 4;
400 ctx
->hflags
|= MIPS_HFLAG_BC
;
401 ctx
->hflags
|= MIPS_HFLAG_BDS32
;
406 static bool trans_BZ_x(DisasContext
*ctx
, arg_msa_bz
*a
)
408 return gen_msa_BxZ(ctx
, a
->df
, a
->wt
, a
->s16
, false);
411 static bool trans_BNZ_x(DisasContext
*ctx
, arg_msa_bz
*a
)
413 return gen_msa_BxZ(ctx
, a
->df
, a
->wt
, a
->s16
, true);
416 static void gen_msa_i8(DisasContext
*ctx
)
418 #define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24)))
419 uint8_t i8
= (ctx
->opcode
>> 16) & 0xff;
420 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
421 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
423 TCGv_i32 twd
= tcg_const_i32(wd
);
424 TCGv_i32 tws
= tcg_const_i32(ws
);
425 TCGv_i32 ti8
= tcg_const_i32(i8
);
427 switch (MASK_MSA_I8(ctx
->opcode
)) {
429 gen_helper_msa_andi_b(cpu_env
, twd
, tws
, ti8
);
432 gen_helper_msa_ori_b(cpu_env
, twd
, tws
, ti8
);
435 gen_helper_msa_nori_b(cpu_env
, twd
, tws
, ti8
);
438 gen_helper_msa_xori_b(cpu_env
, twd
, tws
, ti8
);
441 gen_helper_msa_bmnzi_b(cpu_env
, twd
, tws
, ti8
);
444 gen_helper_msa_bmzi_b(cpu_env
, twd
, tws
, ti8
);
447 gen_helper_msa_bseli_b(cpu_env
, twd
, tws
, ti8
);
453 uint8_t df
= (ctx
->opcode
>> 24) & 0x3;
454 if (df
== DF_DOUBLE
) {
455 gen_reserved_instruction(ctx
);
457 TCGv_i32 tdf
= tcg_const_i32(df
);
458 gen_helper_msa_shf_df(cpu_env
, tdf
, twd
, tws
, ti8
);
459 tcg_temp_free_i32(tdf
);
464 MIPS_INVAL("MSA instruction");
465 gen_reserved_instruction(ctx
);
469 tcg_temp_free_i32(twd
);
470 tcg_temp_free_i32(tws
);
471 tcg_temp_free_i32(ti8
);
474 static void gen_msa_i5(DisasContext
*ctx
)
476 #define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
477 uint8_t df
= (ctx
->opcode
>> 21) & 0x3;
478 int8_t s5
= (int8_t) sextract32(ctx
->opcode
, 16, 5);
479 uint8_t u5
= (ctx
->opcode
>> 16) & 0x1f;
480 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
481 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
483 TCGv_i32 tdf
= tcg_const_i32(df
);
484 TCGv_i32 twd
= tcg_const_i32(wd
);
485 TCGv_i32 tws
= tcg_const_i32(ws
);
486 TCGv_i32 timm
= tcg_temp_new_i32();
487 tcg_gen_movi_i32(timm
, u5
);
489 switch (MASK_MSA_I5(ctx
->opcode
)) {
491 gen_helper_msa_addvi_df(cpu_env
, tdf
, twd
, tws
, timm
);
494 gen_helper_msa_subvi_df(cpu_env
, tdf
, twd
, tws
, timm
);
497 tcg_gen_movi_i32(timm
, s5
);
498 gen_helper_msa_maxi_s_df(cpu_env
, tdf
, twd
, tws
, timm
);
501 gen_helper_msa_maxi_u_df(cpu_env
, tdf
, twd
, tws
, timm
);
504 tcg_gen_movi_i32(timm
, s5
);
505 gen_helper_msa_mini_s_df(cpu_env
, tdf
, twd
, tws
, timm
);
508 gen_helper_msa_mini_u_df(cpu_env
, tdf
, twd
, tws
, timm
);
511 tcg_gen_movi_i32(timm
, s5
);
512 gen_helper_msa_ceqi_df(cpu_env
, tdf
, twd
, tws
, timm
);
515 tcg_gen_movi_i32(timm
, s5
);
516 gen_helper_msa_clti_s_df(cpu_env
, tdf
, twd
, tws
, timm
);
519 gen_helper_msa_clti_u_df(cpu_env
, tdf
, twd
, tws
, timm
);
522 tcg_gen_movi_i32(timm
, s5
);
523 gen_helper_msa_clei_s_df(cpu_env
, tdf
, twd
, tws
, timm
);
526 gen_helper_msa_clei_u_df(cpu_env
, tdf
, twd
, tws
, timm
);
530 int32_t s10
= sextract32(ctx
->opcode
, 11, 10);
531 tcg_gen_movi_i32(timm
, s10
);
532 gen_helper_msa_ldi_df(cpu_env
, tdf
, twd
, timm
);
536 MIPS_INVAL("MSA instruction");
537 gen_reserved_instruction(ctx
);
541 tcg_temp_free_i32(tdf
);
542 tcg_temp_free_i32(twd
);
543 tcg_temp_free_i32(tws
);
544 tcg_temp_free_i32(timm
);
547 static void gen_msa_bit(DisasContext
*ctx
)
549 #define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
550 uint8_t dfm
= (ctx
->opcode
>> 16) & 0x7f;
551 uint32_t df
= 0, m
= 0;
552 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
553 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
560 if ((dfm
& 0x40) == 0x00) {
563 } else if ((dfm
& 0x60) == 0x40) {
566 } else if ((dfm
& 0x70) == 0x60) {
569 } else if ((dfm
& 0x78) == 0x70) {
573 gen_reserved_instruction(ctx
);
577 tdf
= tcg_const_i32(df
);
578 tm
= tcg_const_i32(m
);
579 twd
= tcg_const_i32(wd
);
580 tws
= tcg_const_i32(ws
);
582 switch (MASK_MSA_BIT(ctx
->opcode
)) {
584 gen_helper_msa_slli_df(cpu_env
, tdf
, twd
, tws
, tm
);
587 gen_helper_msa_srai_df(cpu_env
, tdf
, twd
, tws
, tm
);
590 gen_helper_msa_srli_df(cpu_env
, tdf
, twd
, tws
, tm
);
593 gen_helper_msa_bclri_df(cpu_env
, tdf
, twd
, tws
, tm
);
596 gen_helper_msa_bseti_df(cpu_env
, tdf
, twd
, tws
, tm
);
599 gen_helper_msa_bnegi_df(cpu_env
, tdf
, twd
, tws
, tm
);
602 gen_helper_msa_binsli_df(cpu_env
, tdf
, twd
, tws
, tm
);
605 gen_helper_msa_binsri_df(cpu_env
, tdf
, twd
, tws
, tm
);
608 gen_helper_msa_sat_s_df(cpu_env
, tdf
, twd
, tws
, tm
);
611 gen_helper_msa_sat_u_df(cpu_env
, tdf
, twd
, tws
, tm
);
614 gen_helper_msa_srari_df(cpu_env
, tdf
, twd
, tws
, tm
);
617 gen_helper_msa_srlri_df(cpu_env
, tdf
, twd
, tws
, tm
);
620 MIPS_INVAL("MSA instruction");
621 gen_reserved_instruction(ctx
);
625 tcg_temp_free_i32(tdf
);
626 tcg_temp_free_i32(tm
);
627 tcg_temp_free_i32(twd
);
628 tcg_temp_free_i32(tws
);
631 static void gen_msa_3r(DisasContext
*ctx
)
633 #define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
634 uint8_t df
= (ctx
->opcode
>> 21) & 0x3;
635 uint8_t wt
= (ctx
->opcode
>> 16) & 0x1f;
636 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
637 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
639 TCGv_i32 tdf
= tcg_const_i32(df
);
640 TCGv_i32 twd
= tcg_const_i32(wd
);
641 TCGv_i32 tws
= tcg_const_i32(ws
);
642 TCGv_i32 twt
= tcg_const_i32(wt
);
644 switch (MASK_MSA_3R(ctx
->opcode
)) {
648 gen_helper_msa_binsl_b(cpu_env
, twd
, tws
, twt
);
651 gen_helper_msa_binsl_h(cpu_env
, twd
, tws
, twt
);
654 gen_helper_msa_binsl_w(cpu_env
, twd
, tws
, twt
);
657 gen_helper_msa_binsl_d(cpu_env
, twd
, tws
, twt
);
664 gen_helper_msa_binsr_b(cpu_env
, twd
, tws
, twt
);
667 gen_helper_msa_binsr_h(cpu_env
, twd
, tws
, twt
);
670 gen_helper_msa_binsr_w(cpu_env
, twd
, tws
, twt
);
673 gen_helper_msa_binsr_d(cpu_env
, twd
, tws
, twt
);
680 gen_helper_msa_bclr_b(cpu_env
, twd
, tws
, twt
);
683 gen_helper_msa_bclr_h(cpu_env
, twd
, tws
, twt
);
686 gen_helper_msa_bclr_w(cpu_env
, twd
, tws
, twt
);
689 gen_helper_msa_bclr_d(cpu_env
, twd
, tws
, twt
);
696 gen_helper_msa_bneg_b(cpu_env
, twd
, tws
, twt
);
699 gen_helper_msa_bneg_h(cpu_env
, twd
, tws
, twt
);
702 gen_helper_msa_bneg_w(cpu_env
, twd
, tws
, twt
);
705 gen_helper_msa_bneg_d(cpu_env
, twd
, tws
, twt
);
712 gen_helper_msa_bset_b(cpu_env
, twd
, tws
, twt
);
715 gen_helper_msa_bset_h(cpu_env
, twd
, tws
, twt
);
718 gen_helper_msa_bset_w(cpu_env
, twd
, tws
, twt
);
721 gen_helper_msa_bset_d(cpu_env
, twd
, tws
, twt
);
728 gen_helper_msa_add_a_b(cpu_env
, twd
, tws
, twt
);
731 gen_helper_msa_add_a_h(cpu_env
, twd
, tws
, twt
);
734 gen_helper_msa_add_a_w(cpu_env
, twd
, tws
, twt
);
737 gen_helper_msa_add_a_d(cpu_env
, twd
, tws
, twt
);
744 gen_helper_msa_adds_a_b(cpu_env
, twd
, tws
, twt
);
747 gen_helper_msa_adds_a_h(cpu_env
, twd
, tws
, twt
);
750 gen_helper_msa_adds_a_w(cpu_env
, twd
, tws
, twt
);
753 gen_helper_msa_adds_a_d(cpu_env
, twd
, tws
, twt
);
760 gen_helper_msa_adds_s_b(cpu_env
, twd
, tws
, twt
);
763 gen_helper_msa_adds_s_h(cpu_env
, twd
, tws
, twt
);
766 gen_helper_msa_adds_s_w(cpu_env
, twd
, tws
, twt
);
769 gen_helper_msa_adds_s_d(cpu_env
, twd
, tws
, twt
);
776 gen_helper_msa_adds_u_b(cpu_env
, twd
, tws
, twt
);
779 gen_helper_msa_adds_u_h(cpu_env
, twd
, tws
, twt
);
782 gen_helper_msa_adds_u_w(cpu_env
, twd
, tws
, twt
);
785 gen_helper_msa_adds_u_d(cpu_env
, twd
, tws
, twt
);
792 gen_helper_msa_addv_b(cpu_env
, twd
, tws
, twt
);
795 gen_helper_msa_addv_h(cpu_env
, twd
, tws
, twt
);
798 gen_helper_msa_addv_w(cpu_env
, twd
, tws
, twt
);
801 gen_helper_msa_addv_d(cpu_env
, twd
, tws
, twt
);
808 gen_helper_msa_ave_s_b(cpu_env
, twd
, tws
, twt
);
811 gen_helper_msa_ave_s_h(cpu_env
, twd
, tws
, twt
);
814 gen_helper_msa_ave_s_w(cpu_env
, twd
, tws
, twt
);
817 gen_helper_msa_ave_s_d(cpu_env
, twd
, tws
, twt
);
824 gen_helper_msa_ave_u_b(cpu_env
, twd
, tws
, twt
);
827 gen_helper_msa_ave_u_h(cpu_env
, twd
, tws
, twt
);
830 gen_helper_msa_ave_u_w(cpu_env
, twd
, tws
, twt
);
833 gen_helper_msa_ave_u_d(cpu_env
, twd
, tws
, twt
);
840 gen_helper_msa_aver_s_b(cpu_env
, twd
, tws
, twt
);
843 gen_helper_msa_aver_s_h(cpu_env
, twd
, tws
, twt
);
846 gen_helper_msa_aver_s_w(cpu_env
, twd
, tws
, twt
);
849 gen_helper_msa_aver_s_d(cpu_env
, twd
, tws
, twt
);
856 gen_helper_msa_aver_u_b(cpu_env
, twd
, tws
, twt
);
859 gen_helper_msa_aver_u_h(cpu_env
, twd
, tws
, twt
);
862 gen_helper_msa_aver_u_w(cpu_env
, twd
, tws
, twt
);
865 gen_helper_msa_aver_u_d(cpu_env
, twd
, tws
, twt
);
872 gen_helper_msa_ceq_b(cpu_env
, twd
, tws
, twt
);
875 gen_helper_msa_ceq_h(cpu_env
, twd
, tws
, twt
);
878 gen_helper_msa_ceq_w(cpu_env
, twd
, tws
, twt
);
881 gen_helper_msa_ceq_d(cpu_env
, twd
, tws
, twt
);
888 gen_helper_msa_cle_s_b(cpu_env
, twd
, tws
, twt
);
891 gen_helper_msa_cle_s_h(cpu_env
, twd
, tws
, twt
);
894 gen_helper_msa_cle_s_w(cpu_env
, twd
, tws
, twt
);
897 gen_helper_msa_cle_s_d(cpu_env
, twd
, tws
, twt
);
904 gen_helper_msa_cle_u_b(cpu_env
, twd
, tws
, twt
);
907 gen_helper_msa_cle_u_h(cpu_env
, twd
, tws
, twt
);
910 gen_helper_msa_cle_u_w(cpu_env
, twd
, tws
, twt
);
913 gen_helper_msa_cle_u_d(cpu_env
, twd
, tws
, twt
);
920 gen_helper_msa_clt_s_b(cpu_env
, twd
, tws
, twt
);
923 gen_helper_msa_clt_s_h(cpu_env
, twd
, tws
, twt
);
926 gen_helper_msa_clt_s_w(cpu_env
, twd
, tws
, twt
);
929 gen_helper_msa_clt_s_d(cpu_env
, twd
, tws
, twt
);
936 gen_helper_msa_clt_u_b(cpu_env
, twd
, tws
, twt
);
939 gen_helper_msa_clt_u_h(cpu_env
, twd
, tws
, twt
);
942 gen_helper_msa_clt_u_w(cpu_env
, twd
, tws
, twt
);
945 gen_helper_msa_clt_u_d(cpu_env
, twd
, tws
, twt
);
952 gen_helper_msa_div_s_b(cpu_env
, twd
, tws
, twt
);
955 gen_helper_msa_div_s_h(cpu_env
, twd
, tws
, twt
);
958 gen_helper_msa_div_s_w(cpu_env
, twd
, tws
, twt
);
961 gen_helper_msa_div_s_d(cpu_env
, twd
, tws
, twt
);
968 gen_helper_msa_div_u_b(cpu_env
, twd
, tws
, twt
);
971 gen_helper_msa_div_u_h(cpu_env
, twd
, tws
, twt
);
974 gen_helper_msa_div_u_w(cpu_env
, twd
, tws
, twt
);
977 gen_helper_msa_div_u_d(cpu_env
, twd
, tws
, twt
);
984 gen_helper_msa_max_a_b(cpu_env
, twd
, tws
, twt
);
987 gen_helper_msa_max_a_h(cpu_env
, twd
, tws
, twt
);
990 gen_helper_msa_max_a_w(cpu_env
, twd
, tws
, twt
);
993 gen_helper_msa_max_a_d(cpu_env
, twd
, tws
, twt
);
1000 gen_helper_msa_max_s_b(cpu_env
, twd
, tws
, twt
);
1003 gen_helper_msa_max_s_h(cpu_env
, twd
, tws
, twt
);
1006 gen_helper_msa_max_s_w(cpu_env
, twd
, tws
, twt
);
1009 gen_helper_msa_max_s_d(cpu_env
, twd
, tws
, twt
);
1016 gen_helper_msa_max_u_b(cpu_env
, twd
, tws
, twt
);
1019 gen_helper_msa_max_u_h(cpu_env
, twd
, tws
, twt
);
1022 gen_helper_msa_max_u_w(cpu_env
, twd
, tws
, twt
);
1025 gen_helper_msa_max_u_d(cpu_env
, twd
, tws
, twt
);
1032 gen_helper_msa_min_a_b(cpu_env
, twd
, tws
, twt
);
1035 gen_helper_msa_min_a_h(cpu_env
, twd
, tws
, twt
);
1038 gen_helper_msa_min_a_w(cpu_env
, twd
, tws
, twt
);
1041 gen_helper_msa_min_a_d(cpu_env
, twd
, tws
, twt
);
1048 gen_helper_msa_min_s_b(cpu_env
, twd
, tws
, twt
);
1051 gen_helper_msa_min_s_h(cpu_env
, twd
, tws
, twt
);
1054 gen_helper_msa_min_s_w(cpu_env
, twd
, tws
, twt
);
1057 gen_helper_msa_min_s_d(cpu_env
, twd
, tws
, twt
);
1064 gen_helper_msa_min_u_b(cpu_env
, twd
, tws
, twt
);
1067 gen_helper_msa_min_u_h(cpu_env
, twd
, tws
, twt
);
1070 gen_helper_msa_min_u_w(cpu_env
, twd
, tws
, twt
);
1073 gen_helper_msa_min_u_d(cpu_env
, twd
, tws
, twt
);
1080 gen_helper_msa_mod_s_b(cpu_env
, twd
, tws
, twt
);
1083 gen_helper_msa_mod_s_h(cpu_env
, twd
, tws
, twt
);
1086 gen_helper_msa_mod_s_w(cpu_env
, twd
, tws
, twt
);
1089 gen_helper_msa_mod_s_d(cpu_env
, twd
, tws
, twt
);
1096 gen_helper_msa_mod_u_b(cpu_env
, twd
, tws
, twt
);
1099 gen_helper_msa_mod_u_h(cpu_env
, twd
, tws
, twt
);
1102 gen_helper_msa_mod_u_w(cpu_env
, twd
, tws
, twt
);
1105 gen_helper_msa_mod_u_d(cpu_env
, twd
, tws
, twt
);
1112 gen_helper_msa_maddv_b(cpu_env
, twd
, tws
, twt
);
1115 gen_helper_msa_maddv_h(cpu_env
, twd
, tws
, twt
);
1118 gen_helper_msa_maddv_w(cpu_env
, twd
, tws
, twt
);
1121 gen_helper_msa_maddv_d(cpu_env
, twd
, tws
, twt
);
1128 gen_helper_msa_msubv_b(cpu_env
, twd
, tws
, twt
);
1131 gen_helper_msa_msubv_h(cpu_env
, twd
, tws
, twt
);
1134 gen_helper_msa_msubv_w(cpu_env
, twd
, tws
, twt
);
1137 gen_helper_msa_msubv_d(cpu_env
, twd
, tws
, twt
);
1144 gen_helper_msa_asub_s_b(cpu_env
, twd
, tws
, twt
);
1147 gen_helper_msa_asub_s_h(cpu_env
, twd
, tws
, twt
);
1150 gen_helper_msa_asub_s_w(cpu_env
, twd
, tws
, twt
);
1153 gen_helper_msa_asub_s_d(cpu_env
, twd
, tws
, twt
);
1160 gen_helper_msa_asub_u_b(cpu_env
, twd
, tws
, twt
);
1163 gen_helper_msa_asub_u_h(cpu_env
, twd
, tws
, twt
);
1166 gen_helper_msa_asub_u_w(cpu_env
, twd
, tws
, twt
);
1169 gen_helper_msa_asub_u_d(cpu_env
, twd
, tws
, twt
);
1176 gen_helper_msa_ilvev_b(cpu_env
, twd
, tws
, twt
);
1179 gen_helper_msa_ilvev_h(cpu_env
, twd
, tws
, twt
);
1182 gen_helper_msa_ilvev_w(cpu_env
, twd
, tws
, twt
);
1185 gen_helper_msa_ilvev_d(cpu_env
, twd
, tws
, twt
);
1192 gen_helper_msa_ilvod_b(cpu_env
, twd
, tws
, twt
);
1195 gen_helper_msa_ilvod_h(cpu_env
, twd
, tws
, twt
);
1198 gen_helper_msa_ilvod_w(cpu_env
, twd
, tws
, twt
);
1201 gen_helper_msa_ilvod_d(cpu_env
, twd
, tws
, twt
);
1208 gen_helper_msa_ilvl_b(cpu_env
, twd
, tws
, twt
);
1211 gen_helper_msa_ilvl_h(cpu_env
, twd
, tws
, twt
);
1214 gen_helper_msa_ilvl_w(cpu_env
, twd
, tws
, twt
);
1217 gen_helper_msa_ilvl_d(cpu_env
, twd
, tws
, twt
);
1224 gen_helper_msa_ilvr_b(cpu_env
, twd
, tws
, twt
);
1227 gen_helper_msa_ilvr_h(cpu_env
, twd
, tws
, twt
);
1230 gen_helper_msa_ilvr_w(cpu_env
, twd
, tws
, twt
);
1233 gen_helper_msa_ilvr_d(cpu_env
, twd
, tws
, twt
);
1240 gen_helper_msa_pckev_b(cpu_env
, twd
, tws
, twt
);
1243 gen_helper_msa_pckev_h(cpu_env
, twd
, tws
, twt
);
1246 gen_helper_msa_pckev_w(cpu_env
, twd
, tws
, twt
);
1249 gen_helper_msa_pckev_d(cpu_env
, twd
, tws
, twt
);
1256 gen_helper_msa_pckod_b(cpu_env
, twd
, tws
, twt
);
1259 gen_helper_msa_pckod_h(cpu_env
, twd
, tws
, twt
);
1262 gen_helper_msa_pckod_w(cpu_env
, twd
, tws
, twt
);
1265 gen_helper_msa_pckod_d(cpu_env
, twd
, tws
, twt
);
1272 gen_helper_msa_sll_b(cpu_env
, twd
, tws
, twt
);
1275 gen_helper_msa_sll_h(cpu_env
, twd
, tws
, twt
);
1278 gen_helper_msa_sll_w(cpu_env
, twd
, tws
, twt
);
1281 gen_helper_msa_sll_d(cpu_env
, twd
, tws
, twt
);
1288 gen_helper_msa_sra_b(cpu_env
, twd
, tws
, twt
);
1291 gen_helper_msa_sra_h(cpu_env
, twd
, tws
, twt
);
1294 gen_helper_msa_sra_w(cpu_env
, twd
, tws
, twt
);
1297 gen_helper_msa_sra_d(cpu_env
, twd
, tws
, twt
);
1304 gen_helper_msa_srar_b(cpu_env
, twd
, tws
, twt
);
1307 gen_helper_msa_srar_h(cpu_env
, twd
, tws
, twt
);
1310 gen_helper_msa_srar_w(cpu_env
, twd
, tws
, twt
);
1313 gen_helper_msa_srar_d(cpu_env
, twd
, tws
, twt
);
1320 gen_helper_msa_srl_b(cpu_env
, twd
, tws
, twt
);
1323 gen_helper_msa_srl_h(cpu_env
, twd
, tws
, twt
);
1326 gen_helper_msa_srl_w(cpu_env
, twd
, tws
, twt
);
1329 gen_helper_msa_srl_d(cpu_env
, twd
, tws
, twt
);
1336 gen_helper_msa_srlr_b(cpu_env
, twd
, tws
, twt
);
1339 gen_helper_msa_srlr_h(cpu_env
, twd
, tws
, twt
);
1342 gen_helper_msa_srlr_w(cpu_env
, twd
, tws
, twt
);
1345 gen_helper_msa_srlr_d(cpu_env
, twd
, tws
, twt
);
1352 gen_helper_msa_subs_s_b(cpu_env
, twd
, tws
, twt
);
1355 gen_helper_msa_subs_s_h(cpu_env
, twd
, tws
, twt
);
1358 gen_helper_msa_subs_s_w(cpu_env
, twd
, tws
, twt
);
1361 gen_helper_msa_subs_s_d(cpu_env
, twd
, tws
, twt
);
1368 gen_helper_msa_mulv_b(cpu_env
, twd
, tws
, twt
);
1371 gen_helper_msa_mulv_h(cpu_env
, twd
, tws
, twt
);
1374 gen_helper_msa_mulv_w(cpu_env
, twd
, tws
, twt
);
1377 gen_helper_msa_mulv_d(cpu_env
, twd
, tws
, twt
);
1382 gen_helper_msa_sld_df(cpu_env
, tdf
, twd
, tws
, twt
);
1385 gen_helper_msa_vshf_df(cpu_env
, tdf
, twd
, tws
, twt
);
1390 gen_helper_msa_subv_b(cpu_env
, twd
, tws
, twt
);
1393 gen_helper_msa_subv_h(cpu_env
, twd
, tws
, twt
);
1396 gen_helper_msa_subv_w(cpu_env
, twd
, tws
, twt
);
1399 gen_helper_msa_subv_d(cpu_env
, twd
, tws
, twt
);
1406 gen_helper_msa_subs_u_b(cpu_env
, twd
, tws
, twt
);
1409 gen_helper_msa_subs_u_h(cpu_env
, twd
, tws
, twt
);
1412 gen_helper_msa_subs_u_w(cpu_env
, twd
, tws
, twt
);
1415 gen_helper_msa_subs_u_d(cpu_env
, twd
, tws
, twt
);
1420 gen_helper_msa_splat_df(cpu_env
, tdf
, twd
, tws
, twt
);
1422 case OPC_SUBSUS_U_df
:
1425 gen_helper_msa_subsus_u_b(cpu_env
, twd
, tws
, twt
);
1428 gen_helper_msa_subsus_u_h(cpu_env
, twd
, tws
, twt
);
1431 gen_helper_msa_subsus_u_w(cpu_env
, twd
, tws
, twt
);
1434 gen_helper_msa_subsus_u_d(cpu_env
, twd
, tws
, twt
);
1438 case OPC_SUBSUU_S_df
:
1441 gen_helper_msa_subsuu_s_b(cpu_env
, twd
, tws
, twt
);
1444 gen_helper_msa_subsuu_s_h(cpu_env
, twd
, tws
, twt
);
1447 gen_helper_msa_subsuu_s_w(cpu_env
, twd
, tws
, twt
);
1450 gen_helper_msa_subsuu_s_d(cpu_env
, twd
, tws
, twt
);
1457 case OPC_DPADD_S_df
:
1458 case OPC_DPADD_U_df
:
1459 case OPC_DPSUB_S_df
:
1461 case OPC_DPSUB_U_df
:
1465 if (df
== DF_BYTE
) {
1466 gen_reserved_instruction(ctx
);
1469 switch (MASK_MSA_3R(ctx
->opcode
)) {
1473 gen_helper_msa_hadd_s_h(cpu_env
, twd
, tws
, twt
);
1476 gen_helper_msa_hadd_s_w(cpu_env
, twd
, tws
, twt
);
1479 gen_helper_msa_hadd_s_d(cpu_env
, twd
, tws
, twt
);
1486 gen_helper_msa_hadd_u_h(cpu_env
, twd
, tws
, twt
);
1489 gen_helper_msa_hadd_u_w(cpu_env
, twd
, tws
, twt
);
1492 gen_helper_msa_hadd_u_d(cpu_env
, twd
, tws
, twt
);
1499 gen_helper_msa_hsub_s_h(cpu_env
, twd
, tws
, twt
);
1502 gen_helper_msa_hsub_s_w(cpu_env
, twd
, tws
, twt
);
1505 gen_helper_msa_hsub_s_d(cpu_env
, twd
, tws
, twt
);
1512 gen_helper_msa_hsub_u_h(cpu_env
, twd
, tws
, twt
);
1515 gen_helper_msa_hsub_u_w(cpu_env
, twd
, tws
, twt
);
1518 gen_helper_msa_hsub_u_d(cpu_env
, twd
, tws
, twt
);
1525 gen_helper_msa_dotp_s_h(cpu_env
, twd
, tws
, twt
);
1528 gen_helper_msa_dotp_s_w(cpu_env
, twd
, tws
, twt
);
1531 gen_helper_msa_dotp_s_d(cpu_env
, twd
, tws
, twt
);
1538 gen_helper_msa_dotp_u_h(cpu_env
, twd
, tws
, twt
);
1541 gen_helper_msa_dotp_u_w(cpu_env
, twd
, tws
, twt
);
1544 gen_helper_msa_dotp_u_d(cpu_env
, twd
, tws
, twt
);
1548 case OPC_DPADD_S_df
:
1551 gen_helper_msa_dpadd_s_h(cpu_env
, twd
, tws
, twt
);
1554 gen_helper_msa_dpadd_s_w(cpu_env
, twd
, tws
, twt
);
1557 gen_helper_msa_dpadd_s_d(cpu_env
, twd
, tws
, twt
);
1561 case OPC_DPADD_U_df
:
1564 gen_helper_msa_dpadd_u_h(cpu_env
, twd
, tws
, twt
);
1567 gen_helper_msa_dpadd_u_w(cpu_env
, twd
, tws
, twt
);
1570 gen_helper_msa_dpadd_u_d(cpu_env
, twd
, tws
, twt
);
1574 case OPC_DPSUB_S_df
:
1577 gen_helper_msa_dpsub_s_h(cpu_env
, twd
, tws
, twt
);
1580 gen_helper_msa_dpsub_s_w(cpu_env
, twd
, tws
, twt
);
1583 gen_helper_msa_dpsub_s_d(cpu_env
, twd
, tws
, twt
);
1587 case OPC_DPSUB_U_df
:
1590 gen_helper_msa_dpsub_u_h(cpu_env
, twd
, tws
, twt
);
1593 gen_helper_msa_dpsub_u_w(cpu_env
, twd
, tws
, twt
);
1596 gen_helper_msa_dpsub_u_d(cpu_env
, twd
, tws
, twt
);
1603 MIPS_INVAL("MSA instruction");
1604 gen_reserved_instruction(ctx
);
1607 tcg_temp_free_i32(twd
);
1608 tcg_temp_free_i32(tws
);
1609 tcg_temp_free_i32(twt
);
1610 tcg_temp_free_i32(tdf
);
1613 static void gen_msa_elm_3e(DisasContext
*ctx
)
1615 #define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16)))
1616 uint8_t source
= (ctx
->opcode
>> 11) & 0x1f;
1617 uint8_t dest
= (ctx
->opcode
>> 6) & 0x1f;
1618 TCGv telm
= tcg_temp_new();
1619 TCGv_i32 tsr
= tcg_const_i32(source
);
1620 TCGv_i32 tdt
= tcg_const_i32(dest
);
1622 switch (MASK_MSA_ELM_DF3E(ctx
->opcode
)) {
1624 gen_load_gpr(telm
, source
);
1625 gen_helper_msa_ctcmsa(cpu_env
, telm
, tdt
);
1628 gen_helper_msa_cfcmsa(telm
, cpu_env
, tsr
);
1629 gen_store_gpr(telm
, dest
);
1632 gen_helper_msa_move_v(cpu_env
, tdt
, tsr
);
1635 MIPS_INVAL("MSA instruction");
1636 gen_reserved_instruction(ctx
);
1640 tcg_temp_free(telm
);
1641 tcg_temp_free_i32(tdt
);
1642 tcg_temp_free_i32(tsr
);
1645 static void gen_msa_elm_df(DisasContext
*ctx
, uint32_t df
, uint32_t n
)
1647 #define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
1648 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
1649 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
1651 TCGv_i32 tws
= tcg_const_i32(ws
);
1652 TCGv_i32 twd
= tcg_const_i32(wd
);
1653 TCGv_i32 tn
= tcg_const_i32(n
);
1654 TCGv_i32 tdf
= tcg_const_i32(df
);
1656 switch (MASK_MSA_ELM(ctx
->opcode
)) {
1658 gen_helper_msa_sldi_df(cpu_env
, tdf
, twd
, tws
, tn
);
1661 gen_helper_msa_splati_df(cpu_env
, tdf
, twd
, tws
, tn
);
1664 gen_helper_msa_insve_df(cpu_env
, tdf
, twd
, tws
, tn
);
1669 #if !defined(TARGET_MIPS64)
1670 /* Double format valid only for MIPS64 */
1671 if (df
== DF_DOUBLE
) {
1672 gen_reserved_instruction(ctx
);
1675 if ((MASK_MSA_ELM(ctx
->opcode
) == OPC_COPY_U_df
) &&
1677 gen_reserved_instruction(ctx
);
1681 switch (MASK_MSA_ELM(ctx
->opcode
)) {
1683 if (likely(wd
!= 0)) {
1686 gen_helper_msa_copy_s_b(cpu_env
, twd
, tws
, tn
);
1689 gen_helper_msa_copy_s_h(cpu_env
, twd
, tws
, tn
);
1692 gen_helper_msa_copy_s_w(cpu_env
, twd
, tws
, tn
);
1694 #if defined(TARGET_MIPS64)
1696 gen_helper_msa_copy_s_d(cpu_env
, twd
, tws
, tn
);
1705 if (likely(wd
!= 0)) {
1708 gen_helper_msa_copy_u_b(cpu_env
, twd
, tws
, tn
);
1711 gen_helper_msa_copy_u_h(cpu_env
, twd
, tws
, tn
);
1713 #if defined(TARGET_MIPS64)
1715 gen_helper_msa_copy_u_w(cpu_env
, twd
, tws
, tn
);
1726 gen_helper_msa_insert_b(cpu_env
, twd
, tws
, tn
);
1729 gen_helper_msa_insert_h(cpu_env
, twd
, tws
, tn
);
1732 gen_helper_msa_insert_w(cpu_env
, twd
, tws
, tn
);
1734 #if defined(TARGET_MIPS64)
1736 gen_helper_msa_insert_d(cpu_env
, twd
, tws
, tn
);
1746 MIPS_INVAL("MSA instruction");
1747 gen_reserved_instruction(ctx
);
1749 tcg_temp_free_i32(twd
);
1750 tcg_temp_free_i32(tws
);
1751 tcg_temp_free_i32(tn
);
1752 tcg_temp_free_i32(tdf
);
1755 static void gen_msa_elm(DisasContext
*ctx
)
1757 uint8_t dfn
= (ctx
->opcode
>> 16) & 0x3f;
1758 uint32_t df
= 0, n
= 0;
1760 if ((dfn
& 0x30) == 0x00) {
1763 } else if ((dfn
& 0x38) == 0x20) {
1766 } else if ((dfn
& 0x3c) == 0x30) {
1769 } else if ((dfn
& 0x3e) == 0x38) {
1772 } else if (dfn
== 0x3E) {
1773 /* CTCMSA, CFCMSA, MOVE.V */
1774 gen_msa_elm_3e(ctx
);
1777 gen_reserved_instruction(ctx
);
1781 gen_msa_elm_df(ctx
, df
, n
);
1784 static void gen_msa_3rf(DisasContext
*ctx
)
1786 #define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
1787 uint8_t df
= (ctx
->opcode
>> 21) & 0x1;
1788 uint8_t wt
= (ctx
->opcode
>> 16) & 0x1f;
1789 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
1790 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
1792 TCGv_i32 twd
= tcg_const_i32(wd
);
1793 TCGv_i32 tws
= tcg_const_i32(ws
);
1794 TCGv_i32 twt
= tcg_const_i32(wt
);
1795 TCGv_i32 tdf
= tcg_temp_new_i32();
1797 /* adjust df value for floating-point instruction */
1798 tcg_gen_movi_i32(tdf
, df
+ 2);
1800 switch (MASK_MSA_3RF(ctx
->opcode
)) {
1802 gen_helper_msa_fcaf_df(cpu_env
, tdf
, twd
, tws
, twt
);
1805 gen_helper_msa_fadd_df(cpu_env
, tdf
, twd
, tws
, twt
);
1808 gen_helper_msa_fcun_df(cpu_env
, tdf
, twd
, tws
, twt
);
1811 gen_helper_msa_fsub_df(cpu_env
, tdf
, twd
, tws
, twt
);
1814 gen_helper_msa_fcor_df(cpu_env
, tdf
, twd
, tws
, twt
);
1817 gen_helper_msa_fceq_df(cpu_env
, tdf
, twd
, tws
, twt
);
1820 gen_helper_msa_fmul_df(cpu_env
, tdf
, twd
, tws
, twt
);
1823 gen_helper_msa_fcune_df(cpu_env
, tdf
, twd
, tws
, twt
);
1826 gen_helper_msa_fcueq_df(cpu_env
, tdf
, twd
, tws
, twt
);
1829 gen_helper_msa_fdiv_df(cpu_env
, tdf
, twd
, tws
, twt
);
1832 gen_helper_msa_fcne_df(cpu_env
, tdf
, twd
, tws
, twt
);
1835 gen_helper_msa_fclt_df(cpu_env
, tdf
, twd
, tws
, twt
);
1838 gen_helper_msa_fmadd_df(cpu_env
, tdf
, twd
, tws
, twt
);
1841 tcg_gen_movi_i32(tdf
, df
+ 1);
1842 gen_helper_msa_mul_q_df(cpu_env
, tdf
, twd
, tws
, twt
);
1845 gen_helper_msa_fcult_df(cpu_env
, tdf
, twd
, tws
, twt
);
1848 gen_helper_msa_fmsub_df(cpu_env
, tdf
, twd
, tws
, twt
);
1851 tcg_gen_movi_i32(tdf
, df
+ 1);
1852 gen_helper_msa_madd_q_df(cpu_env
, tdf
, twd
, tws
, twt
);
1855 gen_helper_msa_fcle_df(cpu_env
, tdf
, twd
, tws
, twt
);
1858 tcg_gen_movi_i32(tdf
, df
+ 1);
1859 gen_helper_msa_msub_q_df(cpu_env
, tdf
, twd
, tws
, twt
);
1862 gen_helper_msa_fcule_df(cpu_env
, tdf
, twd
, tws
, twt
);
1865 gen_helper_msa_fexp2_df(cpu_env
, tdf
, twd
, tws
, twt
);
1868 gen_helper_msa_fsaf_df(cpu_env
, tdf
, twd
, tws
, twt
);
1871 gen_helper_msa_fexdo_df(cpu_env
, tdf
, twd
, tws
, twt
);
1874 gen_helper_msa_fsun_df(cpu_env
, tdf
, twd
, tws
, twt
);
1877 gen_helper_msa_fsor_df(cpu_env
, tdf
, twd
, tws
, twt
);
1880 gen_helper_msa_fseq_df(cpu_env
, tdf
, twd
, tws
, twt
);
1883 gen_helper_msa_ftq_df(cpu_env
, tdf
, twd
, tws
, twt
);
1886 gen_helper_msa_fsune_df(cpu_env
, tdf
, twd
, tws
, twt
);
1889 gen_helper_msa_fsueq_df(cpu_env
, tdf
, twd
, tws
, twt
);
1892 gen_helper_msa_fsne_df(cpu_env
, tdf
, twd
, tws
, twt
);
1895 gen_helper_msa_fslt_df(cpu_env
, tdf
, twd
, tws
, twt
);
1898 gen_helper_msa_fmin_df(cpu_env
, tdf
, twd
, tws
, twt
);
1901 tcg_gen_movi_i32(tdf
, df
+ 1);
1902 gen_helper_msa_mulr_q_df(cpu_env
, tdf
, twd
, tws
, twt
);
1905 gen_helper_msa_fsult_df(cpu_env
, tdf
, twd
, tws
, twt
);
1908 gen_helper_msa_fmin_a_df(cpu_env
, tdf
, twd
, tws
, twt
);
1910 case OPC_MADDR_Q_df
:
1911 tcg_gen_movi_i32(tdf
, df
+ 1);
1912 gen_helper_msa_maddr_q_df(cpu_env
, tdf
, twd
, tws
, twt
);
1915 gen_helper_msa_fsle_df(cpu_env
, tdf
, twd
, tws
, twt
);
1918 gen_helper_msa_fmax_df(cpu_env
, tdf
, twd
, tws
, twt
);
1920 case OPC_MSUBR_Q_df
:
1921 tcg_gen_movi_i32(tdf
, df
+ 1);
1922 gen_helper_msa_msubr_q_df(cpu_env
, tdf
, twd
, tws
, twt
);
1925 gen_helper_msa_fsule_df(cpu_env
, tdf
, twd
, tws
, twt
);
1928 gen_helper_msa_fmax_a_df(cpu_env
, tdf
, twd
, tws
, twt
);
1931 MIPS_INVAL("MSA instruction");
1932 gen_reserved_instruction(ctx
);
1936 tcg_temp_free_i32(twd
);
1937 tcg_temp_free_i32(tws
);
1938 tcg_temp_free_i32(twt
);
1939 tcg_temp_free_i32(tdf
);
1942 static void gen_msa_2r(DisasContext
*ctx
)
1944 #define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
1946 uint8_t wt
= (ctx
->opcode
>> 16) & 0x1f;
1947 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
1948 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
1949 uint8_t df
= (ctx
->opcode
>> 16) & 0x3;
1950 TCGv_i32 twd
= tcg_const_i32(wd
);
1951 TCGv_i32 tws
= tcg_const_i32(ws
);
1952 TCGv_i32 twt
= tcg_const_i32(wt
);
1953 TCGv_i32 tdf
= tcg_const_i32(df
);
1955 switch (MASK_MSA_2R(ctx
->opcode
)) {
1957 #if !defined(TARGET_MIPS64)
1958 /* Double format valid only for MIPS64 */
1959 if (df
== DF_DOUBLE
) {
1960 gen_reserved_instruction(ctx
);
1964 gen_helper_msa_fill_df(cpu_env
, tdf
, twd
, tws
); /* trs */
1969 gen_helper_msa_nloc_b(cpu_env
, twd
, tws
);
1972 gen_helper_msa_nloc_h(cpu_env
, twd
, tws
);
1975 gen_helper_msa_nloc_w(cpu_env
, twd
, tws
);
1978 gen_helper_msa_nloc_d(cpu_env
, twd
, tws
);
1985 gen_helper_msa_nlzc_b(cpu_env
, twd
, tws
);
1988 gen_helper_msa_nlzc_h(cpu_env
, twd
, tws
);
1991 gen_helper_msa_nlzc_w(cpu_env
, twd
, tws
);
1994 gen_helper_msa_nlzc_d(cpu_env
, twd
, tws
);
2001 gen_helper_msa_pcnt_b(cpu_env
, twd
, tws
);
2004 gen_helper_msa_pcnt_h(cpu_env
, twd
, tws
);
2007 gen_helper_msa_pcnt_w(cpu_env
, twd
, tws
);
2010 gen_helper_msa_pcnt_d(cpu_env
, twd
, tws
);
2015 MIPS_INVAL("MSA instruction");
2016 gen_reserved_instruction(ctx
);
2020 tcg_temp_free_i32(twd
);
2021 tcg_temp_free_i32(tws
);
2022 tcg_temp_free_i32(twt
);
2023 tcg_temp_free_i32(tdf
);
2026 static void gen_msa_2rf(DisasContext
*ctx
)
2028 #define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
2030 uint8_t wt
= (ctx
->opcode
>> 16) & 0x1f;
2031 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
2032 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
2033 uint8_t df
= (ctx
->opcode
>> 16) & 0x1;
2034 TCGv_i32 twd
= tcg_const_i32(wd
);
2035 TCGv_i32 tws
= tcg_const_i32(ws
);
2036 TCGv_i32 twt
= tcg_const_i32(wt
);
2037 /* adjust df value for floating-point instruction */
2038 TCGv_i32 tdf
= tcg_const_i32(df
+ 2);
2040 switch (MASK_MSA_2RF(ctx
->opcode
)) {
2042 gen_helper_msa_fclass_df(cpu_env
, tdf
, twd
, tws
);
2044 case OPC_FTRUNC_S_df
:
2045 gen_helper_msa_ftrunc_s_df(cpu_env
, tdf
, twd
, tws
);
2047 case OPC_FTRUNC_U_df
:
2048 gen_helper_msa_ftrunc_u_df(cpu_env
, tdf
, twd
, tws
);
2051 gen_helper_msa_fsqrt_df(cpu_env
, tdf
, twd
, tws
);
2054 gen_helper_msa_frsqrt_df(cpu_env
, tdf
, twd
, tws
);
2057 gen_helper_msa_frcp_df(cpu_env
, tdf
, twd
, tws
);
2060 gen_helper_msa_frint_df(cpu_env
, tdf
, twd
, tws
);
2063 gen_helper_msa_flog2_df(cpu_env
, tdf
, twd
, tws
);
2066 gen_helper_msa_fexupl_df(cpu_env
, tdf
, twd
, tws
);
2069 gen_helper_msa_fexupr_df(cpu_env
, tdf
, twd
, tws
);
2072 gen_helper_msa_ffql_df(cpu_env
, tdf
, twd
, tws
);
2075 gen_helper_msa_ffqr_df(cpu_env
, tdf
, twd
, tws
);
2077 case OPC_FTINT_S_df
:
2078 gen_helper_msa_ftint_s_df(cpu_env
, tdf
, twd
, tws
);
2080 case OPC_FTINT_U_df
:
2081 gen_helper_msa_ftint_u_df(cpu_env
, tdf
, twd
, tws
);
2083 case OPC_FFINT_S_df
:
2084 gen_helper_msa_ffint_s_df(cpu_env
, tdf
, twd
, tws
);
2086 case OPC_FFINT_U_df
:
2087 gen_helper_msa_ffint_u_df(cpu_env
, tdf
, twd
, tws
);
2091 tcg_temp_free_i32(twd
);
2092 tcg_temp_free_i32(tws
);
2093 tcg_temp_free_i32(twt
);
2094 tcg_temp_free_i32(tdf
);
2097 static void gen_msa_vec_v(DisasContext
*ctx
)
2099 #define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)))
2100 uint8_t wt
= (ctx
->opcode
>> 16) & 0x1f;
2101 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
2102 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
2103 TCGv_i32 twd
= tcg_const_i32(wd
);
2104 TCGv_i32 tws
= tcg_const_i32(ws
);
2105 TCGv_i32 twt
= tcg_const_i32(wt
);
2107 switch (MASK_MSA_VEC(ctx
->opcode
)) {
2109 gen_helper_msa_and_v(cpu_env
, twd
, tws
, twt
);
2112 gen_helper_msa_or_v(cpu_env
, twd
, tws
, twt
);
2115 gen_helper_msa_nor_v(cpu_env
, twd
, tws
, twt
);
2118 gen_helper_msa_xor_v(cpu_env
, twd
, tws
, twt
);
2121 gen_helper_msa_bmnz_v(cpu_env
, twd
, tws
, twt
);
2124 gen_helper_msa_bmz_v(cpu_env
, twd
, tws
, twt
);
2127 gen_helper_msa_bsel_v(cpu_env
, twd
, tws
, twt
);
2130 MIPS_INVAL("MSA instruction");
2131 gen_reserved_instruction(ctx
);
2135 tcg_temp_free_i32(twd
);
2136 tcg_temp_free_i32(tws
);
2137 tcg_temp_free_i32(twt
);
2140 static void gen_msa_vec(DisasContext
*ctx
)
2142 switch (MASK_MSA_VEC(ctx
->opcode
)) {
2159 MIPS_INVAL("MSA instruction");
2160 gen_reserved_instruction(ctx
);
2165 static void gen_msa(DisasContext
*ctx
)
2167 uint32_t opcode
= ctx
->opcode
;
2169 check_msa_access(ctx
);
2171 switch (MASK_MSA_MINOR(opcode
)) {
2181 case OPC_MSA_BIT_09
:
2182 case OPC_MSA_BIT_0A
:
2199 case OPC_MSA_3RF_1A
:
2200 case OPC_MSA_3RF_1B
:
2201 case OPC_MSA_3RF_1C
:
2216 int32_t s10
= sextract32(ctx
->opcode
, 16, 10);
2217 uint8_t rs
= (ctx
->opcode
>> 11) & 0x1f;
2218 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
2219 uint8_t df
= (ctx
->opcode
>> 0) & 0x3;
2221 TCGv_i32 twd
= tcg_const_i32(wd
);
2222 TCGv taddr
= tcg_temp_new();
2223 gen_base_offset_addr(ctx
, taddr
, rs
, s10
<< df
);
2225 switch (MASK_MSA_MINOR(opcode
)) {
2227 gen_helper_msa_ld_b(cpu_env
, twd
, taddr
);
2230 gen_helper_msa_ld_h(cpu_env
, twd
, taddr
);
2233 gen_helper_msa_ld_w(cpu_env
, twd
, taddr
);
2236 gen_helper_msa_ld_d(cpu_env
, twd
, taddr
);
2239 gen_helper_msa_st_b(cpu_env
, twd
, taddr
);
2242 gen_helper_msa_st_h(cpu_env
, twd
, taddr
);
2245 gen_helper_msa_st_w(cpu_env
, twd
, taddr
);
2248 gen_helper_msa_st_d(cpu_env
, twd
, taddr
);
2252 tcg_temp_free_i32(twd
);
2253 tcg_temp_free(taddr
);
2257 MIPS_INVAL("MSA instruction");
2258 gen_reserved_instruction(ctx
);
2263 static bool trans_MSA(DisasContext
*ctx
, arg_MSA
*a
)
2270 static bool trans_LSA(DisasContext
*ctx
, arg_rtype
*a
)
2272 return gen_lsa(ctx
, a
->rd
, a
->rt
, a
->rs
, a
->sa
);
2275 static bool trans_DLSA(DisasContext
*ctx
, arg_rtype
*a
)
2277 return gen_dlsa(ctx
, a
->rd
, a
->rt
, a
->rs
, a
->sa
);
2280 bool decode_ase_msa(DisasContext
*ctx
, uint32_t insn
)
2282 if (TARGET_LONG_BITS
== 64 && decode_msa64(ctx
, insn
)) {
2285 return decode_msa32(ctx
, insn
);