4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
21 #include "qemu/osdep.h"
22 #include "qemu/cutils.h"
23 #include "qemu/qemu-print.h"
24 #include "qapi/error.h"
28 #include "qemu/module.h"
29 #include "sysemu/kvm.h"
30 #include "sysemu/qtest.h"
31 #include "exec/exec-all.h"
32 #include "hw/qdev-properties.h"
33 #include "hw/qdev-clock.h"
34 #include "hw/semihosting/semihost.h"
35 #include "qapi/qapi-commands-machine-target.h"
36 #include "fpu_helper.h"
38 #if !defined(CONFIG_USER_ONLY)
40 /* Called for updates to CP0_Status. */
41 void sync_c0_status(CPUMIPSState
*env
, CPUMIPSState
*cpu
, int tc
)
43 int32_t tcstatus
, *tcst
;
44 uint32_t v
= cpu
->CP0_Status
;
45 uint32_t cu
, mx
, asid
, ksu
;
46 uint32_t mask
= ((1 << CP0TCSt_TCU3
)
52 | (0xff << CP0TCSt_TASID
));
54 cu
= (v
>> CP0St_CU0
) & 0xf;
55 mx
= (v
>> CP0St_MX
) & 0x1;
56 ksu
= (v
>> CP0St_KSU
) & 0x3;
57 asid
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
59 tcstatus
= cu
<< CP0TCSt_TCU0
;
60 tcstatus
|= mx
<< CP0TCSt_TMX
;
61 tcstatus
|= ksu
<< CP0TCSt_TKSU
;
64 if (tc
== cpu
->current_tc
) {
65 tcst
= &cpu
->active_tc
.CP0_TCStatus
;
67 tcst
= &cpu
->tcs
[tc
].CP0_TCStatus
;
75 void cpu_mips_store_status(CPUMIPSState
*env
, target_ulong val
)
77 uint32_t mask
= env
->CP0_Status_rw_bitmask
;
78 target_ulong old
= env
->CP0_Status
;
80 if (env
->insn_flags
& ISA_MIPS_R6
) {
81 bool has_supervisor
= extract32(mask
, CP0St_KSU
, 2) == 0x3;
82 #if defined(TARGET_MIPS64)
83 uint32_t ksux
= (1 << CP0St_KX
) & val
;
84 ksux
|= (ksux
>> 1) & val
; /* KX = 0 forces SX to be 0 */
85 ksux
|= (ksux
>> 1) & val
; /* SX = 0 forces UX to be 0 */
86 val
= (val
& ~(7 << CP0St_UX
)) | ksux
;
88 if (has_supervisor
&& extract32(val
, CP0St_KSU
, 2) == 0x3) {
89 mask
&= ~(3 << CP0St_KSU
);
91 mask
&= ~(((1 << CP0St_SR
) | (1 << CP0St_NMI
)) & val
);
94 env
->CP0_Status
= (old
& ~mask
) | (val
& mask
);
95 #if defined(TARGET_MIPS64)
96 if ((env
->CP0_Status
^ old
) & (old
& (7 << CP0St_UX
))) {
97 /* Access to at least one of the 64-bit segments has been disabled */
98 tlb_flush(env_cpu(env
));
101 if (ase_mt_available(env
)) {
102 sync_c0_status(env
, env
, env
->current_tc
);
108 void cpu_mips_store_cause(CPUMIPSState
*env
, target_ulong val
)
110 uint32_t mask
= 0x00C00300;
111 uint32_t old
= env
->CP0_Cause
;
114 if (env
->insn_flags
& ISA_MIPS_R2
) {
115 mask
|= 1 << CP0Ca_DC
;
117 if (env
->insn_flags
& ISA_MIPS_R6
) {
118 mask
&= ~((1 << CP0Ca_WP
) & val
);
121 env
->CP0_Cause
= (env
->CP0_Cause
& ~mask
) | (val
& mask
);
123 if ((old
^ env
->CP0_Cause
) & (1 << CP0Ca_DC
)) {
124 if (env
->CP0_Cause
& (1 << CP0Ca_DC
)) {
125 cpu_mips_stop_count(env
);
127 cpu_mips_start_count(env
);
131 /* Set/reset software interrupts */
132 for (i
= 0 ; i
< 2 ; i
++) {
133 if ((old
^ env
->CP0_Cause
) & (1 << (CP0Ca_IP
+ i
))) {
134 cpu_mips_soft_irq(env
, i
, env
->CP0_Cause
& (1 << (CP0Ca_IP
+ i
)));
139 #endif /* !CONFIG_USER_ONLY */
141 static const char * const excp_names
[EXCP_LAST
+ 1] = {
142 [EXCP_RESET
] = "reset",
143 [EXCP_SRESET
] = "soft reset",
144 [EXCP_DSS
] = "debug single step",
145 [EXCP_DINT
] = "debug interrupt",
146 [EXCP_NMI
] = "non-maskable interrupt",
147 [EXCP_MCHECK
] = "machine check",
148 [EXCP_EXT_INTERRUPT
] = "interrupt",
149 [EXCP_DFWATCH
] = "deferred watchpoint",
150 [EXCP_DIB
] = "debug instruction breakpoint",
151 [EXCP_IWATCH
] = "instruction fetch watchpoint",
152 [EXCP_AdEL
] = "address error load",
153 [EXCP_AdES
] = "address error store",
154 [EXCP_TLBF
] = "TLB refill",
155 [EXCP_IBE
] = "instruction bus error",
156 [EXCP_DBp
] = "debug breakpoint",
157 [EXCP_SYSCALL
] = "syscall",
158 [EXCP_BREAK
] = "break",
159 [EXCP_CpU
] = "coprocessor unusable",
160 [EXCP_RI
] = "reserved instruction",
161 [EXCP_OVERFLOW
] = "arithmetic overflow",
162 [EXCP_TRAP
] = "trap",
163 [EXCP_FPE
] = "floating point",
164 [EXCP_DDBS
] = "debug data break store",
165 [EXCP_DWATCH
] = "data watchpoint",
166 [EXCP_LTLBL
] = "TLB modify",
167 [EXCP_TLBL
] = "TLB load",
168 [EXCP_TLBS
] = "TLB store",
169 [EXCP_DBE
] = "data bus error",
170 [EXCP_DDBL
] = "debug data break load",
171 [EXCP_THREAD
] = "thread",
172 [EXCP_MDMX
] = "MDMX",
173 [EXCP_C2E
] = "precise coprocessor 2",
174 [EXCP_CACHE
] = "cache error",
175 [EXCP_TLBXI
] = "TLB execute-inhibit",
176 [EXCP_TLBRI
] = "TLB read-inhibit",
177 [EXCP_MSADIS
] = "MSA disabled",
178 [EXCP_MSAFPE
] = "MSA floating point",
181 const char *mips_exception_name(int32_t exception
)
183 if (exception
< 0 || exception
> EXCP_LAST
) {
186 return excp_names
[exception
];
189 void cpu_set_exception_base(int vp_index
, target_ulong address
)
191 MIPSCPU
*vp
= MIPS_CPU(qemu_get_cpu(vp_index
));
192 vp
->env
.exception_base
= address
;
195 target_ulong
exception_resume_pc(CPUMIPSState
*env
)
198 target_ulong isa_mode
;
200 isa_mode
= !!(env
->hflags
& MIPS_HFLAG_M16
);
201 bad_pc
= env
->active_tc
.PC
| isa_mode
;
202 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
204 * If the exception was raised from a delay slot, come back to
207 bad_pc
-= (env
->hflags
& MIPS_HFLAG_B16
? 2 : 4);
213 bool mips_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
215 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
216 MIPSCPU
*cpu
= MIPS_CPU(cs
);
217 CPUMIPSState
*env
= &cpu
->env
;
219 if (cpu_mips_hw_interrupts_enabled(env
) &&
220 cpu_mips_hw_interrupts_pending(env
)) {
222 cs
->exception_index
= EXCP_EXT_INTERRUPT
;
224 mips_cpu_do_interrupt(cs
);
231 void QEMU_NORETURN
do_raise_exception_err(CPUMIPSState
*env
,
236 CPUState
*cs
= env_cpu(env
);
238 qemu_log_mask(CPU_LOG_INT
, "%s: %d (%s) %d\n",
239 __func__
, exception
, mips_exception_name(exception
),
241 cs
->exception_index
= exception
;
242 env
->error_code
= error_code
;
244 cpu_loop_exit_restore(cs
, pc
);
247 static void mips_cpu_set_pc(CPUState
*cs
, vaddr value
)
249 MIPSCPU
*cpu
= MIPS_CPU(cs
);
250 CPUMIPSState
*env
= &cpu
->env
;
252 env
->active_tc
.PC
= value
& ~(target_ulong
)1;
254 env
->hflags
|= MIPS_HFLAG_M16
;
256 env
->hflags
&= ~(MIPS_HFLAG_M16
);
261 static void mips_cpu_synchronize_from_tb(CPUState
*cs
,
262 const TranslationBlock
*tb
)
264 MIPSCPU
*cpu
= MIPS_CPU(cs
);
265 CPUMIPSState
*env
= &cpu
->env
;
267 env
->active_tc
.PC
= tb
->pc
;
268 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
269 env
->hflags
|= tb
->flags
& MIPS_HFLAG_BMASK
;
271 #endif /* CONFIG_TCG */
273 static bool mips_cpu_has_work(CPUState
*cs
)
275 MIPSCPU
*cpu
= MIPS_CPU(cs
);
276 CPUMIPSState
*env
= &cpu
->env
;
277 bool has_work
= false;
280 * Prior to MIPS Release 6 it is implementation dependent if non-enabled
281 * interrupts wake-up the CPU, however most of the implementations only
282 * check for interrupts that can be taken.
284 if ((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
285 cpu_mips_hw_interrupts_pending(env
)) {
286 if (cpu_mips_hw_interrupts_enabled(env
) ||
287 (env
->insn_flags
& ISA_MIPS_R6
)) {
292 /* MIPS-MT has the ability to halt the CPU. */
293 if (ase_mt_available(env
)) {
295 * The QEMU model will issue an _WAKE request whenever the CPUs
296 * should be woken up.
298 if (cs
->interrupt_request
& CPU_INTERRUPT_WAKE
) {
302 if (!mips_vpe_active(env
)) {
306 /* MIPS Release 6 has the ability to halt the CPU. */
307 if (env
->CP0_Config5
& (1 << CP0C5_VP
)) {
308 if (cs
->interrupt_request
& CPU_INTERRUPT_WAKE
) {
311 if (!mips_vp_active(env
)) {
318 #include "cpu-defs.c.inc"
320 static void mips_cpu_reset(DeviceState
*dev
)
322 CPUState
*cs
= CPU(dev
);
323 MIPSCPU
*cpu
= MIPS_CPU(cs
);
324 MIPSCPUClass
*mcc
= MIPS_CPU_GET_CLASS(cpu
);
325 CPUMIPSState
*env
= &cpu
->env
;
327 mcc
->parent_reset(dev
);
329 memset(env
, 0, offsetof(CPUMIPSState
, end_reset_fields
));
331 /* Reset registers to their default values */
332 env
->CP0_PRid
= env
->cpu_model
->CP0_PRid
;
333 env
->CP0_Config0
= env
->cpu_model
->CP0_Config0
;
334 #ifdef TARGET_WORDS_BIGENDIAN
335 env
->CP0_Config0
|= (1 << CP0C0_BE
);
337 env
->CP0_Config1
= env
->cpu_model
->CP0_Config1
;
338 env
->CP0_Config2
= env
->cpu_model
->CP0_Config2
;
339 env
->CP0_Config3
= env
->cpu_model
->CP0_Config3
;
340 env
->CP0_Config4
= env
->cpu_model
->CP0_Config4
;
341 env
->CP0_Config4_rw_bitmask
= env
->cpu_model
->CP0_Config4_rw_bitmask
;
342 env
->CP0_Config5
= env
->cpu_model
->CP0_Config5
;
343 env
->CP0_Config5_rw_bitmask
= env
->cpu_model
->CP0_Config5_rw_bitmask
;
344 env
->CP0_Config6
= env
->cpu_model
->CP0_Config6
;
345 env
->CP0_Config6_rw_bitmask
= env
->cpu_model
->CP0_Config6_rw_bitmask
;
346 env
->CP0_Config7
= env
->cpu_model
->CP0_Config7
;
347 env
->CP0_Config7_rw_bitmask
= env
->cpu_model
->CP0_Config7_rw_bitmask
;
348 env
->CP0_LLAddr_rw_bitmask
= env
->cpu_model
->CP0_LLAddr_rw_bitmask
349 << env
->cpu_model
->CP0_LLAddr_shift
;
350 env
->CP0_LLAddr_shift
= env
->cpu_model
->CP0_LLAddr_shift
;
351 env
->SYNCI_Step
= env
->cpu_model
->SYNCI_Step
;
352 env
->CCRes
= env
->cpu_model
->CCRes
;
353 env
->CP0_Status_rw_bitmask
= env
->cpu_model
->CP0_Status_rw_bitmask
;
354 env
->CP0_TCStatus_rw_bitmask
= env
->cpu_model
->CP0_TCStatus_rw_bitmask
;
355 env
->CP0_SRSCtl
= env
->cpu_model
->CP0_SRSCtl
;
357 env
->SEGBITS
= env
->cpu_model
->SEGBITS
;
358 env
->SEGMask
= (target_ulong
)((1ULL << env
->cpu_model
->SEGBITS
) - 1);
359 #if defined(TARGET_MIPS64)
360 if (env
->cpu_model
->insn_flags
& ISA_MIPS3
) {
361 env
->SEGMask
|= 3ULL << 62;
364 env
->PABITS
= env
->cpu_model
->PABITS
;
365 env
->CP0_SRSConf0_rw_bitmask
= env
->cpu_model
->CP0_SRSConf0_rw_bitmask
;
366 env
->CP0_SRSConf0
= env
->cpu_model
->CP0_SRSConf0
;
367 env
->CP0_SRSConf1_rw_bitmask
= env
->cpu_model
->CP0_SRSConf1_rw_bitmask
;
368 env
->CP0_SRSConf1
= env
->cpu_model
->CP0_SRSConf1
;
369 env
->CP0_SRSConf2_rw_bitmask
= env
->cpu_model
->CP0_SRSConf2_rw_bitmask
;
370 env
->CP0_SRSConf2
= env
->cpu_model
->CP0_SRSConf2
;
371 env
->CP0_SRSConf3_rw_bitmask
= env
->cpu_model
->CP0_SRSConf3_rw_bitmask
;
372 env
->CP0_SRSConf3
= env
->cpu_model
->CP0_SRSConf3
;
373 env
->CP0_SRSConf4_rw_bitmask
= env
->cpu_model
->CP0_SRSConf4_rw_bitmask
;
374 env
->CP0_SRSConf4
= env
->cpu_model
->CP0_SRSConf4
;
375 env
->CP0_PageGrain_rw_bitmask
= env
->cpu_model
->CP0_PageGrain_rw_bitmask
;
376 env
->CP0_PageGrain
= env
->cpu_model
->CP0_PageGrain
;
377 env
->CP0_EBaseWG_rw_bitmask
= env
->cpu_model
->CP0_EBaseWG_rw_bitmask
;
378 env
->active_fpu
.fcr0
= env
->cpu_model
->CP1_fcr0
;
379 env
->active_fpu
.fcr31_rw_bitmask
= env
->cpu_model
->CP1_fcr31_rw_bitmask
;
380 env
->active_fpu
.fcr31
= env
->cpu_model
->CP1_fcr31
;
381 env
->msair
= env
->cpu_model
->MSAIR
;
382 env
->insn_flags
= env
->cpu_model
->insn_flags
;
384 #if defined(CONFIG_USER_ONLY)
385 env
->CP0_Status
= (MIPS_HFLAG_UM
<< CP0St_KSU
);
386 # ifdef TARGET_MIPS64
387 /* Enable 64-bit register mode. */
388 env
->CP0_Status
|= (1 << CP0St_PX
);
390 # ifdef TARGET_ABI_MIPSN64
391 /* Enable 64-bit address mode. */
392 env
->CP0_Status
|= (1 << CP0St_UX
);
395 * Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR
396 * hardware registers.
398 env
->CP0_HWREna
|= 0x0000000F;
399 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
400 env
->CP0_Status
|= (1 << CP0St_CU1
);
402 if (env
->CP0_Config3
& (1 << CP0C3_DSPP
)) {
403 env
->CP0_Status
|= (1 << CP0St_MX
);
405 # if defined(TARGET_MIPS64)
406 /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */
407 if ((env
->CP0_Config1
& (1 << CP0C1_FP
)) &&
408 (env
->CP0_Status_rw_bitmask
& (1 << CP0St_FR
))) {
409 env
->CP0_Status
|= (1 << CP0St_FR
);
412 #else /* !CONFIG_USER_ONLY */
413 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
415 * If the exception was raised from a delay slot,
416 * come back to the jump.
418 env
->CP0_ErrorEPC
= (env
->active_tc
.PC
419 - (env
->hflags
& MIPS_HFLAG_B16
? 2 : 4));
421 env
->CP0_ErrorEPC
= env
->active_tc
.PC
;
423 env
->active_tc
.PC
= env
->exception_base
;
424 env
->CP0_Random
= env
->tlb
->nb_tlb
- 1;
425 env
->tlb
->tlb_in_use
= env
->tlb
->nb_tlb
;
427 env
->CP0_GlobalNumber
= (cs
->cpu_index
& 0xFF) << CP0GN_VPId
;
428 env
->CP0_EBase
= (cs
->cpu_index
& 0x3FF);
429 if (mips_um_ksegs_enabled()) {
430 env
->CP0_EBase
|= 0x40000000;
432 env
->CP0_EBase
|= (int32_t)0x80000000;
434 if (env
->CP0_Config3
& (1 << CP0C3_CMGCR
)) {
435 env
->CP0_CMGCRBase
= 0x1fbf8000 >> 4;
437 env
->CP0_EntryHi_ASID_mask
= (env
->CP0_Config5
& (1 << CP0C5_MI
)) ?
438 0x0 : (env
->CP0_Config4
& (1 << CP0C4_AE
)) ? 0x3ff : 0xff;
439 env
->CP0_Status
= (1 << CP0St_BEV
) | (1 << CP0St_ERL
);
441 * Vectored interrupts not implemented, timer on int 7,
442 * no performance counters.
444 env
->CP0_IntCtl
= 0xe0000000;
448 for (i
= 0; i
< 7; i
++) {
449 env
->CP0_WatchLo
[i
] = 0;
450 env
->CP0_WatchHi
[i
] = 0x80000000;
452 env
->CP0_WatchLo
[7] = 0;
453 env
->CP0_WatchHi
[7] = 0;
455 /* Count register increments in debug mode, EJTAG version 1 */
456 env
->CP0_Debug
= (1 << CP0DB_CNT
) | (0x1 << CP0DB_VER
);
458 cpu_mips_store_count(env
, 1);
460 if (ase_mt_available(env
)) {
463 /* Only TC0 on VPE 0 starts as active. */
464 for (i
= 0; i
< ARRAY_SIZE(env
->tcs
); i
++) {
465 env
->tcs
[i
].CP0_TCBind
= cs
->cpu_index
<< CP0TCBd_CurVPE
;
466 env
->tcs
[i
].CP0_TCHalt
= 1;
468 env
->active_tc
.CP0_TCHalt
= 1;
471 if (cs
->cpu_index
== 0) {
472 /* VPE0 starts up enabled. */
473 env
->mvp
->CP0_MVPControl
|= (1 << CP0MVPCo_EVP
);
474 env
->CP0_VPEConf0
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
476 /* TC0 starts up unhalted. */
478 env
->active_tc
.CP0_TCHalt
= 0;
479 env
->tcs
[0].CP0_TCHalt
= 0;
480 /* With thread 0 active. */
481 env
->active_tc
.CP0_TCStatus
= (1 << CP0TCSt_A
);
482 env
->tcs
[0].CP0_TCStatus
= (1 << CP0TCSt_A
);
487 * Configure default legacy segmentation control. We use this regardless of
488 * whether segmentation control is presented to the guest.
490 /* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */
491 env
->CP0_SegCtl0
= (CP0SC_AM_MK
<< CP0SC_AM
);
492 /* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */
493 env
->CP0_SegCtl0
|= ((CP0SC_AM_MSK
<< CP0SC_AM
)) << 16;
494 /* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */
495 env
->CP0_SegCtl1
= (0 << CP0SC_PA
) | (CP0SC_AM_UK
<< CP0SC_AM
) |
497 /* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */
498 env
->CP0_SegCtl1
|= ((0 << CP0SC_PA
) | (CP0SC_AM_UK
<< CP0SC_AM
) |
499 (3 << CP0SC_C
)) << 16;
500 /* USeg (seg4 0x40000000..0x7FFFFFFF) */
501 env
->CP0_SegCtl2
= (2 << CP0SC_PA
) | (CP0SC_AM_MUSK
<< CP0SC_AM
) |
502 (1 << CP0SC_EU
) | (2 << CP0SC_C
);
503 /* USeg (seg5 0x00000000..0x3FFFFFFF) */
504 env
->CP0_SegCtl2
|= ((0 << CP0SC_PA
) | (CP0SC_AM_MUSK
<< CP0SC_AM
) |
505 (1 << CP0SC_EU
) | (2 << CP0SC_C
)) << 16;
506 /* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */
507 env
->CP0_SegCtl1
|= (CP0SC_AM_UK
<< CP0SC1_XAM
);
508 #endif /* !CONFIG_USER_ONLY */
509 if ((env
->insn_flags
& ISA_MIPS_R6
) &&
510 (env
->active_fpu
.fcr0
& (1 << FCR0_F64
))) {
511 /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */
512 env
->CP0_Status
|= (1 << CP0St_FR
);
515 if (env
->insn_flags
& ISA_MIPS_R6
) {
517 env
->CP0_PWSize
= 0x40;
523 env
->CP0_PWField
= 0x0C30C302;
530 env
->CP0_PWField
= 0x02;
533 if (env
->CP0_Config3
& (1 << CP0C3_ISA
) & (1 << (CP0C3_ISA
+ 1))) {
534 /* microMIPS on reset when Config3.ISA is 3 */
535 env
->hflags
|= MIPS_HFLAG_M16
;
541 restore_fp_status(env
);
543 cs
->exception_index
= EXCP_NONE
;
545 if (semihosting_get_argc()) {
546 /* UHI interface can be used to obtain argc and argv */
547 env
->active_tc
.gpr
[4] = -1;
550 #ifndef CONFIG_USER_ONLY
552 kvm_mips_reset_vcpu(cpu
);
557 static void mips_cpu_disas_set_info(CPUState
*s
, disassemble_info
*info
)
559 MIPSCPU
*cpu
= MIPS_CPU(s
);
560 CPUMIPSState
*env
= &cpu
->env
;
562 if (!(env
->insn_flags
& ISA_NANOMIPS32
)) {
563 #ifdef TARGET_WORDS_BIGENDIAN
564 info
->print_insn
= print_insn_big_mips
;
566 info
->print_insn
= print_insn_little_mips
;
569 #if defined(CONFIG_NANOMIPS_DIS)
570 info
->print_insn
= print_insn_nanomips
;
576 * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz.
578 #define CPU_FREQ_HZ_DEFAULT 200000000
579 #define CP0_COUNT_RATE_DEFAULT 2
581 static void mips_cp0_period_set(MIPSCPU
*cpu
)
583 CPUMIPSState
*env
= &cpu
->env
;
585 env
->cp0_count_ns
= clock_ticks_to_ns(MIPS_CPU(cpu
)->clock
,
586 cpu
->cp0_count_rate
);
587 assert(env
->cp0_count_ns
);
590 static void mips_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
592 CPUState
*cs
= CPU(dev
);
593 MIPSCPU
*cpu
= MIPS_CPU(dev
);
594 CPUMIPSState
*env
= &cpu
->env
;
595 MIPSCPUClass
*mcc
= MIPS_CPU_GET_CLASS(dev
);
596 Error
*local_err
= NULL
;
598 if (!clock_get(cpu
->clock
)) {
599 #ifndef CONFIG_USER_ONLY
600 if (!qtest_enabled()) {
601 g_autofree
char *cpu_freq_str
= freq_to_str(CPU_FREQ_HZ_DEFAULT
);
603 warn_report("CPU input clock is not connected to any output clock, "
604 "using default frequency of %s.", cpu_freq_str
);
607 /* Initialize the frequency in case the clock remains unconnected. */
608 clock_set_hz(cpu
->clock
, CPU_FREQ_HZ_DEFAULT
);
610 mips_cp0_period_set(cpu
);
612 cpu_exec_realizefn(cs
, &local_err
);
613 if (local_err
!= NULL
) {
614 error_propagate(errp
, local_err
);
618 env
->exception_base
= (int32_t)0xBFC00000;
620 #ifndef CONFIG_USER_ONLY
621 mmu_init(env
, env
->cpu_model
);
623 fpu_init(env
, env
->cpu_model
);
629 mcc
->parent_realize(dev
, errp
);
632 static void mips_cpu_initfn(Object
*obj
)
634 MIPSCPU
*cpu
= MIPS_CPU(obj
);
635 CPUMIPSState
*env
= &cpu
->env
;
636 MIPSCPUClass
*mcc
= MIPS_CPU_GET_CLASS(obj
);
638 cpu_set_cpustate_pointers(cpu
);
639 cpu
->clock
= qdev_init_clock_in(DEVICE(obj
), "clk-in", NULL
, cpu
);
640 env
->cpu_model
= mcc
->cpu_def
;
643 static char *mips_cpu_type_name(const char *cpu_model
)
645 return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model
);
648 static ObjectClass
*mips_cpu_class_by_name(const char *cpu_model
)
653 typename
= mips_cpu_type_name(cpu_model
);
654 oc
= object_class_by_name(typename
);
659 static Property mips_cpu_properties
[] = {
660 /* CP0 timer running at half the clock of the CPU */
661 DEFINE_PROP_UINT32("cp0-count-rate", MIPSCPU
, cp0_count_rate
,
662 CP0_COUNT_RATE_DEFAULT
),
663 DEFINE_PROP_END_OF_LIST()
667 #include "hw/core/tcg-cpu-ops.h"
669 * NB: cannot be const, as some elements are changed for specific
670 * mips hardware (see hw/mips/jazz.c).
672 static struct TCGCPUOps mips_tcg_ops
= {
673 .initialize
= mips_tcg_init
,
674 .synchronize_from_tb
= mips_cpu_synchronize_from_tb
,
675 .cpu_exec_interrupt
= mips_cpu_exec_interrupt
,
676 .tlb_fill
= mips_cpu_tlb_fill
,
678 #if !defined(CONFIG_USER_ONLY)
679 .do_interrupt
= mips_cpu_do_interrupt
,
680 .do_transaction_failed
= mips_cpu_do_transaction_failed
,
681 .do_unaligned_access
= mips_cpu_do_unaligned_access
,
682 #endif /* !CONFIG_USER_ONLY */
684 #endif /* CONFIG_TCG */
686 static void mips_cpu_class_init(ObjectClass
*c
, void *data
)
688 MIPSCPUClass
*mcc
= MIPS_CPU_CLASS(c
);
689 CPUClass
*cc
= CPU_CLASS(c
);
690 DeviceClass
*dc
= DEVICE_CLASS(c
);
692 device_class_set_parent_realize(dc
, mips_cpu_realizefn
,
693 &mcc
->parent_realize
);
694 device_class_set_parent_reset(dc
, mips_cpu_reset
, &mcc
->parent_reset
);
695 device_class_set_props(dc
, mips_cpu_properties
);
697 cc
->class_by_name
= mips_cpu_class_by_name
;
698 cc
->has_work
= mips_cpu_has_work
;
699 cc
->dump_state
= mips_cpu_dump_state
;
700 cc
->set_pc
= mips_cpu_set_pc
;
701 cc
->gdb_read_register
= mips_cpu_gdb_read_register
;
702 cc
->gdb_write_register
= mips_cpu_gdb_write_register
;
703 #ifndef CONFIG_USER_ONLY
704 cc
->get_phys_page_debug
= mips_cpu_get_phys_page_debug
;
705 cc
->vmsd
= &vmstate_mips_cpu
;
707 cc
->disas_set_info
= mips_cpu_disas_set_info
;
708 cc
->gdb_num_core_regs
= 73;
709 cc
->gdb_stop_before_watchpoint
= true;
711 cc
->tcg_ops
= &mips_tcg_ops
;
712 #endif /* CONFIG_TCG */
715 static const TypeInfo mips_cpu_type_info
= {
716 .name
= TYPE_MIPS_CPU
,
718 .instance_size
= sizeof(MIPSCPU
),
719 .instance_init
= mips_cpu_initfn
,
721 .class_size
= sizeof(MIPSCPUClass
),
722 .class_init
= mips_cpu_class_init
,
725 static void mips_cpu_cpudef_class_init(ObjectClass
*oc
, void *data
)
727 MIPSCPUClass
*mcc
= MIPS_CPU_CLASS(oc
);
731 static void mips_register_cpudef_type(const struct mips_def_t
*def
)
733 char *typename
= mips_cpu_type_name(def
->name
);
736 .parent
= TYPE_MIPS_CPU
,
737 .class_init
= mips_cpu_cpudef_class_init
,
738 .class_data
= (void *)def
,
745 static void mips_cpu_register_types(void)
749 type_register_static(&mips_cpu_type_info
);
750 for (i
= 0; i
< mips_defs_number
; i
++) {
751 mips_register_cpudef_type(&mips_defs
[i
]);
755 type_init(mips_cpu_register_types
)
757 static void mips_cpu_add_definition(gpointer data
, gpointer user_data
)
759 ObjectClass
*oc
= data
;
760 CpuDefinitionInfoList
**cpu_list
= user_data
;
761 CpuDefinitionInfo
*info
;
762 const char *typename
;
764 typename
= object_class_get_name(oc
);
765 info
= g_malloc0(sizeof(*info
));
766 info
->name
= g_strndup(typename
,
767 strlen(typename
) - strlen("-" TYPE_MIPS_CPU
));
768 info
->q_typename
= g_strdup(typename
);
770 QAPI_LIST_PREPEND(*cpu_list
, info
);
773 CpuDefinitionInfoList
*qmp_query_cpu_definitions(Error
**errp
)
775 CpuDefinitionInfoList
*cpu_list
= NULL
;
778 list
= object_class_get_list(TYPE_MIPS_CPU
, false);
779 g_slist_foreach(list
, mips_cpu_add_definition
, &cpu_list
);
785 /* Could be used by generic CPU object */
786 MIPSCPU
*mips_cpu_create_with_clock(const char *cpu_type
, Clock
*cpu_refclk
)
790 cpu
= DEVICE(object_new(cpu_type
));
791 qdev_connect_clock_in(cpu
, "clk-in", cpu_refclk
);
792 qdev_realize(cpu
, NULL
, &error_abort
);
794 return MIPS_CPU(cpu
);
797 bool cpu_supports_isa(const CPUMIPSState
*env
, uint64_t isa_mask
)
799 return (env
->cpu_model
->insn_flags
& isa_mask
) != 0;
802 bool cpu_type_supports_isa(const char *cpu_type
, uint64_t isa
)
804 const MIPSCPUClass
*mcc
= MIPS_CPU_CLASS(object_class_by_name(cpu_type
));
805 return (mcc
->cpu_def
->insn_flags
& isa
) != 0;
808 bool cpu_type_supports_cps_smp(const char *cpu_type
)
810 const MIPSCPUClass
*mcc
= MIPS_CPU_CLASS(object_class_by_name(cpu_type
));
811 return (mcc
->cpu_def
->CP0_Config3
& (1 << CP0C3_CMGCR
)) != 0;