2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 #include "hw/sysbus.h"
25 #include "qemu/error-report.h"
26 #include "qemu/timer.h"
27 #include "hw/sparc/sun4m.h"
28 #include "hw/timer/m48t59.h"
29 #include "hw/sparc/sparc32_dma.h"
30 #include "hw/block/fdc.h"
31 #include "sysemu/sysemu.h"
33 #include "hw/boards.h"
34 #include "hw/nvram/openbios_firmware_abi.h"
35 #include "hw/scsi/esp.h"
36 #include "hw/i386/pc.h"
37 #include "hw/isa/isa.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/char/escc.h"
40 #include "hw/empty_slot.h"
41 #include "hw/loader.h"
43 #include "sysemu/block-backend.h"
47 * Sun4m architecture was used in the following machines:
49 * SPARCserver 6xxMP/xx
50 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
51 * SPARCclassic X (4/10)
52 * SPARCstation LX/ZX (4/30)
53 * SPARCstation Voyager
54 * SPARCstation 10/xx, SPARCserver 10/xx
55 * SPARCstation 5, SPARCserver 5
56 * SPARCstation 20/xx, SPARCserver 20
59 * See for example: http://www.sunhelp.org/faq/sunref1.html
62 #define KERNEL_LOAD_ADDR 0x00004000
63 #define CMDLINE_ADDR 0x007ff000
64 #define INITRD_LOAD_ADDR 0x00800000
65 #define PROM_SIZE_MAX (1024 * 1024)
66 #define PROM_VADDR 0xffd00000
67 #define PROM_FILENAME "openbios-sparc32"
68 #define CFG_ADDR 0xd00000510ULL
69 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
70 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
71 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
77 #define ESCC_CLOCK 4915200
80 hwaddr iommu_base
, iommu_pad_base
, iommu_pad_len
, slavio_base
;
81 hwaddr intctl_base
, counter_base
, nvram_base
, ms_kb_base
;
82 hwaddr serial_base
, fd_base
;
83 hwaddr afx_base
, idreg_base
, dma_base
, esp_base
, le_base
;
84 hwaddr tcx_base
, cs_base
, apc_base
, aux1_base
, aux2_base
;
85 hwaddr bpp_base
, dbri_base
, sx_base
;
87 hwaddr reg_base
, vram_base
;
91 const char * const default_cpu_model
;
93 uint32_t iommu_version
;
95 uint8_t nvram_machine_id
;
98 int DMA_get_channel_mode (int nchan
)
102 int DMA_read_memory (int nchan
, void *buf
, int pos
, int size
)
106 int DMA_write_memory (int nchan
, void *buf
, int pos
, int size
)
110 void DMA_hold_DREQ (int nchan
) {}
111 void DMA_release_DREQ (int nchan
) {}
112 void DMA_schedule(int nchan
) {}
114 void DMA_init(int high_page_enable
, qemu_irq
*cpu_request_exit
)
118 void DMA_register_channel (int nchan
,
119 DMA_transfer_handler transfer_handler
,
124 static void fw_cfg_boot_set(void *opaque
, const char *boot_device
,
127 fw_cfg_modify_i16(opaque
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
130 static void nvram_init(Nvram
*nvram
, uint8_t *macaddr
,
131 const char *cmdline
, const char *boot_devices
,
132 ram_addr_t RAM_size
, uint32_t kernel_size
,
133 int width
, int height
, int depth
,
134 int nvram_machine_id
, const char *arch
)
138 uint8_t image
[0x1ff0];
139 struct OpenBIOS_nvpart_v1
*part_header
;
140 NvramClass
*k
= NVRAM_GET_CLASS(nvram
);
142 memset(image
, '\0', sizeof(image
));
146 // OpenBIOS nvram variables
147 // Variable partition
148 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
149 part_header
->signature
= OPENBIOS_PART_SYSTEM
;
150 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "system");
152 end
= start
+ sizeof(struct OpenBIOS_nvpart_v1
);
153 for (i
= 0; i
< nb_prom_envs
; i
++)
154 end
= OpenBIOS_set_var(image
, end
, prom_envs
[i
]);
159 end
= start
+ ((end
- start
+ 15) & ~15);
160 OpenBIOS_finish_partition(part_header
, end
- start
);
164 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
165 part_header
->signature
= OPENBIOS_PART_FREE
;
166 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "free");
169 OpenBIOS_finish_partition(part_header
, end
- start
);
171 Sun_init_header((struct Sun_nvram
*)&image
[0x1fd8], macaddr
,
174 for (i
= 0; i
< sizeof(image
); i
++) {
175 (k
->write
)(nvram
, i
, image
[i
]);
179 static DeviceState
*slavio_intctl
;
181 void sun4m_hmp_info_pic(Monitor
*mon
, const QDict
*qdict
)
184 slavio_pic_info(mon
, slavio_intctl
);
187 void sun4m_hmp_info_irq(Monitor
*mon
, const QDict
*qdict
)
190 slavio_irq_info(mon
, slavio_intctl
);
193 void cpu_check_irqs(CPUSPARCState
*env
)
197 if (env
->pil_in
&& (env
->interrupt_index
== 0 ||
198 (env
->interrupt_index
& ~15) == TT_EXTINT
)) {
201 for (i
= 15; i
> 0; i
--) {
202 if (env
->pil_in
& (1 << i
)) {
203 int old_interrupt
= env
->interrupt_index
;
205 env
->interrupt_index
= TT_EXTINT
| i
;
206 if (old_interrupt
!= env
->interrupt_index
) {
207 cs
= CPU(sparc_env_get_cpu(env
));
208 trace_sun4m_cpu_interrupt(i
);
209 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
214 } else if (!env
->pil_in
&& (env
->interrupt_index
& ~15) == TT_EXTINT
) {
215 cs
= CPU(sparc_env_get_cpu(env
));
216 trace_sun4m_cpu_reset_interrupt(env
->interrupt_index
& 15);
217 env
->interrupt_index
= 0;
218 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
222 static void cpu_kick_irq(SPARCCPU
*cpu
)
224 CPUSPARCState
*env
= &cpu
->env
;
225 CPUState
*cs
= CPU(cpu
);
232 static void cpu_set_irq(void *opaque
, int irq
, int level
)
234 SPARCCPU
*cpu
= opaque
;
235 CPUSPARCState
*env
= &cpu
->env
;
238 trace_sun4m_cpu_set_irq_raise(irq
);
239 env
->pil_in
|= 1 << irq
;
242 trace_sun4m_cpu_set_irq_lower(irq
);
243 env
->pil_in
&= ~(1 << irq
);
248 static void dummy_cpu_set_irq(void *opaque
, int irq
, int level
)
252 static void main_cpu_reset(void *opaque
)
254 SPARCCPU
*cpu
= opaque
;
255 CPUState
*cs
= CPU(cpu
);
261 static void secondary_cpu_reset(void *opaque
)
263 SPARCCPU
*cpu
= opaque
;
264 CPUState
*cs
= CPU(cpu
);
270 static void cpu_halt_signal(void *opaque
, int irq
, int level
)
272 if (level
&& current_cpu
) {
273 cpu_interrupt(current_cpu
, CPU_INTERRUPT_HALT
);
277 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
279 return addr
- 0xf0000000ULL
;
282 static unsigned long sun4m_load_kernel(const char *kernel_filename
,
283 const char *initrd_filename
,
288 long initrd_size
, kernel_size
;
291 linux_boot
= (kernel_filename
!= NULL
);
302 kernel_size
= load_elf(kernel_filename
, translate_kernel_address
, NULL
,
303 NULL
, NULL
, NULL
, 1, ELF_MACHINE
, 0);
305 kernel_size
= load_aout(kernel_filename
, KERNEL_LOAD_ADDR
,
306 RAM_size
- KERNEL_LOAD_ADDR
, bswap_needed
,
309 kernel_size
= load_image_targphys(kernel_filename
,
311 RAM_size
- KERNEL_LOAD_ADDR
);
312 if (kernel_size
< 0) {
313 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
320 if (initrd_filename
) {
321 initrd_size
= load_image_targphys(initrd_filename
,
323 RAM_size
- INITRD_LOAD_ADDR
);
324 if (initrd_size
< 0) {
325 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
330 if (initrd_size
> 0) {
331 for (i
= 0; i
< 64 * TARGET_PAGE_SIZE
; i
+= TARGET_PAGE_SIZE
) {
332 ptr
= rom_ptr(KERNEL_LOAD_ADDR
+ i
);
333 if (ldl_p(ptr
) == 0x48647253) { // HdrS
334 stl_p(ptr
+ 16, INITRD_LOAD_ADDR
);
335 stl_p(ptr
+ 20, initrd_size
);
344 static void *iommu_init(hwaddr addr
, uint32_t version
, qemu_irq irq
)
349 dev
= qdev_create(NULL
, "iommu");
350 qdev_prop_set_uint32(dev
, "version", version
);
351 qdev_init_nofail(dev
);
352 s
= SYS_BUS_DEVICE(dev
);
353 sysbus_connect_irq(s
, 0, irq
);
354 sysbus_mmio_map(s
, 0, addr
);
359 static void *sparc32_dma_init(hwaddr daddr
, qemu_irq parent_irq
,
360 void *iommu
, qemu_irq
*dev_irq
, int is_ledma
)
365 dev
= qdev_create(NULL
, "sparc32_dma");
366 qdev_prop_set_ptr(dev
, "iommu_opaque", iommu
);
367 qdev_prop_set_uint32(dev
, "is_ledma", is_ledma
);
368 qdev_init_nofail(dev
);
369 s
= SYS_BUS_DEVICE(dev
);
370 sysbus_connect_irq(s
, 0, parent_irq
);
371 *dev_irq
= qdev_get_gpio_in(dev
, 0);
372 sysbus_mmio_map(s
, 0, daddr
);
377 static void lance_init(NICInfo
*nd
, hwaddr leaddr
,
378 void *dma_opaque
, qemu_irq irq
)
384 qemu_check_nic_model(&nd_table
[0], "lance");
386 dev
= qdev_create(NULL
, "lance");
387 qdev_set_nic_properties(dev
, nd
);
388 qdev_prop_set_ptr(dev
, "dma", dma_opaque
);
389 qdev_init_nofail(dev
);
390 s
= SYS_BUS_DEVICE(dev
);
391 sysbus_mmio_map(s
, 0, leaddr
);
392 sysbus_connect_irq(s
, 0, irq
);
393 reset
= qdev_get_gpio_in(dev
, 0);
394 qdev_connect_gpio_out(dma_opaque
, 0, reset
);
397 static DeviceState
*slavio_intctl_init(hwaddr addr
,
399 qemu_irq
**parent_irq
)
405 dev
= qdev_create(NULL
, "slavio_intctl");
406 qdev_init_nofail(dev
);
408 s
= SYS_BUS_DEVICE(dev
);
410 for (i
= 0; i
< MAX_CPUS
; i
++) {
411 for (j
= 0; j
< MAX_PILS
; j
++) {
412 sysbus_connect_irq(s
, i
* MAX_PILS
+ j
, parent_irq
[i
][j
]);
415 sysbus_mmio_map(s
, 0, addrg
);
416 for (i
= 0; i
< MAX_CPUS
; i
++) {
417 sysbus_mmio_map(s
, i
+ 1, addr
+ i
* TARGET_PAGE_SIZE
);
423 #define SYS_TIMER_OFFSET 0x10000ULL
424 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
426 static void slavio_timer_init_all(hwaddr addr
, qemu_irq master_irq
,
427 qemu_irq
*cpu_irqs
, unsigned int num_cpus
)
433 dev
= qdev_create(NULL
, "slavio_timer");
434 qdev_prop_set_uint32(dev
, "num_cpus", num_cpus
);
435 qdev_init_nofail(dev
);
436 s
= SYS_BUS_DEVICE(dev
);
437 sysbus_connect_irq(s
, 0, master_irq
);
438 sysbus_mmio_map(s
, 0, addr
+ SYS_TIMER_OFFSET
);
440 for (i
= 0; i
< MAX_CPUS
; i
++) {
441 sysbus_mmio_map(s
, i
+ 1, addr
+ (hwaddr
)CPU_TIMER_OFFSET(i
));
442 sysbus_connect_irq(s
, i
+ 1, cpu_irqs
[i
]);
446 static qemu_irq slavio_system_powerdown
;
448 static void slavio_powerdown_req(Notifier
*n
, void *opaque
)
450 qemu_irq_raise(slavio_system_powerdown
);
453 static Notifier slavio_system_powerdown_notifier
= {
454 .notify
= slavio_powerdown_req
457 #define MISC_LEDS 0x01600000
458 #define MISC_CFG 0x01800000
459 #define MISC_DIAG 0x01a00000
460 #define MISC_MDM 0x01b00000
461 #define MISC_SYS 0x01f00000
463 static void slavio_misc_init(hwaddr base
,
465 hwaddr aux2_base
, qemu_irq irq
,
471 dev
= qdev_create(NULL
, "slavio_misc");
472 qdev_init_nofail(dev
);
473 s
= SYS_BUS_DEVICE(dev
);
475 /* 8 bit registers */
477 sysbus_mmio_map(s
, 0, base
+ MISC_CFG
);
479 sysbus_mmio_map(s
, 1, base
+ MISC_DIAG
);
481 sysbus_mmio_map(s
, 2, base
+ MISC_MDM
);
482 /* 16 bit registers */
483 /* ss600mp diag LEDs */
484 sysbus_mmio_map(s
, 3, base
+ MISC_LEDS
);
485 /* 32 bit registers */
487 sysbus_mmio_map(s
, 4, base
+ MISC_SYS
);
490 /* AUX 1 (Misc System Functions) */
491 sysbus_mmio_map(s
, 5, aux1_base
);
494 /* AUX 2 (Software Powerdown Control) */
495 sysbus_mmio_map(s
, 6, aux2_base
);
497 sysbus_connect_irq(s
, 0, irq
);
498 sysbus_connect_irq(s
, 1, fdc_tc
);
499 slavio_system_powerdown
= qdev_get_gpio_in(dev
, 0);
500 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier
);
503 static void ecc_init(hwaddr base
, qemu_irq irq
, uint32_t version
)
508 dev
= qdev_create(NULL
, "eccmemctl");
509 qdev_prop_set_uint32(dev
, "version", version
);
510 qdev_init_nofail(dev
);
511 s
= SYS_BUS_DEVICE(dev
);
512 sysbus_connect_irq(s
, 0, irq
);
513 sysbus_mmio_map(s
, 0, base
);
514 if (version
== 0) { // SS-600MP only
515 sysbus_mmio_map(s
, 1, base
+ 0x1000);
519 static void apc_init(hwaddr power_base
, qemu_irq cpu_halt
)
524 dev
= qdev_create(NULL
, "apc");
525 qdev_init_nofail(dev
);
526 s
= SYS_BUS_DEVICE(dev
);
527 /* Power management (APC) XXX: not a Slavio device */
528 sysbus_mmio_map(s
, 0, power_base
);
529 sysbus_connect_irq(s
, 0, cpu_halt
);
532 static void tcx_init(hwaddr addr
, qemu_irq irq
, int vram_size
, int width
,
533 int height
, int depth
)
538 dev
= qdev_create(NULL
, "SUNW,tcx");
539 qdev_prop_set_uint32(dev
, "vram_size", vram_size
);
540 qdev_prop_set_uint16(dev
, "width", width
);
541 qdev_prop_set_uint16(dev
, "height", height
);
542 qdev_prop_set_uint16(dev
, "depth", depth
);
543 qdev_prop_set_uint64(dev
, "prom_addr", addr
);
544 qdev_init_nofail(dev
);
545 s
= SYS_BUS_DEVICE(dev
);
547 /* 10/ROM : FCode ROM */
548 sysbus_mmio_map(s
, 0, addr
);
549 /* 2/STIP : Stipple */
550 sysbus_mmio_map(s
, 1, addr
+ 0x04000000ULL
);
551 /* 3/BLIT : Blitter */
552 sysbus_mmio_map(s
, 2, addr
+ 0x06000000ULL
);
553 /* 5/RSTIP : Raw Stipple */
554 sysbus_mmio_map(s
, 3, addr
+ 0x0c000000ULL
);
555 /* 6/RBLIT : Raw Blitter */
556 sysbus_mmio_map(s
, 4, addr
+ 0x0e000000ULL
);
557 /* 7/TEC : Transform Engine */
558 sysbus_mmio_map(s
, 5, addr
+ 0x00700000ULL
);
560 sysbus_mmio_map(s
, 6, addr
+ 0x00200000ULL
);
563 sysbus_mmio_map(s
, 7, addr
+ 0x00300000ULL
);
565 sysbus_mmio_map(s
, 7, addr
+ 0x00301000ULL
);
568 sysbus_mmio_map(s
, 8, addr
+ 0x00240000ULL
);
570 sysbus_mmio_map(s
, 9, addr
+ 0x00280000ULL
);
571 /* 0/DFB8 : 8-bit plane */
572 sysbus_mmio_map(s
, 10, addr
+ 0x00800000ULL
);
573 /* 1/DFB24 : 24bit plane */
574 sysbus_mmio_map(s
, 11, addr
+ 0x02000000ULL
);
575 /* 4/RDFB32: Raw framebuffer. Control plane */
576 sysbus_mmio_map(s
, 12, addr
+ 0x0a000000ULL
);
577 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
579 sysbus_mmio_map(s
, 13, addr
+ 0x00301000ULL
);
582 sysbus_connect_irq(s
, 0, irq
);
585 static void cg3_init(hwaddr addr
, qemu_irq irq
, int vram_size
, int width
,
586 int height
, int depth
)
591 dev
= qdev_create(NULL
, "cgthree");
592 qdev_prop_set_uint32(dev
, "vram-size", vram_size
);
593 qdev_prop_set_uint16(dev
, "width", width
);
594 qdev_prop_set_uint16(dev
, "height", height
);
595 qdev_prop_set_uint16(dev
, "depth", depth
);
596 qdev_prop_set_uint64(dev
, "prom-addr", addr
);
597 qdev_init_nofail(dev
);
598 s
= SYS_BUS_DEVICE(dev
);
601 sysbus_mmio_map(s
, 0, addr
);
603 sysbus_mmio_map(s
, 1, addr
+ 0x400000ULL
);
605 sysbus_mmio_map(s
, 2, addr
+ 0x800000ULL
);
607 sysbus_connect_irq(s
, 0, irq
);
610 /* NCR89C100/MACIO Internal ID register */
612 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
614 static const uint8_t idreg_data
[] = { 0xfe, 0x81, 0x01, 0x03 };
616 static void idreg_init(hwaddr addr
)
621 dev
= qdev_create(NULL
, TYPE_MACIO_ID_REGISTER
);
622 qdev_init_nofail(dev
);
623 s
= SYS_BUS_DEVICE(dev
);
625 sysbus_mmio_map(s
, 0, addr
);
626 cpu_physical_memory_write_rom(&address_space_memory
,
627 addr
, idreg_data
, sizeof(idreg_data
));
630 #define MACIO_ID_REGISTER(obj) \
631 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
633 typedef struct IDRegState
{
634 SysBusDevice parent_obj
;
639 static int idreg_init1(SysBusDevice
*dev
)
641 IDRegState
*s
= MACIO_ID_REGISTER(dev
);
643 memory_region_init_ram(&s
->mem
, OBJECT(s
),
644 "sun4m.idreg", sizeof(idreg_data
), &error_abort
);
645 vmstate_register_ram_global(&s
->mem
);
646 memory_region_set_readonly(&s
->mem
, true);
647 sysbus_init_mmio(dev
, &s
->mem
);
651 static void idreg_class_init(ObjectClass
*klass
, void *data
)
653 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
655 k
->init
= idreg_init1
;
658 static const TypeInfo idreg_info
= {
659 .name
= TYPE_MACIO_ID_REGISTER
,
660 .parent
= TYPE_SYS_BUS_DEVICE
,
661 .instance_size
= sizeof(IDRegState
),
662 .class_init
= idreg_class_init
,
665 #define TYPE_TCX_AFX "tcx_afx"
666 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
668 typedef struct AFXState
{
669 SysBusDevice parent_obj
;
674 /* SS-5 TCX AFX register */
675 static void afx_init(hwaddr addr
)
680 dev
= qdev_create(NULL
, TYPE_TCX_AFX
);
681 qdev_init_nofail(dev
);
682 s
= SYS_BUS_DEVICE(dev
);
684 sysbus_mmio_map(s
, 0, addr
);
687 static int afx_init1(SysBusDevice
*dev
)
689 AFXState
*s
= TCX_AFX(dev
);
691 memory_region_init_ram(&s
->mem
, OBJECT(s
), "sun4m.afx", 4, &error_abort
);
692 vmstate_register_ram_global(&s
->mem
);
693 sysbus_init_mmio(dev
, &s
->mem
);
697 static void afx_class_init(ObjectClass
*klass
, void *data
)
699 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
704 static const TypeInfo afx_info
= {
705 .name
= TYPE_TCX_AFX
,
706 .parent
= TYPE_SYS_BUS_DEVICE
,
707 .instance_size
= sizeof(AFXState
),
708 .class_init
= afx_class_init
,
711 #define TYPE_OPENPROM "openprom"
712 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
714 typedef struct PROMState
{
715 SysBusDevice parent_obj
;
720 /* Boot PROM (OpenBIOS) */
721 static uint64_t translate_prom_address(void *opaque
, uint64_t addr
)
723 hwaddr
*base_addr
= (hwaddr
*)opaque
;
724 return addr
+ *base_addr
- PROM_VADDR
;
727 static void prom_init(hwaddr addr
, const char *bios_name
)
734 dev
= qdev_create(NULL
, TYPE_OPENPROM
);
735 qdev_init_nofail(dev
);
736 s
= SYS_BUS_DEVICE(dev
);
738 sysbus_mmio_map(s
, 0, addr
);
741 if (bios_name
== NULL
) {
742 bios_name
= PROM_FILENAME
;
744 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
746 ret
= load_elf(filename
, translate_prom_address
, &addr
, NULL
,
747 NULL
, NULL
, 1, ELF_MACHINE
, 0);
748 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
749 ret
= load_image_targphys(filename
, addr
, PROM_SIZE_MAX
);
755 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
756 fprintf(stderr
, "qemu: could not load prom '%s'\n", bios_name
);
761 static int prom_init1(SysBusDevice
*dev
)
763 PROMState
*s
= OPENPROM(dev
);
765 memory_region_init_ram(&s
->prom
, OBJECT(s
), "sun4m.prom", PROM_SIZE_MAX
,
767 vmstate_register_ram_global(&s
->prom
);
768 memory_region_set_readonly(&s
->prom
, true);
769 sysbus_init_mmio(dev
, &s
->prom
);
773 static Property prom_properties
[] = {
774 {/* end of property list */},
777 static void prom_class_init(ObjectClass
*klass
, void *data
)
779 DeviceClass
*dc
= DEVICE_CLASS(klass
);
780 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
782 k
->init
= prom_init1
;
783 dc
->props
= prom_properties
;
786 static const TypeInfo prom_info
= {
787 .name
= TYPE_OPENPROM
,
788 .parent
= TYPE_SYS_BUS_DEVICE
,
789 .instance_size
= sizeof(PROMState
),
790 .class_init
= prom_class_init
,
793 #define TYPE_SUN4M_MEMORY "memory"
794 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
796 typedef struct RamDevice
{
797 SysBusDevice parent_obj
;
804 static int ram_init1(SysBusDevice
*dev
)
806 RamDevice
*d
= SUN4M_RAM(dev
);
808 memory_region_allocate_system_memory(&d
->ram
, OBJECT(d
), "sun4m.ram",
810 sysbus_init_mmio(dev
, &d
->ram
);
814 static void ram_init(hwaddr addr
, ram_addr_t RAM_size
,
822 if ((uint64_t)RAM_size
> max_mem
) {
824 "qemu: Too much memory for this machine: %d, maximum %d\n",
825 (unsigned int)(RAM_size
/ (1024 * 1024)),
826 (unsigned int)(max_mem
/ (1024 * 1024)));
829 dev
= qdev_create(NULL
, "memory");
830 s
= SYS_BUS_DEVICE(dev
);
834 qdev_init_nofail(dev
);
836 sysbus_mmio_map(s
, 0, addr
);
839 static Property ram_properties
[] = {
840 DEFINE_PROP_UINT64("size", RamDevice
, size
, 0),
841 DEFINE_PROP_END_OF_LIST(),
844 static void ram_class_init(ObjectClass
*klass
, void *data
)
846 DeviceClass
*dc
= DEVICE_CLASS(klass
);
847 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
850 dc
->props
= ram_properties
;
853 static const TypeInfo ram_info
= {
854 .name
= TYPE_SUN4M_MEMORY
,
855 .parent
= TYPE_SYS_BUS_DEVICE
,
856 .instance_size
= sizeof(RamDevice
),
857 .class_init
= ram_class_init
,
860 static void cpu_devinit(const char *cpu_model
, unsigned int id
,
861 uint64_t prom_addr
, qemu_irq
**cpu_irqs
)
867 cpu
= cpu_sparc_init(cpu_model
);
869 fprintf(stderr
, "qemu: Unable to find Sparc CPU definition\n");
874 cpu_sparc_set_id(env
, id
);
876 qemu_register_reset(main_cpu_reset
, cpu
);
878 qemu_register_reset(secondary_cpu_reset
, cpu
);
882 *cpu_irqs
= qemu_allocate_irqs(cpu_set_irq
, cpu
, MAX_PILS
);
883 env
->prom_addr
= prom_addr
;
886 static void dummy_fdc_tc(void *opaque
, int irq
, int level
)
890 static void sun4m_hw_init(const struct sun4m_hwdef
*hwdef
,
891 MachineState
*machine
)
893 const char *cpu_model
= machine
->cpu_model
;
895 void *iommu
, *espdma
, *ledma
, *nvram
;
896 qemu_irq
*cpu_irqs
[MAX_CPUS
], slavio_irq
[32], slavio_cpu_irq
[MAX_CPUS
],
897 espdma_irq
, ledma_irq
;
898 qemu_irq esp_reset
, dma_enable
;
900 unsigned long kernel_size
;
901 DriveInfo
*fd
[MAX_FD
];
903 unsigned int num_vsimms
;
907 cpu_model
= hwdef
->default_cpu_model
;
909 for(i
= 0; i
< smp_cpus
; i
++) {
910 cpu_devinit(cpu_model
, i
, hwdef
->slavio_base
, &cpu_irqs
[i
]);
913 for (i
= smp_cpus
; i
< MAX_CPUS
; i
++)
914 cpu_irqs
[i
] = qemu_allocate_irqs(dummy_cpu_set_irq
, NULL
, MAX_PILS
);
918 ram_init(0, machine
->ram_size
, hwdef
->max_mem
);
919 /* models without ECC don't trap when missing ram is accessed */
920 if (!hwdef
->ecc_base
) {
921 empty_slot_init(machine
->ram_size
, hwdef
->max_mem
- machine
->ram_size
);
924 prom_init(hwdef
->slavio_base
, bios_name
);
926 slavio_intctl
= slavio_intctl_init(hwdef
->intctl_base
,
927 hwdef
->intctl_base
+ 0x10000ULL
,
930 for (i
= 0; i
< 32; i
++) {
931 slavio_irq
[i
] = qdev_get_gpio_in(slavio_intctl
, i
);
933 for (i
= 0; i
< MAX_CPUS
; i
++) {
934 slavio_cpu_irq
[i
] = qdev_get_gpio_in(slavio_intctl
, 32 + i
);
937 if (hwdef
->idreg_base
) {
938 idreg_init(hwdef
->idreg_base
);
941 if (hwdef
->afx_base
) {
942 afx_init(hwdef
->afx_base
);
945 iommu
= iommu_init(hwdef
->iommu_base
, hwdef
->iommu_version
,
948 if (hwdef
->iommu_pad_base
) {
949 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
950 Software shouldn't use aliased addresses, neither should it crash
951 when does. Using empty_slot instead of aliasing can help with
952 debugging such accesses */
953 empty_slot_init(hwdef
->iommu_pad_base
,hwdef
->iommu_pad_len
);
956 espdma
= sparc32_dma_init(hwdef
->dma_base
, slavio_irq
[18],
957 iommu
, &espdma_irq
, 0);
959 ledma
= sparc32_dma_init(hwdef
->dma_base
+ 16ULL,
960 slavio_irq
[16], iommu
, &ledma_irq
, 1);
962 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
963 error_report("Unsupported depth: %d", graphic_depth
);
967 if (num_vsimms
== 0) {
968 if (vga_interface_type
== VGA_CG3
) {
969 if (graphic_depth
!= 8) {
970 error_report("Unsupported depth: %d", graphic_depth
);
974 if (!(graphic_width
== 1024 && graphic_height
== 768) &&
975 !(graphic_width
== 1152 && graphic_height
== 900)) {
976 error_report("Unsupported resolution: %d x %d", graphic_width
,
982 cg3_init(hwdef
->tcx_base
, slavio_irq
[11], 0x00100000,
983 graphic_width
, graphic_height
, graphic_depth
);
985 /* If no display specified, default to TCX */
986 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
987 error_report("Unsupported depth: %d", graphic_depth
);
991 if (!(graphic_width
== 1024 && graphic_height
== 768)) {
992 error_report("Unsupported resolution: %d x %d",
993 graphic_width
, graphic_height
);
997 tcx_init(hwdef
->tcx_base
, slavio_irq
[11], 0x00100000,
998 graphic_width
, graphic_height
, graphic_depth
);
1002 for (i
= num_vsimms
; i
< MAX_VSIMMS
; i
++) {
1003 /* vsimm registers probed by OBP */
1004 if (hwdef
->vsimm
[i
].reg_base
) {
1005 empty_slot_init(hwdef
->vsimm
[i
].reg_base
, 0x2000);
1009 if (hwdef
->sx_base
) {
1010 empty_slot_init(hwdef
->sx_base
, 0x2000);
1013 lance_init(&nd_table
[0], hwdef
->le_base
, ledma
, ledma_irq
);
1015 nvram
= m48t59_init(slavio_irq
[0], hwdef
->nvram_base
, 0, 0x2000, 1968, 8);
1017 slavio_timer_init_all(hwdef
->counter_base
, slavio_irq
[19], slavio_cpu_irq
, smp_cpus
);
1019 slavio_serial_ms_kbd_init(hwdef
->ms_kb_base
, slavio_irq
[14],
1020 display_type
== DT_NOGRAPHIC
, ESCC_CLOCK
, 1);
1021 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1022 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1023 escc_init(hwdef
->serial_base
, slavio_irq
[15], slavio_irq
[15],
1024 serial_hds
[0], serial_hds
[1], ESCC_CLOCK
, 1);
1026 if (hwdef
->apc_base
) {
1027 apc_init(hwdef
->apc_base
, qemu_allocate_irq(cpu_halt_signal
, NULL
, 0));
1030 if (hwdef
->fd_base
) {
1031 /* there is zero or one floppy drive */
1032 memset(fd
, 0, sizeof(fd
));
1033 fd
[0] = drive_get(IF_FLOPPY
, 0, 0);
1034 sun4m_fdctrl_init(slavio_irq
[22], hwdef
->fd_base
, fd
,
1037 fdc_tc
= qemu_allocate_irq(dummy_fdc_tc
, NULL
, 0);
1040 slavio_misc_init(hwdef
->slavio_base
, hwdef
->aux1_base
, hwdef
->aux2_base
,
1041 slavio_irq
[30], fdc_tc
);
1043 if (drive_get_max_bus(IF_SCSI
) > 0) {
1044 fprintf(stderr
, "qemu: too many SCSI bus\n");
1048 esp_init(hwdef
->esp_base
, 2,
1049 espdma_memory_read
, espdma_memory_write
,
1050 espdma
, espdma_irq
, &esp_reset
, &dma_enable
);
1052 qdev_connect_gpio_out(espdma
, 0, esp_reset
);
1053 qdev_connect_gpio_out(espdma
, 1, dma_enable
);
1055 if (hwdef
->cs_base
) {
1056 sysbus_create_simple("SUNW,CS4231", hwdef
->cs_base
,
1060 if (hwdef
->dbri_base
) {
1061 /* ISDN chip with attached CS4215 audio codec */
1063 empty_slot_init(hwdef
->dbri_base
+0x1000, 0x30);
1065 empty_slot_init(hwdef
->dbri_base
+0x10000, 0x100);
1068 if (hwdef
->bpp_base
) {
1070 empty_slot_init(hwdef
->bpp_base
, 0x20);
1073 kernel_size
= sun4m_load_kernel(machine
->kernel_filename
,
1074 machine
->initrd_filename
,
1077 nvram_init(nvram
, (uint8_t *)&nd_table
[0].macaddr
, machine
->kernel_cmdline
,
1078 machine
->boot_order
, machine
->ram_size
, kernel_size
,
1079 graphic_width
, graphic_height
, graphic_depth
,
1080 hwdef
->nvram_machine_id
, "Sun4m");
1082 if (hwdef
->ecc_base
)
1083 ecc_init(hwdef
->ecc_base
, slavio_irq
[28],
1084 hwdef
->ecc_version
);
1086 fw_cfg
= fw_cfg_init_mem(CFG_ADDR
, CFG_ADDR
+ 2);
1087 fw_cfg_add_i16(fw_cfg
, FW_CFG_MAX_CPUS
, (uint16_t)max_cpus
);
1088 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
1089 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
1090 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_DEPTH
, graphic_depth
);
1091 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_WIDTH
, graphic_width
);
1092 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_HEIGHT
, graphic_height
);
1093 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
1094 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1095 if (machine
->kernel_cmdline
) {
1096 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, CMDLINE_ADDR
);
1097 pstrcpy_targphys("cmdline", CMDLINE_ADDR
, TARGET_PAGE_SIZE
,
1098 machine
->kernel_cmdline
);
1099 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
, machine
->kernel_cmdline
);
1100 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
,
1101 strlen(machine
->kernel_cmdline
) + 1);
1103 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, 0);
1104 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, 0);
1106 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
1107 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, 0); // not used
1108 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, machine
->boot_order
[0]);
1109 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
1124 static const struct sun4m_hwdef sun4m_hwdefs
[] = {
1127 .iommu_base
= 0x10000000,
1128 .iommu_pad_base
= 0x10004000,
1129 .iommu_pad_len
= 0x0fffb000,
1130 .tcx_base
= 0x50000000,
1131 .cs_base
= 0x6c000000,
1132 .slavio_base
= 0x70000000,
1133 .ms_kb_base
= 0x71000000,
1134 .serial_base
= 0x71100000,
1135 .nvram_base
= 0x71200000,
1136 .fd_base
= 0x71400000,
1137 .counter_base
= 0x71d00000,
1138 .intctl_base
= 0x71e00000,
1139 .idreg_base
= 0x78000000,
1140 .dma_base
= 0x78400000,
1141 .esp_base
= 0x78800000,
1142 .le_base
= 0x78c00000,
1143 .apc_base
= 0x6a000000,
1144 .afx_base
= 0x6e000000,
1145 .aux1_base
= 0x71900000,
1146 .aux2_base
= 0x71910000,
1147 .nvram_machine_id
= 0x80,
1148 .machine_id
= ss5_id
,
1149 .iommu_version
= 0x05000000,
1150 .max_mem
= 0x10000000,
1151 .default_cpu_model
= "Fujitsu MB86904",
1155 .iommu_base
= 0xfe0000000ULL
,
1156 .tcx_base
= 0xe20000000ULL
,
1157 .slavio_base
= 0xff0000000ULL
,
1158 .ms_kb_base
= 0xff1000000ULL
,
1159 .serial_base
= 0xff1100000ULL
,
1160 .nvram_base
= 0xff1200000ULL
,
1161 .fd_base
= 0xff1700000ULL
,
1162 .counter_base
= 0xff1300000ULL
,
1163 .intctl_base
= 0xff1400000ULL
,
1164 .idreg_base
= 0xef0000000ULL
,
1165 .dma_base
= 0xef0400000ULL
,
1166 .esp_base
= 0xef0800000ULL
,
1167 .le_base
= 0xef0c00000ULL
,
1168 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1169 .aux1_base
= 0xff1800000ULL
,
1170 .aux2_base
= 0xff1a01000ULL
,
1171 .ecc_base
= 0xf00000000ULL
,
1172 .ecc_version
= 0x10000000, // version 0, implementation 1
1173 .nvram_machine_id
= 0x72,
1174 .machine_id
= ss10_id
,
1175 .iommu_version
= 0x03000000,
1176 .max_mem
= 0xf00000000ULL
,
1177 .default_cpu_model
= "TI SuperSparc II",
1181 .iommu_base
= 0xfe0000000ULL
,
1182 .tcx_base
= 0xe20000000ULL
,
1183 .slavio_base
= 0xff0000000ULL
,
1184 .ms_kb_base
= 0xff1000000ULL
,
1185 .serial_base
= 0xff1100000ULL
,
1186 .nvram_base
= 0xff1200000ULL
,
1187 .counter_base
= 0xff1300000ULL
,
1188 .intctl_base
= 0xff1400000ULL
,
1189 .dma_base
= 0xef0081000ULL
,
1190 .esp_base
= 0xef0080000ULL
,
1191 .le_base
= 0xef0060000ULL
,
1192 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1193 .aux1_base
= 0xff1800000ULL
,
1194 .aux2_base
= 0xff1a01000ULL
, // XXX should not exist
1195 .ecc_base
= 0xf00000000ULL
,
1196 .ecc_version
= 0x00000000, // version 0, implementation 0
1197 .nvram_machine_id
= 0x71,
1198 .machine_id
= ss600mp_id
,
1199 .iommu_version
= 0x01000000,
1200 .max_mem
= 0xf00000000ULL
,
1201 .default_cpu_model
= "TI SuperSparc II",
1205 .iommu_base
= 0xfe0000000ULL
,
1206 .tcx_base
= 0xe20000000ULL
,
1207 .slavio_base
= 0xff0000000ULL
,
1208 .ms_kb_base
= 0xff1000000ULL
,
1209 .serial_base
= 0xff1100000ULL
,
1210 .nvram_base
= 0xff1200000ULL
,
1211 .fd_base
= 0xff1700000ULL
,
1212 .counter_base
= 0xff1300000ULL
,
1213 .intctl_base
= 0xff1400000ULL
,
1214 .idreg_base
= 0xef0000000ULL
,
1215 .dma_base
= 0xef0400000ULL
,
1216 .esp_base
= 0xef0800000ULL
,
1217 .le_base
= 0xef0c00000ULL
,
1218 .bpp_base
= 0xef4800000ULL
,
1219 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1220 .aux1_base
= 0xff1800000ULL
,
1221 .aux2_base
= 0xff1a01000ULL
,
1222 .dbri_base
= 0xee0000000ULL
,
1223 .sx_base
= 0xf80000000ULL
,
1226 .reg_base
= 0x9c000000ULL
,
1227 .vram_base
= 0xfc000000ULL
1229 .reg_base
= 0x90000000ULL
,
1230 .vram_base
= 0xf0000000ULL
1232 .reg_base
= 0x94000000ULL
1234 .reg_base
= 0x98000000ULL
1237 .ecc_base
= 0xf00000000ULL
,
1238 .ecc_version
= 0x20000000, // version 0, implementation 2
1239 .nvram_machine_id
= 0x72,
1240 .machine_id
= ss20_id
,
1241 .iommu_version
= 0x13000000,
1242 .max_mem
= 0xf00000000ULL
,
1243 .default_cpu_model
= "TI SuperSparc II",
1247 .iommu_base
= 0x10000000,
1248 .tcx_base
= 0x50000000,
1249 .slavio_base
= 0x70000000,
1250 .ms_kb_base
= 0x71000000,
1251 .serial_base
= 0x71100000,
1252 .nvram_base
= 0x71200000,
1253 .fd_base
= 0x71400000,
1254 .counter_base
= 0x71d00000,
1255 .intctl_base
= 0x71e00000,
1256 .idreg_base
= 0x78000000,
1257 .dma_base
= 0x78400000,
1258 .esp_base
= 0x78800000,
1259 .le_base
= 0x78c00000,
1260 .apc_base
= 0x71300000, // pmc
1261 .aux1_base
= 0x71900000,
1262 .aux2_base
= 0x71910000,
1263 .nvram_machine_id
= 0x80,
1264 .machine_id
= vger_id
,
1265 .iommu_version
= 0x05000000,
1266 .max_mem
= 0x10000000,
1267 .default_cpu_model
= "Fujitsu MB86904",
1271 .iommu_base
= 0x10000000,
1272 .iommu_pad_base
= 0x10004000,
1273 .iommu_pad_len
= 0x0fffb000,
1274 .tcx_base
= 0x50000000,
1275 .slavio_base
= 0x70000000,
1276 .ms_kb_base
= 0x71000000,
1277 .serial_base
= 0x71100000,
1278 .nvram_base
= 0x71200000,
1279 .fd_base
= 0x71400000,
1280 .counter_base
= 0x71d00000,
1281 .intctl_base
= 0x71e00000,
1282 .idreg_base
= 0x78000000,
1283 .dma_base
= 0x78400000,
1284 .esp_base
= 0x78800000,
1285 .le_base
= 0x78c00000,
1286 .aux1_base
= 0x71900000,
1287 .aux2_base
= 0x71910000,
1288 .nvram_machine_id
= 0x80,
1289 .machine_id
= lx_id
,
1290 .iommu_version
= 0x04000000,
1291 .max_mem
= 0x10000000,
1292 .default_cpu_model
= "TI MicroSparc I",
1296 .iommu_base
= 0x10000000,
1297 .tcx_base
= 0x50000000,
1298 .cs_base
= 0x6c000000,
1299 .slavio_base
= 0x70000000,
1300 .ms_kb_base
= 0x71000000,
1301 .serial_base
= 0x71100000,
1302 .nvram_base
= 0x71200000,
1303 .fd_base
= 0x71400000,
1304 .counter_base
= 0x71d00000,
1305 .intctl_base
= 0x71e00000,
1306 .idreg_base
= 0x78000000,
1307 .dma_base
= 0x78400000,
1308 .esp_base
= 0x78800000,
1309 .le_base
= 0x78c00000,
1310 .apc_base
= 0x6a000000,
1311 .aux1_base
= 0x71900000,
1312 .aux2_base
= 0x71910000,
1313 .nvram_machine_id
= 0x80,
1314 .machine_id
= ss4_id
,
1315 .iommu_version
= 0x05000000,
1316 .max_mem
= 0x10000000,
1317 .default_cpu_model
= "Fujitsu MB86904",
1321 .iommu_base
= 0x10000000,
1322 .tcx_base
= 0x50000000,
1323 .slavio_base
= 0x70000000,
1324 .ms_kb_base
= 0x71000000,
1325 .serial_base
= 0x71100000,
1326 .nvram_base
= 0x71200000,
1327 .fd_base
= 0x71400000,
1328 .counter_base
= 0x71d00000,
1329 .intctl_base
= 0x71e00000,
1330 .idreg_base
= 0x78000000,
1331 .dma_base
= 0x78400000,
1332 .esp_base
= 0x78800000,
1333 .le_base
= 0x78c00000,
1334 .apc_base
= 0x6a000000,
1335 .aux1_base
= 0x71900000,
1336 .aux2_base
= 0x71910000,
1337 .nvram_machine_id
= 0x80,
1338 .machine_id
= scls_id
,
1339 .iommu_version
= 0x05000000,
1340 .max_mem
= 0x10000000,
1341 .default_cpu_model
= "TI MicroSparc I",
1345 .iommu_base
= 0x10000000,
1346 .tcx_base
= 0x50000000, // XXX
1347 .slavio_base
= 0x70000000,
1348 .ms_kb_base
= 0x71000000,
1349 .serial_base
= 0x71100000,
1350 .nvram_base
= 0x71200000,
1351 .fd_base
= 0x71400000,
1352 .counter_base
= 0x71d00000,
1353 .intctl_base
= 0x71e00000,
1354 .idreg_base
= 0x78000000,
1355 .dma_base
= 0x78400000,
1356 .esp_base
= 0x78800000,
1357 .le_base
= 0x78c00000,
1358 .apc_base
= 0x6a000000,
1359 .aux1_base
= 0x71900000,
1360 .aux2_base
= 0x71910000,
1361 .nvram_machine_id
= 0x80,
1362 .machine_id
= sbook_id
,
1363 .iommu_version
= 0x05000000,
1364 .max_mem
= 0x10000000,
1365 .default_cpu_model
= "TI MicroSparc I",
1369 /* SPARCstation 5 hardware initialisation */
1370 static void ss5_init(MachineState
*machine
)
1372 sun4m_hw_init(&sun4m_hwdefs
[0], machine
);
1375 /* SPARCstation 10 hardware initialisation */
1376 static void ss10_init(MachineState
*machine
)
1378 sun4m_hw_init(&sun4m_hwdefs
[1], machine
);
1381 /* SPARCserver 600MP hardware initialisation */
1382 static void ss600mp_init(MachineState
*machine
)
1384 sun4m_hw_init(&sun4m_hwdefs
[2], machine
);
1387 /* SPARCstation 20 hardware initialisation */
1388 static void ss20_init(MachineState
*machine
)
1390 sun4m_hw_init(&sun4m_hwdefs
[3], machine
);
1393 /* SPARCstation Voyager hardware initialisation */
1394 static void vger_init(MachineState
*machine
)
1396 sun4m_hw_init(&sun4m_hwdefs
[4], machine
);
1399 /* SPARCstation LX hardware initialisation */
1400 static void ss_lx_init(MachineState
*machine
)
1402 sun4m_hw_init(&sun4m_hwdefs
[5], machine
);
1405 /* SPARCstation 4 hardware initialisation */
1406 static void ss4_init(MachineState
*machine
)
1408 sun4m_hw_init(&sun4m_hwdefs
[6], machine
);
1411 /* SPARCClassic hardware initialisation */
1412 static void scls_init(MachineState
*machine
)
1414 sun4m_hw_init(&sun4m_hwdefs
[7], machine
);
1417 /* SPARCbook hardware initialisation */
1418 static void sbook_init(MachineState
*machine
)
1420 sun4m_hw_init(&sun4m_hwdefs
[8], machine
);
1423 static QEMUMachine ss5_machine
= {
1425 .desc
= "Sun4m platform, SPARCstation 5",
1427 .block_default_type
= IF_SCSI
,
1429 .default_boot_order
= "c",
1432 static QEMUMachine ss10_machine
= {
1434 .desc
= "Sun4m platform, SPARCstation 10",
1436 .block_default_type
= IF_SCSI
,
1438 .default_boot_order
= "c",
1441 static QEMUMachine ss600mp_machine
= {
1443 .desc
= "Sun4m platform, SPARCserver 600MP",
1444 .init
= ss600mp_init
,
1445 .block_default_type
= IF_SCSI
,
1447 .default_boot_order
= "c",
1450 static QEMUMachine ss20_machine
= {
1452 .desc
= "Sun4m platform, SPARCstation 20",
1454 .block_default_type
= IF_SCSI
,
1456 .default_boot_order
= "c",
1459 static QEMUMachine voyager_machine
= {
1461 .desc
= "Sun4m platform, SPARCstation Voyager",
1463 .block_default_type
= IF_SCSI
,
1464 .default_boot_order
= "c",
1467 static QEMUMachine ss_lx_machine
= {
1469 .desc
= "Sun4m platform, SPARCstation LX",
1471 .block_default_type
= IF_SCSI
,
1472 .default_boot_order
= "c",
1475 static QEMUMachine ss4_machine
= {
1477 .desc
= "Sun4m platform, SPARCstation 4",
1479 .block_default_type
= IF_SCSI
,
1480 .default_boot_order
= "c",
1483 static QEMUMachine scls_machine
= {
1484 .name
= "SPARCClassic",
1485 .desc
= "Sun4m platform, SPARCClassic",
1487 .block_default_type
= IF_SCSI
,
1488 .default_boot_order
= "c",
1491 static QEMUMachine sbook_machine
= {
1492 .name
= "SPARCbook",
1493 .desc
= "Sun4m platform, SPARCbook",
1495 .block_default_type
= IF_SCSI
,
1496 .default_boot_order
= "c",
1499 static void sun4m_register_types(void)
1501 type_register_static(&idreg_info
);
1502 type_register_static(&afx_info
);
1503 type_register_static(&prom_info
);
1504 type_register_static(&ram_info
);
1507 static void sun4m_machine_init(void)
1509 qemu_register_machine(&ss5_machine
);
1510 qemu_register_machine(&ss10_machine
);
1511 qemu_register_machine(&ss600mp_machine
);
1512 qemu_register_machine(&ss20_machine
);
1513 qemu_register_machine(&voyager_machine
);
1514 qemu_register_machine(&ss_lx_machine
);
1515 qemu_register_machine(&ss4_machine
);
1516 qemu_register_machine(&scls_machine
);
1517 qemu_register_machine(&sbook_machine
);
1520 type_init(sun4m_register_types
)
1521 machine_init(sun4m_machine_init
);