hw/i386/pc_q35.c

   1 /*
   2  * Q35 chipset based pc system emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2009, 2010
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9  *
  10  * This is based on pc.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30
  31 #include "qemu/osdep.h"
  32 #include "qemu/units.h"
  33 #include "hw/loader.h"
  34 #include "hw/i2c/smbus_eeprom.h"
  35 #include "hw/rtc/mc146818rtc.h"
  36 #include "sysemu/kvm.h"
  37 #include "hw/kvm/clock.h"
  38 #include "hw/pci-host/q35.h"
  39 #include "hw/pci/pcie_port.h"
  40 #include "hw/qdev-properties.h"
  41 #include "hw/i386/x86.h"
  42 #include "hw/i386/pc.h"
  43 #include "hw/i386/ich9.h"
  44 #include "hw/i386/amd_iommu.h"
  45 #include "hw/i386/intel_iommu.h"
  46 #include "hw/display/ramfb.h"
  47 #include "hw/firmware/smbios.h"
  48 #include "hw/ide/pci.h"
  49 #include "hw/ide/ahci.h"
  50 #include "hw/usb.h"
  51 #include "qapi/error.h"
  52 #include "qemu/error-report.h"
  53 #include "sysemu/numa.h"
  54 #include "hw/hyperv/vmbus-bridge.h"
  55 #include "hw/mem/nvdimm.h"
  56 #include "hw/i386/acpi-build.h"
  57
  58 /* ICH9 AHCI has 6 ports */
  59 #define MAX_SATA_PORTS     6
  60
  61 struct ehci_companions {
  62     const char *name;
  63     int func;
  64     int port;
  65 };
  66
  67 static const struct ehci_companions ich9_1d[] = {
  68     { .name = "ich9-usb-uhci1", .func = 0, .port = 0 },
  69     { .name = "ich9-usb-uhci2", .func = 1, .port = 2 },
  70     { .name = "ich9-usb-uhci3", .func = 2, .port = 4 },
  71 };
  72
  73 static const struct ehci_companions ich9_1a[] = {
  74     { .name = "ich9-usb-uhci4", .func = 0, .port = 0 },
  75     { .name = "ich9-usb-uhci5", .func = 1, .port = 2 },
  76     { .name = "ich9-usb-uhci6", .func = 2, .port = 4 },
  77 };
  78
  79 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot)
  80 {
  81     const struct ehci_companions *comp;
  82     PCIDevice *ehci, *uhci;
  83     BusState *usbbus;
  84     const char *name;
  85     int i;
  86
  87     switch (slot) {
  88     case 0x1d:
  89         name = "ich9-usb-ehci1";
  90         comp = ich9_1d;
  91         break;
  92     case 0x1a:
  93         name = "ich9-usb-ehci2";
  94         comp = ich9_1a;
  95         break;
  96     default:
  97         return -1;
  98     }
  99
 100     ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), true, name);
 101     pci_realize_and_unref(ehci, bus, &error_fatal);
 102     usbbus = QLIST_FIRST(&ehci->qdev.child_bus);
 103
 104     for (i = 0; i < 3; i++) {
 105         uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), true,
 106                                      comp[i].name);
 107         qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name);
 108         qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port);
 109         pci_realize_and_unref(uhci, bus, &error_fatal);
 110     }
 111     return 0;
 112 }
 113
 114 /* PC hardware initialisation */
 115 static void pc_q35_init(MachineState *machine)
 116 {
 117     PCMachineState *pcms = PC_MACHINE(machine);
 118     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
 119     X86MachineState *x86ms = X86_MACHINE(machine);
 120     Q35PCIHost *q35_host;
 121     PCIHostState *phb;
 122     PCIBus *host_bus;
 123     PCIDevice *lpc;
 124     DeviceState *lpc_dev;
 125     BusState *idebus[MAX_SATA_PORTS];
 126     ISADevice *rtc_state;
 127     MemoryRegion *system_io = get_system_io();
 128     MemoryRegion *pci_memory;
 129     MemoryRegion *rom_memory;
 130     MemoryRegion *ram_memory;
 131     GSIState *gsi_state;
 132     ISABus *isa_bus;
 133     int i;
 134     ICH9LPCState *ich9_lpc;
 135     PCIDevice *ahci;
 136     ram_addr_t lowmem;
 137     DriveInfo *hd[MAX_SATA_PORTS];
 138     MachineClass *mc = MACHINE_GET_CLASS(machine);
 139     bool acpi_pcihp;
 140     bool keep_pci_slot_hpc;
 141
 142     /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
 143      * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
 144      * also known as MMCFG).
 145      * If it doesn't, we need to split it in chunks below and above 4G.
 146      * In any case, try to make sure that guest addresses aligned at
 147      * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
 148      */
 149     if (machine->ram_size >= 0xb0000000) {
 150         lowmem = 0x80000000;
 151     } else {
 152         lowmem = 0xb0000000;
 153     }
 154
 155     /* Handle the machine opt max-ram-below-4g.  It is basically doing
 156      * min(qemu limit, user limit).
 157      */
 158     if (!pcms->max_ram_below_4g) {
 159         pcms->max_ram_below_4g = 4 * GiB;
 160     }
 161     if (lowmem > pcms->max_ram_below_4g) {
 162         lowmem = pcms->max_ram_below_4g;
 163         if (machine->ram_size - lowmem > lowmem &&
 164             lowmem & (1 * GiB - 1)) {
 165             warn_report("There is possibly poor performance as the ram size "
 166                         " (0x%" PRIx64 ") is more then twice the size of"
 167                         " max-ram-below-4g (%"PRIu64") and"
 168                         " max-ram-below-4g is not a multiple of 1G.",
 169                         (uint64_t)machine->ram_size, pcms->max_ram_below_4g);
 170         }
 171     }
 172
 173     if (machine->ram_size >= lowmem) {
 174         x86ms->above_4g_mem_size = machine->ram_size - lowmem;
 175         x86ms->below_4g_mem_size = lowmem;
 176     } else {
 177         x86ms->above_4g_mem_size = 0;
 178         x86ms->below_4g_mem_size = machine->ram_size;
 179     }
 180
 181     pc_machine_init_sgx_epc(pcms);
 182     x86_cpus_init(x86ms, pcmc->default_cpu_version);
 183
 184     kvmclock_create(pcmc->kvmclock_create_always);
 185
 186     /* pci enabled */
 187     if (pcmc->pci_enabled) {
 188         pci_memory = g_new(MemoryRegion, 1);
 189         memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
 190         rom_memory = pci_memory;
 191     } else {
 192         pci_memory = NULL;
 193         rom_memory = get_system_memory();
 194     }
 195
 196     pc_guest_info_init(pcms);
 197
 198     if (pcmc->smbios_defaults) {
 199         /* These values are guest ABI, do not change */
 200         smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
 201                             mc->name, pcmc->smbios_legacy_mode,
 202                             pcmc->smbios_uuid_encoded,
 203                             pcms->smbios_entry_point_type);
 204     }
 205
 206     /* create pci host bus */
 207     q35_host = Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE));
 208
 209     /* allocate ram and load rom/bios */
 210     pc_memory_init(pcms, get_system_memory(), rom_memory, &ram_memory);
 211
 212     object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host));
 213     object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM,
 214                              OBJECT(ram_memory), NULL);
 215     object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_PCI_MEM,
 216                              OBJECT(pci_memory), NULL);
 217     object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_SYSTEM_MEM,
 218                              OBJECT(get_system_memory()), NULL);
 219     object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_IO_MEM,
 220                              OBJECT(system_io), NULL);
 221     object_property_set_int(OBJECT(q35_host), PCI_HOST_BELOW_4G_MEM_SIZE,
 222                             x86ms->below_4g_mem_size, NULL);
 223     object_property_set_int(OBJECT(q35_host), PCI_HOST_ABOVE_4G_MEM_SIZE,
 224                             x86ms->above_4g_mem_size, NULL);
 225     /* pci */
 226     sysbus_realize_and_unref(SYS_BUS_DEVICE(q35_host), &error_fatal);
 227     phb = PCI_HOST_BRIDGE(q35_host);
 228     host_bus = phb->bus;
 229     /* create ISA bus */
 230     lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
 231                                           ICH9_LPC_FUNC), true,
 232                                           TYPE_ICH9_LPC_DEVICE);
 233
 234     object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
 235                              TYPE_HOTPLUG_HANDLER,
 236                              (Object **)&x86ms->acpi_dev,
 237                              object_property_allow_set_link,
 238                              OBJ_PROP_LINK_STRONG);
 239     object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
 240                              OBJECT(lpc), &error_abort);
 241
 242     acpi_pcihp = object_property_get_bool(OBJECT(lpc),
 243                                           ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
 244                                           NULL);
 245
 246     keep_pci_slot_hpc = object_property_get_bool(OBJECT(lpc),
 247                                                  "x-keep-pci-slot-hpc",
 248                                                  NULL);
 249
 250     if (!keep_pci_slot_hpc && acpi_pcihp) {
 251         object_register_sugar_prop(TYPE_PCIE_SLOT, "x-native-hotplug",
 252                                    "false", true);
 253     }
 254
 255     /* irq lines */
 256     gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled);
 257
 258     ich9_lpc = ICH9_LPC_DEVICE(lpc);
 259     lpc_dev = DEVICE(lpc);
 260     for (i = 0; i < GSI_NUM_PINS; i++) {
 261         qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
 262     }
 263     pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
 264                  ICH9_LPC_NB_PIRQS);
 265     pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
 266     isa_bus = ich9_lpc->isa_bus;
 267
 268     if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) {
 269         pc_i8259_create(isa_bus, gsi_state->i8259_irq);
 270     }
 271
 272     if (pcmc->pci_enabled) {
 273         ioapic_init_gsi(gsi_state, "q35");
 274     }
 275
 276     if (tcg_enabled()) {
 277         x86_register_ferr_irq(x86ms->gsi[13]);
 278     }
 279
 280     assert(pcms->vmport != ON_OFF_AUTO__MAX);
 281     if (pcms->vmport == ON_OFF_AUTO_AUTO) {
 282         pcms->vmport = ON_OFF_AUTO_ON;
 283     }
 284
 285     /* init basic PC hardware */
 286     pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, !mc->no_floppy,
 287                          0xff0104);
 288
 289     /* connect pm stuff to lpc */
 290     ich9_lpc_pm_init(lpc, x86_machine_is_smm_enabled(x86ms));
 291
 292     if (pcms->sata_enabled) {
 293         /* ahci and SATA device, for q35 1 ahci controller is built-in */
 294         ahci = pci_create_simple_multifunction(host_bus,
 295                                                PCI_DEVFN(ICH9_SATA1_DEV,
 296                                                          ICH9_SATA1_FUNC),
 297                                                true, "ich9-ahci");
 298         idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
 299         idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
 300         g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci));
 301         ide_drive_get(hd, ahci_get_num_ports(ahci));
 302         ahci_ide_create_devs(ahci, hd);
 303     } else {
 304         idebus[0] = idebus[1] = NULL;
 305     }
 306
 307     if (machine_usb(machine)) {
 308         /* Should we create 6 UHCI according to ich9 spec? */
 309         ehci_create_ich9_with_companions(host_bus, 0x1d);
 310     }
 311
 312     if (pcms->smbus_enabled) {
 313         /* TODO: Populate SPD eeprom data.  */
 314         pcms->smbus = ich9_smb_init(host_bus,
 315                                     PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
 316                                     0xb100);
 317         smbus_eeprom_init(pcms->smbus, 8, NULL, 0);
 318     }
 319
 320     pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
 321
 322     /* the rest devices to which pci devfn is automatically assigned */
 323     pc_vga_init(isa_bus, host_bus);
 324     pc_nic_init(pcmc, isa_bus, host_bus);
 325
 326     if (machine->nvdimms_state->is_enabled) {
 327         nvdimm_init_acpi_state(machine->nvdimms_state, system_io,
 328                                x86_nvdimm_acpi_dsmio,
 329                                x86ms->fw_cfg, OBJECT(pcms));
 330     }
 331 }
 332
 333 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
 334     static void pc_init_##suffix(MachineState *machine) \
 335     { \
 336         void (*compat)(MachineState *m) = (compatfn); \
 337         if (compat) { \
 338             compat(machine); \
 339         } \
 340         pc_q35_init(machine); \
 341     } \
 342     DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
 343
 344
 345 static void pc_q35_machine_options(MachineClass *m)
 346 {
 347     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 348     pcmc->default_nic_model = "e1000e";
 349     pcmc->pci_root_uid = 0;
 350
 351     m->family = "pc_q35";
 352     m->desc = "Standard PC (Q35 + ICH9, 2009)";
 353     m->units_per_default_bus = 1;
 354     m->default_machine_opts = "firmware=bios-256k.bin";
 355     m->default_display = "std";
 356     m->default_kernel_irqchip_split = false;
 357     m->no_floppy = 1;
 358     machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE);
 359     machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE);
 360     machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE);
 361     machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE);
 362     m->max_cpus = 288;
 363 }
 364
 365 static void pc_q35_7_1_machine_options(MachineClass *m)
 366 {
 367     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 368     pc_q35_machine_options(m);
 369     m->alias = "q35";
 370     pcmc->default_cpu_version = 1;
 371 }
 372
 373 DEFINE_Q35_MACHINE(v7_1, "pc-q35-7.1", NULL,
 374                    pc_q35_7_1_machine_options);
 375
 376 static void pc_q35_7_0_machine_options(MachineClass *m)
 377 {
 378     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 379     pc_q35_7_1_machine_options(m);
 380     m->alias = NULL;
 381     pcmc->legacy_no_rng_seed = true;
 382     compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len);
 383     compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len);
 384 }
 385
 386 DEFINE_Q35_MACHINE(v7_0, "pc-q35-7.0", NULL,
 387                    pc_q35_7_0_machine_options);
 388
 389 static void pc_q35_6_2_machine_options(MachineClass *m)
 390 {
 391     pc_q35_7_0_machine_options(m);
 392     m->alias = NULL;
 393     compat_props_add(m->compat_props, hw_compat_6_2, hw_compat_6_2_len);
 394     compat_props_add(m->compat_props, pc_compat_6_2, pc_compat_6_2_len);
 395 }
 396
 397 DEFINE_Q35_MACHINE(v6_2, "pc-q35-6.2", NULL,
 398                    pc_q35_6_2_machine_options);
 399
 400 static void pc_q35_6_1_machine_options(MachineClass *m)
 401 {
 402     pc_q35_6_2_machine_options(m);
 403     m->alias = NULL;
 404     compat_props_add(m->compat_props, hw_compat_6_1, hw_compat_6_1_len);
 405     compat_props_add(m->compat_props, pc_compat_6_1, pc_compat_6_1_len);
 406     m->smp_props.prefer_sockets = true;
 407 }
 408
 409 DEFINE_Q35_MACHINE(v6_1, "pc-q35-6.1", NULL,
 410                    pc_q35_6_1_machine_options);
 411
 412 static void pc_q35_6_0_machine_options(MachineClass *m)
 413 {
 414     pc_q35_6_1_machine_options(m);
 415     m->alias = NULL;
 416     compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len);
 417     compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len);
 418 }
 419
 420 DEFINE_Q35_MACHINE(v6_0, "pc-q35-6.0", NULL,
 421                    pc_q35_6_0_machine_options);
 422
 423 static void pc_q35_5_2_machine_options(MachineClass *m)
 424 {
 425     pc_q35_6_0_machine_options(m);
 426     m->alias = NULL;
 427     compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len);
 428     compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len);
 429 }
 430
 431 DEFINE_Q35_MACHINE(v5_2, "pc-q35-5.2", NULL,
 432                    pc_q35_5_2_machine_options);
 433
 434 static void pc_q35_5_1_machine_options(MachineClass *m)
 435 {
 436     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 437
 438     pc_q35_5_2_machine_options(m);
 439     m->alias = NULL;
 440     compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len);
 441     compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len);
 442     pcmc->kvmclock_create_always = false;
 443     pcmc->pci_root_uid = 1;
 444 }
 445
 446 DEFINE_Q35_MACHINE(v5_1, "pc-q35-5.1", NULL,
 447                    pc_q35_5_1_machine_options);
 448
 449 static void pc_q35_5_0_machine_options(MachineClass *m)
 450 {
 451     pc_q35_5_1_machine_options(m);
 452     m->alias = NULL;
 453     m->numa_mem_supported = true;
 454     compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len);
 455     compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len);
 456     m->auto_enable_numa_with_memdev = false;
 457 }
 458
 459 DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL,
 460                    pc_q35_5_0_machine_options);
 461
 462 static void pc_q35_4_2_machine_options(MachineClass *m)
 463 {
 464     pc_q35_5_0_machine_options(m);
 465     m->alias = NULL;
 466     compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len);
 467     compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len);
 468 }
 469
 470 DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL,
 471                    pc_q35_4_2_machine_options);
 472
 473 static void pc_q35_4_1_machine_options(MachineClass *m)
 474 {
 475     pc_q35_4_2_machine_options(m);
 476     m->alias = NULL;
 477     compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len);
 478     compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len);
 479 }
 480
 481 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL,
 482                    pc_q35_4_1_machine_options);
 483
 484 static void pc_q35_4_0_1_machine_options(MachineClass *m)
 485 {
 486     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 487     pc_q35_4_1_machine_options(m);
 488     m->alias = NULL;
 489     pcmc->default_cpu_version = CPU_VERSION_LEGACY;
 490     /*
 491      * This is the default machine for the 4.0-stable branch. It is basically
 492      * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the
 493      * 4.0 compat props.
 494      */
 495     compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len);
 496     compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len);
 497 }
 498
 499 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL,
 500                    pc_q35_4_0_1_machine_options);
 501
 502 static void pc_q35_4_0_machine_options(MachineClass *m)
 503 {
 504     pc_q35_4_0_1_machine_options(m);
 505     m->default_kernel_irqchip_split = true;
 506     m->alias = NULL;
 507     /* Compat props are applied by the 4.0.1 machine */
 508 }
 509
 510 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL,
 511                    pc_q35_4_0_machine_options);
 512
 513 static void pc_q35_3_1_machine_options(MachineClass *m)
 514 {
 515     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 516
 517     pc_q35_4_0_machine_options(m);
 518     m->default_kernel_irqchip_split = false;
 519     m->smbus_no_migration_support = true;
 520     m->alias = NULL;
 521     pcmc->pvh_enabled = false;
 522     compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len);
 523     compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len);
 524 }
 525
 526 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL,
 527                    pc_q35_3_1_machine_options);
 528
 529 static void pc_q35_3_0_machine_options(MachineClass *m)
 530 {
 531     pc_q35_3_1_machine_options(m);
 532     compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len);
 533     compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len);
 534 }
 535
 536 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL,
 537                     pc_q35_3_0_machine_options);
 538
 539 static void pc_q35_2_12_machine_options(MachineClass *m)
 540 {
 541     pc_q35_3_0_machine_options(m);
 542     compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len);
 543     compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len);
 544 }
 545
 546 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL,
 547                    pc_q35_2_12_machine_options);
 548
 549 static void pc_q35_2_11_machine_options(MachineClass *m)
 550 {
 551     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 552
 553     pc_q35_2_12_machine_options(m);
 554     pcmc->default_nic_model = "e1000";
 555     compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len);
 556     compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len);
 557 }
 558
 559 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL,
 560                    pc_q35_2_11_machine_options);
 561
 562 static void pc_q35_2_10_machine_options(MachineClass *m)
 563 {
 564     pc_q35_2_11_machine_options(m);
 565     compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len);
 566     compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len);
 567     m->auto_enable_numa_with_memhp = false;
 568 }
 569
 570 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL,
 571                    pc_q35_2_10_machine_options);
 572
 573 static void pc_q35_2_9_machine_options(MachineClass *m)
 574 {
 575     pc_q35_2_10_machine_options(m);
 576     compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len);
 577     compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len);
 578 }
 579
 580 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL,
 581                    pc_q35_2_9_machine_options);
 582
 583 static void pc_q35_2_8_machine_options(MachineClass *m)
 584 {
 585     pc_q35_2_9_machine_options(m);
 586     compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len);
 587     compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len);
 588 }
 589
 590 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL,
 591                    pc_q35_2_8_machine_options);
 592
 593 static void pc_q35_2_7_machine_options(MachineClass *m)
 594 {
 595     pc_q35_2_8_machine_options(m);
 596     m->max_cpus = 255;
 597     compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len);
 598     compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len);
 599 }
 600
 601 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL,
 602                    pc_q35_2_7_machine_options);
 603
 604 static void pc_q35_2_6_machine_options(MachineClass *m)
 605 {
 606     X86MachineClass *x86mc = X86_MACHINE_CLASS(m);
 607     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 608
 609     pc_q35_2_7_machine_options(m);
 610     pcmc->legacy_cpu_hotplug = true;
 611     x86mc->fwcfg_dma_enabled = false;
 612     compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len);
 613     compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len);
 614 }
 615
 616 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL,
 617                    pc_q35_2_6_machine_options);
 618
 619 static void pc_q35_2_5_machine_options(MachineClass *m)
 620 {
 621     X86MachineClass *x86mc = X86_MACHINE_CLASS(m);
 622
 623     pc_q35_2_6_machine_options(m);
 624     x86mc->save_tsc_khz = false;
 625     m->legacy_fw_cfg_order = 1;
 626     compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len);
 627     compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len);
 628 }
 629
 630 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL,
 631                    pc_q35_2_5_machine_options);
 632
 633 static void pc_q35_2_4_machine_options(MachineClass *m)
 634 {
 635     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 636
 637     pc_q35_2_5_machine_options(m);
 638     m->hw_version = "2.4.0";
 639     pcmc->broken_reserved_end = true;
 640     compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len);
 641     compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len);
 642 }
 643
 644 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL,
 645                    pc_q35_2_4_machine_options);