2 * ARM Generic Interrupt Controller using KVM in-kernel support
4 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
5 * Written by Pavel Fedin
6 * Based on vGICv2 code by Peter Maydell
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
24 #include "hw/intc/arm_gicv3_common.h"
25 #include "hw/sysbus.h"
26 #include "qemu/error-report.h"
27 #include "qemu/module.h"
28 #include "sysemu/kvm.h"
29 #include "sysemu/runstate.h"
31 #include "gicv3_internal.h"
32 #include "vgic_common.h"
33 #include "migration/blocker.h"
34 #include "qom/object.h"
36 #ifdef DEBUG_GICV3_KVM
37 #define DPRINTF(fmt, ...) \
38 do { fprintf(stderr, "kvm_gicv3: " fmt, ## __VA_ARGS__); } while (0)
40 #define DPRINTF(fmt, ...) \
44 #define TYPE_KVM_ARM_GICV3 "kvm-arm-gicv3"
45 typedef struct KVMARMGICv3Class KVMARMGICv3Class
;
46 /* This is reusing the GICv3State typedef from ARM_GICV3_ITS_COMMON */
47 DECLARE_OBJ_CHECKERS(GICv3State
, KVMARMGICv3Class
,
48 KVM_ARM_GICV3
, TYPE_KVM_ARM_GICV3
)
50 #define KVM_DEV_ARM_VGIC_SYSREG(op0, op1, crn, crm, op2) \
51 (ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
52 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
53 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
54 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
55 ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
58 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 4, 6, 0)
59 #define ICC_BPR0_EL1 \
60 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 3)
61 #define ICC_AP0R_EL1(n) \
62 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 4 | n)
63 #define ICC_AP1R_EL1(n) \
64 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 9, n)
65 #define ICC_BPR1_EL1 \
66 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 3)
67 #define ICC_CTLR_EL1 \
68 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 4)
70 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 5)
71 #define ICC_IGRPEN0_EL1 \
72 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 6)
73 #define ICC_IGRPEN1_EL1 \
74 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 7)
76 struct KVMARMGICv3Class
{
77 ARMGICv3CommonClass parent_class
;
78 DeviceRealize parent_realize
;
79 void (*parent_reset
)(DeviceState
*dev
);
82 static void kvm_arm_gicv3_set_irq(void *opaque
, int irq
, int level
)
84 GICv3State
*s
= (GICv3State
*)opaque
;
86 kvm_arm_gic_set_irq(s
->num_irq
, irq
, level
);
89 #define KVM_VGIC_ATTR(reg, typer) \
90 ((typer & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) | (reg))
92 static inline void kvm_gicd_access(GICv3State
*s
, int offset
,
93 uint32_t *val
, bool write
)
95 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_DIST_REGS
,
96 KVM_VGIC_ATTR(offset
, 0),
97 val
, write
, &error_abort
);
100 static inline void kvm_gicr_access(GICv3State
*s
, int offset
, int cpu
,
101 uint32_t *val
, bool write
)
103 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS
,
104 KVM_VGIC_ATTR(offset
, s
->cpu
[cpu
].gicr_typer
),
105 val
, write
, &error_abort
);
108 static inline void kvm_gicc_access(GICv3State
*s
, uint64_t reg
, int cpu
,
109 uint64_t *val
, bool write
)
111 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS
,
112 KVM_VGIC_ATTR(reg
, s
->cpu
[cpu
].gicr_typer
),
113 val
, write
, &error_abort
);
116 static inline void kvm_gic_line_level_access(GICv3State
*s
, int irq
, int cpu
,
117 uint32_t *val
, bool write
)
119 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO
,
120 KVM_VGIC_ATTR(irq
, s
->cpu
[cpu
].gicr_typer
) |
121 (VGIC_LEVEL_INFO_LINE_LEVEL
<<
122 KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT
),
123 val
, write
, &error_abort
);
126 /* Loop through each distributor IRQ related register; since bits
127 * corresponding to SPIs and PPIs are RAZ/WI when affinity routing
128 * is enabled, we skip those.
130 #define for_each_dist_irq_reg(_irq, _max, _field_width) \
131 for (_irq = GIC_INTERNAL; _irq < _max; _irq += (32 / _field_width))
133 static void kvm_dist_get_priority(GICv3State
*s
, uint32_t offset
, uint8_t *bmp
)
135 uint32_t reg
, *field
;
138 /* For the KVM GICv3, affinity routing is always enabled, and the first 8
139 * GICD_IPRIORITYR<n> registers are always RAZ/WI. The corresponding
140 * functionality is replaced by GICR_IPRIORITYR<n>. It doesn't need to
141 * sync them. So it needs to skip the field of GIC_INTERNAL irqs in bmp and
144 field
= (uint32_t *)(bmp
+ GIC_INTERNAL
);
145 offset
+= (GIC_INTERNAL
* 8) / 8;
146 for_each_dist_irq_reg(irq
, s
->num_irq
, 8) {
147 kvm_gicd_access(s
, offset
, ®
, false);
154 static void kvm_dist_put_priority(GICv3State
*s
, uint32_t offset
, uint8_t *bmp
)
156 uint32_t reg
, *field
;
159 /* For the KVM GICv3, affinity routing is always enabled, and the first 8
160 * GICD_IPRIORITYR<n> registers are always RAZ/WI. The corresponding
161 * functionality is replaced by GICR_IPRIORITYR<n>. It doesn't need to
162 * sync them. So it needs to skip the field of GIC_INTERNAL irqs in bmp and
165 field
= (uint32_t *)(bmp
+ GIC_INTERNAL
);
166 offset
+= (GIC_INTERNAL
* 8) / 8;
167 for_each_dist_irq_reg(irq
, s
->num_irq
, 8) {
169 kvm_gicd_access(s
, offset
, ®
, true);
175 static void kvm_dist_get_edge_trigger(GICv3State
*s
, uint32_t offset
,
181 /* For the KVM GICv3, affinity routing is always enabled, and the first 2
182 * GICD_ICFGR<n> registers are always RAZ/WI. The corresponding
183 * functionality is replaced by GICR_ICFGR<n>. It doesn't need to sync
184 * them. So it should increase the offset to skip GIC_INTERNAL irqs.
185 * This matches the for_each_dist_irq_reg() macro which also skips the
186 * first GIC_INTERNAL irqs.
188 offset
+= (GIC_INTERNAL
* 2) / 8;
189 for_each_dist_irq_reg(irq
, s
->num_irq
, 2) {
190 kvm_gicd_access(s
, offset
, ®
, false);
191 reg
= half_unshuffle32(reg
>> 1);
195 *gic_bmp_ptr32(bmp
, irq
) |= reg
;
200 static void kvm_dist_put_edge_trigger(GICv3State
*s
, uint32_t offset
,
206 /* For the KVM GICv3, affinity routing is always enabled, and the first 2
207 * GICD_ICFGR<n> registers are always RAZ/WI. The corresponding
208 * functionality is replaced by GICR_ICFGR<n>. It doesn't need to sync
209 * them. So it should increase the offset to skip GIC_INTERNAL irqs.
210 * This matches the for_each_dist_irq_reg() macro which also skips the
211 * first GIC_INTERNAL irqs.
213 offset
+= (GIC_INTERNAL
* 2) / 8;
214 for_each_dist_irq_reg(irq
, s
->num_irq
, 2) {
215 reg
= *gic_bmp_ptr32(bmp
, irq
);
217 reg
= (reg
& 0xffff0000) >> 16;
221 reg
= half_shuffle32(reg
) << 1;
222 kvm_gicd_access(s
, offset
, ®
, true);
227 static void kvm_gic_get_line_level_bmp(GICv3State
*s
, uint32_t *bmp
)
232 for_each_dist_irq_reg(irq
, s
->num_irq
, 1) {
233 kvm_gic_line_level_access(s
, irq
, 0, ®
, false);
234 *gic_bmp_ptr32(bmp
, irq
) = reg
;
238 static void kvm_gic_put_line_level_bmp(GICv3State
*s
, uint32_t *bmp
)
243 for_each_dist_irq_reg(irq
, s
->num_irq
, 1) {
244 reg
= *gic_bmp_ptr32(bmp
, irq
);
245 kvm_gic_line_level_access(s
, irq
, 0, ®
, true);
249 /* Read a bitmap register group from the kernel VGIC. */
250 static void kvm_dist_getbmp(GICv3State
*s
, uint32_t offset
, uint32_t *bmp
)
255 /* For the KVM GICv3, affinity routing is always enabled, and the
256 * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/
257 * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding
258 * functionality is replaced by the GICR registers. It doesn't need to sync
259 * them. So it should increase the offset to skip GIC_INTERNAL irqs.
260 * This matches the for_each_dist_irq_reg() macro which also skips the
261 * first GIC_INTERNAL irqs.
263 offset
+= (GIC_INTERNAL
* 1) / 8;
264 for_each_dist_irq_reg(irq
, s
->num_irq
, 1) {
265 kvm_gicd_access(s
, offset
, ®
, false);
266 *gic_bmp_ptr32(bmp
, irq
) = reg
;
271 static void kvm_dist_putbmp(GICv3State
*s
, uint32_t offset
,
272 uint32_t clroffset
, uint32_t *bmp
)
277 /* For the KVM GICv3, affinity routing is always enabled, and the
278 * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/
279 * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding
280 * functionality is replaced by the GICR registers. It doesn't need to sync
281 * them. So it should increase the offset and clroffset to skip GIC_INTERNAL
282 * irqs. This matches the for_each_dist_irq_reg() macro which also skips the
283 * first GIC_INTERNAL irqs.
285 offset
+= (GIC_INTERNAL
* 1) / 8;
286 if (clroffset
!= 0) {
287 clroffset
+= (GIC_INTERNAL
* 1) / 8;
290 for_each_dist_irq_reg(irq
, s
->num_irq
, 1) {
291 /* If this bitmap is a set/clear register pair, first write to the
292 * clear-reg to clear all bits before using the set-reg to write
295 if (clroffset
!= 0) {
297 kvm_gicd_access(s
, clroffset
, ®
, true);
300 reg
= *gic_bmp_ptr32(bmp
, irq
);
301 kvm_gicd_access(s
, offset
, ®
, true);
306 static void kvm_arm_gicv3_check(GICv3State
*s
)
311 /* Sanity checking s->num_irq */
312 kvm_gicd_access(s
, GICD_TYPER
, ®
, false);
313 num_irq
= ((reg
& 0x1f) + 1) * 32;
315 if (num_irq
< s
->num_irq
) {
316 error_report("Model requests %u IRQs, but kernel supports max %u",
317 s
->num_irq
, num_irq
);
322 static void kvm_arm_gicv3_put(GICv3State
*s
)
324 uint32_t regl
, regh
, reg
;
325 uint64_t reg64
, redist_typer
;
328 kvm_arm_gicv3_check(s
);
330 kvm_gicr_access(s
, GICR_TYPER
, 0, ®l
, false);
331 kvm_gicr_access(s
, GICR_TYPER
+ 4, 0, ®h
, false);
332 redist_typer
= ((uint64_t)regh
<< 32) | regl
;
335 kvm_gicd_access(s
, GICD_CTLR
, ®
, true);
337 if (redist_typer
& GICR_TYPER_PLPIS
) {
339 * Restore base addresses before LPIs are potentially enabled by
342 for (ncpu
= 0; ncpu
< s
->num_cpu
; ncpu
++) {
343 GICv3CPUState
*c
= &s
->cpu
[ncpu
];
345 reg64
= c
->gicr_propbaser
;
346 regl
= (uint32_t)reg64
;
347 kvm_gicr_access(s
, GICR_PROPBASER
, ncpu
, ®l
, true);
348 regh
= (uint32_t)(reg64
>> 32);
349 kvm_gicr_access(s
, GICR_PROPBASER
+ 4, ncpu
, ®h
, true);
351 reg64
= c
->gicr_pendbaser
;
352 regl
= (uint32_t)reg64
;
353 kvm_gicr_access(s
, GICR_PENDBASER
, ncpu
, ®l
, true);
354 regh
= (uint32_t)(reg64
>> 32);
355 kvm_gicr_access(s
, GICR_PENDBASER
+ 4, ncpu
, ®h
, true);
359 /* Redistributor state (one per CPU) */
361 for (ncpu
= 0; ncpu
< s
->num_cpu
; ncpu
++) {
362 GICv3CPUState
*c
= &s
->cpu
[ncpu
];
365 kvm_gicr_access(s
, GICR_CTLR
, ncpu
, ®
, true);
367 reg
= c
->gicr_statusr
[GICV3_NS
];
368 kvm_gicr_access(s
, GICR_STATUSR
, ncpu
, ®
, true);
371 kvm_gicr_access(s
, GICR_WAKER
, ncpu
, ®
, true);
373 reg
= c
->gicr_igroupr0
;
374 kvm_gicr_access(s
, GICR_IGROUPR0
, ncpu
, ®
, true);
377 kvm_gicr_access(s
, GICR_ICENABLER0
, ncpu
, ®
, true);
378 reg
= c
->gicr_ienabler0
;
379 kvm_gicr_access(s
, GICR_ISENABLER0
, ncpu
, ®
, true);
381 /* Restore config before pending so we treat level/edge correctly */
382 reg
= half_shuffle32(c
->edge_trigger
>> 16) << 1;
383 kvm_gicr_access(s
, GICR_ICFGR1
, ncpu
, ®
, true);
386 kvm_gic_line_level_access(s
, 0, ncpu
, ®
, true);
389 kvm_gicr_access(s
, GICR_ICPENDR0
, ncpu
, ®
, true);
390 reg
= c
->gicr_ipendr0
;
391 kvm_gicr_access(s
, GICR_ISPENDR0
, ncpu
, ®
, true);
394 kvm_gicr_access(s
, GICR_ICACTIVER0
, ncpu
, ®
, true);
395 reg
= c
->gicr_iactiver0
;
396 kvm_gicr_access(s
, GICR_ISACTIVER0
, ncpu
, ®
, true);
398 for (i
= 0; i
< GIC_INTERNAL
; i
+= 4) {
399 reg
= c
->gicr_ipriorityr
[i
] |
400 (c
->gicr_ipriorityr
[i
+ 1] << 8) |
401 (c
->gicr_ipriorityr
[i
+ 2] << 16) |
402 (c
->gicr_ipriorityr
[i
+ 3] << 24);
403 kvm_gicr_access(s
, GICR_IPRIORITYR
+ i
, ncpu
, ®
, true);
407 /* Distributor state (shared between all CPUs */
408 reg
= s
->gicd_statusr
[GICV3_NS
];
409 kvm_gicd_access(s
, GICD_STATUSR
, ®
, true);
411 /* s->enable bitmap -> GICD_ISENABLERn */
412 kvm_dist_putbmp(s
, GICD_ISENABLER
, GICD_ICENABLER
, s
->enabled
);
414 /* s->group bitmap -> GICD_IGROUPRn */
415 kvm_dist_putbmp(s
, GICD_IGROUPR
, 0, s
->group
);
417 /* Restore targets before pending to ensure the pending state is set on
418 * the appropriate CPU interfaces in the kernel
421 /* s->gicd_irouter[irq] -> GICD_IROUTERn
422 * We can't use kvm_dist_put() here because the registers are 64-bit
424 for (i
= GIC_INTERNAL
; i
< s
->num_irq
; i
++) {
427 offset
= GICD_IROUTER
+ (sizeof(uint32_t) * i
);
428 reg
= (uint32_t)s
->gicd_irouter
[i
];
429 kvm_gicd_access(s
, offset
, ®
, true);
431 offset
= GICD_IROUTER
+ (sizeof(uint32_t) * i
) + 4;
432 reg
= (uint32_t)(s
->gicd_irouter
[i
] >> 32);
433 kvm_gicd_access(s
, offset
, ®
, true);
436 /* s->trigger bitmap -> GICD_ICFGRn
437 * (restore configuration registers before pending IRQs so we treat
438 * level/edge correctly)
440 kvm_dist_put_edge_trigger(s
, GICD_ICFGR
, s
->edge_trigger
);
442 /* s->level bitmap -> line_level */
443 kvm_gic_put_line_level_bmp(s
, s
->level
);
445 /* s->pending bitmap -> GICD_ISPENDRn */
446 kvm_dist_putbmp(s
, GICD_ISPENDR
, GICD_ICPENDR
, s
->pending
);
448 /* s->active bitmap -> GICD_ISACTIVERn */
449 kvm_dist_putbmp(s
, GICD_ISACTIVER
, GICD_ICACTIVER
, s
->active
);
451 /* s->gicd_ipriority[] -> GICD_IPRIORITYRn */
452 kvm_dist_put_priority(s
, GICD_IPRIORITYR
, s
->gicd_ipriority
);
454 /* CPU Interface state (one per CPU) */
456 for (ncpu
= 0; ncpu
< s
->num_cpu
; ncpu
++) {
457 GICv3CPUState
*c
= &s
->cpu
[ncpu
];
460 kvm_gicc_access(s
, ICC_SRE_EL1
, ncpu
, &c
->icc_sre_el1
, true);
461 kvm_gicc_access(s
, ICC_CTLR_EL1
, ncpu
,
462 &c
->icc_ctlr_el1
[GICV3_NS
], true);
463 kvm_gicc_access(s
, ICC_IGRPEN0_EL1
, ncpu
,
464 &c
->icc_igrpen
[GICV3_G0
], true);
465 kvm_gicc_access(s
, ICC_IGRPEN1_EL1
, ncpu
,
466 &c
->icc_igrpen
[GICV3_G1NS
], true);
467 kvm_gicc_access(s
, ICC_PMR_EL1
, ncpu
, &c
->icc_pmr_el1
, true);
468 kvm_gicc_access(s
, ICC_BPR0_EL1
, ncpu
, &c
->icc_bpr
[GICV3_G0
], true);
469 kvm_gicc_access(s
, ICC_BPR1_EL1
, ncpu
, &c
->icc_bpr
[GICV3_G1NS
], true);
471 num_pri_bits
= ((c
->icc_ctlr_el1
[GICV3_NS
] &
472 ICC_CTLR_EL1_PRIBITS_MASK
) >>
473 ICC_CTLR_EL1_PRIBITS_SHIFT
) + 1;
475 switch (num_pri_bits
) {
477 reg64
= c
->icc_apr
[GICV3_G0
][3];
478 kvm_gicc_access(s
, ICC_AP0R_EL1(3), ncpu
, ®64
, true);
479 reg64
= c
->icc_apr
[GICV3_G0
][2];
480 kvm_gicc_access(s
, ICC_AP0R_EL1(2), ncpu
, ®64
, true);
482 reg64
= c
->icc_apr
[GICV3_G0
][1];
483 kvm_gicc_access(s
, ICC_AP0R_EL1(1), ncpu
, ®64
, true);
485 reg64
= c
->icc_apr
[GICV3_G0
][0];
486 kvm_gicc_access(s
, ICC_AP0R_EL1(0), ncpu
, ®64
, true);
489 switch (num_pri_bits
) {
491 reg64
= c
->icc_apr
[GICV3_G1NS
][3];
492 kvm_gicc_access(s
, ICC_AP1R_EL1(3), ncpu
, ®64
, true);
493 reg64
= c
->icc_apr
[GICV3_G1NS
][2];
494 kvm_gicc_access(s
, ICC_AP1R_EL1(2), ncpu
, ®64
, true);
496 reg64
= c
->icc_apr
[GICV3_G1NS
][1];
497 kvm_gicc_access(s
, ICC_AP1R_EL1(1), ncpu
, ®64
, true);
499 reg64
= c
->icc_apr
[GICV3_G1NS
][0];
500 kvm_gicc_access(s
, ICC_AP1R_EL1(0), ncpu
, ®64
, true);
505 static void kvm_arm_gicv3_get(GICv3State
*s
)
507 uint32_t regl
, regh
, reg
;
508 uint64_t reg64
, redist_typer
;
511 kvm_arm_gicv3_check(s
);
513 kvm_gicr_access(s
, GICR_TYPER
, 0, ®l
, false);
514 kvm_gicr_access(s
, GICR_TYPER
+ 4, 0, ®h
, false);
515 redist_typer
= ((uint64_t)regh
<< 32) | regl
;
517 kvm_gicd_access(s
, GICD_CTLR
, ®
, false);
520 /* Redistributor state (one per CPU) */
522 for (ncpu
= 0; ncpu
< s
->num_cpu
; ncpu
++) {
523 GICv3CPUState
*c
= &s
->cpu
[ncpu
];
525 kvm_gicr_access(s
, GICR_CTLR
, ncpu
, ®
, false);
528 kvm_gicr_access(s
, GICR_STATUSR
, ncpu
, ®
, false);
529 c
->gicr_statusr
[GICV3_NS
] = reg
;
531 kvm_gicr_access(s
, GICR_WAKER
, ncpu
, ®
, false);
534 kvm_gicr_access(s
, GICR_IGROUPR0
, ncpu
, ®
, false);
535 c
->gicr_igroupr0
= reg
;
536 kvm_gicr_access(s
, GICR_ISENABLER0
, ncpu
, ®
, false);
537 c
->gicr_ienabler0
= reg
;
538 kvm_gicr_access(s
, GICR_ICFGR1
, ncpu
, ®
, false);
539 c
->edge_trigger
= half_unshuffle32(reg
>> 1) << 16;
540 kvm_gic_line_level_access(s
, 0, ncpu
, ®
, false);
542 kvm_gicr_access(s
, GICR_ISPENDR0
, ncpu
, ®
, false);
543 c
->gicr_ipendr0
= reg
;
544 kvm_gicr_access(s
, GICR_ISACTIVER0
, ncpu
, ®
, false);
545 c
->gicr_iactiver0
= reg
;
547 for (i
= 0; i
< GIC_INTERNAL
; i
+= 4) {
548 kvm_gicr_access(s
, GICR_IPRIORITYR
+ i
, ncpu
, ®
, false);
549 c
->gicr_ipriorityr
[i
] = extract32(reg
, 0, 8);
550 c
->gicr_ipriorityr
[i
+ 1] = extract32(reg
, 8, 8);
551 c
->gicr_ipriorityr
[i
+ 2] = extract32(reg
, 16, 8);
552 c
->gicr_ipriorityr
[i
+ 3] = extract32(reg
, 24, 8);
556 if (redist_typer
& GICR_TYPER_PLPIS
) {
557 for (ncpu
= 0; ncpu
< s
->num_cpu
; ncpu
++) {
558 GICv3CPUState
*c
= &s
->cpu
[ncpu
];
560 kvm_gicr_access(s
, GICR_PROPBASER
, ncpu
, ®l
, false);
561 kvm_gicr_access(s
, GICR_PROPBASER
+ 4, ncpu
, ®h
, false);
562 c
->gicr_propbaser
= ((uint64_t)regh
<< 32) | regl
;
564 kvm_gicr_access(s
, GICR_PENDBASER
, ncpu
, ®l
, false);
565 kvm_gicr_access(s
, GICR_PENDBASER
+ 4, ncpu
, ®h
, false);
566 c
->gicr_pendbaser
= ((uint64_t)regh
<< 32) | regl
;
570 /* Distributor state (shared between all CPUs */
572 kvm_gicd_access(s
, GICD_STATUSR
, ®
, false);
573 s
->gicd_statusr
[GICV3_NS
] = reg
;
575 /* GICD_IGROUPRn -> s->group bitmap */
576 kvm_dist_getbmp(s
, GICD_IGROUPR
, s
->group
);
578 /* GICD_ISENABLERn -> s->enabled bitmap */
579 kvm_dist_getbmp(s
, GICD_ISENABLER
, s
->enabled
);
581 /* Line level of irq */
582 kvm_gic_get_line_level_bmp(s
, s
->level
);
583 /* GICD_ISPENDRn -> s->pending bitmap */
584 kvm_dist_getbmp(s
, GICD_ISPENDR
, s
->pending
);
586 /* GICD_ISACTIVERn -> s->active bitmap */
587 kvm_dist_getbmp(s
, GICD_ISACTIVER
, s
->active
);
589 /* GICD_ICFGRn -> s->trigger bitmap */
590 kvm_dist_get_edge_trigger(s
, GICD_ICFGR
, s
->edge_trigger
);
592 /* GICD_IPRIORITYRn -> s->gicd_ipriority[] */
593 kvm_dist_get_priority(s
, GICD_IPRIORITYR
, s
->gicd_ipriority
);
595 /* GICD_IROUTERn -> s->gicd_irouter[irq] */
596 for (i
= GIC_INTERNAL
; i
< s
->num_irq
; i
++) {
599 offset
= GICD_IROUTER
+ (sizeof(uint32_t) * i
);
600 kvm_gicd_access(s
, offset
, ®l
, false);
601 offset
= GICD_IROUTER
+ (sizeof(uint32_t) * i
) + 4;
602 kvm_gicd_access(s
, offset
, ®h
, false);
603 s
->gicd_irouter
[i
] = ((uint64_t)regh
<< 32) | regl
;
606 /*****************************************************************
607 * CPU Interface(s) State
610 for (ncpu
= 0; ncpu
< s
->num_cpu
; ncpu
++) {
611 GICv3CPUState
*c
= &s
->cpu
[ncpu
];
614 kvm_gicc_access(s
, ICC_SRE_EL1
, ncpu
, &c
->icc_sre_el1
, false);
615 kvm_gicc_access(s
, ICC_CTLR_EL1
, ncpu
,
616 &c
->icc_ctlr_el1
[GICV3_NS
], false);
617 kvm_gicc_access(s
, ICC_IGRPEN0_EL1
, ncpu
,
618 &c
->icc_igrpen
[GICV3_G0
], false);
619 kvm_gicc_access(s
, ICC_IGRPEN1_EL1
, ncpu
,
620 &c
->icc_igrpen
[GICV3_G1NS
], false);
621 kvm_gicc_access(s
, ICC_PMR_EL1
, ncpu
, &c
->icc_pmr_el1
, false);
622 kvm_gicc_access(s
, ICC_BPR0_EL1
, ncpu
, &c
->icc_bpr
[GICV3_G0
], false);
623 kvm_gicc_access(s
, ICC_BPR1_EL1
, ncpu
, &c
->icc_bpr
[GICV3_G1NS
], false);
624 num_pri_bits
= ((c
->icc_ctlr_el1
[GICV3_NS
] &
625 ICC_CTLR_EL1_PRIBITS_MASK
) >>
626 ICC_CTLR_EL1_PRIBITS_SHIFT
) + 1;
628 switch (num_pri_bits
) {
630 kvm_gicc_access(s
, ICC_AP0R_EL1(3), ncpu
, ®64
, false);
631 c
->icc_apr
[GICV3_G0
][3] = reg64
;
632 kvm_gicc_access(s
, ICC_AP0R_EL1(2), ncpu
, ®64
, false);
633 c
->icc_apr
[GICV3_G0
][2] = reg64
;
635 kvm_gicc_access(s
, ICC_AP0R_EL1(1), ncpu
, ®64
, false);
636 c
->icc_apr
[GICV3_G0
][1] = reg64
;
638 kvm_gicc_access(s
, ICC_AP0R_EL1(0), ncpu
, ®64
, false);
639 c
->icc_apr
[GICV3_G0
][0] = reg64
;
642 switch (num_pri_bits
) {
644 kvm_gicc_access(s
, ICC_AP1R_EL1(3), ncpu
, ®64
, false);
645 c
->icc_apr
[GICV3_G1NS
][3] = reg64
;
646 kvm_gicc_access(s
, ICC_AP1R_EL1(2), ncpu
, ®64
, false);
647 c
->icc_apr
[GICV3_G1NS
][2] = reg64
;
649 kvm_gicc_access(s
, ICC_AP1R_EL1(1), ncpu
, ®64
, false);
650 c
->icc_apr
[GICV3_G1NS
][1] = reg64
;
652 kvm_gicc_access(s
, ICC_AP1R_EL1(0), ncpu
, ®64
, false);
653 c
->icc_apr
[GICV3_G1NS
][0] = reg64
;
658 static void arm_gicv3_icc_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
663 c
= (GICv3CPUState
*)env
->gicv3state
;
667 c
->icc_bpr
[GICV3_G0
] = GIC_MIN_BPR
;
668 c
->icc_bpr
[GICV3_G1
] = GIC_MIN_BPR
;
669 c
->icc_bpr
[GICV3_G1NS
] = GIC_MIN_BPR
;
671 c
->icc_sre_el1
= 0x7;
672 memset(c
->icc_apr
, 0, sizeof(c
->icc_apr
));
673 memset(c
->icc_igrpen
, 0, sizeof(c
->icc_igrpen
));
675 if (s
->migration_blocker
) {
679 /* Initialize to actual HW supported configuration */
680 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS
,
681 KVM_VGIC_ATTR(ICC_CTLR_EL1
, c
->gicr_typer
),
682 &c
->icc_ctlr_el1
[GICV3_NS
], false, &error_abort
);
684 c
->icc_ctlr_el1
[GICV3_S
] = c
->icc_ctlr_el1
[GICV3_NS
];
687 static void kvm_arm_gicv3_reset(DeviceState
*dev
)
689 GICv3State
*s
= ARM_GICV3_COMMON(dev
);
690 KVMARMGICv3Class
*kgc
= KVM_ARM_GICV3_GET_CLASS(s
);
694 kgc
->parent_reset(dev
);
696 if (s
->migration_blocker
) {
697 DPRINTF("Cannot put kernel gic state, no kernel interface\n");
701 kvm_arm_gicv3_put(s
);
705 * CPU interface registers of GIC needs to be reset on CPU reset.
706 * For the calling arm_gicv3_icc_reset() on CPU reset, we register
707 * below ARMCPRegInfo. As we reset the whole cpu interface under single
708 * register reset, we define only one register of CPU interface instead
709 * of defining all the registers.
711 static const ARMCPRegInfo gicv3_cpuif_reginfo
[] = {
712 { .name
= "ICC_CTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
713 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 12, .opc2
= 4,
715 * If ARM_CP_NOP is used, resetfn is not called,
716 * So ARM_CP_NO_RAW is appropriate type.
718 .type
= ARM_CP_NO_RAW
,
720 .readfn
= arm_cp_read_zero
,
721 .writefn
= arm_cp_write_ignore
,
723 * We hang the whole cpu interface reset routine off here
724 * rather than parcelling it out into one little function
727 .resetfn
= arm_gicv3_icc_reset
,
733 * vm_change_state_handler - VM change state callback aiming at flushing
734 * RDIST pending tables into guest RAM
736 * The tables get flushed to guest RAM whenever the VM gets stopped.
738 static void vm_change_state_handler(void *opaque
, int running
,
741 GICv3State
*s
= (GICv3State
*)opaque
;
749 ret
= kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_CTRL
,
750 KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES
,
753 error_report_err(err
);
755 if (ret
< 0 && ret
!= -EFAULT
) {
761 static void kvm_arm_gicv3_realize(DeviceState
*dev
, Error
**errp
)
763 GICv3State
*s
= KVM_ARM_GICV3(dev
);
764 KVMARMGICv3Class
*kgc
= KVM_ARM_GICV3_GET_CLASS(s
);
765 bool multiple_redist_region_allowed
;
766 Error
*local_err
= NULL
;
769 DPRINTF("kvm_arm_gicv3_realize\n");
771 kgc
->parent_realize(dev
, &local_err
);
773 error_propagate(errp
, local_err
);
777 if (s
->security_extn
) {
778 error_setg(errp
, "the in-kernel VGICv3 does not implement the "
779 "security extensions");
783 gicv3_init_irqs_and_mmio(s
, kvm_arm_gicv3_set_irq
, NULL
, &local_err
);
785 error_propagate(errp
, local_err
);
789 for (i
= 0; i
< s
->num_cpu
; i
++) {
790 ARMCPU
*cpu
= ARM_CPU(qemu_get_cpu(i
));
792 define_arm_cp_regs(cpu
, gicv3_cpuif_reginfo
);
795 /* Try to create the device via the device control API */
796 s
->dev_fd
= kvm_create_device(kvm_state
, KVM_DEV_TYPE_ARM_VGIC_V3
, false);
798 error_setg_errno(errp
, -s
->dev_fd
, "error creating in-kernel VGIC");
802 multiple_redist_region_allowed
=
803 kvm_device_check_attr(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_ADDR
,
804 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION
);
806 if (!multiple_redist_region_allowed
&& s
->nb_redist_regions
> 1) {
807 error_setg(errp
, "Multiple VGICv3 redistributor regions are not "
808 "supported by this host kernel");
809 error_append_hint(errp
, "A maximum of %d VCPUs can be used",
810 s
->redist_region_count
[0]);
814 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_NR_IRQS
,
815 0, &s
->num_irq
, true, &error_abort
);
817 /* Tell the kernel to complete VGIC initialization now */
818 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_CTRL
,
819 KVM_DEV_ARM_VGIC_CTRL_INIT
, NULL
, true, &error_abort
);
821 kvm_arm_register_device(&s
->iomem_dist
, -1, KVM_DEV_ARM_VGIC_GRP_ADDR
,
822 KVM_VGIC_V3_ADDR_TYPE_DIST
, s
->dev_fd
, 0);
824 if (!multiple_redist_region_allowed
) {
825 kvm_arm_register_device(&s
->iomem_redist
[0], -1,
826 KVM_DEV_ARM_VGIC_GRP_ADDR
,
827 KVM_VGIC_V3_ADDR_TYPE_REDIST
, s
->dev_fd
, 0);
829 /* we register regions in reverse order as "devices" are inserted at
830 * the head of a QSLIST and the list is then popped from the head
831 * onwards by kvm_arm_machine_init_done()
833 for (i
= s
->nb_redist_regions
- 1; i
>= 0; i
--) {
834 /* Address mask made of the rdist region index and count */
835 uint64_t addr_ormask
=
836 i
| ((uint64_t)s
->redist_region_count
[i
] << 52);
838 kvm_arm_register_device(&s
->iomem_redist
[i
], -1,
839 KVM_DEV_ARM_VGIC_GRP_ADDR
,
840 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION
,
841 s
->dev_fd
, addr_ormask
);
845 if (kvm_has_gsi_routing()) {
846 /* set up irq routing */
847 for (i
= 0; i
< s
->num_irq
- GIC_INTERNAL
; ++i
) {
848 kvm_irqchip_add_irq_route(kvm_state
, i
, 0, i
);
851 kvm_gsi_routing_allowed
= true;
853 kvm_irqchip_commit_routes(kvm_state
);
856 if (!kvm_device_check_attr(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_DIST_REGS
,
858 error_setg(&s
->migration_blocker
, "This operating system kernel does "
859 "not support vGICv3 migration");
860 if (migrate_add_blocker(s
->migration_blocker
, errp
) < 0) {
861 error_free(s
->migration_blocker
);
865 if (kvm_device_check_attr(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_CTRL
,
866 KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES
)) {
867 qemu_add_vm_change_state_handler(vm_change_state_handler
, s
);
871 static void kvm_arm_gicv3_class_init(ObjectClass
*klass
, void *data
)
873 DeviceClass
*dc
= DEVICE_CLASS(klass
);
874 ARMGICv3CommonClass
*agcc
= ARM_GICV3_COMMON_CLASS(klass
);
875 KVMARMGICv3Class
*kgc
= KVM_ARM_GICV3_CLASS(klass
);
877 agcc
->pre_save
= kvm_arm_gicv3_get
;
878 agcc
->post_load
= kvm_arm_gicv3_put
;
879 device_class_set_parent_realize(dc
, kvm_arm_gicv3_realize
,
880 &kgc
->parent_realize
);
881 device_class_set_parent_reset(dc
, kvm_arm_gicv3_reset
, &kgc
->parent_reset
);
884 static const TypeInfo kvm_arm_gicv3_info
= {
885 .name
= TYPE_KVM_ARM_GICV3
,
886 .parent
= TYPE_ARM_GICV3_COMMON
,
887 .instance_size
= sizeof(GICv3State
),
888 .class_init
= kvm_arm_gicv3_class_init
,
889 .class_size
= sizeof(KVMARMGICv3Class
),
892 static void kvm_arm_gicv3_register_types(void)
894 type_register_static(&kvm_arm_gicv3_info
);
897 type_init(kvm_arm_gicv3_register_types
)