target/riscv/translate.c

   1 /*
   2  * RISC-V emulation for qemu: main translation routines.
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "qemu/osdep.h"
  20 #include "qemu/log.h"
  21 #include "cpu.h"
  22 #include "tcg/tcg-op.h"
  23 #include "disas/disas.h"
  24 #include "exec/cpu_ldst.h"
  25 #include "exec/exec-all.h"
  26 #include "exec/helper-proto.h"
  27 #include "exec/helper-gen.h"
  28
  29 #include "exec/translator.h"
  30 #include "exec/log.h"
  31
  32 #include "instmap.h"
  33
  34 /* global register indices */
  35 static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
  36 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
  37 static TCGv load_res;
  38 static TCGv load_val;
  39
  40 #include "exec/gen-icount.h"
  41
  42 typedef struct DisasContext {
  43     DisasContextBase base;
  44     /* pc_succ_insn points to the instruction following base.pc_next */
  45     target_ulong pc_succ_insn;
  46     target_ulong priv_ver;
  47     bool virt_enabled;
  48     uint32_t opcode;
  49     uint32_t mstatus_fs;
  50     uint32_t misa;
  51     uint32_t mem_idx;
  52     /* Remember the rounding mode encoded in the previous fp instruction,
  53        which we have already installed into env->fp_status.  Or -1 for
  54        no previous fp instruction.  Note that we exit the TB when writing
  55        to any system register, which includes CSR_FRM, so we do not have
  56        to reset this known value.  */
  57     int frm;
  58     bool ext_ifencei;
  59     /* vector extension */
  60     bool vill;
  61     uint8_t lmul;
  62     uint8_t sew;
  63     uint16_t vlen;
  64     uint16_t mlen;
  65     bool vl_eq_vlmax;
  66 } DisasContext;
  67
  68 #ifdef TARGET_RISCV64
  69 /* convert riscv funct3 to qemu memop for load/store */
  70 static const int tcg_memop_lookup[8] = {
  71     [0 ... 7] = -1,
  72     [0] = MO_SB,
  73     [1] = MO_TESW,
  74     [2] = MO_TESL,
  75     [3] = MO_TEQ,
  76     [4] = MO_UB,
  77     [5] = MO_TEUW,
  78     [6] = MO_TEUL,
  79 };
  80 #endif
  81
  82 #ifdef TARGET_RISCV64
  83 #define CASE_OP_32_64(X) case X: case glue(X, W)
  84 #else
  85 #define CASE_OP_32_64(X) case X
  86 #endif
  87
  88 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
  89 {
  90     return ctx->misa & ext;
  91 }
  92
  93 static void generate_exception(DisasContext *ctx, int excp)
  94 {
  95     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
  96     TCGv_i32 helper_tmp = tcg_const_i32(excp);
  97     gen_helper_raise_exception(cpu_env, helper_tmp);
  98     tcg_temp_free_i32(helper_tmp);
  99     ctx->base.is_jmp = DISAS_NORETURN;
 100 }
 101
 102 static void generate_exception_mbadaddr(DisasContext *ctx, int excp)
 103 {
 104     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
 105     tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
 106     TCGv_i32 helper_tmp = tcg_const_i32(excp);
 107     gen_helper_raise_exception(cpu_env, helper_tmp);
 108     tcg_temp_free_i32(helper_tmp);
 109     ctx->base.is_jmp = DISAS_NORETURN;
 110 }
 111
 112 static void gen_exception_debug(void)
 113 {
 114     TCGv_i32 helper_tmp = tcg_const_i32(EXCP_DEBUG);
 115     gen_helper_raise_exception(cpu_env, helper_tmp);
 116     tcg_temp_free_i32(helper_tmp);
 117 }
 118
 119 /* Wrapper around tcg_gen_exit_tb that handles single stepping */
 120 static void exit_tb(DisasContext *ctx)
 121 {
 122     if (ctx->base.singlestep_enabled) {
 123         gen_exception_debug();
 124     } else {
 125         tcg_gen_exit_tb(NULL, 0);
 126     }
 127 }
 128
 129 /* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */
 130 static void lookup_and_goto_ptr(DisasContext *ctx)
 131 {
 132     if (ctx->base.singlestep_enabled) {
 133         gen_exception_debug();
 134     } else {
 135         tcg_gen_lookup_and_goto_ptr();
 136     }
 137 }
 138
 139 static void gen_exception_illegal(DisasContext *ctx)
 140 {
 141     generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
 142 }
 143
 144 static void gen_exception_inst_addr_mis(DisasContext *ctx)
 145 {
 146     generate_exception_mbadaddr(ctx, RISCV_EXCP_INST_ADDR_MIS);
 147 }
 148
 149 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
 150 {
 151     if (unlikely(ctx->base.singlestep_enabled)) {
 152         return false;
 153     }
 154
 155 #ifndef CONFIG_USER_ONLY
 156     return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
 157 #else
 158     return true;
 159 #endif
 160 }
 161
 162 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
 163 {
 164     if (use_goto_tb(ctx, dest)) {
 165         /* chaining is only allowed when the jump is to the same page */
 166         tcg_gen_goto_tb(n);
 167         tcg_gen_movi_tl(cpu_pc, dest);
 168
 169         /* No need to check for single stepping here as use_goto_tb() will
 170          * return false in case of single stepping.
 171          */
 172         tcg_gen_exit_tb(ctx->base.tb, n);
 173     } else {
 174         tcg_gen_movi_tl(cpu_pc, dest);
 175         lookup_and_goto_ptr(ctx);
 176     }
 177 }
 178
 179 /* Wrapper for getting reg values - need to check of reg is zero since
 180  * cpu_gpr[0] is not actually allocated
 181  */
 182 static inline void gen_get_gpr(TCGv t, int reg_num)
 183 {
 184     if (reg_num == 0) {
 185         tcg_gen_movi_tl(t, 0);
 186     } else {
 187         tcg_gen_mov_tl(t, cpu_gpr[reg_num]);
 188     }
 189 }
 190
 191 /* Wrapper for setting reg values - need to check of reg is zero since
 192  * cpu_gpr[0] is not actually allocated. this is more for safety purposes,
 193  * since we usually avoid calling the OP_TYPE_gen function if we see a write to
 194  * $zero
 195  */
 196 static inline void gen_set_gpr(int reg_num_dst, TCGv t)
 197 {
 198     if (reg_num_dst != 0) {
 199         tcg_gen_mov_tl(cpu_gpr[reg_num_dst], t);
 200     }
 201 }
 202
 203 static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
 204 {
 205     TCGv rl = tcg_temp_new();
 206     TCGv rh = tcg_temp_new();
 207
 208     tcg_gen_mulu2_tl(rl, rh, arg1, arg2);
 209     /* fix up for one negative */
 210     tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1);
 211     tcg_gen_and_tl(rl, rl, arg2);
 212     tcg_gen_sub_tl(ret, rh, rl);
 213
 214     tcg_temp_free(rl);
 215     tcg_temp_free(rh);
 216 }
 217
 218 static void gen_div(TCGv ret, TCGv source1, TCGv source2)
 219 {
 220     TCGv cond1, cond2, zeroreg, resultopt1;
 221     /*
 222      * Handle by altering args to tcg_gen_div to produce req'd results:
 223      * For overflow: want source1 in source1 and 1 in source2
 224      * For div by zero: want -1 in source1 and 1 in source2 -> -1 result
 225      */
 226     cond1 = tcg_temp_new();
 227     cond2 = tcg_temp_new();
 228     zeroreg = tcg_const_tl(0);
 229     resultopt1 = tcg_temp_new();
 230
 231     tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
 232     tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L));
 233     tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
 234                         ((target_ulong)1) << (TARGET_LONG_BITS - 1));
 235     tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */
 236     tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */
 237     /* if div by zero, set source1 to -1, otherwise don't change */
 238     tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1,
 239             resultopt1);
 240     /* if overflow or div by zero, set source2 to 1, else don't change */
 241     tcg_gen_or_tl(cond1, cond1, cond2);
 242     tcg_gen_movi_tl(resultopt1, (target_ulong)1);
 243     tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
 244             resultopt1);
 245     tcg_gen_div_tl(ret, source1, source2);
 246
 247     tcg_temp_free(cond1);
 248     tcg_temp_free(cond2);
 249     tcg_temp_free(zeroreg);
 250     tcg_temp_free(resultopt1);
 251 }
 252
 253 static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
 254 {
 255     TCGv cond1, zeroreg, resultopt1;
 256     cond1 = tcg_temp_new();
 257
 258     zeroreg = tcg_const_tl(0);
 259     resultopt1 = tcg_temp_new();
 260
 261     tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
 262     tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
 263     tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1,
 264             resultopt1);
 265     tcg_gen_movi_tl(resultopt1, (target_ulong)1);
 266     tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
 267             resultopt1);
 268     tcg_gen_divu_tl(ret, source1, source2);
 269
 270     tcg_temp_free(cond1);
 271     tcg_temp_free(zeroreg);
 272     tcg_temp_free(resultopt1);
 273 }
 274
 275 static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
 276 {
 277     TCGv cond1, cond2, zeroreg, resultopt1;
 278
 279     cond1 = tcg_temp_new();
 280     cond2 = tcg_temp_new();
 281     zeroreg = tcg_const_tl(0);
 282     resultopt1 = tcg_temp_new();
 283
 284     tcg_gen_movi_tl(resultopt1, 1L);
 285     tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1);
 286     tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
 287                         (target_ulong)1 << (TARGET_LONG_BITS - 1));
 288     tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */
 289     tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */
 290     /* if overflow or div by zero, set source2 to 1, else don't change */
 291     tcg_gen_or_tl(cond2, cond1, cond2);
 292     tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2,
 293             resultopt1);
 294     tcg_gen_rem_tl(resultopt1, source1, source2);
 295     /* if div by zero, just return the original dividend */
 296     tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
 297             source1);
 298
 299     tcg_temp_free(cond1);
 300     tcg_temp_free(cond2);
 301     tcg_temp_free(zeroreg);
 302     tcg_temp_free(resultopt1);
 303 }
 304
 305 static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
 306 {
 307     TCGv cond1, zeroreg, resultopt1;
 308     cond1 = tcg_temp_new();
 309     zeroreg = tcg_const_tl(0);
 310     resultopt1 = tcg_temp_new();
 311
 312     tcg_gen_movi_tl(resultopt1, (target_ulong)1);
 313     tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
 314     tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
 315             resultopt1);
 316     tcg_gen_remu_tl(resultopt1, source1, source2);
 317     /* if div by zero, just return the original dividend */
 318     tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
 319             source1);
 320
 321     tcg_temp_free(cond1);
 322     tcg_temp_free(zeroreg);
 323     tcg_temp_free(resultopt1);
 324 }
 325
 326 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
 327 {
 328     target_ulong next_pc;
 329
 330     /* check misaligned: */
 331     next_pc = ctx->base.pc_next + imm;
 332     if (!has_ext(ctx, RVC)) {
 333         if ((next_pc & 0x3) != 0) {
 334             gen_exception_inst_addr_mis(ctx);
 335             return;
 336         }
 337     }
 338     if (rd != 0) {
 339         tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
 340     }
 341
 342     gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */
 343     ctx->base.is_jmp = DISAS_NORETURN;
 344 }
 345
 346 #ifdef TARGET_RISCV64
 347 static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
 348         target_long imm)
 349 {
 350     TCGv t0 = tcg_temp_new();
 351     TCGv t1 = tcg_temp_new();
 352     gen_get_gpr(t0, rs1);
 353     tcg_gen_addi_tl(t0, t0, imm);
 354     int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
 355
 356     if (memop < 0) {
 357         gen_exception_illegal(ctx);
 358         return;
 359     }
 360
 361     tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
 362     gen_set_gpr(rd, t1);
 363     tcg_temp_free(t0);
 364     tcg_temp_free(t1);
 365 }
 366
 367 static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
 368         target_long imm)
 369 {
 370     TCGv t0 = tcg_temp_new();
 371     TCGv dat = tcg_temp_new();
 372     gen_get_gpr(t0, rs1);
 373     tcg_gen_addi_tl(t0, t0, imm);
 374     gen_get_gpr(dat, rs2);
 375     int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
 376
 377     if (memop < 0) {
 378         gen_exception_illegal(ctx);
 379         return;
 380     }
 381
 382     tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
 383     tcg_temp_free(t0);
 384     tcg_temp_free(dat);
 385 }
 386 #endif
 387
 388 #ifndef CONFIG_USER_ONLY
 389 /* The states of mstatus_fs are:
 390  * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
 391  * We will have already diagnosed disabled state,
 392  * and need to turn initial/clean into dirty.
 393  */
 394 static void mark_fs_dirty(DisasContext *ctx)
 395 {
 396     TCGv tmp;
 397     if (ctx->mstatus_fs == MSTATUS_FS) {
 398         return;
 399     }
 400     /* Remember the state change for the rest of the TB.  */
 401     ctx->mstatus_fs = MSTATUS_FS;
 402
 403     tmp = tcg_temp_new();
 404     tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
 405     tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
 406     tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
 407
 408     if (ctx->virt_enabled) {
 409         tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
 410         tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
 411         tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
 412     }
 413     tcg_temp_free(tmp);
 414 }
 415 #else
 416 static inline void mark_fs_dirty(DisasContext *ctx) { }
 417 #endif
 418
 419 #if !defined(TARGET_RISCV64)
 420 static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
 421         int rs1, target_long imm)
 422 {
 423     TCGv t0;
 424
 425     if (ctx->mstatus_fs == 0) {
 426         gen_exception_illegal(ctx);
 427         return;
 428     }
 429
 430     t0 = tcg_temp_new();
 431     gen_get_gpr(t0, rs1);
 432     tcg_gen_addi_tl(t0, t0, imm);
 433
 434     switch (opc) {
 435     case OPC_RISC_FLW:
 436         if (!has_ext(ctx, RVF)) {
 437             goto do_illegal;
 438         }
 439         tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
 440         /* RISC-V requires NaN-boxing of narrower width floating point values */
 441         tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
 442         break;
 443     case OPC_RISC_FLD:
 444         if (!has_ext(ctx, RVD)) {
 445             goto do_illegal;
 446         }
 447         tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
 448         break;
 449     do_illegal:
 450     default:
 451         gen_exception_illegal(ctx);
 452         break;
 453     }
 454     tcg_temp_free(t0);
 455
 456     mark_fs_dirty(ctx);
 457 }
 458
 459 static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
 460         int rs2, target_long imm)
 461 {
 462     TCGv t0;
 463
 464     if (ctx->mstatus_fs == 0) {
 465         gen_exception_illegal(ctx);
 466         return;
 467     }
 468
 469     t0 = tcg_temp_new();
 470     gen_get_gpr(t0, rs1);
 471     tcg_gen_addi_tl(t0, t0, imm);
 472
 473     switch (opc) {
 474     case OPC_RISC_FSW:
 475         if (!has_ext(ctx, RVF)) {
 476             goto do_illegal;
 477         }
 478         tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
 479         break;
 480     case OPC_RISC_FSD:
 481         if (!has_ext(ctx, RVD)) {
 482             goto do_illegal;
 483         }
 484         tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
 485         break;
 486     do_illegal:
 487     default:
 488         gen_exception_illegal(ctx);
 489         break;
 490     }
 491
 492     tcg_temp_free(t0);
 493 }
 494 #endif
 495
 496 static void gen_set_rm(DisasContext *ctx, int rm)
 497 {
 498     TCGv_i32 t0;
 499
 500     if (ctx->frm == rm) {
 501         return;
 502     }
 503     ctx->frm = rm;
 504     t0 = tcg_const_i32(rm);
 505     gen_helper_set_rounding_mode(cpu_env, t0);
 506     tcg_temp_free_i32(t0);
 507 }
 508
 509 static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
 510 {
 511     uint8_t funct3 = extract16(opcode, 13, 3);
 512     uint8_t rd_rs2 = GET_C_RS2S(opcode);
 513     uint8_t rs1s = GET_C_RS1S(opcode);
 514
 515     switch (funct3) {
 516     case 3:
 517 #if defined(TARGET_RISCV64)
 518         /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
 519         gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
 520                  GET_C_LD_IMM(opcode));
 521 #else
 522         /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
 523         gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
 524                     GET_C_LW_IMM(opcode));
 525 #endif
 526         break;
 527     case 7:
 528 #if defined(TARGET_RISCV64)
 529         /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
 530         gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
 531                   GET_C_LD_IMM(opcode));
 532 #else
 533         /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
 534         gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
 535                      GET_C_LW_IMM(opcode));
 536 #endif
 537         break;
 538     }
 539 }
 540
 541 static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
 542 {
 543     uint8_t op = extract16(opcode, 0, 2);
 544
 545     switch (op) {
 546     case 0:
 547         decode_RV32_64C0(ctx, opcode);
 548         break;
 549     }
 550 }
 551
 552 static int ex_plus_1(DisasContext *ctx, int nf)
 553 {
 554     return nf + 1;
 555 }
 556
 557 #define EX_SH(amount) \
 558     static int ex_shift_##amount(DisasContext *ctx, int imm) \
 559     {                                         \
 560         return imm << amount;                 \
 561     }
 562 EX_SH(1)
 563 EX_SH(2)
 564 EX_SH(3)
 565 EX_SH(4)
 566 EX_SH(12)
 567
 568 #define REQUIRE_EXT(ctx, ext) do { \
 569     if (!has_ext(ctx, ext)) {      \
 570         return false;              \
 571     }                              \
 572 } while (0)
 573
 574 static int ex_rvc_register(DisasContext *ctx, int reg)
 575 {
 576     return 8 + reg;
 577 }
 578
 579 static int ex_rvc_shifti(DisasContext *ctx, int imm)
 580 {
 581     /* For RV128 a shamt of 0 means a shift by 64. */
 582     return imm ? imm : 64;
 583 }
 584
 585 /* Include the auto-generated decoder for 32 bit insn */
 586 #include "decode-insn32.c.inc"
 587
 588 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a,
 589                              void (*func)(TCGv, TCGv, target_long))
 590 {
 591     TCGv source1;
 592     source1 = tcg_temp_new();
 593
 594     gen_get_gpr(source1, a->rs1);
 595
 596     (*func)(source1, source1, a->imm);
 597
 598     gen_set_gpr(a->rd, source1);
 599     tcg_temp_free(source1);
 600     return true;
 601 }
 602
 603 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
 604                              void (*func)(TCGv, TCGv, TCGv))
 605 {
 606     TCGv source1, source2;
 607     source1 = tcg_temp_new();
 608     source2 = tcg_temp_new();
 609
 610     gen_get_gpr(source1, a->rs1);
 611     tcg_gen_movi_tl(source2, a->imm);
 612
 613     (*func)(source1, source1, source2);
 614
 615     gen_set_gpr(a->rd, source1);
 616     tcg_temp_free(source1);
 617     tcg_temp_free(source2);
 618     return true;
 619 }
 620
 621 #ifdef TARGET_RISCV64
 622 static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
 623 {
 624     tcg_gen_add_tl(ret, arg1, arg2);
 625     tcg_gen_ext32s_tl(ret, ret);
 626 }
 627
 628 static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2)
 629 {
 630     tcg_gen_sub_tl(ret, arg1, arg2);
 631     tcg_gen_ext32s_tl(ret, ret);
 632 }
 633
 634 static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2)
 635 {
 636     tcg_gen_mul_tl(ret, arg1, arg2);
 637     tcg_gen_ext32s_tl(ret, ret);
 638 }
 639
 640 static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
 641                             void(*func)(TCGv, TCGv, TCGv))
 642 {
 643     TCGv source1, source2;
 644     source1 = tcg_temp_new();
 645     source2 = tcg_temp_new();
 646
 647     gen_get_gpr(source1, a->rs1);
 648     gen_get_gpr(source2, a->rs2);
 649     tcg_gen_ext32s_tl(source1, source1);
 650     tcg_gen_ext32s_tl(source2, source2);
 651
 652     (*func)(source1, source1, source2);
 653
 654     tcg_gen_ext32s_tl(source1, source1);
 655     gen_set_gpr(a->rd, source1);
 656     tcg_temp_free(source1);
 657     tcg_temp_free(source2);
 658     return true;
 659 }
 660
 661 static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
 662                             void(*func)(TCGv, TCGv, TCGv))
 663 {
 664     TCGv source1, source2;
 665     source1 = tcg_temp_new();
 666     source2 = tcg_temp_new();
 667
 668     gen_get_gpr(source1, a->rs1);
 669     gen_get_gpr(source2, a->rs2);
 670     tcg_gen_ext32u_tl(source1, source1);
 671     tcg_gen_ext32u_tl(source2, source2);
 672
 673     (*func)(source1, source1, source2);
 674
 675     tcg_gen_ext32s_tl(source1, source1);
 676     gen_set_gpr(a->rd, source1);
 677     tcg_temp_free(source1);
 678     tcg_temp_free(source2);
 679     return true;
 680 }
 681
 682 #endif
 683
 684 static bool gen_arith(DisasContext *ctx, arg_r *a,
 685                       void(*func)(TCGv, TCGv, TCGv))
 686 {
 687     TCGv source1, source2;
 688     source1 = tcg_temp_new();
 689     source2 = tcg_temp_new();
 690
 691     gen_get_gpr(source1, a->rs1);
 692     gen_get_gpr(source2, a->rs2);
 693
 694     (*func)(source1, source1, source2);
 695
 696     gen_set_gpr(a->rd, source1);
 697     tcg_temp_free(source1);
 698     tcg_temp_free(source2);
 699     return true;
 700 }
 701
 702 static bool gen_shift(DisasContext *ctx, arg_r *a,
 703                         void(*func)(TCGv, TCGv, TCGv))
 704 {
 705     TCGv source1 = tcg_temp_new();
 706     TCGv source2 = tcg_temp_new();
 707
 708     gen_get_gpr(source1, a->rs1);
 709     gen_get_gpr(source2, a->rs2);
 710
 711     tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
 712     (*func)(source1, source1, source2);
 713
 714     gen_set_gpr(a->rd, source1);
 715     tcg_temp_free(source1);
 716     tcg_temp_free(source2);
 717     return true;
 718 }
 719
 720 /* Include insn module translation function */
 721 #include "insn_trans/trans_rvi.c.inc"
 722 #include "insn_trans/trans_rvm.c.inc"
 723 #include "insn_trans/trans_rva.c.inc"
 724 #include "insn_trans/trans_rvf.c.inc"
 725 #include "insn_trans/trans_rvd.c.inc"
 726 #include "insn_trans/trans_rvh.c.inc"
 727 #include "insn_trans/trans_rvv.c.inc"
 728 #include "insn_trans/trans_privileged.c.inc"
 729
 730 /* Include the auto-generated decoder for 16 bit insn */
 731 #include "decode-insn16.c.inc"
 732
 733 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 734 {
 735     /* check for compressed insn */
 736     if (extract16(opcode, 0, 2) != 3) {
 737         if (!has_ext(ctx, RVC)) {
 738             gen_exception_illegal(ctx);
 739         } else {
 740             ctx->pc_succ_insn = ctx->base.pc_next + 2;
 741             if (!decode_insn16(ctx, opcode)) {
 742                 /* fall back to old decoder */
 743                 decode_RV32_64C(ctx, opcode);
 744             }
 745         }
 746     } else {
 747         uint32_t opcode32 = opcode;
 748         opcode32 = deposit32(opcode32, 16, 16,
 749                              translator_lduw(env, ctx->base.pc_next + 2));
 750         ctx->pc_succ_insn = ctx->base.pc_next + 4;
 751         if (!decode_insn32(ctx, opcode32)) {
 752             gen_exception_illegal(ctx);
 753         }
 754     }
 755 }
 756
 757 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
 758 {
 759     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 760     CPURISCVState *env = cs->env_ptr;
 761     RISCVCPU *cpu = RISCV_CPU(cs);
 762     uint32_t tb_flags = ctx->base.tb->flags;
 763
 764     ctx->pc_succ_insn = ctx->base.pc_first;
 765     ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK;
 766     ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
 767     ctx->priv_ver = env->priv_ver;
 768 #if !defined(CONFIG_USER_ONLY)
 769     if (riscv_has_ext(env, RVH)) {
 770         ctx->virt_enabled = riscv_cpu_virt_enabled(env);
 771         if (env->priv_ver == PRV_M &&
 772             get_field(env->mstatus, MSTATUS_MPRV) &&
 773             MSTATUS_MPV_ISSET(env)) {
 774             ctx->virt_enabled = true;
 775         } else if (env->priv == PRV_S &&
 776                    !riscv_cpu_virt_enabled(env) &&
 777                    get_field(env->hstatus, HSTATUS_SPRV) &&
 778                    get_field(env->hstatus, HSTATUS_SPV)) {
 779             ctx->virt_enabled = true;
 780         }
 781     } else {
 782         ctx->virt_enabled = false;
 783     }
 784 #else
 785     ctx->virt_enabled = false;
 786 #endif
 787     ctx->misa = env->misa;
 788     ctx->frm = -1;  /* unknown rounding mode */
 789     ctx->ext_ifencei = cpu->cfg.ext_ifencei;
 790     ctx->vlen = cpu->cfg.vlen;
 791     ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
 792     ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
 793     ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
 794     ctx->mlen = 1 << (ctx->sew  + 3 - ctx->lmul);
 795     ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
 796 }
 797
 798 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
 799 {
 800 }
 801
 802 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
 803 {
 804     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 805
 806     tcg_gen_insn_start(ctx->base.pc_next);
 807 }
 808
 809 static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
 810                                       const CPUBreakpoint *bp)
 811 {
 812     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 813
 814     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
 815     ctx->base.is_jmp = DISAS_NORETURN;
 816     gen_exception_debug();
 817     /* The address covered by the breakpoint must be included in
 818        [tb->pc, tb->pc + tb->size) in order to for it to be
 819        properly cleared -- thus we increment the PC here so that
 820        the logic setting tb->size below does the right thing.  */
 821     ctx->base.pc_next += 4;
 822     return true;
 823 }
 824
 825 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
 826 {
 827     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 828     CPURISCVState *env = cpu->env_ptr;
 829     uint16_t opcode16 = translator_lduw(env, ctx->base.pc_next);
 830
 831     decode_opc(env, ctx, opcode16);
 832     ctx->base.pc_next = ctx->pc_succ_insn;
 833
 834     if (ctx->base.is_jmp == DISAS_NEXT) {
 835         target_ulong page_start;
 836
 837         page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
 838         if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) {
 839             ctx->base.is_jmp = DISAS_TOO_MANY;
 840         }
 841     }
 842 }
 843
 844 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
 845 {
 846     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 847
 848     switch (ctx->base.is_jmp) {
 849     case DISAS_TOO_MANY:
 850         gen_goto_tb(ctx, 0, ctx->base.pc_next);
 851         break;
 852     case DISAS_NORETURN:
 853         break;
 854     default:
 855         g_assert_not_reached();
 856     }
 857 }
 858
 859 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
 860 {
 861 #ifndef CONFIG_USER_ONLY
 862     RISCVCPU *rvcpu = RISCV_CPU(cpu);
 863     CPURISCVState *env = &rvcpu->env;
 864 #endif
 865
 866     qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
 867 #ifndef CONFIG_USER_ONLY
 868     qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt);
 869 #endif
 870     log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
 871 }
 872
 873 static const TranslatorOps riscv_tr_ops = {
 874     .init_disas_context = riscv_tr_init_disas_context,
 875     .tb_start           = riscv_tr_tb_start,
 876     .insn_start         = riscv_tr_insn_start,
 877     .breakpoint_check   = riscv_tr_breakpoint_check,
 878     .translate_insn     = riscv_tr_translate_insn,
 879     .tb_stop            = riscv_tr_tb_stop,
 880     .disas_log          = riscv_tr_disas_log,
 881 };
 882
 883 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
 884 {
 885     DisasContext ctx;
 886
 887     translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns);
 888 }
 889
 890 void riscv_translate_init(void)
 891 {
 892     int i;
 893
 894     /* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */
 895     /* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */
 896     /* registers, unless you specifically block reads/writes to reg 0 */
 897     cpu_gpr[0] = NULL;
 898
 899     for (i = 1; i < 32; i++) {
 900         cpu_gpr[i] = tcg_global_mem_new(cpu_env,
 901             offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]);
 902     }
 903
 904     for (i = 0; i < 32; i++) {
 905         cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
 906             offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]);
 907     }
 908
 909     cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc");
 910     cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl");
 911     load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res),
 912                              "load_res");
 913     load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
 914                              "load_val");
 915 }