4 * Copyright (c) 2004-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>
19 #include "apic_internal.h"
22 #include "host-utils.h"
26 #define MAX_APIC_WORDS 8
28 /* Intel APIC constants: from include/asm/msidef.h */
29 #define MSI_DATA_VECTOR_SHIFT 0
30 #define MSI_DATA_VECTOR_MASK 0x000000ff
31 #define MSI_DATA_DELIVERY_MODE_SHIFT 8
32 #define MSI_DATA_TRIGGER_SHIFT 15
33 #define MSI_DATA_LEVEL_SHIFT 14
34 #define MSI_ADDR_DEST_MODE_SHIFT 2
35 #define MSI_ADDR_DEST_ID_SHIFT 12
36 #define MSI_ADDR_DEST_ID_MASK 0x00ffff0
38 static APICCommonState
*local_apics
[MAX_APICS
+ 1];
40 static void apic_set_irq(APICCommonState
*s
, int vector_num
, int trigger_mode
);
41 static void apic_update_irq(APICCommonState
*s
);
42 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask
,
43 uint8_t dest
, uint8_t dest_mode
);
45 /* Find first bit starting from msb */
46 static int fls_bit(uint32_t value
)
48 return 31 - clz32(value
);
51 /* Find first bit starting from lsb */
52 static int ffs_bit(uint32_t value
)
57 static inline void set_bit(uint32_t *tab
, int index
)
61 mask
= 1 << (index
& 0x1f);
65 static inline void reset_bit(uint32_t *tab
, int index
)
69 mask
= 1 << (index
& 0x1f);
73 static inline int get_bit(uint32_t *tab
, int index
)
77 mask
= 1 << (index
& 0x1f);
78 return !!(tab
[i
] & mask
);
81 static void apic_local_deliver(APICCommonState
*s
, int vector
)
83 uint32_t lvt
= s
->lvt
[vector
];
86 trace_apic_local_deliver(vector
, (lvt
>> 8) & 7);
88 if (lvt
& APIC_LVT_MASKED
)
91 switch ((lvt
>> 8) & 7) {
93 cpu_interrupt(s
->cpu_env
, CPU_INTERRUPT_SMI
);
97 cpu_interrupt(s
->cpu_env
, CPU_INTERRUPT_NMI
);
101 cpu_interrupt(s
->cpu_env
, CPU_INTERRUPT_HARD
);
105 trigger_mode
= APIC_TRIGGER_EDGE
;
106 if ((vector
== APIC_LVT_LINT0
|| vector
== APIC_LVT_LINT1
) &&
107 (lvt
& APIC_LVT_LEVEL_TRIGGER
))
108 trigger_mode
= APIC_TRIGGER_LEVEL
;
109 apic_set_irq(s
, lvt
& 0xff, trigger_mode
);
113 void apic_deliver_pic_intr(DeviceState
*d
, int level
)
115 APICCommonState
*s
= DO_UPCAST(APICCommonState
, busdev
.qdev
, d
);
118 apic_local_deliver(s
, APIC_LVT_LINT0
);
120 uint32_t lvt
= s
->lvt
[APIC_LVT_LINT0
];
122 switch ((lvt
>> 8) & 7) {
124 if (!(lvt
& APIC_LVT_LEVEL_TRIGGER
))
126 reset_bit(s
->irr
, lvt
& 0xff);
129 cpu_reset_interrupt(s
->cpu_env
, CPU_INTERRUPT_HARD
);
135 static void apic_external_nmi(APICCommonState
*s
)
137 apic_local_deliver(s
, APIC_LVT_LINT1
);
140 #define foreach_apic(apic, deliver_bitmask, code) \
142 int __i, __j, __mask;\
143 for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
144 __mask = deliver_bitmask[__i];\
146 for(__j = 0; __j < 32; __j++) {\
147 if (__mask & (1 << __j)) {\
148 apic = local_apics[__i * 32 + __j];\
158 static void apic_bus_deliver(const uint32_t *deliver_bitmask
,
159 uint8_t delivery_mode
, uint8_t vector_num
,
160 uint8_t trigger_mode
)
162 APICCommonState
*apic_iter
;
164 switch (delivery_mode
) {
166 /* XXX: search for focus processor, arbitration */
170 for(i
= 0; i
< MAX_APIC_WORDS
; i
++) {
171 if (deliver_bitmask
[i
]) {
172 d
= i
* 32 + ffs_bit(deliver_bitmask
[i
]);
177 apic_iter
= local_apics
[d
];
179 apic_set_irq(apic_iter
, vector_num
, trigger_mode
);
189 foreach_apic(apic_iter
, deliver_bitmask
,
190 cpu_interrupt(apic_iter
->cpu_env
, CPU_INTERRUPT_SMI
) );
194 foreach_apic(apic_iter
, deliver_bitmask
,
195 cpu_interrupt(apic_iter
->cpu_env
, CPU_INTERRUPT_NMI
) );
199 /* normal INIT IPI sent to processors */
200 foreach_apic(apic_iter
, deliver_bitmask
,
201 cpu_interrupt(apic_iter
->cpu_env
, CPU_INTERRUPT_INIT
) );
205 /* handled in I/O APIC code */
212 foreach_apic(apic_iter
, deliver_bitmask
,
213 apic_set_irq(apic_iter
, vector_num
, trigger_mode
) );
216 void apic_deliver_irq(uint8_t dest
, uint8_t dest_mode
, uint8_t delivery_mode
,
217 uint8_t vector_num
, uint8_t trigger_mode
)
219 uint32_t deliver_bitmask
[MAX_APIC_WORDS
];
221 trace_apic_deliver_irq(dest
, dest_mode
, delivery_mode
, vector_num
,
224 apic_get_delivery_bitmask(deliver_bitmask
, dest
, dest_mode
);
225 apic_bus_deliver(deliver_bitmask
, delivery_mode
, vector_num
, trigger_mode
);
228 static void apic_set_base(APICCommonState
*s
, uint64_t val
)
230 s
->apicbase
= (val
& 0xfffff000) |
231 (s
->apicbase
& (MSR_IA32_APICBASE_BSP
| MSR_IA32_APICBASE_ENABLE
));
232 /* if disabled, cannot be enabled again */
233 if (!(val
& MSR_IA32_APICBASE_ENABLE
)) {
234 s
->apicbase
&= ~MSR_IA32_APICBASE_ENABLE
;
235 cpu_clear_apic_feature(s
->cpu_env
);
236 s
->spurious_vec
&= ~APIC_SV_ENABLE
;
240 static void apic_set_tpr(APICCommonState
*s
, uint8_t val
)
242 s
->tpr
= (val
& 0x0f) << 4;
246 /* return -1 if no bit is set */
247 static int get_highest_priority_int(uint32_t *tab
)
250 for(i
= 7; i
>= 0; i
--) {
252 return i
* 32 + fls_bit(tab
[i
]);
258 static int apic_get_ppr(APICCommonState
*s
)
263 isrv
= get_highest_priority_int(s
->isr
);
274 static int apic_get_arb_pri(APICCommonState
*s
)
276 /* XXX: arbitration */
282 * <0 - low prio interrupt,
284 * >0 - interrupt number
286 static int apic_irq_pending(APICCommonState
*s
)
289 irrv
= get_highest_priority_int(s
->irr
);
293 ppr
= apic_get_ppr(s
);
294 if (ppr
&& (irrv
& 0xf0) <= (ppr
& 0xf0)) {
301 /* signal the CPU if an irq is pending */
302 static void apic_update_irq(APICCommonState
*s
)
304 if (!(s
->spurious_vec
& APIC_SV_ENABLE
)) {
307 if (apic_irq_pending(s
) > 0) {
308 cpu_interrupt(s
->cpu_env
, CPU_INTERRUPT_HARD
);
309 } else if (apic_accept_pic_intr(&s
->busdev
.qdev
) &&
310 pic_get_output(isa_pic
)) {
311 apic_deliver_pic_intr(&s
->busdev
.qdev
, 1);
315 static void apic_set_irq(APICCommonState
*s
, int vector_num
, int trigger_mode
)
317 apic_report_irq_delivered(!get_bit(s
->irr
, vector_num
));
319 set_bit(s
->irr
, vector_num
);
321 set_bit(s
->tmr
, vector_num
);
323 reset_bit(s
->tmr
, vector_num
);
327 static void apic_eoi(APICCommonState
*s
)
330 isrv
= get_highest_priority_int(s
->isr
);
333 reset_bit(s
->isr
, isrv
);
334 if (!(s
->spurious_vec
& APIC_SV_DIRECTED_IO
) && get_bit(s
->tmr
, isrv
)) {
335 ioapic_eoi_broadcast(isrv
);
340 static int apic_find_dest(uint8_t dest
)
342 APICCommonState
*apic
= local_apics
[dest
];
345 if (apic
&& apic
->id
== dest
)
346 return dest
; /* shortcut in case apic->id == apic->idx */
348 for (i
= 0; i
< MAX_APICS
; i
++) {
349 apic
= local_apics
[i
];
350 if (apic
&& apic
->id
== dest
)
359 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask
,
360 uint8_t dest
, uint8_t dest_mode
)
362 APICCommonState
*apic_iter
;
365 if (dest_mode
== 0) {
367 memset(deliver_bitmask
, 0xff, MAX_APIC_WORDS
* sizeof(uint32_t));
369 int idx
= apic_find_dest(dest
);
370 memset(deliver_bitmask
, 0x00, MAX_APIC_WORDS
* sizeof(uint32_t));
372 set_bit(deliver_bitmask
, idx
);
375 /* XXX: cluster mode */
376 memset(deliver_bitmask
, 0x00, MAX_APIC_WORDS
* sizeof(uint32_t));
377 for(i
= 0; i
< MAX_APICS
; i
++) {
378 apic_iter
= local_apics
[i
];
380 if (apic_iter
->dest_mode
== 0xf) {
381 if (dest
& apic_iter
->log_dest
)
382 set_bit(deliver_bitmask
, i
);
383 } else if (apic_iter
->dest_mode
== 0x0) {
384 if ((dest
& 0xf0) == (apic_iter
->log_dest
& 0xf0) &&
385 (dest
& apic_iter
->log_dest
& 0x0f)) {
386 set_bit(deliver_bitmask
, i
);
396 static void apic_startup(APICCommonState
*s
, int vector_num
)
398 s
->sipi_vector
= vector_num
;
399 cpu_interrupt(s
->cpu_env
, CPU_INTERRUPT_SIPI
);
402 void apic_sipi(DeviceState
*d
)
404 APICCommonState
*s
= DO_UPCAST(APICCommonState
, busdev
.qdev
, d
);
406 cpu_reset_interrupt(s
->cpu_env
, CPU_INTERRUPT_SIPI
);
408 if (!s
->wait_for_sipi
)
410 cpu_x86_load_seg_cache_sipi(s
->cpu_env
, s
->sipi_vector
);
411 s
->wait_for_sipi
= 0;
414 static void apic_deliver(DeviceState
*d
, uint8_t dest
, uint8_t dest_mode
,
415 uint8_t delivery_mode
, uint8_t vector_num
,
416 uint8_t trigger_mode
)
418 APICCommonState
*s
= DO_UPCAST(APICCommonState
, busdev
.qdev
, d
);
419 uint32_t deliver_bitmask
[MAX_APIC_WORDS
];
420 int dest_shorthand
= (s
->icr
[0] >> 18) & 3;
421 APICCommonState
*apic_iter
;
423 switch (dest_shorthand
) {
425 apic_get_delivery_bitmask(deliver_bitmask
, dest
, dest_mode
);
428 memset(deliver_bitmask
, 0x00, sizeof(deliver_bitmask
));
429 set_bit(deliver_bitmask
, s
->idx
);
432 memset(deliver_bitmask
, 0xff, sizeof(deliver_bitmask
));
435 memset(deliver_bitmask
, 0xff, sizeof(deliver_bitmask
));
436 reset_bit(deliver_bitmask
, s
->idx
);
440 switch (delivery_mode
) {
443 int trig_mode
= (s
->icr
[0] >> 15) & 1;
444 int level
= (s
->icr
[0] >> 14) & 1;
445 if (level
== 0 && trig_mode
== 1) {
446 foreach_apic(apic_iter
, deliver_bitmask
,
447 apic_iter
->arb_id
= apic_iter
->id
);
454 foreach_apic(apic_iter
, deliver_bitmask
,
455 apic_startup(apic_iter
, vector_num
) );
459 apic_bus_deliver(deliver_bitmask
, delivery_mode
, vector_num
, trigger_mode
);
462 int apic_get_interrupt(DeviceState
*d
)
464 APICCommonState
*s
= DO_UPCAST(APICCommonState
, busdev
.qdev
, d
);
467 /* if the APIC is installed or enabled, we let the 8259 handle the
471 if (!(s
->spurious_vec
& APIC_SV_ENABLE
))
474 intno
= apic_irq_pending(s
);
478 } else if (intno
< 0) {
479 return s
->spurious_vec
& 0xff;
481 reset_bit(s
->irr
, intno
);
482 set_bit(s
->isr
, intno
);
487 int apic_accept_pic_intr(DeviceState
*d
)
489 APICCommonState
*s
= DO_UPCAST(APICCommonState
, busdev
.qdev
, d
);
495 lvt0
= s
->lvt
[APIC_LVT_LINT0
];
497 if ((s
->apicbase
& MSR_IA32_APICBASE_ENABLE
) == 0 ||
498 (lvt0
& APIC_LVT_MASKED
) == 0)
504 static uint32_t apic_get_current_count(APICCommonState
*s
)
508 d
= (qemu_get_clock_ns(vm_clock
) - s
->initial_count_load_time
) >>
510 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_TIMER_PERIODIC
) {
512 val
= s
->initial_count
- (d
% ((uint64_t)s
->initial_count
+ 1));
514 if (d
>= s
->initial_count
)
517 val
= s
->initial_count
- d
;
522 static void apic_timer_update(APICCommonState
*s
, int64_t current_time
)
524 if (apic_next_timer(s
, current_time
)) {
525 qemu_mod_timer(s
->timer
, s
->next_time
);
527 qemu_del_timer(s
->timer
);
531 static void apic_timer(void *opaque
)
533 APICCommonState
*s
= opaque
;
535 apic_local_deliver(s
, APIC_LVT_TIMER
);
536 apic_timer_update(s
, s
->next_time
);
539 static uint32_t apic_mem_readb(void *opaque
, target_phys_addr_t addr
)
544 static uint32_t apic_mem_readw(void *opaque
, target_phys_addr_t addr
)
549 static void apic_mem_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
553 static void apic_mem_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
557 static uint32_t apic_mem_readl(void *opaque
, target_phys_addr_t addr
)
564 d
= cpu_get_current_apic();
568 s
= DO_UPCAST(APICCommonState
, busdev
.qdev
, d
);
570 index
= (addr
>> 4) & 0xff;
575 case 0x03: /* version */
576 val
= 0x11 | ((APIC_LVT_NB
- 1) << 16); /* version 0x11 */
582 val
= apic_get_arb_pri(s
);
586 val
= apic_get_ppr(s
);
592 val
= s
->log_dest
<< 24;
595 val
= s
->dest_mode
<< 28;
598 val
= s
->spurious_vec
;
601 val
= s
->isr
[index
& 7];
604 val
= s
->tmr
[index
& 7];
607 val
= s
->irr
[index
& 7];
614 val
= s
->icr
[index
& 1];
617 val
= s
->lvt
[index
- 0x32];
620 val
= s
->initial_count
;
623 val
= apic_get_current_count(s
);
626 val
= s
->divide_conf
;
629 s
->esr
|= ESR_ILLEGAL_ADDRESS
;
633 trace_apic_mem_readl(addr
, val
);
637 static void apic_send_msi(target_phys_addr_t addr
, uint32_t data
)
639 uint8_t dest
= (addr
& MSI_ADDR_DEST_ID_MASK
) >> MSI_ADDR_DEST_ID_SHIFT
;
640 uint8_t vector
= (data
& MSI_DATA_VECTOR_MASK
) >> MSI_DATA_VECTOR_SHIFT
;
641 uint8_t dest_mode
= (addr
>> MSI_ADDR_DEST_MODE_SHIFT
) & 0x1;
642 uint8_t trigger_mode
= (data
>> MSI_DATA_TRIGGER_SHIFT
) & 0x1;
643 uint8_t delivery
= (data
>> MSI_DATA_DELIVERY_MODE_SHIFT
) & 0x7;
644 /* XXX: Ignore redirection hint. */
645 apic_deliver_irq(dest
, dest_mode
, delivery
, vector
, trigger_mode
);
648 static void apic_mem_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
652 int index
= (addr
>> 4) & 0xff;
653 if (addr
> 0xfff || !index
) {
654 /* MSI and MMIO APIC are at the same memory location,
655 * but actually not on the global bus: MSI is on PCI bus
656 * APIC is connected directly to the CPU.
657 * Mapping them on the global bus happens to work because
658 * MSI registers are reserved in APIC MMIO and vice versa. */
659 apic_send_msi(addr
, val
);
663 d
= cpu_get_current_apic();
667 s
= DO_UPCAST(APICCommonState
, busdev
.qdev
, d
);
669 trace_apic_mem_writel(addr
, val
);
688 s
->log_dest
= val
>> 24;
691 s
->dest_mode
= val
>> 28;
694 s
->spurious_vec
= val
& 0x1ff;
704 apic_deliver(d
, (s
->icr
[1] >> 24) & 0xff, (s
->icr
[0] >> 11) & 1,
705 (s
->icr
[0] >> 8) & 7, (s
->icr
[0] & 0xff),
706 (s
->icr
[0] >> 15) & 1);
713 int n
= index
- 0x32;
715 if (n
== APIC_LVT_TIMER
)
716 apic_timer_update(s
, qemu_get_clock_ns(vm_clock
));
720 s
->initial_count
= val
;
721 s
->initial_count_load_time
= qemu_get_clock_ns(vm_clock
);
722 apic_timer_update(s
, s
->initial_count_load_time
);
729 s
->divide_conf
= val
& 0xb;
730 v
= (s
->divide_conf
& 3) | ((s
->divide_conf
>> 1) & 4);
731 s
->count_shift
= (v
+ 1) & 7;
735 s
->esr
|= ESR_ILLEGAL_ADDRESS
;
740 static void apic_post_load(APICCommonState
*s
)
742 if (s
->timer_expiry
!= -1) {
743 qemu_mod_timer(s
->timer
, s
->timer_expiry
);
745 qemu_del_timer(s
->timer
);
749 static const MemoryRegionOps apic_io_ops
= {
751 .read
= { apic_mem_readb
, apic_mem_readw
, apic_mem_readl
, },
752 .write
= { apic_mem_writeb
, apic_mem_writew
, apic_mem_writel
, },
754 .endianness
= DEVICE_NATIVE_ENDIAN
,
757 static void apic_init(APICCommonState
*s
)
759 memory_region_init_io(&s
->io_memory
, &apic_io_ops
, s
, "apic-msi",
762 s
->timer
= qemu_new_timer_ns(vm_clock
, apic_timer
, s
);
763 local_apics
[s
->idx
] = s
;
766 static void apic_class_init(ObjectClass
*klass
, void *data
)
768 APICCommonClass
*k
= APIC_COMMON_CLASS(klass
);
771 k
->set_base
= apic_set_base
;
772 k
->set_tpr
= apic_set_tpr
;
773 k
->external_nmi
= apic_external_nmi
;
774 k
->post_load
= apic_post_load
;
777 static DeviceInfo apic_info
= {
779 .class_init
= apic_class_init
,
782 static void apic_register_devices(void)
784 apic_qdev_register(&apic_info
);
787 device_init(apic_register_devices
)