hw/cpu/a15mpcore.c

   1 /*
   2  * Cortex-A15MPCore internal peripheral emulation.
   3  *
   4  * Copyright (c) 2012 Linaro Limited.
   5  * Written by Peter Maydell.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "qemu/module.h"
  24 #include "hw/cpu/a15mpcore.h"
  25 #include "hw/irq.h"
  26 #include "hw/qdev-properties.h"
  27 #include "sysemu/kvm.h"
  28 #include "kvm_arm.h"
  29
  30 static void a15mp_priv_set_irq(void *opaque, int irq, int level)
  31 {
  32     A15MPPrivState *s = (A15MPPrivState *)opaque;
  33
  34     qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
  35 }
  36
  37 static void a15mp_priv_initfn(Object *obj)
  38 {
  39     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
  40     A15MPPrivState *s = A15MPCORE_PRIV(obj);
  41
  42     memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000);
  43     sysbus_init_mmio(sbd, &s->container);
  44
  45     object_initialize_child(obj, "gic", &s->gic, gic_class_name());
  46     qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
  47 }
  48
  49 static void a15mp_priv_realize(DeviceState *dev, Error **errp)
  50 {
  51     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
  52     A15MPPrivState *s = A15MPCORE_PRIV(dev);
  53     DeviceState *gicdev;
  54     SysBusDevice *busdev;
  55     int i;
  56     Error *err = NULL;
  57     bool has_el3;
  58     bool has_el2 = false;
  59     Object *cpuobj;
  60
  61     gicdev = DEVICE(&s->gic);
  62     qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
  63     qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
  64
  65     if (!kvm_irqchip_in_kernel()) {
  66         /* Make the GIC's TZ support match the CPUs. We assume that
  67          * either all the CPUs have TZ, or none do.
  68          */
  69         cpuobj = OBJECT(qemu_get_cpu(0));
  70         has_el3 = object_property_find(cpuobj, "has_el3", NULL) &&
  71             object_property_get_bool(cpuobj, "has_el3", &error_abort);
  72         qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
  73         /* Similarly for virtualization support */
  74         has_el2 = object_property_find(cpuobj, "has_el2", NULL) &&
  75             object_property_get_bool(cpuobj, "has_el2", &error_abort);
  76         qdev_prop_set_bit(gicdev, "has-virtualization-extensions", has_el2);
  77     }
  78
  79     sysbus_realize(SYS_BUS_DEVICE(&s->gic), &err);
  80     if (err != NULL) {
  81         error_propagate(errp, err);
  82         return;
  83     }
  84     busdev = SYS_BUS_DEVICE(&s->gic);
  85
  86     /* Pass through outbound IRQ lines from the GIC */
  87     sysbus_pass_irq(sbd, busdev);
  88
  89     /* Pass through inbound GPIO lines to the GIC */
  90     qdev_init_gpio_in(dev, a15mp_priv_set_irq, s->num_irq - 32);
  91
  92     /* Wire the outputs from each CPU's generic timer to the
  93      * appropriate GIC PPI inputs
  94      */
  95     for (i = 0; i < s->num_cpu; i++) {
  96         DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
  97         int ppibase = s->num_irq - 32 + i * 32;
  98         int irq;
  99         /* Mapping from the output timer irq lines from the CPU to the
 100          * GIC PPI inputs used on the A15:
 101          */
 102         const int timer_irq[] = {
 103             [GTIMER_PHYS] = 30,
 104             [GTIMER_VIRT] = 27,
 105             [GTIMER_HYP]  = 26,
 106             [GTIMER_SEC]  = 29,
 107         };
 108         for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
 109             qdev_connect_gpio_out(cpudev, irq,
 110                                   qdev_get_gpio_in(gicdev,
 111                                                    ppibase + timer_irq[irq]));
 112         }
 113         if (has_el2) {
 114             /* Connect the GIC maintenance interrupt to PPI ID 25 */
 115             sysbus_connect_irq(SYS_BUS_DEVICE(gicdev), i + 4 * s->num_cpu,
 116                                qdev_get_gpio_in(gicdev, ppibase + 25));
 117         }
 118     }
 119
 120     /* Memory map (addresses are offsets from PERIPHBASE):
 121      *  0x0000-0x0fff -- reserved
 122      *  0x1000-0x1fff -- GIC Distributor
 123      *  0x2000-0x3fff -- GIC CPU interface
 124      *  0x4000-0x4fff -- GIC virtual interface control for this CPU
 125      *  0x5000-0x51ff -- GIC virtual interface control for CPU 0
 126      *  0x5200-0x53ff -- GIC virtual interface control for CPU 1
 127      *  0x5400-0x55ff -- GIC virtual interface control for CPU 2
 128      *  0x5600-0x57ff -- GIC virtual interface control for CPU 3
 129      *  0x6000-0x7fff -- GIC virtual CPU interface
 130      */
 131     memory_region_add_subregion(&s->container, 0x1000,
 132                                 sysbus_mmio_get_region(busdev, 0));
 133     memory_region_add_subregion(&s->container, 0x2000,
 134                                 sysbus_mmio_get_region(busdev, 1));
 135     if (has_el2) {
 136         memory_region_add_subregion(&s->container, 0x4000,
 137                                     sysbus_mmio_get_region(busdev, 2));
 138         memory_region_add_subregion(&s->container, 0x6000,
 139                                     sysbus_mmio_get_region(busdev, 3));
 140         for (i = 0; i < s->num_cpu; i++) {
 141             hwaddr base = 0x5000 + i * 0x200;
 142             MemoryRegion *mr = sysbus_mmio_get_region(busdev,
 143                                                       4 + s->num_cpu + i);
 144             memory_region_add_subregion(&s->container, base, mr);
 145         }
 146     }
 147 }
 148
 149 static Property a15mp_priv_properties[] = {
 150     DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1),
 151     /* The Cortex-A15MP may have anything from 0 to 224 external interrupt
 152      * IRQ lines (with another 32 internal). We default to 128+32, which
 153      * is the number provided by the Cortex-A15MP test chip in the
 154      * Versatile Express A15 development board.
 155      * Other boards may differ and should set this property appropriately.
 156      */
 157     DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 160),
 158     DEFINE_PROP_END_OF_LIST(),
 159 };
 160
 161 static void a15mp_priv_class_init(ObjectClass *klass, void *data)
 162 {
 163     DeviceClass *dc = DEVICE_CLASS(klass);
 164
 165     dc->realize = a15mp_priv_realize;
 166     device_class_set_props(dc, a15mp_priv_properties);
 167     /* We currently have no savable state */
 168 }
 169
 170 static const TypeInfo a15mp_priv_info = {
 171     .name  = TYPE_A15MPCORE_PRIV,
 172     .parent = TYPE_SYS_BUS_DEVICE,
 173     .instance_size  = sizeof(A15MPPrivState),
 174     .instance_init = a15mp_priv_initfn,
 175     .class_init = a15mp_priv_class_init,
 176 };
 177
 178 static void a15mp_register_types(void)
 179 {
 180     type_register_static(&a15mp_priv_info);
 181 }
 182
 183 type_init(a15mp_register_types)