2 * MIPS emulation for qemu: CPU initialisation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2007 Herve Poussineau
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 /* CPU / CPU family specific config register values. */
23 /* Have config1, uncached coherency */
24 #define MIPS_CONFIG0 \
25 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
27 /* Have config2, no coprocessor2 attached, no MDMX support attached,
28 no performance counters, watch registers present,
29 no code compression, EJTAG present, no FPU */
30 #define MIPS_CONFIG1 \
32 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
33 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
36 /* Have config3, no tertiary/secondary caches implemented */
37 #define MIPS_CONFIG2 \
40 /* No config4, no DSP ASE, no large physaddr (PABITS),
41 no external interrupt controller, no vectored interrupts,
42 no 1kb pages, no SmartMIPS ASE, no trace logic */
43 #define MIPS_CONFIG3 \
44 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
45 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
46 (0 << CP0C3_SM) | (0 << CP0C3_TL))
48 #define MIPS_CONFIG4 \
51 #define MIPS_CONFIG5 \
54 /* MMU types, the first four entries have the same layout as the
74 int32_t CP0_Config4_rw_bitmask
;
76 int32_t CP0_Config5_rw_bitmask
;
79 target_ulong CP0_LLAddr_rw_bitmask
;
83 int32_t CP0_Status_rw_bitmask
;
84 int32_t CP0_TCStatus_rw_bitmask
;
87 int32_t CP1_fcr31_rw_bitmask
;
92 int32_t CP0_SRSConf0_rw_bitmask
;
94 int32_t CP0_SRSConf1_rw_bitmask
;
96 int32_t CP0_SRSConf2_rw_bitmask
;
98 int32_t CP0_SRSConf3_rw_bitmask
;
100 int32_t CP0_SRSConf4_rw_bitmask
;
101 int32_t CP0_SRSConf4
;
102 int32_t CP0_PageGrain_rw_bitmask
;
103 int32_t CP0_PageGrain
;
104 target_ulong CP0_EBaseWG_rw_bitmask
;
106 enum mips_mmu_types mmu_type
;
109 /*****************************************************************************/
110 /* MIPS CPU definitions */
111 static const mips_def_t mips_defs
[] =
115 .CP0_PRid
= 0x00018000,
116 .CP0_Config0
= MIPS_CONFIG0
| (MMU_TYPE_R4000
<< CP0C0_MT
),
117 .CP0_Config1
= MIPS_CONFIG1
| (15 << CP0C1_MMU
) |
118 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
119 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
) |
121 .CP0_Config2
= MIPS_CONFIG2
,
122 .CP0_Config3
= MIPS_CONFIG3
,
123 .CP0_LLAddr_rw_bitmask
= 0,
124 .CP0_LLAddr_shift
= 4,
127 .CP0_Status_rw_bitmask
= 0x1278FF17,
130 .insn_flags
= CPU_MIPS32
,
131 .mmu_type
= MMU_TYPE_R4000
,
135 .CP0_PRid
= 0x00018300,
136 /* Config1 implemented, fixed mapping MMU,
137 no virtual icache, uncached coherency. */
138 .CP0_Config0
= MIPS_CONFIG0
| (MMU_TYPE_FMT
<< CP0C0_MT
),
139 .CP0_Config1
= MIPS_CONFIG1
|
140 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
141 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
) |
143 .CP0_Config2
= MIPS_CONFIG2
,
144 .CP0_Config3
= MIPS_CONFIG3
,
145 .CP0_LLAddr_rw_bitmask
= 0,
146 .CP0_LLAddr_shift
= 4,
149 .CP0_Status_rw_bitmask
= 0x1258FF17,
152 .insn_flags
= CPU_MIPS32
| ASE_MIPS16
,
153 .mmu_type
= MMU_TYPE_FMT
,
157 .CP0_PRid
= 0x00018400,
158 .CP0_Config0
= MIPS_CONFIG0
| (MMU_TYPE_R4000
<< CP0C0_MT
),
159 .CP0_Config1
= MIPS_CONFIG1
| (15 << CP0C1_MMU
) |
160 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
161 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
) |
163 .CP0_Config2
= MIPS_CONFIG2
,
164 .CP0_Config3
= MIPS_CONFIG3
,
165 .CP0_LLAddr_rw_bitmask
= 0,
166 .CP0_LLAddr_shift
= 4,
169 .CP0_Status_rw_bitmask
= 0x1278FF17,
172 .insn_flags
= CPU_MIPS32
,
173 .mmu_type
= MMU_TYPE_R4000
,
177 .CP0_PRid
= 0x00018500,
178 .CP0_Config0
= MIPS_CONFIG0
| (MMU_TYPE_FMT
<< CP0C0_MT
),
179 .CP0_Config1
= MIPS_CONFIG1
|
180 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
181 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
) |
183 .CP0_Config2
= MIPS_CONFIG2
,
184 .CP0_Config3
= MIPS_CONFIG3
,
185 .CP0_LLAddr_rw_bitmask
= 0,
186 .CP0_LLAddr_shift
= 4,
189 .CP0_Status_rw_bitmask
= 0x1258FF17,
192 .insn_flags
= CPU_MIPS32
| ASE_MIPS16
,
193 .mmu_type
= MMU_TYPE_FMT
,
197 .CP0_PRid
= 0x00019000,
198 .CP0_Config0
= MIPS_CONFIG0
| (0x1 << CP0C0_AR
) |
199 (MMU_TYPE_R4000
<< CP0C0_MT
),
200 .CP0_Config1
= MIPS_CONFIG1
| (15 << CP0C1_MMU
) |
201 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
202 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
) |
204 .CP0_Config2
= MIPS_CONFIG2
,
205 .CP0_Config3
= MIPS_CONFIG3
| (0 << CP0C3_VInt
),
206 .CP0_LLAddr_rw_bitmask
= 0,
207 .CP0_LLAddr_shift
= 4,
210 .CP0_Status_rw_bitmask
= 0x1278FF17,
213 .insn_flags
= CPU_MIPS32R2
,
214 .mmu_type
= MMU_TYPE_R4000
,
218 .CP0_PRid
= 0x00019100,
219 .CP0_Config0
= MIPS_CONFIG0
| (0x1 << CP0C0_AR
) |
220 (MMU_TYPE_FMT
<< CP0C0_MT
),
221 .CP0_Config1
= MIPS_CONFIG1
|
222 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
223 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
) |
225 .CP0_Config2
= MIPS_CONFIG2
,
226 .CP0_Config3
= MIPS_CONFIG3
,
227 .CP0_LLAddr_rw_bitmask
= 0,
228 .CP0_LLAddr_shift
= 4,
231 .CP0_Status_rw_bitmask
= 0x1258FF17,
234 .insn_flags
= CPU_MIPS32R2
| ASE_MIPS16
,
235 .mmu_type
= MMU_TYPE_FMT
,
239 .CP0_PRid
= 0x00019300,
240 .CP0_Config0
= MIPS_CONFIG0
| (0x1 << CP0C0_AR
) |
241 (MMU_TYPE_R4000
<< CP0C0_MT
),
242 .CP0_Config1
= MIPS_CONFIG1
| (15 << CP0C1_MMU
) |
243 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
244 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
) |
246 .CP0_Config2
= MIPS_CONFIG2
,
247 .CP0_Config3
= MIPS_CONFIG3
| (0 << CP0C3_VInt
),
248 .CP0_LLAddr_rw_bitmask
= 0,
249 .CP0_LLAddr_shift
= 4,
252 /* No DSP implemented. */
253 .CP0_Status_rw_bitmask
= 0x1278FF1F,
256 .insn_flags
= CPU_MIPS32R2
| ASE_MIPS16
,
257 .mmu_type
= MMU_TYPE_R4000
,
261 .CP0_PRid
= 0x00019600,
262 .CP0_Config0
= MIPS_CONFIG0
| (0x1 << CP0C0_AR
) |
263 (MMU_TYPE_R4000
<< CP0C0_MT
),
264 .CP0_Config1
= MIPS_CONFIG1
| (15 << CP0C1_MMU
) |
265 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
266 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
) |
268 .CP0_Config2
= MIPS_CONFIG2
,
269 .CP0_Config3
= MIPS_CONFIG3
| (1 << CP0C3_DSPP
) | (0 << CP0C3_VInt
),
270 .CP0_LLAddr_rw_bitmask
= 0,
271 .CP0_LLAddr_shift
= 4,
274 /* we have a DSP, but no FPU */
275 .CP0_Status_rw_bitmask
= 0x1378FF1F,
278 .insn_flags
= CPU_MIPS32R2
| ASE_MIPS16
| ASE_DSP
,
279 .mmu_type
= MMU_TYPE_R4000
,
283 .CP0_PRid
= 0x00019300,
284 .CP0_Config0
= MIPS_CONFIG0
| (0x1 << CP0C0_AR
) |
285 (MMU_TYPE_R4000
<< CP0C0_MT
),
286 .CP0_Config1
= MIPS_CONFIG1
| (1 << CP0C1_FP
) | (15 << CP0C1_MMU
) |
287 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
288 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
) |
290 .CP0_Config2
= MIPS_CONFIG2
,
291 .CP0_Config3
= MIPS_CONFIG3
| (0 << CP0C3_VInt
),
292 .CP0_LLAddr_rw_bitmask
= 0,
293 .CP0_LLAddr_shift
= 4,
296 /* No DSP implemented. */
297 .CP0_Status_rw_bitmask
= 0x3678FF1F,
298 .CP1_fcr0
= (1 << FCR0_F64
) | (1 << FCR0_L
) | (1 << FCR0_W
) |
299 (1 << FCR0_D
) | (1 << FCR0_S
) | (0x93 << FCR0_PRID
),
301 .CP1_fcr31_rw_bitmask
= 0xFF83FFFF,
304 .insn_flags
= CPU_MIPS32R2
| ASE_MIPS16
,
305 .mmu_type
= MMU_TYPE_R4000
,
309 .CP0_PRid
= 0x00019500,
310 .CP0_Config0
= MIPS_CONFIG0
| (0x1 << CP0C0_AR
) |
311 (MMU_TYPE_R4000
<< CP0C0_MT
),
312 .CP0_Config1
= MIPS_CONFIG1
| (1 << CP0C1_FP
) | (15 << CP0C1_MMU
) |
313 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
314 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
) |
316 .CP0_Config2
= MIPS_CONFIG2
,
317 .CP0_Config3
= MIPS_CONFIG3
| (1 << CP0C3_VInt
) | (1 << CP0C3_MT
) |
319 .CP0_LLAddr_rw_bitmask
= 0,
320 .CP0_LLAddr_shift
= 0,
323 .CP0_Status_rw_bitmask
= 0x3778FF1F,
324 .CP0_TCStatus_rw_bitmask
= (0 << CP0TCSt_TCU3
) | (0 << CP0TCSt_TCU2
) |
325 (1 << CP0TCSt_TCU1
) | (1 << CP0TCSt_TCU0
) |
326 (0 << CP0TCSt_TMX
) | (1 << CP0TCSt_DT
) |
327 (1 << CP0TCSt_DA
) | (1 << CP0TCSt_A
) |
328 (0x3 << CP0TCSt_TKSU
) | (1 << CP0TCSt_IXMT
) |
329 (0xff << CP0TCSt_TASID
),
330 .CP1_fcr0
= (1 << FCR0_F64
) | (1 << FCR0_L
) | (1 << FCR0_W
) |
331 (1 << FCR0_D
) | (1 << FCR0_S
) | (0x95 << FCR0_PRID
),
333 .CP1_fcr31_rw_bitmask
= 0xFF83FFFF,
334 .CP0_SRSCtl
= (0xf << CP0SRSCtl_HSS
),
335 .CP0_SRSConf0_rw_bitmask
= 0x3fffffff,
336 .CP0_SRSConf0
= (1U << CP0SRSC0_M
) | (0x3fe << CP0SRSC0_SRS3
) |
337 (0x3fe << CP0SRSC0_SRS2
) | (0x3fe << CP0SRSC0_SRS1
),
338 .CP0_SRSConf1_rw_bitmask
= 0x3fffffff,
339 .CP0_SRSConf1
= (1U << CP0SRSC1_M
) | (0x3fe << CP0SRSC1_SRS6
) |
340 (0x3fe << CP0SRSC1_SRS5
) | (0x3fe << CP0SRSC1_SRS4
),
341 .CP0_SRSConf2_rw_bitmask
= 0x3fffffff,
342 .CP0_SRSConf2
= (1U << CP0SRSC2_M
) | (0x3fe << CP0SRSC2_SRS9
) |
343 (0x3fe << CP0SRSC2_SRS8
) | (0x3fe << CP0SRSC2_SRS7
),
344 .CP0_SRSConf3_rw_bitmask
= 0x3fffffff,
345 .CP0_SRSConf3
= (1U << CP0SRSC3_M
) | (0x3fe << CP0SRSC3_SRS12
) |
346 (0x3fe << CP0SRSC3_SRS11
) | (0x3fe << CP0SRSC3_SRS10
),
347 .CP0_SRSConf4_rw_bitmask
= 0x3fffffff,
348 .CP0_SRSConf4
= (0x3fe << CP0SRSC4_SRS15
) |
349 (0x3fe << CP0SRSC4_SRS14
) | (0x3fe << CP0SRSC4_SRS13
),
352 .insn_flags
= CPU_MIPS32R2
| ASE_MIPS16
| ASE_DSP
| ASE_MT
,
353 .mmu_type
= MMU_TYPE_R4000
,
357 .CP0_PRid
= 0x00019700,
358 .CP0_Config0
= MIPS_CONFIG0
| (0x1 << CP0C0_AR
) |
359 (MMU_TYPE_R4000
<< CP0C0_MT
),
360 .CP0_Config1
= MIPS_CONFIG1
| (1 << CP0C1_FP
) | (15 << CP0C1_MMU
) |
361 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
362 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
) |
364 .CP0_Config2
= MIPS_CONFIG2
,
365 .CP0_Config3
= MIPS_CONFIG3
| (1 << CP0C3_DSP2P
) | (1 << CP0C3_DSPP
) |
367 .CP0_LLAddr_rw_bitmask
= 0,
368 .CP0_LLAddr_shift
= 4,
371 .CP0_Status_rw_bitmask
= 0x3778FF1F,
372 .CP1_fcr0
= (1 << FCR0_F64
) | (1 << FCR0_L
) | (1 << FCR0_W
) |
373 (1 << FCR0_D
) | (1 << FCR0_S
) | (0x93 << FCR0_PRID
),
375 .CP1_fcr31_rw_bitmask
= 0xFF83FFFF,
378 .insn_flags
= CPU_MIPS32R2
| ASE_MIPS16
| ASE_DSP
| ASE_DSPR2
,
379 .mmu_type
= MMU_TYPE_R4000
,
383 .CP0_PRid
= 0x00019b00,
384 /* Config1 implemented, fixed mapping MMU,
385 no virtual icache, uncached coherency. */
386 .CP0_Config0
= MIPS_CONFIG0
| (0x2 << CP0C0_KU
) | (0x2 << CP0C0_K23
) |
387 (0x1 << CP0C0_AR
) | (MMU_TYPE_FMT
<< CP0C0_MT
),
388 .CP0_Config1
= MIPS_CONFIG1
,
389 .CP0_Config2
= MIPS_CONFIG2
,
390 .CP0_Config3
= MIPS_CONFIG3
| (0x2 << CP0C3_ISA
) | (1 << CP0C3_VInt
),
391 .CP0_LLAddr_rw_bitmask
= 0,
392 .CP0_LLAddr_shift
= 4,
395 .CP0_Status_rw_bitmask
= 0x1258FF17,
398 .insn_flags
= CPU_MIPS32R2
| ASE_MICROMIPS
,
399 .mmu_type
= MMU_TYPE_FMT
,
403 /* This is the TLB-based MMU core. */
404 .CP0_PRid
= 0x00019c00,
405 .CP0_Config0
= MIPS_CONFIG0
| (0x1 << CP0C0_AR
) |
406 (MMU_TYPE_R4000
<< CP0C0_MT
),
407 .CP0_Config1
= MIPS_CONFIG1
| (15 << CP0C1_MMU
) |
408 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
409 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
),
410 .CP0_Config2
= MIPS_CONFIG2
,
411 .CP0_Config3
= MIPS_CONFIG3
| (0x2 << CP0C3_ISA
) | (0 << CP0C3_VInt
),
412 .CP0_LLAddr_rw_bitmask
= 0,
413 .CP0_LLAddr_shift
= 4,
416 .CP0_Status_rw_bitmask
= 0x1278FF17,
419 .insn_flags
= CPU_MIPS32R2
| ASE_MICROMIPS
,
420 .mmu_type
= MMU_TYPE_R4000
,
424 * Config3: CMGCR, PW, VZ, CTXTC, CDMM, TL
430 .CP0_PRid
= 0x0001A800,
431 .CP0_Config0
= MIPS_CONFIG0
| (1 << CP0C0_MM
) | (1 << CP0C0_AR
) |
432 (MMU_TYPE_R4000
<< CP0C0_MT
),
433 .CP0_Config1
= MIPS_CONFIG1
| (0x3F << CP0C1_MMU
) |
434 (2 << CP0C1_IS
) | (4 << CP0C1_IL
) | (3 << CP0C1_IA
) |
435 (2 << CP0C1_DS
) | (4 << CP0C1_DL
) | (3 << CP0C1_DA
) |
436 (1 << CP0C1_PC
) | (1 << CP0C1_FP
),
437 .CP0_Config2
= MIPS_CONFIG2
,
438 .CP0_Config3
= MIPS_CONFIG3
| (1U << CP0C3_M
) | (1 << CP0C3_MSAP
) |
439 (1 << CP0C3_BP
) | (1 << CP0C3_BI
) | (1 << CP0C3_SC
) |
440 (1 << CP0C3_ULRI
) | (1 << CP0C3_RXI
) | (1 << CP0C3_LPA
) |
442 .CP0_Config4
= MIPS_CONFIG4
| (1U << CP0C4_M
) | (2 << CP0C4_IE
) |
443 (0x1c << CP0C4_KScrExist
),
444 .CP0_Config4_rw_bitmask
= 0,
445 .CP0_Config5
= MIPS_CONFIG5
| (1 << CP0C5_EVA
) | (1 << CP0C5_MVH
) |
446 (1 << CP0C5_LLB
) | (1 << CP0C5_MRP
),
447 .CP0_Config5_rw_bitmask
= (1 << CP0C5_K
) | (1 << CP0C5_CV
) |
448 (1 << CP0C5_MSAEn
) | (1 << CP0C5_UFE
) |
449 (1 << CP0C5_FRE
) | (1 << CP0C5_UFR
),
450 .CP0_LLAddr_rw_bitmask
= 0,
451 .CP0_LLAddr_shift
= 0,
454 .CP0_Status_rw_bitmask
= 0x3C68FF1F,
455 .CP0_PageGrain_rw_bitmask
= (1U << CP0PG_RIE
) | (1 << CP0PG_XIE
) |
456 (1 << CP0PG_ELPA
) | (1 << CP0PG_IEC
),
457 .CP0_EBaseWG_rw_bitmask
= (1 << CP0EBase_WG
),
458 .CP1_fcr0
= (1 << FCR0_FREP
) | (1 << FCR0_UFRP
) | (1 << FCR0_HAS2008
) |
459 (1 << FCR0_F64
) | (1 << FCR0_L
) | (1 << FCR0_W
) |
460 (1 << FCR0_D
) | (1 << FCR0_S
) | (0x03 << FCR0_PRID
),
461 .CP1_fcr31
= (1 << FCR31_ABS2008
) | (1 << FCR31_NAN2008
),
462 .CP1_fcr31_rw_bitmask
= 0xFF83FFFF,
465 .insn_flags
= CPU_MIPS32R5
| ASE_MSA
,
466 .mmu_type
= MMU_TYPE_R4000
,
469 /* A generic CPU supporting MIPS32 Release 6 ISA.
470 FIXME: Support IEEE 754-2008 FP.
471 Eventually this should be replaced by a real CPU model. */
472 .name
= "mips32r6-generic",
473 .CP0_PRid
= 0x00010000,
474 .CP0_Config0
= MIPS_CONFIG0
| (0x2 << CP0C0_AR
) |
475 (MMU_TYPE_R4000
<< CP0C0_MT
),
476 .CP0_Config1
= MIPS_CONFIG1
| (1 << CP0C1_FP
) | (31 << CP0C1_MMU
) |
477 (2 << CP0C1_IS
) | (4 << CP0C1_IL
) | (3 << CP0C1_IA
) |
478 (2 << CP0C1_DS
) | (4 << CP0C1_DL
) | (3 << CP0C1_DA
) |
479 (0 << CP0C1_PC
) | (1 << CP0C1_WR
) | (1 << CP0C1_EP
),
480 .CP0_Config2
= MIPS_CONFIG2
,
481 .CP0_Config3
= MIPS_CONFIG3
| (1 << CP0C3_BP
) | (1 << CP0C3_BI
) |
482 (2 << CP0C3_ISA
) | (1 << CP0C3_ULRI
) |
483 (1 << CP0C3_RXI
) | (1U << CP0C3_M
),
484 .CP0_Config4
= MIPS_CONFIG4
| (0xfc << CP0C4_KScrExist
) |
485 (3 << CP0C4_IE
) | (1U << CP0C4_M
),
486 .CP0_Config5
= MIPS_CONFIG5
| (1 << CP0C5_XNP
) | (1 << CP0C5_LLB
),
487 .CP0_Config5_rw_bitmask
= (1 << CP0C5_SBRI
) | (1 << CP0C5_FRE
) |
489 .CP0_LLAddr_rw_bitmask
= 0,
490 .CP0_LLAddr_shift
= 0,
493 .CP0_Status_rw_bitmask
= 0x3058FF1F,
494 .CP0_PageGrain
= (1 << CP0PG_IEC
) | (1 << CP0PG_XIE
) |
496 .CP0_PageGrain_rw_bitmask
= 0,
497 .CP1_fcr0
= (1 << FCR0_FREP
) | (1 << FCR0_HAS2008
) | (1 << FCR0_F64
) |
498 (1 << FCR0_L
) | (1 << FCR0_W
) | (1 << FCR0_D
) |
499 (1 << FCR0_S
) | (0x00 << FCR0_PRID
) | (0x0 << FCR0_REV
),
500 .CP1_fcr31
= (1 << FCR31_ABS2008
) | (1 << FCR31_NAN2008
),
501 .CP1_fcr31_rw_bitmask
= 0x0103FFFF,
504 .insn_flags
= CPU_MIPS32R6
| ASE_MICROMIPS
,
505 .mmu_type
= MMU_TYPE_R4000
,
507 #if defined(TARGET_MIPS64)
510 .CP0_PRid
= 0x00000400,
511 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
512 .CP0_Config0
= (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0
),
513 /* Note: Config1 is only used internally, the R4000 has only Config0. */
514 .CP0_Config1
= (1 << CP0C1_FP
) | (47 << CP0C1_MMU
),
515 .CP0_LLAddr_rw_bitmask
= 0xFFFFFFFF,
516 .CP0_LLAddr_shift
= 4,
519 .CP0_Status_rw_bitmask
= 0x3678FFFF,
520 /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
521 .CP1_fcr0
= (0x5 << FCR0_PRID
) | (0x0 << FCR0_REV
),
523 .CP1_fcr31_rw_bitmask
= 0x0183FFFF,
526 .insn_flags
= CPU_MIPS3
,
527 .mmu_type
= MMU_TYPE_R4000
,
531 .CP0_PRid
= 0x00005400,
532 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
533 .CP0_Config0
= (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0
),
534 .CP0_Config1
= (1 << CP0C1_FP
) | (47 << CP0C1_MMU
),
535 .CP0_LLAddr_rw_bitmask
= 0xFFFFFFFFL
,
536 .CP0_LLAddr_shift
= 4,
539 .CP0_Status_rw_bitmask
= 0x3678FFFF,
540 /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
541 .CP1_fcr0
= (0x54 << FCR0_PRID
) | (0x0 << FCR0_REV
),
543 .CP1_fcr31_rw_bitmask
= 0xFF83FFFF,
546 .insn_flags
= CPU_VR54XX
,
547 .mmu_type
= MMU_TYPE_R4000
,
551 .CP0_PRid
= 0x00018100,
552 .CP0_Config0
= MIPS_CONFIG0
| (0x2 << CP0C0_AT
) |
553 (MMU_TYPE_R4000
<< CP0C0_MT
),
554 .CP0_Config1
= MIPS_CONFIG1
| (31 << CP0C1_MMU
) |
555 (1 << CP0C1_IS
) | (4 << CP0C1_IL
) | (1 << CP0C1_IA
) |
556 (1 << CP0C1_DS
) | (4 << CP0C1_DL
) | (1 << CP0C1_DA
) |
557 (1 << CP0C1_PC
) | (1 << CP0C1_WR
) | (1 << CP0C1_EP
),
558 .CP0_Config2
= MIPS_CONFIG2
,
559 .CP0_Config3
= MIPS_CONFIG3
,
560 .CP0_LLAddr_rw_bitmask
= 0,
561 .CP0_LLAddr_shift
= 4,
564 .CP0_Status_rw_bitmask
= 0x12F8FFFF,
567 .insn_flags
= CPU_MIPS64
,
568 .mmu_type
= MMU_TYPE_R4000
,
572 .CP0_PRid
= 0x00018100,
573 .CP0_Config0
= MIPS_CONFIG0
| (0x2 << CP0C0_AT
) |
574 (MMU_TYPE_R4000
<< CP0C0_MT
),
575 .CP0_Config1
= MIPS_CONFIG1
| (1 << CP0C1_FP
) | (31 << CP0C1_MMU
) |
576 (1 << CP0C1_IS
) | (4 << CP0C1_IL
) | (1 << CP0C1_IA
) |
577 (1 << CP0C1_DS
) | (4 << CP0C1_DL
) | (1 << CP0C1_DA
) |
578 (1 << CP0C1_PC
) | (1 << CP0C1_WR
) | (1 << CP0C1_EP
),
579 .CP0_Config2
= MIPS_CONFIG2
,
580 .CP0_Config3
= MIPS_CONFIG3
,
581 .CP0_LLAddr_rw_bitmask
= 0,
582 .CP0_LLAddr_shift
= 4,
585 .CP0_Status_rw_bitmask
= 0x36F8FFFF,
586 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
587 .CP1_fcr0
= (1 << FCR0_D
) | (1 << FCR0_S
) |
588 (0x81 << FCR0_PRID
) | (0x0 << FCR0_REV
),
590 .CP1_fcr31_rw_bitmask
= 0xFF83FFFF,
593 .insn_flags
= CPU_MIPS64
,
594 .mmu_type
= MMU_TYPE_R4000
,
598 /* We emulate a later version of the 20Kc, earlier ones had a broken
600 .CP0_PRid
= 0x000182a0,
601 .CP0_Config0
= MIPS_CONFIG0
| (0x2 << CP0C0_AT
) |
602 (MMU_TYPE_R4000
<< CP0C0_MT
) | (1 << CP0C0_VI
),
603 .CP0_Config1
= MIPS_CONFIG1
| (1 << CP0C1_FP
) | (47 << CP0C1_MMU
) |
604 (2 << CP0C1_IS
) | (4 << CP0C1_IL
) | (3 << CP0C1_IA
) |
605 (2 << CP0C1_DS
) | (4 << CP0C1_DL
) | (3 << CP0C1_DA
) |
606 (1 << CP0C1_PC
) | (1 << CP0C1_WR
) | (1 << CP0C1_EP
),
607 .CP0_Config2
= MIPS_CONFIG2
,
608 .CP0_Config3
= MIPS_CONFIG3
,
609 .CP0_LLAddr_rw_bitmask
= 0,
610 .CP0_LLAddr_shift
= 0,
613 .CP0_Status_rw_bitmask
= 0x36FBFFFF,
614 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
615 .CP1_fcr0
= (1 << FCR0_3D
) | (1 << FCR0_PS
) |
616 (1 << FCR0_D
) | (1 << FCR0_S
) |
617 (0x82 << FCR0_PRID
) | (0x0 << FCR0_REV
),
619 .CP1_fcr31_rw_bitmask
= 0xFF83FFFF,
622 .insn_flags
= CPU_MIPS64
| ASE_MIPS3D
,
623 .mmu_type
= MMU_TYPE_R4000
,
626 /* A generic CPU providing MIPS64 Release 2 features.
627 FIXME: Eventually this should be replaced by a real CPU model. */
628 .name
= "MIPS64R2-generic",
629 .CP0_PRid
= 0x00010000,
630 .CP0_Config0
= MIPS_CONFIG0
| (0x1 << CP0C0_AR
) | (0x2 << CP0C0_AT
) |
631 (MMU_TYPE_R4000
<< CP0C0_MT
),
632 .CP0_Config1
= MIPS_CONFIG1
| (1 << CP0C1_FP
) | (63 << CP0C1_MMU
) |
633 (2 << CP0C1_IS
) | (4 << CP0C1_IL
) | (3 << CP0C1_IA
) |
634 (2 << CP0C1_DS
) | (4 << CP0C1_DL
) | (3 << CP0C1_DA
) |
635 (1 << CP0C1_PC
) | (1 << CP0C1_WR
) | (1 << CP0C1_EP
),
636 .CP0_Config2
= MIPS_CONFIG2
,
637 .CP0_Config3
= MIPS_CONFIG3
| (1 << CP0C3_LPA
),
638 .CP0_LLAddr_rw_bitmask
= 0,
639 .CP0_LLAddr_shift
= 0,
642 .CP0_Status_rw_bitmask
= 0x36FBFFFF,
643 .CP0_EBaseWG_rw_bitmask
= (1 << CP0EBase_WG
),
644 .CP1_fcr0
= (1 << FCR0_F64
) | (1 << FCR0_3D
) | (1 << FCR0_PS
) |
645 (1 << FCR0_L
) | (1 << FCR0_W
) | (1 << FCR0_D
) |
646 (1 << FCR0_S
) | (0x00 << FCR0_PRID
) | (0x0 << FCR0_REV
),
648 .CP1_fcr31_rw_bitmask
= 0xFF83FFFF,
651 .insn_flags
= CPU_MIPS64R2
| ASE_MIPS3D
,
652 .mmu_type
= MMU_TYPE_R4000
,
656 .CP0_PRid
= 0x00018900,
657 .CP0_Config0
= MIPS_CONFIG0
| (0x1 << CP0C0_AR
) | (0x2 << CP0C0_AT
) |
658 (MMU_TYPE_R4000
<< CP0C0_MT
),
659 .CP0_Config1
= MIPS_CONFIG1
| (31 << CP0C1_MMU
) |
660 (1 << CP0C1_IS
) | (4 << CP0C1_IL
) | (1 << CP0C1_IA
) |
661 (1 << CP0C1_DS
) | (4 << CP0C1_DL
) | (1 << CP0C1_DA
) |
662 (1 << CP0C1_PC
) | (1 << CP0C1_WR
) | (1 << CP0C1_EP
),
663 .CP0_Config2
= MIPS_CONFIG2
,
664 .CP0_Config3
= MIPS_CONFIG3
,
665 .CP0_LLAddr_rw_bitmask
= 0,
666 .CP0_LLAddr_shift
= 4,
669 .CP0_Status_rw_bitmask
= 0x12F8FFFF,
672 .insn_flags
= CPU_MIPS64R2
,
673 .mmu_type
= MMU_TYPE_R4000
,
677 .CP0_PRid
= 0x00018900,
678 .CP0_Config0
= MIPS_CONFIG0
| (0x1 << CP0C0_AR
) | (0x2 << CP0C0_AT
) |
679 (MMU_TYPE_R4000
<< CP0C0_MT
),
680 .CP0_Config1
= MIPS_CONFIG1
| (1 << CP0C1_FP
) | (31 << CP0C1_MMU
) |
681 (1 << CP0C1_IS
) | (4 << CP0C1_IL
) | (1 << CP0C1_IA
) |
682 (1 << CP0C1_DS
) | (4 << CP0C1_DL
) | (1 << CP0C1_DA
) |
683 (1 << CP0C1_PC
) | (1 << CP0C1_WR
) | (1 << CP0C1_EP
),
684 .CP0_Config2
= MIPS_CONFIG2
,
685 .CP0_Config3
= MIPS_CONFIG3
,
686 .CP0_LLAddr_rw_bitmask
= 0,
687 .CP0_LLAddr_shift
= 4,
690 .CP0_Status_rw_bitmask
= 0x36F8FFFF,
691 .CP1_fcr0
= (1 << FCR0_F64
) | (1 << FCR0_L
) | (1 << FCR0_W
) |
692 (1 << FCR0_D
) | (1 << FCR0_S
) |
693 (0x89 << FCR0_PRID
) | (0x0 << FCR0_REV
),
696 .insn_flags
= CPU_MIPS64R2
,
697 .mmu_type
= MMU_TYPE_R4000
,
702 .CP0_Config0
= MIPS_CONFIG0
| (0x2 << CP0C0_AR
) | (0x2 << CP0C0_AT
) |
703 (MMU_TYPE_R4000
<< CP0C0_MT
),
704 .CP0_Config1
= MIPS_CONFIG1
| (1 << CP0C1_FP
) | (15 << CP0C1_MMU
) |
705 (2 << CP0C1_IS
) | (5 << CP0C1_IL
) | (3 << CP0C1_IA
) |
706 (2 << CP0C1_DS
) | (5 << CP0C1_DL
) | (3 << CP0C1_DA
) |
707 (0 << CP0C1_PC
) | (1 << CP0C1_WR
) | (1 << CP0C1_EP
),
708 .CP0_Config2
= MIPS_CONFIG2
,
709 .CP0_Config3
= MIPS_CONFIG3
| (1U << CP0C3_M
) |
710 (1 << CP0C3_CMGCR
) | (1 << CP0C3_MSAP
) |
711 (1 << CP0C3_BP
) | (1 << CP0C3_BI
) | (1 << CP0C3_ULRI
) |
712 (1 << CP0C3_RXI
) | (1 << CP0C3_LPA
) | (1 << CP0C3_VInt
),
713 .CP0_Config4
= MIPS_CONFIG4
| (1U << CP0C4_M
) | (3 << CP0C4_IE
) |
714 (1 << CP0C4_AE
) | (0xfc << CP0C4_KScrExist
),
715 .CP0_Config5
= MIPS_CONFIG5
| (1 << CP0C5_XNP
) | (1 << CP0C5_VP
) |
716 (1 << CP0C5_LLB
) | (1 << CP0C5_MRP
),
717 .CP0_Config5_rw_bitmask
= (1 << CP0C5_MSAEn
) | (1 << CP0C5_SBRI
) |
718 (1 << CP0C5_FRE
) | (1 << CP0C5_UFE
),
719 .CP0_LLAddr_rw_bitmask
= 0,
720 .CP0_LLAddr_shift
= 0,
723 .CP0_Status_rw_bitmask
= 0x30D8FFFF,
724 .CP0_PageGrain
= (1 << CP0PG_IEC
) | (1 << CP0PG_XIE
) |
726 .CP0_PageGrain_rw_bitmask
= (1 << CP0PG_ELPA
),
727 .CP0_EBaseWG_rw_bitmask
= (1 << CP0EBase_WG
),
728 .CP1_fcr0
= (1 << FCR0_FREP
) | (1 << FCR0_HAS2008
) | (1 << FCR0_F64
) |
729 (1 << FCR0_L
) | (1 << FCR0_W
) | (1 << FCR0_D
) |
730 (1 << FCR0_S
) | (0x03 << FCR0_PRID
) | (0x0 << FCR0_REV
),
731 .CP1_fcr31
= (1 << FCR31_ABS2008
) | (1 << FCR31_NAN2008
),
732 .CP1_fcr31_rw_bitmask
= 0x0103FFFF,
733 .MSAIR
= 0x03 << MSAIR_ProcID
,
736 .insn_flags
= CPU_MIPS64R6
| ASE_MSA
,
737 .mmu_type
= MMU_TYPE_R4000
,
740 .name
= "Loongson-2E",
742 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
743 .CP0_Config0
= (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
744 (0x1<<5) | (0x1<<4) | (0x1<<1),
745 /* Note: Config1 is only used internally,
746 Loongson-2E has only Config0. */
747 .CP0_Config1
= (1 << CP0C1_FP
) | (47 << CP0C1_MMU
),
750 .CP0_Status_rw_bitmask
= 0x35D0FFFF,
751 .CP1_fcr0
= (0x5 << FCR0_PRID
) | (0x1 << FCR0_REV
),
753 .CP1_fcr31_rw_bitmask
= 0xFF83FFFF,
756 .insn_flags
= CPU_LOONGSON2E
,
757 .mmu_type
= MMU_TYPE_R4000
,
760 .name
= "Loongson-2F",
762 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
763 .CP0_Config0
= (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
764 (0x1<<5) | (0x1<<4) | (0x1<<1),
765 /* Note: Config1 is only used internally,
766 Loongson-2F has only Config0. */
767 .CP0_Config1
= (1 << CP0C1_FP
) | (47 << CP0C1_MMU
),
770 .CP0_Status_rw_bitmask
= 0xF5D0FF1F, /* Bits 7:5 not writable. */
771 .CP1_fcr0
= (0x5 << FCR0_PRID
) | (0x1 << FCR0_REV
),
773 .CP1_fcr31_rw_bitmask
= 0xFF83FFFF,
776 .insn_flags
= CPU_LOONGSON2F
,
777 .mmu_type
= MMU_TYPE_R4000
,
780 /* A generic CPU providing MIPS64 ASE DSP 2 features.
781 FIXME: Eventually this should be replaced by a real CPU model. */
782 .name
= "mips64dspr2",
783 .CP0_PRid
= 0x00010000,
784 .CP0_Config0
= MIPS_CONFIG0
| (0x1 << CP0C0_AR
) | (0x2 << CP0C0_AT
) |
785 (MMU_TYPE_R4000
<< CP0C0_MT
),
786 .CP0_Config1
= MIPS_CONFIG1
| (1 << CP0C1_FP
) | (63 << CP0C1_MMU
) |
787 (2 << CP0C1_IS
) | (4 << CP0C1_IL
) | (3 << CP0C1_IA
) |
788 (2 << CP0C1_DS
) | (4 << CP0C1_DL
) | (3 << CP0C1_DA
) |
789 (1 << CP0C1_PC
) | (1 << CP0C1_WR
) | (1 << CP0C1_EP
),
790 .CP0_Config2
= MIPS_CONFIG2
,
791 .CP0_Config3
= MIPS_CONFIG3
| (1U << CP0C3_M
) | (1 << CP0C3_DSP2P
) |
792 (1 << CP0C3_DSPP
) | (1 << CP0C3_LPA
),
793 .CP0_LLAddr_rw_bitmask
= 0,
794 .CP0_LLAddr_shift
= 0,
797 .CP0_Status_rw_bitmask
= 0x37FBFFFF,
798 .CP1_fcr0
= (1 << FCR0_F64
) | (1 << FCR0_3D
) | (1 << FCR0_PS
) |
799 (1 << FCR0_L
) | (1 << FCR0_W
) | (1 << FCR0_D
) |
800 (1 << FCR0_S
) | (0x00 << FCR0_PRID
) | (0x0 << FCR0_REV
),
802 .CP1_fcr31_rw_bitmask
= 0xFF83FFFF,
805 .insn_flags
= CPU_MIPS64R2
| ASE_DSP
| ASE_DSPR2
,
806 .mmu_type
= MMU_TYPE_R4000
,
812 static const mips_def_t
*cpu_mips_find_by_name (const char *name
)
816 for (i
= 0; i
< ARRAY_SIZE(mips_defs
); i
++) {
817 if (strcasecmp(name
, mips_defs
[i
].name
) == 0) {
818 return &mips_defs
[i
];
824 void mips_cpu_list (FILE *f
, fprintf_function cpu_fprintf
)
828 for (i
= 0; i
< ARRAY_SIZE(mips_defs
); i
++) {
829 (*cpu_fprintf
)(f
, "MIPS '%s'\n",
834 #ifndef CONFIG_USER_ONLY
835 static void no_mmu_init (CPUMIPSState
*env
, const mips_def_t
*def
)
837 env
->tlb
->nb_tlb
= 1;
838 env
->tlb
->map_address
= &no_mmu_map_address
;
841 static void fixed_mmu_init (CPUMIPSState
*env
, const mips_def_t
*def
)
843 env
->tlb
->nb_tlb
= 1;
844 env
->tlb
->map_address
= &fixed_mmu_map_address
;
847 static void r4k_mmu_init (CPUMIPSState
*env
, const mips_def_t
*def
)
849 env
->tlb
->nb_tlb
= 1 + ((def
->CP0_Config1
>> CP0C1_MMU
) & 63);
850 env
->tlb
->map_address
= &r4k_map_address
;
851 env
->tlb
->helper_tlbwi
= r4k_helper_tlbwi
;
852 env
->tlb
->helper_tlbwr
= r4k_helper_tlbwr
;
853 env
->tlb
->helper_tlbp
= r4k_helper_tlbp
;
854 env
->tlb
->helper_tlbr
= r4k_helper_tlbr
;
855 env
->tlb
->helper_tlbinv
= r4k_helper_tlbinv
;
856 env
->tlb
->helper_tlbinvf
= r4k_helper_tlbinvf
;
859 static void mmu_init (CPUMIPSState
*env
, const mips_def_t
*def
)
861 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
863 env
->tlb
= g_malloc0(sizeof(CPUMIPSTLBContext
));
865 switch (def
->mmu_type
) {
867 no_mmu_init(env
, def
);
870 r4k_mmu_init(env
, def
);
873 fixed_mmu_init(env
, def
);
879 cpu_abort(CPU(cpu
), "MMU type not supported\n");
882 #endif /* CONFIG_USER_ONLY */
884 static void fpu_init (CPUMIPSState
*env
, const mips_def_t
*def
)
888 for (i
= 0; i
< MIPS_FPU_MAX
; i
++)
889 env
->fpus
[i
].fcr0
= def
->CP1_fcr0
;
891 memcpy(&env
->active_fpu
, &env
->fpus
[0], sizeof(env
->active_fpu
));
894 static void mvp_init (CPUMIPSState
*env
, const mips_def_t
*def
)
896 env
->mvp
= g_malloc0(sizeof(CPUMIPSMVPContext
));
898 /* MVPConf1 implemented, TLB sharable, no gating storage support,
899 programmable cache partitioning implemented, number of allocatable
900 and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
901 implemented, 5 TCs implemented. */
902 env
->mvp
->CP0_MVPConf0
= (1U << CP0MVPC0_M
) | (1 << CP0MVPC0_TLBS
) |
903 (0 << CP0MVPC0_GS
) | (1 << CP0MVPC0_PCP
) |
904 // TODO: actually do 2 VPEs.
905 // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
906 // (0x04 << CP0MVPC0_PTC);
907 (1 << CP0MVPC0_TCA
) | (0x0 << CP0MVPC0_PVPE
) |
908 (0x00 << CP0MVPC0_PTC
);
909 #if !defined(CONFIG_USER_ONLY)
910 /* Usermode has no TLB support */
911 env
->mvp
->CP0_MVPConf0
|= (env
->tlb
->nb_tlb
<< CP0MVPC0_PTLBE
);
914 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
915 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
916 env
->mvp
->CP0_MVPConf1
= (1U << CP0MVPC1_CIM
) | (1 << CP0MVPC1_CIF
) |
917 (0x0 << CP0MVPC1_PCX
) | (0x0 << CP0MVPC1_PCP2
) |
918 (0x1 << CP0MVPC1_PCP1
);
921 static void msa_reset(CPUMIPSState
*env
)
923 #ifdef CONFIG_USER_ONLY
924 /* MSA access enabled */
925 env
->CP0_Config5
|= 1 << CP0C5_MSAEn
;
926 env
->CP0_Status
|= (1 << CP0St_CU1
) | (1 << CP0St_FR
);
930 - non-signaling floating point exception mode off (NX bit is 0)
931 - Cause, Enables, and Flags are all 0
932 - round to nearest / ties to even (RM bits are 0) */
933 env
->active_tc
.msacsr
= 0;
935 restore_msa_fp_status(env
);
937 /* tininess detected after rounding.*/
938 set_float_detect_tininess(float_tininess_after_rounding
,
939 &env
->active_tc
.msa_fp_status
);
941 /* clear float_status exception flags */
942 set_float_exception_flags(0, &env
->active_tc
.msa_fp_status
);
944 /* clear float_status nan mode */
945 set_default_nan_mode(0, &env
->active_tc
.msa_fp_status
);
947 /* set proper signanling bit meaning ("1" means "quiet") */
948 set_snan_bit_is_one(0, &env
->active_tc
.msa_fp_status
);