seccomp: add cacheflush to whitelist
[qemu/ar7.git] / target-moxie / helper.c
blobf91ac28d34a6ab5e6851f2fc964adafd693336df
1 /*
2 * Moxie helper routines.
4 * Copyright (c) 2008, 2009, 2010, 2013 Anthony Green
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <stdio.h>
21 #include <string.h>
23 #include "config.h"
24 #include "cpu.h"
25 #include "mmu.h"
26 #include "exec/exec-all.h"
27 #include "exec/cpu_ldst.h"
28 #include "qemu/host-utils.h"
29 #include "exec/helper-proto.h"
31 /* Try to fill the TLB and return an exception if error. If retaddr is
32 NULL, it means that the function was called in C code (i.e. not
33 from generated code or from helper.c) */
34 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
35 uintptr_t retaddr)
37 int ret;
39 ret = moxie_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
40 if (unlikely(ret)) {
41 if (retaddr) {
42 cpu_restore_state(cs, retaddr);
45 cpu_loop_exit(cs);
48 void helper_raise_exception(CPUMoxieState *env, int ex)
50 CPUState *cs = CPU(moxie_env_get_cpu(env));
52 cs->exception_index = ex;
53 /* Stash the exception type. */
54 env->sregs[2] = ex;
55 /* Stash the address where the exception occurred. */
56 cpu_restore_state(cs, GETPC());
57 env->sregs[5] = env->pc;
58 /* Jump to the exception handline routine. */
59 env->pc = env->sregs[1];
60 cpu_loop_exit(cs);
63 uint32_t helper_div(CPUMoxieState *env, uint32_t a, uint32_t b)
65 if (unlikely(b == 0)) {
66 helper_raise_exception(env, MOXIE_EX_DIV0);
67 return 0;
69 if (unlikely(a == INT_MIN && b == -1)) {
70 return INT_MIN;
73 return (int32_t)a / (int32_t)b;
76 uint32_t helper_udiv(CPUMoxieState *env, uint32_t a, uint32_t b)
78 if (unlikely(b == 0)) {
79 helper_raise_exception(env, MOXIE_EX_DIV0);
80 return 0;
82 return a / b;
85 void helper_debug(CPUMoxieState *env)
87 CPUState *cs = CPU(moxie_env_get_cpu(env));
89 cs->exception_index = EXCP_DEBUG;
90 cpu_loop_exit(cs);
93 #if defined(CONFIG_USER_ONLY)
95 void moxie_cpu_do_interrupt(CPUState *cs)
97 CPUState *cs = CPU(moxie_env_get_cpu(env));
99 cs->exception_index = -1;
102 int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
103 int rw, int mmu_idx)
105 MoxieCPU *cpu = MOXIE_CPU(cs);
107 cs->exception_index = 0xaa;
108 cpu->env.debug1 = address;
109 cpu_dump_state(cs, stderr, fprintf, 0);
110 return 1;
113 #else /* !CONFIG_USER_ONLY */
115 int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
116 int rw, int mmu_idx)
118 MoxieCPU *cpu = MOXIE_CPU(cs);
119 CPUMoxieState *env = &cpu->env;
120 MoxieMMUResult res;
121 int prot, miss;
122 target_ulong phy;
123 int r = 1;
125 address &= TARGET_PAGE_MASK;
126 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
127 miss = moxie_mmu_translate(&res, env, address, rw, mmu_idx);
128 if (miss) {
129 /* handle the miss. */
130 phy = 0;
131 cs->exception_index = MOXIE_EX_MMU_MISS;
132 } else {
133 phy = res.phy;
134 r = 0;
136 tlb_set_page(cs, address, phy, prot, mmu_idx, TARGET_PAGE_SIZE);
137 return r;
141 void moxie_cpu_do_interrupt(CPUState *cs)
143 switch (cs->exception_index) {
144 case MOXIE_EX_BREAK:
145 break;
146 default:
147 break;
151 hwaddr moxie_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
153 MoxieCPU *cpu = MOXIE_CPU(cs);
154 uint32_t phy = addr;
155 MoxieMMUResult res;
156 int miss;
158 miss = moxie_mmu_translate(&res, &cpu->env, addr, 0, 0);
159 if (!miss) {
160 phy = res.phy;
162 return phy;
164 #endif