hw/timer/arm_timer.c

   1 /*
   2  * ARM PrimeCell Timer modules.
   3  *
   4  * Copyright (c) 2005-2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "hw/sysbus.h"
  11 #include "qemu/timer.h"
  12 #include "qemu-common.h"
  13 #include "hw/qdev.h"
  14 #include "hw/ptimer.h"
  15 #include "qemu/main-loop.h"
  16
  17 /* Common timer implementation.  */
  18
  19 #define TIMER_CTRL_ONESHOT      (1 << 0)
  20 #define TIMER_CTRL_32BIT        (1 << 1)
  21 #define TIMER_CTRL_DIV1         (0 << 2)
  22 #define TIMER_CTRL_DIV16        (1 << 2)
  23 #define TIMER_CTRL_DIV256       (2 << 2)
  24 #define TIMER_CTRL_IE           (1 << 5)
  25 #define TIMER_CTRL_PERIODIC     (1 << 6)
  26 #define TIMER_CTRL_ENABLE       (1 << 7)
  27
  28 typedef struct {
  29     ptimer_state *timer;
  30     uint32_t control;
  31     uint32_t limit;
  32     int freq;
  33     int int_level;
  34     qemu_irq irq;
  35 } arm_timer_state;
  36
  37 /* Check all active timers, and schedule the next timer interrupt.  */
  38
  39 static void arm_timer_update(arm_timer_state *s)
  40 {
  41     /* Update interrupts.  */
  42     if (s->int_level && (s->control & TIMER_CTRL_IE)) {
  43         qemu_irq_raise(s->irq);
  44     } else {
  45         qemu_irq_lower(s->irq);
  46     }
  47 }
  48
  49 static uint32_t arm_timer_read(void *opaque, hwaddr offset)
  50 {
  51     arm_timer_state *s = (arm_timer_state *)opaque;
  52
  53     switch (offset >> 2) {
  54     case 0: /* TimerLoad */
  55     case 6: /* TimerBGLoad */
  56         return s->limit;
  57     case 1: /* TimerValue */
  58         return ptimer_get_count(s->timer);
  59     case 2: /* TimerControl */
  60         return s->control;
  61     case 4: /* TimerRIS */
  62         return s->int_level;
  63     case 5: /* TimerMIS */
  64         if ((s->control & TIMER_CTRL_IE) == 0)
  65             return 0;
  66         return s->int_level;
  67     default:
  68         qemu_log_mask(LOG_GUEST_ERROR,
  69                       "%s: Bad offset %x\n", __func__, (int)offset);
  70         return 0;
  71     }
  72 }
  73
  74 /* Reset the timer limit after settings have changed.  */
  75 static void arm_timer_recalibrate(arm_timer_state *s, int reload)
  76 {
  77     uint32_t limit;
  78
  79     if ((s->control & (TIMER_CTRL_PERIODIC | TIMER_CTRL_ONESHOT)) == 0) {
  80         /* Free running.  */
  81         if (s->control & TIMER_CTRL_32BIT)
  82             limit = 0xffffffff;
  83         else
  84             limit = 0xffff;
  85     } else {
  86           /* Periodic.  */
  87           limit = s->limit;
  88     }
  89     ptimer_set_limit(s->timer, limit, reload);
  90 }
  91
  92 static void arm_timer_write(void *opaque, hwaddr offset,
  93                             uint32_t value)
  94 {
  95     arm_timer_state *s = (arm_timer_state *)opaque;
  96     int freq;
  97
  98     switch (offset >> 2) {
  99     case 0: /* TimerLoad */
 100         s->limit = value;
 101         arm_timer_recalibrate(s, 1);
 102         break;
 103     case 1: /* TimerValue */
 104         /* ??? Linux seems to want to write to this readonly register.
 105            Ignore it.  */
 106         break;
 107     case 2: /* TimerControl */
 108         if (s->control & TIMER_CTRL_ENABLE) {
 109             /* Pause the timer if it is running.  This may cause some
 110                inaccuracy dure to rounding, but avoids a whole lot of other
 111                messyness.  */
 112             ptimer_stop(s->timer);
 113         }
 114         s->control = value;
 115         freq = s->freq;
 116         /* ??? Need to recalculate expiry time after changing divisor.  */
 117         switch ((value >> 2) & 3) {
 118         case 1: freq >>= 4; break;
 119         case 2: freq >>= 8; break;
 120         }
 121         arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE);
 122         ptimer_set_freq(s->timer, freq);
 123         if (s->control & TIMER_CTRL_ENABLE) {
 124             /* Restart the timer if still enabled.  */
 125             ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0);
 126         }
 127         break;
 128     case 3: /* TimerIntClr */
 129         s->int_level = 0;
 130         break;
 131     case 6: /* TimerBGLoad */
 132         s->limit = value;
 133         arm_timer_recalibrate(s, 0);
 134         break;
 135     default:
 136         qemu_log_mask(LOG_GUEST_ERROR,
 137                       "%s: Bad offset %x\n", __func__, (int)offset);
 138     }
 139     arm_timer_update(s);
 140 }
 141
 142 static void arm_timer_tick(void *opaque)
 143 {
 144     arm_timer_state *s = (arm_timer_state *)opaque;
 145     s->int_level = 1;
 146     arm_timer_update(s);
 147 }
 148
 149 static const VMStateDescription vmstate_arm_timer = {
 150     .name = "arm_timer",
 151     .version_id = 1,
 152     .minimum_version_id = 1,
 153     .fields = (VMStateField[]) {
 154         VMSTATE_UINT32(control, arm_timer_state),
 155         VMSTATE_UINT32(limit, arm_timer_state),
 156         VMSTATE_INT32(int_level, arm_timer_state),
 157         VMSTATE_PTIMER(timer, arm_timer_state),
 158         VMSTATE_END_OF_LIST()
 159     }
 160 };
 161
 162 static arm_timer_state *arm_timer_init(uint32_t freq)
 163 {
 164     arm_timer_state *s;
 165     QEMUBH *bh;
 166
 167     s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state));
 168     s->freq = freq;
 169     s->control = TIMER_CTRL_IE;
 170
 171     bh = qemu_bh_new(arm_timer_tick, s);
 172     s->timer = ptimer_init(bh);
 173     vmstate_register(NULL, -1, &vmstate_arm_timer, s);
 174     return s;
 175 }
 176
 177 /* ARM PrimeCell SP804 dual timer module.
 178  * Docs at
 179  * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html
 180 */
 181
 182 #define TYPE_SP804 "sp804"
 183 #define SP804(obj) OBJECT_CHECK(SP804State, (obj), TYPE_SP804)
 184
 185 typedef struct SP804State {
 186     SysBusDevice parent_obj;
 187
 188     MemoryRegion iomem;
 189     arm_timer_state *timer[2];
 190     uint32_t freq0, freq1;
 191     int level[2];
 192     qemu_irq irq;
 193 } SP804State;
 194
 195 static const uint8_t sp804_ids[] = {
 196     /* Timer ID */
 197     0x04, 0x18, 0x14, 0,
 198     /* PrimeCell ID */
 199     0xd, 0xf0, 0x05, 0xb1
 200 };
 201
 202 /* Merge the IRQs from the two component devices.  */
 203 static void sp804_set_irq(void *opaque, int irq, int level)
 204 {
 205     SP804State *s = (SP804State *)opaque;
 206
 207     s->level[irq] = level;
 208     qemu_set_irq(s->irq, s->level[0] || s->level[1]);
 209 }
 210
 211 static uint64_t sp804_read(void *opaque, hwaddr offset,
 212                            unsigned size)
 213 {
 214     SP804State *s = (SP804State *)opaque;
 215
 216     if (offset < 0x20) {
 217         return arm_timer_read(s->timer[0], offset);
 218     }
 219     if (offset < 0x40) {
 220         return arm_timer_read(s->timer[1], offset - 0x20);
 221     }
 222
 223     /* TimerPeriphID */
 224     if (offset >= 0xfe0 && offset <= 0xffc) {
 225         return sp804_ids[(offset - 0xfe0) >> 2];
 226     }
 227
 228     switch (offset) {
 229     /* Integration Test control registers, which we won't support */
 230     case 0xf00: /* TimerITCR */
 231     case 0xf04: /* TimerITOP (strictly write only but..) */
 232         qemu_log_mask(LOG_UNIMP,
 233                       "%s: integration test registers unimplemented\n",
 234                       __func__);
 235         return 0;
 236     }
 237
 238     qemu_log_mask(LOG_GUEST_ERROR,
 239                   "%s: Bad offset %x\n", __func__, (int)offset);
 240     return 0;
 241 }
 242
 243 static void sp804_write(void *opaque, hwaddr offset,
 244                         uint64_t value, unsigned size)
 245 {
 246     SP804State *s = (SP804State *)opaque;
 247
 248     if (offset < 0x20) {
 249         arm_timer_write(s->timer[0], offset, value);
 250         return;
 251     }
 252
 253     if (offset < 0x40) {
 254         arm_timer_write(s->timer[1], offset - 0x20, value);
 255         return;
 256     }
 257
 258     /* Technically we could be writing to the Test Registers, but not likely */
 259     qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %x\n",
 260                   __func__, (int)offset);
 261 }
 262
 263 static const MemoryRegionOps sp804_ops = {
 264     .read = sp804_read,
 265     .write = sp804_write,
 266     .endianness = DEVICE_NATIVE_ENDIAN,
 267 };
 268
 269 static const VMStateDescription vmstate_sp804 = {
 270     .name = "sp804",
 271     .version_id = 1,
 272     .minimum_version_id = 1,
 273     .fields = (VMStateField[]) {
 274         VMSTATE_INT32_ARRAY(level, SP804State, 2),
 275         VMSTATE_END_OF_LIST()
 276     }
 277 };
 278
 279 static int sp804_init(SysBusDevice *sbd)
 280 {
 281     DeviceState *dev = DEVICE(sbd);
 282     SP804State *s = SP804(dev);
 283
 284     sysbus_init_irq(sbd, &s->irq);
 285     s->timer[0] = arm_timer_init(s->freq0);
 286     s->timer[1] = arm_timer_init(s->freq1);
 287     s->timer[0]->irq = qemu_allocate_irq(sp804_set_irq, s, 0);
 288     s->timer[1]->irq = qemu_allocate_irq(sp804_set_irq, s, 1);
 289     memory_region_init_io(&s->iomem, OBJECT(s), &sp804_ops, s,
 290                           "sp804", 0x1000);
 291     sysbus_init_mmio(sbd, &s->iomem);
 292     vmstate_register(dev, -1, &vmstate_sp804, s);
 293     return 0;
 294 }
 295
 296 /* Integrator/CP timer module.  */
 297
 298 #define TYPE_INTEGRATOR_PIT "integrator_pit"
 299 #define INTEGRATOR_PIT(obj) \
 300     OBJECT_CHECK(icp_pit_state, (obj), TYPE_INTEGRATOR_PIT)
 301
 302 typedef struct {
 303     SysBusDevice parent_obj;
 304
 305     MemoryRegion iomem;
 306     arm_timer_state *timer[3];
 307 } icp_pit_state;
 308
 309 static uint64_t icp_pit_read(void *opaque, hwaddr offset,
 310                              unsigned size)
 311 {
 312     icp_pit_state *s = (icp_pit_state *)opaque;
 313     int n;
 314
 315     /* ??? Don't know the PrimeCell ID for this device.  */
 316     n = offset >> 8;
 317     if (n > 2) {
 318         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n);
 319         return 0;
 320     }
 321
 322     return arm_timer_read(s->timer[n], offset & 0xff);
 323 }
 324
 325 static void icp_pit_write(void *opaque, hwaddr offset,
 326                           uint64_t value, unsigned size)
 327 {
 328     icp_pit_state *s = (icp_pit_state *)opaque;
 329     int n;
 330
 331     n = offset >> 8;
 332     if (n > 2) {
 333         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n);
 334         return;
 335     }
 336
 337     arm_timer_write(s->timer[n], offset & 0xff, value);
 338 }
 339
 340 static const MemoryRegionOps icp_pit_ops = {
 341     .read = icp_pit_read,
 342     .write = icp_pit_write,
 343     .endianness = DEVICE_NATIVE_ENDIAN,
 344 };
 345
 346 static int icp_pit_init(SysBusDevice *dev)
 347 {
 348     icp_pit_state *s = INTEGRATOR_PIT(dev);
 349
 350     /* Timer 0 runs at the system clock speed (40MHz).  */
 351     s->timer[0] = arm_timer_init(40000000);
 352     /* The other two timers run at 1MHz.  */
 353     s->timer[1] = arm_timer_init(1000000);
 354     s->timer[2] = arm_timer_init(1000000);
 355
 356     sysbus_init_irq(dev, &s->timer[0]->irq);
 357     sysbus_init_irq(dev, &s->timer[1]->irq);
 358     sysbus_init_irq(dev, &s->timer[2]->irq);
 359
 360     memory_region_init_io(&s->iomem, OBJECT(s), &icp_pit_ops, s,
 361                           "icp_pit", 0x1000);
 362     sysbus_init_mmio(dev, &s->iomem);
 363     /* This device has no state to save/restore.  The component timers will
 364        save themselves.  */
 365     return 0;
 366 }
 367
 368 static void icp_pit_class_init(ObjectClass *klass, void *data)
 369 {
 370     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 371
 372     sdc->init = icp_pit_init;
 373 }
 374
 375 static const TypeInfo icp_pit_info = {
 376     .name          = TYPE_INTEGRATOR_PIT,
 377     .parent        = TYPE_SYS_BUS_DEVICE,
 378     .instance_size = sizeof(icp_pit_state),
 379     .class_init    = icp_pit_class_init,
 380 };
 381
 382 static Property sp804_properties[] = {
 383     DEFINE_PROP_UINT32("freq0", SP804State, freq0, 1000000),
 384     DEFINE_PROP_UINT32("freq1", SP804State, freq1, 1000000),
 385     DEFINE_PROP_END_OF_LIST(),
 386 };
 387
 388 static void sp804_class_init(ObjectClass *klass, void *data)
 389 {
 390     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 391     DeviceClass *k = DEVICE_CLASS(klass);
 392
 393     sdc->init = sp804_init;
 394     k->props = sp804_properties;
 395 }
 396
 397 static const TypeInfo sp804_info = {
 398     .name          = TYPE_SP804,
 399     .parent        = TYPE_SYS_BUS_DEVICE,
 400     .instance_size = sizeof(SP804State),
 401     .class_init    = sp804_class_init,
 402 };
 403
 404 static void arm_timer_register_types(void)
 405 {
 406     type_register_static(&icp_pit_info);
 407     type_register_static(&sp804_info);
 408 }
 409
 410 type_init(arm_timer_register_types)