hw/nvram/fw_cfg.c

   1 /*
   2  * QEMU Firmware configuration device emulation
   3  *
   4  * Copyright (c) 2008 Gleb Natapov
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw/hw.h"
  25 #include "sysemu/sysemu.h"
  26 #include "sysemu/dma.h"
  27 #include "hw/isa/isa.h"
  28 #include "hw/nvram/fw_cfg.h"
  29 #include "hw/sysbus.h"
  30 #include "trace.h"
  31 #include "qemu/error-report.h"
  32 #include "qemu/config-file.h"
  33
  34 #define FW_CFG_CTL_SIZE 2
  35 #define FW_CFG_NAME "fw_cfg"
  36 #define FW_CFG_PATH "/machine/" FW_CFG_NAME
  37
  38 #define TYPE_FW_CFG     "fw_cfg"
  39 #define TYPE_FW_CFG_IO  "fw_cfg_io"
  40 #define TYPE_FW_CFG_MEM "fw_cfg_mem"
  41
  42 #define FW_CFG(obj)     OBJECT_CHECK(FWCfgState,    (obj), TYPE_FW_CFG)
  43 #define FW_CFG_IO(obj)  OBJECT_CHECK(FWCfgIoState,  (obj), TYPE_FW_CFG_IO)
  44 #define FW_CFG_MEM(obj) OBJECT_CHECK(FWCfgMemState, (obj), TYPE_FW_CFG_MEM)
  45
  46 /* FW_CFG_VERSION bits */
  47 #define FW_CFG_VERSION      0x01
  48 #define FW_CFG_VERSION_DMA  0x02
  49
  50 /* FW_CFG_DMA_CONTROL bits */
  51 #define FW_CFG_DMA_CTL_ERROR   0x01
  52 #define FW_CFG_DMA_CTL_READ    0x02
  53 #define FW_CFG_DMA_CTL_SKIP    0x04
  54 #define FW_CFG_DMA_CTL_SELECT  0x08
  55
  56 #define FW_CFG_DMA_SIGNATURE 0x51454d5520434647ULL /* "QEMU CFG" */
  57
  58 typedef struct FWCfgEntry {
  59     uint32_t len;
  60     uint8_t *data;
  61     void *callback_opaque;
  62     FWCfgReadCallback read_callback;
  63 } FWCfgEntry;
  64
  65 struct FWCfgState {
  66     /*< private >*/
  67     SysBusDevice parent_obj;
  68     /*< public >*/
  69
  70     FWCfgEntry entries[2][FW_CFG_MAX_ENTRY];
  71     FWCfgFiles *files;
  72     uint16_t cur_entry;
  73     uint32_t cur_offset;
  74     Notifier machine_ready;
  75
  76     bool dma_enabled;
  77     dma_addr_t dma_addr;
  78     AddressSpace *dma_as;
  79     MemoryRegion dma_iomem;
  80 };
  81
  82 struct FWCfgIoState {
  83     /*< private >*/
  84     FWCfgState parent_obj;
  85     /*< public >*/
  86
  87     MemoryRegion comb_iomem;
  88     uint32_t iobase, dma_iobase;
  89 };
  90
  91 struct FWCfgMemState {
  92     /*< private >*/
  93     FWCfgState parent_obj;
  94     /*< public >*/
  95
  96     MemoryRegion ctl_iomem, data_iomem;
  97     uint32_t data_width;
  98     MemoryRegionOps wide_data_ops;
  99 };
 100
 101 #define JPG_FILE 0
 102 #define BMP_FILE 1
 103
 104 static char *read_splashfile(char *filename, gsize *file_sizep,
 105                              int *file_typep)
 106 {
 107     GError *err = NULL;
 108     gboolean res;
 109     gchar *content;
 110     int file_type;
 111     unsigned int filehead;
 112     int bmp_bpp;
 113
 114     res = g_file_get_contents(filename, &content, file_sizep, &err);
 115     if (res == FALSE) {
 116         error_report("failed to read splash file '%s'", filename);
 117         g_error_free(err);
 118         return NULL;
 119     }
 120
 121     /* check file size */
 122     if (*file_sizep < 30) {
 123         goto error;
 124     }
 125
 126     /* check magic ID */
 127     filehead = ((content[0] & 0xff) + (content[1] << 8)) & 0xffff;
 128     if (filehead == 0xd8ff) {
 129         file_type = JPG_FILE;
 130     } else if (filehead == 0x4d42) {
 131         file_type = BMP_FILE;
 132     } else {
 133         goto error;
 134     }
 135
 136     /* check BMP bpp */
 137     if (file_type == BMP_FILE) {
 138         bmp_bpp = (content[28] + (content[29] << 8)) & 0xffff;
 139         if (bmp_bpp != 24) {
 140             goto error;
 141         }
 142     }
 143
 144     /* return values */
 145     *file_typep = file_type;
 146
 147     return content;
 148
 149 error:
 150     error_report("splash file '%s' format not recognized; must be JPEG "
 151                  "or 24 bit BMP", filename);
 152     g_free(content);
 153     return NULL;
 154 }
 155
 156 static void fw_cfg_bootsplash(FWCfgState *s)
 157 {
 158     int boot_splash_time = -1;
 159     const char *boot_splash_filename = NULL;
 160     char *p;
 161     char *filename, *file_data;
 162     gsize file_size;
 163     int file_type;
 164     const char *temp;
 165
 166     /* get user configuration */
 167     QemuOptsList *plist = qemu_find_opts("boot-opts");
 168     QemuOpts *opts = QTAILQ_FIRST(&plist->head);
 169     if (opts != NULL) {
 170         temp = qemu_opt_get(opts, "splash");
 171         if (temp != NULL) {
 172             boot_splash_filename = temp;
 173         }
 174         temp = qemu_opt_get(opts, "splash-time");
 175         if (temp != NULL) {
 176             p = (char *)temp;
 177             boot_splash_time = strtol(p, (char **)&p, 10);
 178         }
 179     }
 180
 181     /* insert splash time if user configurated */
 182     if (boot_splash_time >= 0) {
 183         /* validate the input */
 184         if (boot_splash_time > 0xffff) {
 185             error_report("splash time is big than 65535, force it to 65535.");
 186             boot_splash_time = 0xffff;
 187         }
 188         /* use little endian format */
 189         qemu_extra_params_fw[0] = (uint8_t)(boot_splash_time & 0xff);
 190         qemu_extra_params_fw[1] = (uint8_t)((boot_splash_time >> 8) & 0xff);
 191         fw_cfg_add_file(s, "etc/boot-menu-wait", qemu_extra_params_fw, 2);
 192     }
 193
 194     /* insert splash file if user configurated */
 195     if (boot_splash_filename != NULL) {
 196         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, boot_splash_filename);
 197         if (filename == NULL) {
 198             error_report("failed to find file '%s'.", boot_splash_filename);
 199             return;
 200         }
 201
 202         /* loading file data */
 203         file_data = read_splashfile(filename, &file_size, &file_type);
 204         if (file_data == NULL) {
 205             g_free(filename);
 206             return;
 207         }
 208         g_free(boot_splash_filedata);
 209         boot_splash_filedata = (uint8_t *)file_data;
 210         boot_splash_filedata_size = file_size;
 211
 212         /* insert data */
 213         if (file_type == JPG_FILE) {
 214             fw_cfg_add_file(s, "bootsplash.jpg",
 215                     boot_splash_filedata, boot_splash_filedata_size);
 216         } else {
 217             fw_cfg_add_file(s, "bootsplash.bmp",
 218                     boot_splash_filedata, boot_splash_filedata_size);
 219         }
 220         g_free(filename);
 221     }
 222 }
 223
 224 static void fw_cfg_reboot(FWCfgState *s)
 225 {
 226     int reboot_timeout = -1;
 227     char *p;
 228     const char *temp;
 229
 230     /* get user configuration */
 231     QemuOptsList *plist = qemu_find_opts("boot-opts");
 232     QemuOpts *opts = QTAILQ_FIRST(&plist->head);
 233     if (opts != NULL) {
 234         temp = qemu_opt_get(opts, "reboot-timeout");
 235         if (temp != NULL) {
 236             p = (char *)temp;
 237             reboot_timeout = strtol(p, (char **)&p, 10);
 238         }
 239     }
 240     /* validate the input */
 241     if (reboot_timeout > 0xffff) {
 242         error_report("reboot timeout is larger than 65535, force it to 65535.");
 243         reboot_timeout = 0xffff;
 244     }
 245     fw_cfg_add_file(s, "etc/boot-fail-wait", g_memdup(&reboot_timeout, 4), 4);
 246 }
 247
 248 static void fw_cfg_write(FWCfgState *s, uint8_t value)
 249 {
 250     /* nothing, write support removed in QEMU v2.4+ */
 251 }
 252
 253 static int fw_cfg_select(FWCfgState *s, uint16_t key)
 254 {
 255     int ret;
 256
 257     s->cur_offset = 0;
 258     if ((key & FW_CFG_ENTRY_MASK) >= FW_CFG_MAX_ENTRY) {
 259         s->cur_entry = FW_CFG_INVALID;
 260         ret = 0;
 261     } else {
 262         s->cur_entry = key;
 263         ret = 1;
 264     }
 265
 266     trace_fw_cfg_select(s, key, ret);
 267     return ret;
 268 }
 269
 270 static uint8_t fw_cfg_read(FWCfgState *s)
 271 {
 272     int arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL);
 273     FWCfgEntry *e = &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK];
 274     uint8_t ret;
 275
 276     if (s->cur_entry == FW_CFG_INVALID || !e->data || s->cur_offset >= e->len)
 277         ret = 0;
 278     else {
 279         if (e->read_callback) {
 280             e->read_callback(e->callback_opaque, s->cur_offset);
 281         }
 282         ret = e->data[s->cur_offset++];
 283     }
 284
 285     trace_fw_cfg_read(s, ret);
 286     return ret;
 287 }
 288
 289 static uint64_t fw_cfg_data_mem_read(void *opaque, hwaddr addr,
 290                                      unsigned size)
 291 {
 292     FWCfgState *s = opaque;
 293     uint64_t value = 0;
 294     unsigned i;
 295
 296     for (i = 0; i < size; ++i) {
 297         value = (value << 8) | fw_cfg_read(s);
 298     }
 299     return value;
 300 }
 301
 302 static void fw_cfg_data_mem_write(void *opaque, hwaddr addr,
 303                                   uint64_t value, unsigned size)
 304 {
 305     FWCfgState *s = opaque;
 306     unsigned i = size;
 307
 308     do {
 309         fw_cfg_write(s, value >> (8 * --i));
 310     } while (i);
 311 }
 312
 313 static void fw_cfg_dma_transfer(FWCfgState *s)
 314 {
 315     dma_addr_t len;
 316     FWCfgDmaAccess dma;
 317     int arch;
 318     FWCfgEntry *e;
 319     int read;
 320     dma_addr_t dma_addr;
 321
 322     /* Reset the address before the next access */
 323     dma_addr = s->dma_addr;
 324     s->dma_addr = 0;
 325
 326     if (dma_memory_read(s->dma_as, dma_addr, &dma, sizeof(dma))) {
 327         stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control),
 328                    FW_CFG_DMA_CTL_ERROR);
 329         return;
 330     }
 331
 332     dma.address = be64_to_cpu(dma.address);
 333     dma.length = be32_to_cpu(dma.length);
 334     dma.control = be32_to_cpu(dma.control);
 335
 336     if (dma.control & FW_CFG_DMA_CTL_SELECT) {
 337         fw_cfg_select(s, dma.control >> 16);
 338     }
 339
 340     arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL);
 341     e = &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK];
 342
 343     if (dma.control & FW_CFG_DMA_CTL_READ) {
 344         read = 1;
 345     } else if (dma.control & FW_CFG_DMA_CTL_SKIP) {
 346         read = 0;
 347     } else {
 348         dma.length = 0;
 349     }
 350
 351     dma.control = 0;
 352
 353     while (dma.length > 0 && !(dma.control & FW_CFG_DMA_CTL_ERROR)) {
 354         if (s->cur_entry == FW_CFG_INVALID || !e->data ||
 355                                 s->cur_offset >= e->len) {
 356             len = dma.length;
 357
 358             /* If the access is not a read access, it will be a skip access,
 359              * tested before.
 360              */
 361             if (read) {
 362                 if (dma_memory_set(s->dma_as, dma.address, 0, len)) {
 363                     dma.control |= FW_CFG_DMA_CTL_ERROR;
 364                 }
 365             }
 366
 367         } else {
 368             if (dma.length <= (e->len - s->cur_offset)) {
 369                 len = dma.length;
 370             } else {
 371                 len = (e->len - s->cur_offset);
 372             }
 373
 374             if (e->read_callback) {
 375                 e->read_callback(e->callback_opaque, s->cur_offset);
 376             }
 377
 378             /* If the access is not a read access, it will be a skip access,
 379              * tested before.
 380              */
 381             if (read) {
 382                 if (dma_memory_write(s->dma_as, dma.address,
 383                                     &e->data[s->cur_offset], len)) {
 384                     dma.control |= FW_CFG_DMA_CTL_ERROR;
 385                 }
 386             }
 387
 388             s->cur_offset += len;
 389         }
 390
 391         dma.address += len;
 392         dma.length  -= len;
 393
 394     }
 395
 396     stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control),
 397                 dma.control);
 398
 399     trace_fw_cfg_read(s, 0);
 400 }
 401
 402 static uint64_t fw_cfg_dma_mem_read(void *opaque, hwaddr addr,
 403                                     unsigned size)
 404 {
 405     /* Return a signature value (and handle various read sizes) */
 406     return extract64(FW_CFG_DMA_SIGNATURE, (8 - addr - size) * 8, size * 8);
 407 }
 408
 409 static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr,
 410                                  uint64_t value, unsigned size)
 411 {
 412     FWCfgState *s = opaque;
 413
 414     if (size == 4) {
 415         if (addr == 0) {
 416             /* FWCfgDmaAccess high address */
 417             s->dma_addr = value << 32;
 418         } else if (addr == 4) {
 419             /* FWCfgDmaAccess low address */
 420             s->dma_addr |= value;
 421             fw_cfg_dma_transfer(s);
 422         }
 423     } else if (size == 8 && addr == 0) {
 424         s->dma_addr = value;
 425         fw_cfg_dma_transfer(s);
 426     }
 427 }
 428
 429 static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr,
 430                                   unsigned size, bool is_write)
 431 {
 432     return !is_write || ((size == 4 && (addr == 0 || addr == 4)) ||
 433                          (size == 8 && addr == 0));
 434 }
 435
 436 static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr,
 437                                   unsigned size, bool is_write)
 438 {
 439     return addr == 0;
 440 }
 441
 442 static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
 443                                  uint64_t value, unsigned size)
 444 {
 445     fw_cfg_select(opaque, (uint16_t)value);
 446 }
 447
 448 static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
 449                                  unsigned size, bool is_write)
 450 {
 451     return is_write && size == 2;
 452 }
 453
 454 static uint64_t fw_cfg_comb_read(void *opaque, hwaddr addr,
 455                                  unsigned size)
 456 {
 457     return fw_cfg_read(opaque);
 458 }
 459
 460 static void fw_cfg_comb_write(void *opaque, hwaddr addr,
 461                               uint64_t value, unsigned size)
 462 {
 463     switch (size) {
 464     case 1:
 465         fw_cfg_write(opaque, (uint8_t)value);
 466         break;
 467     case 2:
 468         fw_cfg_select(opaque, (uint16_t)value);
 469         break;
 470     }
 471 }
 472
 473 static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
 474                                   unsigned size, bool is_write)
 475 {
 476     return (size == 1) || (is_write && size == 2);
 477 }
 478
 479 static const MemoryRegionOps fw_cfg_ctl_mem_ops = {
 480     .write = fw_cfg_ctl_mem_write,
 481     .endianness = DEVICE_BIG_ENDIAN,
 482     .valid.accepts = fw_cfg_ctl_mem_valid,
 483 };
 484
 485 static const MemoryRegionOps fw_cfg_data_mem_ops = {
 486     .read = fw_cfg_data_mem_read,
 487     .write = fw_cfg_data_mem_write,
 488     .endianness = DEVICE_BIG_ENDIAN,
 489     .valid = {
 490         .min_access_size = 1,
 491         .max_access_size = 1,
 492         .accepts = fw_cfg_data_mem_valid,
 493     },
 494 };
 495
 496 static const MemoryRegionOps fw_cfg_comb_mem_ops = {
 497     .read = fw_cfg_comb_read,
 498     .write = fw_cfg_comb_write,
 499     .endianness = DEVICE_LITTLE_ENDIAN,
 500     .valid.accepts = fw_cfg_comb_valid,
 501 };
 502
 503 static const MemoryRegionOps fw_cfg_dma_mem_ops = {
 504     .read = fw_cfg_dma_mem_read,
 505     .write = fw_cfg_dma_mem_write,
 506     .endianness = DEVICE_BIG_ENDIAN,
 507     .valid.accepts = fw_cfg_dma_mem_valid,
 508     .valid.max_access_size = 8,
 509     .impl.max_access_size = 8,
 510 };
 511
 512 static void fw_cfg_reset(DeviceState *d)
 513 {
 514     FWCfgState *s = FW_CFG(d);
 515
 516     fw_cfg_select(s, 0);
 517 }
 518
 519 /* Save restore 32 bit int as uint16_t
 520    This is a Big hack, but it is how the old state did it.
 521    Or we broke compatibility in the state, or we can't use struct tm
 522  */
 523
 524 static int get_uint32_as_uint16(QEMUFile *f, void *pv, size_t size)
 525 {
 526     uint32_t *v = pv;
 527     *v = qemu_get_be16(f);
 528     return 0;
 529 }
 530
 531 static void put_unused(QEMUFile *f, void *pv, size_t size)
 532 {
 533     fprintf(stderr, "uint32_as_uint16 is only used for backward compatibility.\n");
 534     fprintf(stderr, "This functions shouldn't be called.\n");
 535 }
 536
 537 static const VMStateInfo vmstate_hack_uint32_as_uint16 = {
 538     .name = "int32_as_uint16",
 539     .get  = get_uint32_as_uint16,
 540     .put  = put_unused,
 541 };
 542
 543 #define VMSTATE_UINT16_HACK(_f, _s, _t)                                    \
 544     VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint32_as_uint16, uint32_t)
 545
 546
 547 static bool is_version_1(void *opaque, int version_id)
 548 {
 549     return version_id == 1;
 550 }
 551
 552 static bool fw_cfg_dma_enabled(void *opaque)
 553 {
 554     FWCfgState *s = opaque;
 555
 556     return s->dma_enabled;
 557 }
 558
 559 static const VMStateDescription vmstate_fw_cfg_dma = {
 560     .name = "fw_cfg/dma",
 561     .needed = fw_cfg_dma_enabled,
 562     .fields = (VMStateField[]) {
 563         VMSTATE_UINT64(dma_addr, FWCfgState),
 564         VMSTATE_END_OF_LIST()
 565     },
 566 };
 567
 568 static const VMStateDescription vmstate_fw_cfg = {
 569     .name = "fw_cfg",
 570     .version_id = 2,
 571     .minimum_version_id = 1,
 572     .fields = (VMStateField[]) {
 573         VMSTATE_UINT16(cur_entry, FWCfgState),
 574         VMSTATE_UINT16_HACK(cur_offset, FWCfgState, is_version_1),
 575         VMSTATE_UINT32_V(cur_offset, FWCfgState, 2),
 576         VMSTATE_END_OF_LIST()
 577     },
 578     .subsections = (const VMStateDescription*[]) {
 579         &vmstate_fw_cfg_dma,
 580         NULL,
 581     }
 582 };
 583
 584 static void fw_cfg_add_bytes_read_callback(FWCfgState *s, uint16_t key,
 585                                            FWCfgReadCallback callback,
 586                                            void *callback_opaque,
 587                                            void *data, size_t len)
 588 {
 589     int arch = !!(key & FW_CFG_ARCH_LOCAL);
 590
 591     key &= FW_CFG_ENTRY_MASK;
 592
 593     assert(key < FW_CFG_MAX_ENTRY && len < UINT32_MAX);
 594     assert(s->entries[arch][key].data == NULL); /* avoid key conflict */
 595
 596     s->entries[arch][key].data = data;
 597     s->entries[arch][key].len = (uint32_t)len;
 598     s->entries[arch][key].read_callback = callback;
 599     s->entries[arch][key].callback_opaque = callback_opaque;
 600 }
 601
 602 static void *fw_cfg_modify_bytes_read(FWCfgState *s, uint16_t key,
 603                                               void *data, size_t len)
 604 {
 605     void *ptr;
 606     int arch = !!(key & FW_CFG_ARCH_LOCAL);
 607
 608     key &= FW_CFG_ENTRY_MASK;
 609
 610     assert(key < FW_CFG_MAX_ENTRY && len < UINT32_MAX);
 611
 612     /* return the old data to the function caller, avoid memory leak */
 613     ptr = s->entries[arch][key].data;
 614     s->entries[arch][key].data = data;
 615     s->entries[arch][key].len = len;
 616     s->entries[arch][key].callback_opaque = NULL;
 617
 618     return ptr;
 619 }
 620
 621 void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len)
 622 {
 623     fw_cfg_add_bytes_read_callback(s, key, NULL, NULL, data, len);
 624 }
 625
 626 void fw_cfg_add_string(FWCfgState *s, uint16_t key, const char *value)
 627 {
 628     size_t sz = strlen(value) + 1;
 629
 630     fw_cfg_add_bytes(s, key, g_memdup(value, sz), sz);
 631 }
 632
 633 void fw_cfg_add_i16(FWCfgState *s, uint16_t key, uint16_t value)
 634 {
 635     uint16_t *copy;
 636
 637     copy = g_malloc(sizeof(value));
 638     *copy = cpu_to_le16(value);
 639     fw_cfg_add_bytes(s, key, copy, sizeof(value));
 640 }
 641
 642 void fw_cfg_modify_i16(FWCfgState *s, uint16_t key, uint16_t value)
 643 {
 644     uint16_t *copy, *old;
 645
 646     copy = g_malloc(sizeof(value));
 647     *copy = cpu_to_le16(value);
 648     old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value));
 649     g_free(old);
 650 }
 651
 652 void fw_cfg_add_i32(FWCfgState *s, uint16_t key, uint32_t value)
 653 {
 654     uint32_t *copy;
 655
 656     copy = g_malloc(sizeof(value));
 657     *copy = cpu_to_le32(value);
 658     fw_cfg_add_bytes(s, key, copy, sizeof(value));
 659 }
 660
 661 void fw_cfg_add_i64(FWCfgState *s, uint16_t key, uint64_t value)
 662 {
 663     uint64_t *copy;
 664
 665     copy = g_malloc(sizeof(value));
 666     *copy = cpu_to_le64(value);
 667     fw_cfg_add_bytes(s, key, copy, sizeof(value));
 668 }
 669
 670 void fw_cfg_add_file_callback(FWCfgState *s,  const char *filename,
 671                               FWCfgReadCallback callback, void *callback_opaque,
 672                               void *data, size_t len)
 673 {
 674     int i, index;
 675     size_t dsize;
 676
 677     if (!s->files) {
 678         dsize = sizeof(uint32_t) + sizeof(FWCfgFile) * FW_CFG_FILE_SLOTS;
 679         s->files = g_malloc0(dsize);
 680         fw_cfg_add_bytes(s, FW_CFG_FILE_DIR, s->files, dsize);
 681     }
 682
 683     index = be32_to_cpu(s->files->count);
 684     assert(index < FW_CFG_FILE_SLOTS);
 685
 686     pstrcpy(s->files->f[index].name, sizeof(s->files->f[index].name),
 687             filename);
 688     for (i = 0; i < index; i++) {
 689         if (strcmp(s->files->f[index].name, s->files->f[i].name) == 0) {
 690             error_report("duplicate fw_cfg file name: %s",
 691                          s->files->f[index].name);
 692             exit(1);
 693         }
 694     }
 695
 696     fw_cfg_add_bytes_read_callback(s, FW_CFG_FILE_FIRST + index,
 697                                    callback, callback_opaque, data, len);
 698
 699     s->files->f[index].size   = cpu_to_be32(len);
 700     s->files->f[index].select = cpu_to_be16(FW_CFG_FILE_FIRST + index);
 701     trace_fw_cfg_add_file(s, index, s->files->f[index].name, len);
 702
 703     s->files->count = cpu_to_be32(index+1);
 704 }
 705
 706 void fw_cfg_add_file(FWCfgState *s,  const char *filename,
 707                      void *data, size_t len)
 708 {
 709     fw_cfg_add_file_callback(s, filename, NULL, NULL, data, len);
 710 }
 711
 712 void *fw_cfg_modify_file(FWCfgState *s, const char *filename,
 713                         void *data, size_t len)
 714 {
 715     int i, index;
 716     void *ptr = NULL;
 717
 718     assert(s->files);
 719
 720     index = be32_to_cpu(s->files->count);
 721     assert(index < FW_CFG_FILE_SLOTS);
 722
 723     for (i = 0; i < index; i++) {
 724         if (strcmp(filename, s->files->f[i].name) == 0) {
 725             ptr = fw_cfg_modify_bytes_read(s, FW_CFG_FILE_FIRST + i,
 726                                            data, len);
 727             s->files->f[i].size   = cpu_to_be32(len);
 728             return ptr;
 729         }
 730     }
 731     /* add new one */
 732     fw_cfg_add_file_callback(s, filename, NULL, NULL, data, len);
 733     return NULL;
 734 }
 735
 736 static void fw_cfg_machine_reset(void *opaque)
 737 {
 738     void *ptr;
 739     size_t len;
 740     FWCfgState *s = opaque;
 741     char *bootindex = get_boot_devices_list(&len, false);
 742
 743     ptr = fw_cfg_modify_file(s, "bootorder", (uint8_t *)bootindex, len);
 744     g_free(ptr);
 745 }
 746
 747 static void fw_cfg_machine_ready(struct Notifier *n, void *data)
 748 {
 749     FWCfgState *s = container_of(n, FWCfgState, machine_ready);
 750     qemu_register_reset(fw_cfg_machine_reset, s);
 751 }
 752
 753
 754
 755 static void fw_cfg_init1(DeviceState *dev)
 756 {
 757     FWCfgState *s = FW_CFG(dev);
 758
 759     assert(!object_resolve_path(FW_CFG_PATH, NULL));
 760
 761     object_property_add_child(qdev_get_machine(), FW_CFG_NAME, OBJECT(s), NULL);
 762
 763     qdev_init_nofail(dev);
 764
 765     fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (char *)"QEMU", 4);
 766     fw_cfg_add_bytes(s, FW_CFG_UUID, qemu_uuid, 16);
 767     fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)(display_type == DT_NOGRAPHIC));
 768     fw_cfg_add_i16(s, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
 769     fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu);
 770     fw_cfg_bootsplash(s);
 771     fw_cfg_reboot(s);
 772
 773     s->machine_ready.notify = fw_cfg_machine_ready;
 774     qemu_add_machine_init_done_notifier(&s->machine_ready);
 775 }
 776
 777 FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase,
 778                                 AddressSpace *dma_as)
 779 {
 780     DeviceState *dev;
 781     FWCfgState *s;
 782     uint32_t version = FW_CFG_VERSION;
 783     bool dma_enabled = dma_iobase && dma_as;
 784
 785     dev = qdev_create(NULL, TYPE_FW_CFG_IO);
 786     qdev_prop_set_uint32(dev, "iobase", iobase);
 787     qdev_prop_set_uint32(dev, "dma_iobase", dma_iobase);
 788     qdev_prop_set_bit(dev, "dma_enabled", dma_enabled);
 789
 790     fw_cfg_init1(dev);
 791     s = FW_CFG(dev);
 792
 793     if (dma_enabled) {
 794         /* 64 bits for the address field */
 795         s->dma_as = dma_as;
 796         s->dma_addr = 0;
 797
 798         version |= FW_CFG_VERSION_DMA;
 799     }
 800
 801     fw_cfg_add_i32(s, FW_CFG_ID, version);
 802
 803     return s;
 804 }
 805
 806 FWCfgState *fw_cfg_init_io(uint32_t iobase)
 807 {
 808     return fw_cfg_init_io_dma(iobase, 0, NULL);
 809 }
 810
 811 FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr,
 812                                  hwaddr data_addr, uint32_t data_width,
 813                                  hwaddr dma_addr, AddressSpace *dma_as)
 814 {
 815     DeviceState *dev;
 816     SysBusDevice *sbd;
 817     FWCfgState *s;
 818     uint32_t version = FW_CFG_VERSION;
 819     bool dma_enabled = dma_addr && dma_as;
 820
 821     dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
 822     qdev_prop_set_uint32(dev, "data_width", data_width);
 823     qdev_prop_set_bit(dev, "dma_enabled", dma_enabled);
 824
 825     fw_cfg_init1(dev);
 826
 827     sbd = SYS_BUS_DEVICE(dev);
 828     sysbus_mmio_map(sbd, 0, ctl_addr);
 829     sysbus_mmio_map(sbd, 1, data_addr);
 830
 831     s = FW_CFG(dev);
 832
 833     if (dma_enabled) {
 834         s->dma_as = dma_as;
 835         s->dma_addr = 0;
 836         sysbus_mmio_map(sbd, 2, dma_addr);
 837         version |= FW_CFG_VERSION_DMA;
 838     }
 839
 840     fw_cfg_add_i32(s, FW_CFG_ID, version);
 841
 842     return s;
 843 }
 844
 845 FWCfgState *fw_cfg_init_mem(hwaddr ctl_addr, hwaddr data_addr)
 846 {
 847     return fw_cfg_init_mem_wide(ctl_addr, data_addr,
 848                                 fw_cfg_data_mem_ops.valid.max_access_size,
 849                                 0, NULL);
 850 }
 851
 852
 853 FWCfgState *fw_cfg_find(void)
 854 {
 855     return FW_CFG(object_resolve_path(FW_CFG_PATH, NULL));
 856 }
 857
 858 static void fw_cfg_class_init(ObjectClass *klass, void *data)
 859 {
 860     DeviceClass *dc = DEVICE_CLASS(klass);
 861
 862     dc->reset = fw_cfg_reset;
 863     dc->vmsd = &vmstate_fw_cfg;
 864 }
 865
 866 static const TypeInfo fw_cfg_info = {
 867     .name          = TYPE_FW_CFG,
 868     .parent        = TYPE_SYS_BUS_DEVICE,
 869     .instance_size = sizeof(FWCfgState),
 870     .class_init    = fw_cfg_class_init,
 871 };
 872
 873
 874 static Property fw_cfg_io_properties[] = {
 875     DEFINE_PROP_UINT32("iobase", FWCfgIoState, iobase, -1),
 876     DEFINE_PROP_UINT32("dma_iobase", FWCfgIoState, dma_iobase, -1),
 877     DEFINE_PROP_BOOL("dma_enabled", FWCfgIoState, parent_obj.dma_enabled,
 878                      false),
 879     DEFINE_PROP_END_OF_LIST(),
 880 };
 881
 882 static void fw_cfg_io_realize(DeviceState *dev, Error **errp)
 883 {
 884     FWCfgIoState *s = FW_CFG_IO(dev);
 885     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 886
 887     memory_region_init_io(&s->comb_iomem, OBJECT(s), &fw_cfg_comb_mem_ops,
 888                           FW_CFG(s), "fwcfg", FW_CFG_CTL_SIZE);
 889     sysbus_add_io(sbd, s->iobase, &s->comb_iomem);
 890
 891     if (FW_CFG(s)->dma_enabled) {
 892         memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s),
 893                               &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma",
 894                               sizeof(dma_addr_t));
 895         sysbus_add_io(sbd, s->dma_iobase, &FW_CFG(s)->dma_iomem);
 896     }
 897 }
 898
 899 static void fw_cfg_io_class_init(ObjectClass *klass, void *data)
 900 {
 901     DeviceClass *dc = DEVICE_CLASS(klass);
 902
 903     dc->realize = fw_cfg_io_realize;
 904     dc->props = fw_cfg_io_properties;
 905 }
 906
 907 static const TypeInfo fw_cfg_io_info = {
 908     .name          = TYPE_FW_CFG_IO,
 909     .parent        = TYPE_FW_CFG,
 910     .instance_size = sizeof(FWCfgIoState),
 911     .class_init    = fw_cfg_io_class_init,
 912 };
 913
 914
 915 static Property fw_cfg_mem_properties[] = {
 916     DEFINE_PROP_UINT32("data_width", FWCfgMemState, data_width, -1),
 917     DEFINE_PROP_BOOL("dma_enabled", FWCfgMemState, parent_obj.dma_enabled,
 918                      false),
 919     DEFINE_PROP_END_OF_LIST(),
 920 };
 921
 922 static void fw_cfg_mem_realize(DeviceState *dev, Error **errp)
 923 {
 924     FWCfgMemState *s = FW_CFG_MEM(dev);
 925     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 926     const MemoryRegionOps *data_ops = &fw_cfg_data_mem_ops;
 927
 928     memory_region_init_io(&s->ctl_iomem, OBJECT(s), &fw_cfg_ctl_mem_ops,
 929                           FW_CFG(s), "fwcfg.ctl", FW_CFG_CTL_SIZE);
 930     sysbus_init_mmio(sbd, &s->ctl_iomem);
 931
 932     if (s->data_width > data_ops->valid.max_access_size) {
 933         /* memberwise copy because the "old_mmio" member is const */
 934         s->wide_data_ops.read       = data_ops->read;
 935         s->wide_data_ops.write      = data_ops->write;
 936         s->wide_data_ops.endianness = data_ops->endianness;
 937         s->wide_data_ops.valid      = data_ops->valid;
 938         s->wide_data_ops.impl       = data_ops->impl;
 939
 940         s->wide_data_ops.valid.max_access_size = s->data_width;
 941         s->wide_data_ops.impl.max_access_size  = s->data_width;
 942         data_ops = &s->wide_data_ops;
 943     }
 944     memory_region_init_io(&s->data_iomem, OBJECT(s), data_ops, FW_CFG(s),
 945                           "fwcfg.data", data_ops->valid.max_access_size);
 946     sysbus_init_mmio(sbd, &s->data_iomem);
 947
 948     if (FW_CFG(s)->dma_enabled) {
 949         memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s),
 950                               &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma",
 951                               sizeof(dma_addr_t));
 952         sysbus_init_mmio(sbd, &FW_CFG(s)->dma_iomem);
 953     }
 954 }
 955
 956 static void fw_cfg_mem_class_init(ObjectClass *klass, void *data)
 957 {
 958     DeviceClass *dc = DEVICE_CLASS(klass);
 959
 960     dc->realize = fw_cfg_mem_realize;
 961     dc->props = fw_cfg_mem_properties;
 962 }
 963
 964 static const TypeInfo fw_cfg_mem_info = {
 965     .name          = TYPE_FW_CFG_MEM,
 966     .parent        = TYPE_FW_CFG,
 967     .instance_size = sizeof(FWCfgMemState),
 968     .class_init    = fw_cfg_mem_class_init,
 969 };
 970
 971
 972 static void fw_cfg_register_types(void)
 973 {
 974     type_register_static(&fw_cfg_info);
 975     type_register_static(&fw_cfg_io_info);
 976     type_register_static(&fw_cfg_mem_info);
 977 }
 978
 979 type_init(fw_cfg_register_types)