seccomp: add cacheflush to whitelist
[qemu/ar7.git] / hw / i2c / pm_smbus.c
blobce1713d267e2db765b09ca9a9d510d7edf2984fc
1 /*
2 * PC SMBus implementation
3 * splitted from acpi.c
5 * Copyright (c) 2006 Fabrice Bellard
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License version 2 as published by the Free Software Foundation.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/>.
20 #include "hw/hw.h"
21 #include "hw/i386/pc.h"
22 #include "hw/i2c/pm_smbus.h"
23 #include "hw/i2c/smbus.h"
25 /* no save/load? */
27 #define SMBHSTSTS 0x00
28 #define SMBHSTCNT 0x02
29 #define SMBHSTCMD 0x03
30 #define SMBHSTADD 0x04
31 #define SMBHSTDAT0 0x05
32 #define SMBHSTDAT1 0x06
33 #define SMBBLKDAT 0x07
35 #define STS_HOST_BUSY (1)
36 #define STS_INTR (1<<1)
37 #define STS_DEV_ERR (1<<2)
38 #define STS_BUS_ERR (1<<3)
39 #define STS_FAILED (1<<4)
40 #define STS_SMBALERT (1<<5)
41 #define STS_INUSE_STS (1<<6)
42 #define STS_BYTE_DONE (1<<7)
43 /* Signs of successfully transaction end :
44 * ByteDoneStatus = 1 (STS_BYTE_DONE) and INTR = 1 (STS_INTR )
47 //#define DEBUG
49 #ifdef DEBUG
50 # define SMBUS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
51 #else
52 # define SMBUS_DPRINTF(format, ...) do { } while (0)
53 #endif
56 static void smb_transaction(PMSMBus *s)
58 uint8_t prot = (s->smb_ctl >> 2) & 0x07;
59 uint8_t read = s->smb_addr & 0x01;
60 uint8_t cmd = s->smb_cmd;
61 uint8_t addr = s->smb_addr >> 1;
62 I2CBus *bus = s->smbus;
63 int ret;
65 SMBUS_DPRINTF("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
66 /* Transaction isn't exec if STS_DEV_ERR bit set */
67 if ((s->smb_stat & STS_DEV_ERR) != 0) {
68 goto error;
70 switch(prot) {
71 case 0x0:
72 ret = smbus_quick_command(bus, addr, read);
73 goto done;
74 case 0x1:
75 if (read) {
76 ret = smbus_receive_byte(bus, addr);
77 goto data8;
78 } else {
79 ret = smbus_send_byte(bus, addr, cmd);
80 goto done;
82 case 0x2:
83 if (read) {
84 ret = smbus_read_byte(bus, addr, cmd);
85 goto data8;
86 } else {
87 ret = smbus_write_byte(bus, addr, cmd, s->smb_data0);
88 goto done;
90 break;
91 case 0x3:
92 if (read) {
93 ret = smbus_read_word(bus, addr, cmd);
94 goto data16;
95 } else {
96 ret = smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
97 goto done;
99 break;
100 case 0x5:
101 if (read) {
102 ret = smbus_read_block(bus, addr, cmd, s->smb_data);
103 goto data8;
104 } else {
105 ret = smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
106 goto done;
108 break;
109 default:
110 goto error;
112 abort();
114 data16:
115 if (ret < 0) {
116 goto error;
118 s->smb_data1 = ret >> 8;
119 data8:
120 if (ret < 0) {
121 goto error;
123 s->smb_data0 = ret;
124 done:
125 if (ret < 0) {
126 goto error;
128 s->smb_stat |= STS_BYTE_DONE | STS_INTR;
129 return;
131 error:
132 s->smb_stat |= STS_DEV_ERR;
133 return;
137 static void smb_ioport_writeb(void *opaque, hwaddr addr, uint64_t val,
138 unsigned width)
140 PMSMBus *s = opaque;
142 SMBUS_DPRINTF("SMB writeb port=0x%04" HWADDR_PRIx
143 " val=0x%02" PRIx64 "\n", addr, val);
144 switch(addr) {
145 case SMBHSTSTS:
146 s->smb_stat = (~(val & 0xff)) & s->smb_stat;
147 s->smb_index = 0;
148 break;
149 case SMBHSTCNT:
150 s->smb_ctl = val;
151 if (val & 0x40)
152 smb_transaction(s);
153 break;
154 case SMBHSTCMD:
155 s->smb_cmd = val;
156 break;
157 case SMBHSTADD:
158 s->smb_addr = val;
159 break;
160 case SMBHSTDAT0:
161 s->smb_data0 = val;
162 break;
163 case SMBHSTDAT1:
164 s->smb_data1 = val;
165 break;
166 case SMBBLKDAT:
167 s->smb_data[s->smb_index++] = val;
168 if (s->smb_index > 31)
169 s->smb_index = 0;
170 break;
171 default:
172 break;
176 static uint64_t smb_ioport_readb(void *opaque, hwaddr addr, unsigned width)
178 PMSMBus *s = opaque;
179 uint32_t val;
181 switch(addr) {
182 case SMBHSTSTS:
183 val = s->smb_stat;
184 break;
185 case SMBHSTCNT:
186 s->smb_index = 0;
187 val = s->smb_ctl & 0x1f;
188 break;
189 case SMBHSTCMD:
190 val = s->smb_cmd;
191 break;
192 case SMBHSTADD:
193 val = s->smb_addr;
194 break;
195 case SMBHSTDAT0:
196 val = s->smb_data0;
197 break;
198 case SMBHSTDAT1:
199 val = s->smb_data1;
200 break;
201 case SMBBLKDAT:
202 val = s->smb_data[s->smb_index++];
203 if (s->smb_index > 31)
204 s->smb_index = 0;
205 break;
206 default:
207 val = 0;
208 break;
210 SMBUS_DPRINTF("SMB readb port=0x%04" HWADDR_PRIx " val=0x%02x\n", addr, val);
211 return val;
214 static const MemoryRegionOps pm_smbus_ops = {
215 .read = smb_ioport_readb,
216 .write = smb_ioport_writeb,
217 .valid.min_access_size = 1,
218 .valid.max_access_size = 1,
219 .endianness = DEVICE_LITTLE_ENDIAN,
222 void pm_smbus_init(DeviceState *parent, PMSMBus *smb)
224 smb->smbus = i2c_init_bus(parent, "i2c");
225 memory_region_init_io(&smb->io, OBJECT(parent), &pm_smbus_ops, smb,
226 "pm-smbus", 64);